201231738 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電鍍方法用以同時鍍覆基板的正、 反面，該基板有垂直穿過其内部的穿孔（through-hole)， 以將金屬（例如，銅或其類似物）的鍍覆膜填入該穿孔。 【先前技術】 形成垂直穿過基板之複數個金屬通孔（through-via) 的技術習知為電性連接由數個基板（例如，半導體基板）組 成之多層堆疊中之諸層的方法。習慣上是藉由同時鍍覆有 穿孔垂直穿過其内部之基板的正、反面來製作基板的垂直 通孔，藉此將金屬的鍍覆膜填入穿孔。 已知有一種用於製作通孔的電鍍設備（參考曰本專利 第4138542號）。此電鍍設備包括基板固持件用以固持基板 同時暴露正、反面上的某些區域以及密封在該等某些區域 四周的周圍區域，以及將一對陽極配置成分別與被基板固 持件固持之基板的正、反面面對面。被基板固持件固持的 基板與該等陽極浸入鍍覆液，然後在該基板、該等陽極之 間施加電壓以同時鍍覆有垂直穿孔定義於其中之基板的 正、反面，這可嵌入金屬（例如，銅）於穿孔中。 第1A圖至第1D圖所示的製程步驟序列係圖解說明用 以將鍍覆膜填入定義於基板之穿孔以於其中形成通孔的方 法（參考曰本專利第4248353號)。 如第1A圖所示，預備基板W，其係包含有垂直穿孔 100a定義於其中的基部100，以及由鈦或其類似物製成的 4 323761 201231738 -阻障層（banrier layer)102 與用作饋電層（electric feed layer)及覆蓋基部100之所有表面（包括穿孔的内表 面）的種子層104。同時鍍覆基板W的正、反面以沉積金屬 (例如，銅或其類似物）的鍍覆膜106於基板w的正、反面 上及穿孔100a中，如第1B圖所示。穿孔1〇〇a中的鍍覆膜 106沿著深度方向在中央處有最大厚度。然後，如第圖 所示，成長鍍覆膜106直到已由穿孔100a壁面長成之鍍覆 膜106層的尖端在穿孔10〇3沿著深度方向的中央處相互連 結。穿孔100a沿著深度方向的中央因而被鍍覆膜1〇6阻 塞’而在封閉區的上下方形成凹處1〇8。進一步繼續該鍍 覆裝程以在凹處1〇8中成長鍍覆膜直到錢覆膜填 滿凹處108，如第1D圖所示。以此方式，在基板⑻中產生 由鍍覆獏106構成的通孔。 已有人提出一種用金屬鍍覆膜填滿定義於基板之穿 孔的電鍍方法（參考日本專利早期公開案第2〇〇8_513985 號）。根據此電鍍方法，供給正向脈衝電流以在作為陰極的 基板、陽極之間流動，以及也供給流動方向與正向脈衝電 流相反的反向脈衝電流以在該基板、該陽極之間流動，藉 此完全或實質完全填滿穿孔的中央。 已有人也提出一種用以在用銅鍍覆印刷線路板或其 類似物時防止晶鬚（whisker)產生的方法（參考參考曰本專 利早期公開案第2010-95775號）。根據此方法，用以施加 直流電壓於陰極、陽極之間的直流電源有可逆極性。在交 替的正常直流電壓、反向直流電壓下電鍍印刷線路板，亦 323761 5 201231738 即，交替地使用印刷線路板用作陰極的正常電解周期，以 及印刷線路板用作陽極的逆向電解周期。 【發明内容】 為了在基板中形成無例如，空洞（v〇ids)或其類似物 之缺陷鍍覆膜形式的通孔，如第1A圖至第1D圖所示，理 想的方式是在穿孔沿著深度方向的中央處優先成長鍍覆膜 直到穿孔100a的中央被鍍覆膜106阻塞，然後再繼續該鍍 覆製程。不過，實務上大體難以企圖滿足理想的要求同時 有效率地將鍍覆膜填入穿孔以縮短完成鍍覆製程所需時 間。換言之，習知電鍍製程未能實現在鍍覆期間用較高的 平均鍍覆電流理想地將鍍覆膜填入穿孔以及有效率地將鍍 覆膜填入穿孔兩者。 鑑於上述情形，已做出本發明。因此，本發明的目標 是要提供一種電鍍方法用以在鍍覆期間用較高的平均鍍覆 電流有效率地將鍍覆膜填入穿孔以縮短完成鍍覆製程所需 時間以及也理想地將鍍覆膜填入穿孔。 為了達成上述目標，本發明提供一種電鍍方法，其係 包含下列步驟：將有-穿孔定義於其中的基板浸入在錢覆 槽中的鍍覆液；將在該鍍覆槽之該鍍覆液中的一對陽極配 置成分別與在該鍍覆液中之該基板的正、反面面對面；對 於泫基板的正、反面，藉由各自供給脈衝電流於該基板之 該正面與該等陽極中面對該基板之該正面的一個之間，以 及於該基板之該反面與該等陽極中面對該基板之該反面的 另一個之間，進行各自持續一預定時段的複數個鍍覆製 323761 6 201231738 程；以及在該等鍍覆製程的相鄰製程之間對於該基板的 正、=面，藉由各自供給與該等鍍覆製程之脈衝電流相反 的電流於該基板之該正面與該等陽極中面對該基板之該正 面的個之間，以及於該基板之該反面與該等陽極中面對 該基板之該反面的另一個之間，進行一逆向電解製程。 由於對於該基板的正、反面，藉由各自供給脈衝電流 於該基板之該正面與該等陽極中面對該基板之該正面的一 個之間，以及於該基板之該反面與該等陽極中面對該基板 之該反面的另一個之間，進行各自持續一預定時段的ς數 個錢覆製程，因此有可能用遞增的平均電流值有效率地將 鍍覆膜填入穿孔，從而縮短完成鍍覆製程所需時間。執行 於該等鍍覆製程之間的逆向電解製程可有效地溶解沉積於 穿孔角、落祕覆膜。因此，藉由在穿孔沿著深度方向的中 央處優先成長鍍覆膜有可能理想地將鍍覆膜填入穿孔。 在本發明的一較佳態樣中，該等脈衝電流中之每一包 含以正向流動電流與反向流動電流之交替重覆呈現的pr 脈衝電流（PR pulsed current)。 在使用PR脈衝電流的鍍覆製程之間重覆執行該逆向 電解製程，藉此防止異常沉積於鍍覆膜微觀表面上所產生 的精細不規則性從而防止鍍覆膜形成因精細不規則性而引 起的精細空洞。 在本發明的一較佳態樣中，該等脈衝電流中之每—包 含以供給及不供給正向流動鍍覆電流之交替重覆呈現的開 /關脈衝電流。 323761 7 201231738 由於開/關脈衝電流在鍍覆製程中提供不供給鍍覆電 流的非鍍覆時段（non_plating peri〇d)，穿孔内鍍覆.液的 金屬離子濃度會在非鍍覆時段恢復藉此鍍覆膜形成缺陷， 例如’空洞或其類似物。 在本發明的一較佳態樣中，該等脈衝電流中之每一包 含以有不同電流值之兩個脈衝電流之一組合呈現的組合脈 衝電流。 由於在有該組合脈衝電流的該鍍覆製程中，該鍍覆膜 會繼續成長，因此該鍍覆製程可防止該鍍覆膜溶入該鍍覆 液。 在本發明的一較佳態樣中，一起執行該等鍍覆製程及 該逆向電解製程以隨著基板的鍍覆進展來逐漸增加平均電 流密度。 當錢覆製程使穿孔逐漸填滿鍍覆膜時，穿孔的實質高 深寬比也跟著改變。當穿孔的實質高深寬比改變時，藉由 遞增鑛覆製程的平均電流密度有可能以與穿孔的實質高深 寬比變化匹配的方式來有效率地將鍍覆膜填入穿孔。結 果，可進一步縮短鍍覆基板所需要的時間。 在本發明的一較佳態樣中，在正向供給脈衝電流的正 常電解周期之前及之後多次執行該逆向電解製程。 例如’用在-30至-40 ASD之間的負值陰極電流密度、 以0.1至10毫秒之間的脈衝間距，來執行該逆向電解製 程。取決於定義於該基板之穿孔的高深寬比，根據脈衝間 距小於1.0毫秒的逆向電解製程，優先在穿孔沿著深度方 8 323761 201231738 向的中央處理想地填入鑛覆膜也許不可能。不過，如果在 正向供給脈衝電流的正常電解周期之前及之後，以小於 1. 0毫秒的脈衝間距重覆多次執行該逆向電解製程，則有 可能理想地將鍍覆膜填入該穿孔。 根據本發明’如上述，對於該基板的正、反面，藉由 各自供給脈衝電流於該基板之該正面與該等陽極中面對該 基板之該正面的一個之間，以及於該基板之該反面與該等 陽極中面對該基板之該反面的另一個之間，進行各自持續 一預定時段的複數個鍍覆製程。因此，有可能以遞增的平 均電流值有效率地將鍍覆膜填入穿孔藉此縮短完成鍍覆製 程所需時間。執行於該等鍍覆製程之間的逆向電解製程可 有效地溶解沉積於穿孔角落的鍍覆膜。因此，藉由在穿孔 沿著深度方向的中央處優先成長鐘覆膜有可能理想地將鑛 覆膜填入穿孔。 由以下說明及舉例說明本發明較佳實施例的附圖可 明白以上及其他的本發明目標、特徵及優點。 【實施方式】 此時用附圖描述本發明的較佳具體實施例。第2圖的 垂直剖面正視圖示意圖示用於實施本發明電鐘方法的電鍍 設備50。如第2圖所示，電鍍設備50包含保存鍍覆液q 於其中的鍍覆槽51，以及固持基板W(例如，半導體晶圓片 或其類似物）且垂直懸吊於鍍覆液Q之中的基板固持件 10。有基板固持件10浸在其中的鍍覆液Q在鍍覆槽51上 端有水平面L，如第2圖所示。各自夫撐於陽極固持器58 9 323761 201231738 上的兩個不溶陽極52在鍍覆槽51令配置成分別與由基板 固持件10固持之基板W的兩面（亦即，正、反面）面對面。 如第3圖所不，基板固持件1〇包含有圓孔lla定義於其中 的第-固持構件11與有圓孔12a定義於其中的第二固持構 件12第一固持構件11與第二固持構件丨2用來固持基板 w於其間。不溶陽極52為圓形以及尺寸與第一及第二固持 構件11、12的圓孔lia、i2a實質相同。 由絕緣材料製成的兩個調整板在鍵覆槽51中配置 於基板固持件10與各自的不溶陽極52之間。調整板6〇 各有定義於其中的圓孔而形狀與第一及第二固持構件 11、12之圓孔na、12a的類似。不溶陽極52電氣各自連 接至延伸自鍍覆電源53之端子的電線61a，鍍覆電源 各自能夠改變供給電流的方向從而也改變電流值。鍍覆電 源53有各自電性連接至電線61b的另一端子，電線61b 各自連接至基板固持件1〇的端子板27、28(參考第3圖）。 鐘覆電源53也電性連接至個別控制鑛覆電源53的控制器 59。 二 ° 兩個攪拌漿62在鍍覆槽51中配置於由基板固持件1〇 固持的基板W與各自的調整板6〇之間。攪拌漿62可與由 基板固持件10固持之基板W平行地來回運動用以攪拌鍍覆 液Q。電鍍設備50也包含配置於鍍覆槽51四周的外槽57 用以保存溢出鍍覆槽51的鍍覆液Q。溢出鍍覆槽51進入 外槽57的鑛覆液q藉由鍍覆液循環果54通過怪溫單元55 及濾器56由底部循環回到鍍覆槽51。 323761 10 201231738201231738 VI. Description of the Invention: [Technical Field] The present invention relates to an electroplating method for simultaneously plating the front and back sides of a substrate having a through-hole vertically passing through the inside thereof to A plating film of a metal such as copper or the like is filled in the perforations. [Prior Art] A technique of forming a plurality of through-vias vertically through a substrate is conventionally a method of electrically connecting layers in a multilayer stack composed of a plurality of substrates (e.g., semiconductor substrates). It is customary to form a vertical through hole of the substrate by simultaneously plating the front and back surfaces of the substrate through which the perforations are vertically passed, thereby filling the metal plating film into the perforations. There is known an electroplating apparatus for making a through hole (refer to Japanese Patent No. 4138542). The electroplating apparatus includes a substrate holder for holding the substrate while exposing certain areas on the front and back sides, and surrounding areas surrounding the certain areas, and a pair of anodes respectively configured to be held by the substrate holding member Face to face, face to face. The substrate held by the substrate holding member and the anode are immersed in the plating solution, and then a voltage is applied between the substrate and the anode to simultaneously plate the front and back surfaces of the substrate defined by the vertical perforations, which can be embedded in the metal ( For example, copper) is in the perforation. The sequence of process steps shown in Figs. 1A to 1D illustrates a method for filling a plating film into a perforation defined in a substrate to form a via hole therein (refer to Japanese Patent No. 4248353). As shown in FIG. 1A, a preliminary substrate W comprising a base 100 in which a vertical through hole 100a is defined, and a 4 323761 201231738 - banrier layer 102 made of titanium or the like is used as An electric feed layer and a seed layer 104 covering all surfaces of the base 100, including the inner surface of the perforations. At the same time, the plating film 106 of the metal (e.g., copper or the like) is deposited on the front and back sides of the substrate W on the front and back sides of the substrate w and in the perforations 100a as shown in Fig. 1B. The plating film 106 in the perforation 1〇〇a has a maximum thickness at the center in the depth direction. Then, as shown in the figure, the growth plating film 106 is joined to each other at the center of the perforation 10〇3 in the depth direction up to the tip end of the plating film 106 which has been formed by the wall surface of the perforation 100a. The center of the perforation 100a in the depth direction is thus blocked by the plating film 1〇6, and the recess 1〇8 is formed above and below the closed region. The plating process is further continued to grow the plating film in the recess 1 〇 8 until the money film fills the recess 108 as shown in Fig. 1D. In this way, a through hole composed of the plated crucible 106 is generated in the substrate (8). A plating method in which a through-hole defined by a substrate is filled with a metal plating film has been proposed (refer to Japanese Patent Laid-Open Publication No. 2-513985). According to this plating method, a forward pulse current is supplied to flow between a substrate as a cathode, an anode, and a reverse pulse current having a flow direction opposite to a forward pulse current is also supplied to flow between the substrate and the anode, This completely or substantially completely fills the center of the perforation. A method for preventing whisker generation when plating a printed wiring board or the like with copper has also been proposed (refer to Japanese Patent Laid-Open Publication No. 2010-95775). According to this method, the DC power source for applying a DC voltage between the cathode and the anode has a reversible polarity. The printed circuit board is electroplated at alternate normal DC voltages and reverse DC voltages, also 323761 5 201231738, that is, the normal electrolysis period in which the printed wiring board is used as a cathode, and the reverse electrolysis period in which the printed wiring board is used as an anode. SUMMARY OF THE INVENTION In order to form a via hole in the form of a defect-free plating film of, for example, a void or the like in a substrate, as shown in FIGS. 1A to 1D, the ideal way is at the perforation edge. The plating film is preferentially grown at the center in the depth direction until the center of the perforation 100a is blocked by the plating film 106, and then the plating process is continued. However, in practice, it is generally difficult to attempt to meet the desired requirements while efficiently filling the plating film into the perforations to shorten the time required to complete the plating process. In other words, the conventional plating process fails to achieve a high average plating current during plating, ideally filling the plating film into the perforations and efficiently filling the plating film into both of the perforations. The present invention has been made in view of the above circumstances. Accordingly, it is an object of the present invention to provide an electroplating method for efficiently filling a plating film into a perforation with a higher average plating current during plating to shorten the time required to complete the plating process and also desirably The plated film is filled with perforations. In order to achieve the above object, the present invention provides a plating method comprising the steps of: dipping a substrate having a perforation defined therein into a plating solution in a money coating; and in the plating solution of the plating tank a pair of anodes are disposed to face the front and back sides of the substrate in the plating solution, respectively; for the front and back sides of the substrate, the pulse current is respectively supplied to the front surface of the substrate and the anodes Between one of the front faces of the substrate, and between the opposite side of the substrate and the other of the opposite sides of the substrate facing the substrate, a plurality of plating processes each continuing for a predetermined period of time are performed 323761 6 201231738 And the positive and negative faces of the substrate between the adjacent processes of the plating processes, by respectively supplying a current opposite to the pulse current of the plating processes to the front surface of the substrate and the anodes A reverse electrolysis process is performed between the faces facing the front surface of the substrate and between the opposite side of the substrate and the other of the opposite sides of the anode facing the substrate. For the positive and negative sides of the substrate, by supplying a pulse current between the front surface of the substrate and one of the front faces of the substrate facing the substrate, and the opposite side of the substrate and the anodes Between the other side of the opposite side of the substrate, a plurality of winding processes each continuing for a predetermined period of time are performed, so that it is possible to efficiently fill the perforated film with the increasing average current value, thereby shortening the completion. The time required for the plating process. The reverse electrolysis process performed between the plating processes can effectively dissolve the deposition on the perforation angle and the falling film. Therefore, it is possible to ideally fill the perforations with the plating film by preferentially growing the plating film at the center of the perforation in the depth direction. In a preferred aspect of the invention, each of the pulse currents comprises a PR pulsed current that is alternately repeated with a forward flow current and a reverse flow current. The reverse electrolysis process is repeatedly performed between plating processes using PR pulse currents, thereby preventing fine irregularities generated by abnormal deposition on the microscopic surface of the plating film to prevent the formation of the plating film due to fine irregularities. The fine holes caused. In a preferred aspect of the invention, each of the pulsed currents comprises an on/off pulse current presented in alternating repetitions of supply current and no supply of forward flow plating current. 323761 7 201231738 Since the on/off pulse current provides a non-plating period (non_plating peri〇d) in the plating process that does not supply the plating current, the metal ion concentration in the perforation will be recovered during the non-plating period. This plating film forms defects such as 'cavities or the like. In a preferred aspect of the invention, each of the pulsed currents comprises a combined pulse current presented in combination of one of two pulsed currents having different current values. Since the plating film continues to grow in the plating process having the combined pulse current, the plating process prevents the plating film from being dissolved in the plating solution. In a preferred aspect of the invention, the plating process and the reverse electrolysis process are performed together to gradually increase the average current density as the plating of the substrate progresses. When the money-filling process causes the perforations to gradually fill the plating film, the substantial aspect ratio of the perforations also changes. When the substantial high aspect ratio of the perforations is changed, it is possible to efficiently fill the perforations with the plating film by increasing the average current density of the ore-covering process in such a manner as to match the substantial aspect ratio of the perforations. As a result, the time required to plate the substrate can be further shortened. In a preferred aspect of the invention, the reverse electrolysis process is performed a plurality of times before and after the normal electrolysis cycle of the forward supply pulse current. For example, the reverse electrolysis process is performed with a negative cathode current density between -30 and -40 ASD with a pulse pitch of between 0.1 and 10 milliseconds. Depending on the high aspect ratio of the perforations defined on the substrate, depending on the reverse electrolysis process with a pulse interval of less than 1.0 milliseconds, it may not be possible to preferentially fill the mineral film at the center of the perforation along the depth side 8 323761 201231738. However, if the reverse electrolysis process is repeated a plurality of times at a pulse pitch of less than 1.0 msec before and after the normal electrolysis cycle of supplying the pulse current in the forward direction, it is possible to ideally fill the perforation with the plating film. According to the present invention, as described above, for the front and back sides of the substrate, a pulse current is supplied between the front surface of the substrate and one of the front surfaces of the substrate facing the substrate, and the substrate Between the reverse side and the other of the anodes facing the opposite side of the substrate, a plurality of plating processes each continuing for a predetermined period of time are performed. Therefore, it is possible to efficiently fill the plating film into the perforations with increasing average current values, thereby shortening the time required to complete the plating process. The reverse electrolysis process performed between the plating processes effectively dissolves the plating film deposited on the corners of the perforations. Therefore, it is possible to ideally fill the perforation film by growing the bell film preferentially at the center of the perforation along the depth direction. The above and other objects, features and advantages of the present invention will become apparent from the description and appended claims appended claims. [Embodiment] A preferred embodiment of the present invention will now be described with reference to the drawings. A vertical cross-sectional front view of Fig. 2 shows a plating apparatus 50 for carrying out the electric clock method of the present invention. As shown in FIG. 2, the plating apparatus 50 includes a plating tank 51 in which the plating solution q is stored, and a holding substrate W (for example, a semiconductor wafer or the like) and vertically suspended in the plating liquid Q. The substrate holder 10 in the middle. The plating solution Q having the substrate holder 10 immersed therein has a horizontal plane L at the upper end of the plating tank 51 as shown in Fig. 2. The two insoluble anodes 52, which are supported by the anode holders 58 9 323761 201231738, are disposed in the plating tank 51 so as to face each other on both sides (i.e., the front and back sides) of the substrate W held by the substrate holding member 10. As shown in FIG. 3, the substrate holding member 1 includes a first holding member 11 in which the circular hole 11a is defined and a second holding member 12 in which the circular hole 12a is defined, the first holding member 11 and the second holding member.丨 2 is used to hold the substrate w therebetween. The insoluble anode 52 is circular and substantially the same size as the circular holes lia, i2a of the first and second holding members 11, 12. Two adjustment plates made of an insulating material are disposed between the substrate holder 10 and the respective insoluble anodes 52 in the key groove 51. The adjustment plates 6'' each have a circular hole defined therein and have a shape similar to that of the circular holes na, 12a of the first and second holding members 11, 12. The insoluble anodes 52 are electrically connected to the electric wires 61a extending from the terminals of the plating power source 53, respectively, and the plating power sources are each capable of changing the direction of the supply current and also changing the current value. The plating power source 53 has the other terminals electrically connected to the electric wires 61b, respectively, and the electric wires 61b are each connected to the terminal plates 27, 28 of the substrate holding member 1 (refer to Fig. 3). The clock power supply 53 is also electrically coupled to the controller 59 that individually controls the ore power supply 53. The two agitating pastes 62 are disposed between the substrate W held by the substrate holder 1A and the respective adjustment plates 6A in the plating tank 51. The agitating paddle 62 is movable back and forth in parallel with the substrate W held by the substrate holding member 10 to agitate the plating solution Q. The plating apparatus 50 also includes an outer tank 57 disposed around the plating tank 51 for holding the plating liquid Q overflowing the plating tank 51. The ore coating liquid q which has overflowed the plating tank 51 and enters the outer tank 57 is circulated from the bottom portion back to the plating tank 51 by the plating liquid circulation fruit 54 through the weft temperature unit 55 and the filter 56. 323761 10 201231738
第3圖為基板固持件ι〇的正視圖。第4圖為基板固 持件10的平面圖。第5圖為基板固持件1〇的仰視圖。第 6圖為沿著第3圖之直線κ_κ繪出的橫截面圖。第7圖圖 示以第6圖之箭頭Α為視線繪出的基板固持件1〇。第8圖 圖示以第6圖之箭頭B為視線繪出的基板固持件1 〇。第9 圖圖示以第6圖之箭頭C為視線繪出的基板固持件1〇。第 10圖為沿著第7圖之直線D-D繪出的橫截面圖。第u圖 為沿著第7圖之直線E-E繪出的橫戴面圖。第12圖為沿著 第3圖之直線繪出的橫截面圖。第13圖為沿著第7 圖之直線G-G繪出的橫截面圖。第14圖為沿著第 線H-H繪出的橫截面圖。 弟S之直 如第3圖所示，基板固持件1〇的第一固持構件u及 第-固持構件12(各自呈平面形）各自有用枢接機構㈤卿 隱hanism)13可樞轉地相互耦合的下端。樞接機構η有 由合成樹脂（例如，HTPVC)製成且固定於第二固持構件12 的兩個鉤13-1 〇鉤13-1用由不鏽鋼（例如，sus 3〇3)製成 的鉤銷（hookPin)13-2可角度運動地支樓於第一固持構件 U的下端上。第-固持構件u由合成樹脂（例如，訂㈣ 製成以及呈實質五角形。圓孔lla定義於第一固持構件U 的中央，如第7圖所示。如第3圖所示，由合成樹脂（例如， 順0製成的τ形掛架14與第—固持構件u的上端整體 成形。第二固持構件12由合成樹脂(例如，HTPVC)製成以 及呈^五角形。圓孔12a定義於第二固持構件12的令成央。Figure 3 is a front elevational view of the substrate holder ι. Fig. 4 is a plan view of the substrate holder 10. Fig. 5 is a bottom view of the substrate holder 1〇. Fig. 6 is a cross-sectional view taken along line κ_κ of Fig. 3. Fig. 7 is a view showing the substrate holding member 1〇 drawn by the arrow 第 in Fig. 6. Fig. 8 is a view showing the substrate holder 1 绘 drawn by the arrow B in Fig. 6. Fig. 9 is a view showing the substrate holder 1〇 drawn with the arrow C of Fig. 6 as a line of sight. Fig. 10 is a cross-sectional view taken along line D-D of Fig. 7. Figure u is a cross-sectional view taken along line E-E of Figure 7. Figure 12 is a cross-sectional view taken along the line of Figure 3. Figure 13 is a cross-sectional view taken along line G-G of Figure 7. Figure 14 is a cross-sectional view taken along line H-H. As shown in FIG. 3, the first holding member u and the first holding member 12 of the substrate holding member 1 (each in a planar shape) are pivotally mutually mutually pivotable by a pivoting mechanism (5) The lower end of the coupling. The pivoting mechanism η has two hooks 13-1 made of synthetic resin (for example, HTPVC) and fixed to the second holding member 12, and the hook 13-1 is made of a hook made of stainless steel (for example, sus 3〇3). The hookPin 13-2 is angularly movable on the lower end of the first holding member U. The first-holding member u is made of a synthetic resin (for example, (4) and has a substantially pentagonal shape. The circular hole 11a is defined in the center of the first holding member U as shown in Fig. 7. As shown in Fig. 3, by synthetic resin (For example, the τ-shaped pylon 14 made of cis is integrally formed with the upper end of the first holding member u. The second holding member 12 is made of synthetic resin (for example, HTPVC) and has a pentagon shape. The circular hole 12a is defined in the first The second holding member 12 is in the center of the order.
田第ϋ持構件11與第二固持構件12以枢接機構U 323761 11 201231738 ί=:Γ重叠時，亦即，當基板固持件10關閉時， 11與第二固持構件12用左、右夾细15、16 15、i:起二合成樹脂(例如’ HTPVC)製成的左、右夾钳 凹槽15a、16a用以容納相互重疊之第一 持構件11與第二固持構件12的兩側邊緣於其中。左 =:下端各自藉由插銷Η，而可角度運動地 牙於第固持構件11之兩對邊的下端上。 如第7圖所示，密封環19裝在第一固持構件u中面 第一固持構件12的表面上，以及繞著孔11a延伸。如第 9圖所示，密封環2〇農在第二固持構件12中面對第一固 冓件11的表面上，以及繞著孔心^伸^密封環Μ、 '由橡膠製成’例如，％氧樹脂橡膠（silieQne rubber)。 〇% 29裝在第二固持構件12中面對第一固持構件“的表 面上，以及繞著密封環20延伸。 各有矩形橫截面形狀的密封環19、2〇各自有由其内 周緣徑向向内突出及延伸的隆脊19a、20a。當第一固持構 件11與第二固持構件12在有基板w介於其間下相互重疊 =，隆脊19a、20a各自壓著基板w的表面以及與其保持^ 费接觸’這在〇 ί衣29與徑向在孔11 a、i2a之外的隆脊iga、 2〇a之間定義無鍍覆液Q的水密空間。如第7圖及第圖 所示，用於定位基板1的8個基板導銷21係裝在第一固持 構件11中面對第二固持構件12的表面上，徑向在孔Ua 之外，以及突出穿過密封環19。 如第7圖、第Π圖及第12圖所示，6個導電板22繞 323761 12 201231738 •著孔1 la裝在第一固持構件11中面對第二固持構件12的 表面上。如第11圖所示’ 6個導電板22中有3個通過導 電針腳（conductive pin)23與基板W中之一面（例如，正 面）上的種子層1〇4(參考第1A圖至第1D圖）保持電接觸。 如第12圖所示，其他3個導電板22通過導電針腳23與在 基板W之另一面（例如’反面）上的種子層1〇4保持電接觸。 與基板W中之一面（例如，正面）上的種子層1〇4保持 電接觸3個導電板22通過延伸穿過電線插槽25(參考第13 圖）的絕緣包覆電線26各自電性連接至設於掛架14之端子 板27上的電極端子27a、27b、27c(參考第4圖）。與在基 板W之另一面（例如，反面）上的種子層1〇4保持電接觸的 其他3個導電板22通過延伸穿過電線插槽25(參考第13 圖）的絕緣包覆電線26各自電性連接至設於掛架14之另一 端子板28上的電極端子撕、、28c(參考第4圖）。如 第7圖及第13圖所示，絕緣包覆電線％用由合成樹脂（例 如’ pvc)製成的電線失持器3〇固定。 基板固持件1Q的操作如下：當第-固持構件11鱼第 二固持構件12叫接機構13為中心轉動而相互分開時’ 亦即’田基板固持件10打開時，基板W位於第一固持構件 11上被8個基板導蝕91 ^ _ 幵褥件 *等麵21 &圍的區域中。基板W此時固定 在第一固持構件U μ^ 口疋 上。第一固持構件11與第二固持檨徠 12以樞接機構13 口付稱件 d為中心轉向對方，亦即，基板固持 關閉。然後’左、女+ Λ 口符件10 右失鉗15、16繞著插銷17、18做备潘 動直到第一固持構株η 月運 11與第二固持構件12的兩側邊緣各 323761 201231738 自插入左、右夹鉗15、16的凹槽15a、16a。固定在第一 固持構件11上的基板W此時夾在第一固持構件11與第二 固持構件12之間。 〇環29與密封環19、20的隆脊19a、20a —起定義在 其間無鍍覆液Q的水密空間。此時，基板W的外周緣區（徑 向在隆脊19a、20a之外）位於該水密空間裡，以及基板w 兩面的表面區域（第一固持構件丨丨與第二固持構件丨2之孔 11a、12a共延）暴露於孔iia、i2a。在6個導電板22中， 與在基板W之一面上之種子層1〇4保持電接觸的3個導電 板22電性連接至設於掛架丨4之端子板27上的電極端子 27a、27b、27c，以及與在基板w另一面上之種子層i〇4 保持電接觸的其他3個導電板22電性連接至設於掛架14 之端子板28上的電極端子28a、28b、28c。 第15圖的正視圖圖示第2圖電鍍設備中固持不溶陽 極52於其中的陽極固持器58，而第16圖為第15圖的橫 截面圖。在此具體實施例中，為了防止陽極被㈣液的添 加劑（或數種）溶解’使用陽極主體各由鈦構成以及塗上例 如氧化銥的不溶陽極52。 如第15圖及帛16圖所*，陽極固持器58中之每一 包含有中心孔7〇&定義於其中的固持器主體70,配置於固 持器主體7G反面及封閉中心孔7Qa的封_ 72，配置於 固持器主體π)之中心孔70a中及保持不溶陽極52於其表 面上使得不«極52位於巾心幻Qa巾的圓形支撐板 74，以及裝在固料主體7()正面上及圍住中 323761 14 201231738 -形陽極遮蔽物76。支撐板74有定義於其中的通道74a，通 " 道74a容納電性連接至延伸自鍍覆電源53之電線61a的導 ^電板78於其中。導電板78延伸至支撐板74的中央區，在 此導電板78電性連接至不溶陽極52。 作成為中性薄膜形式的隔離薄膜經配置成可覆蓋 不溶陽極52中位於固持器主體70之中心孔7〇a的表面。 隔離薄膜80有被固持器主體70及陽極遮蔽物π夾住的周 邊，而且固定於固持器主體70。陽極遮蔽物76用螺絲82 固疋於固持器主體70 ’以及封閉板72也用螺絲固定於固 持器主體70。 在陽極固持器58浸入鍍覆液Q時，鍍覆液q進入固 持器主體70中心孔70a中在不溶陽極52、支撐板74之間 的間隙。 使用不溶陽極52與隔離薄膜80的理由如下：要添加 於鍍覆液Q的添加劑包含用以促進形成單價鋼的組份，這 會損及其他添加劑的功能，因為它造成其他添加劑氧化分 解。結果，不能使用可溶陽極。在使用不溶陽極時，不溶 陽極在其附近產生氡氣，產生的氧氣部份溶入鍍覆液q， 而增加溶解氧（dissolved oxygen)的濃度。溶解氧的濃产 增加容易造成添加劑氧化分解。因此，合意的方式是，將 形式為中性薄膜的隔離薄臈8〇配置成與不溶陽極Μ的表 面呈覆蓋關係以防對於基板w附近之添加劑的纽份有不利 影響，即使它們在不溶陽極52附近經受氧化分解。 ， 另一合意的方式是，用空氣或氮供給過孔（例如，通 323761 15 201231738 氣管’未圖示)使不溶陽極52附近的鍍覆液Q充滿氣泡或 氣體用以防止溶解氧的濃度在不溶陽極52側不適當地上 升。 -由於被陽極固持$ 58固持之不溶陽極52 &表面覆蓋 著隔離薄膜8G而不溶陽極52係酉&置成允許隔離薄膜別 面對被基板固持件1G固持及配置於鍍覆槽51内的基板 W，因，在魏覆液Q充滿氣泡及氣_有可能防止氧氣在 不办陽極52附近產生以及溶入鍍覆液從而防止溶解氧在 鍍覆液Q中的濃度增加。 *以此方式構成之電鑛設備50的操作如下：將固持暴 露正、反面之基的基㈣持件1G放人㈣槽51的鍵 覆液Q使得基板W之-面（例如，正面）面對不溶陽極52 中之個卩及基板W的另—面（例如，反面）面對另一個 不溶陽極52。链覆雷;周ώ , 復€原53各自在基板w正面與面對基板w 的不*陽極52之間，以及在基板w反面與面對基板⑻ 面=不溶陽極52之間，供給用控制器59控制的錄覆電 :覆鑛覆基板W的正、反面。如果必要的話，在 的正、反面時’使料漿62與基板W平行地來 回運動以攪拌鍍覆液Q。 所示，錢覆膜106會在定義上=第1Α圖至第1D圖 筮17 隹疋義於基板W穿孔l〇〇a中成長。 橫截面綠:的至另第一= 的基板固拄 土 寺件。圖不於第17圖至第19圖 ==與上述基板固持件不同的地方如下:如第η 板固持件包含近端各自固定於第-固持構件 323761 201231738 11及第二固持構件12的彈性導電板90、92，而不是第11 圖及第12圖的導電針腳22、23。當基板W被第一固持構 件11及第二固持構件12固持時，彈性導電板90、92的遠 側自由端分別有彈性地頂著基板W的正、反面與基板w之 正、反面上的種子層104(參考第1A圖至第1D圖）保持電 接觸。 如第18圖及第19圖所示，該基板固持件也包含各自 用以固持密封環19、20的密封環固持器94、96。密封環 固持器94、96各自固定於第一固持構件11、第二固持構 件12。密封環固持器94、96各自有由交替導齒97、98構 成的陣列用以定位基板W，而不是圖示於第7圖及第1〇圖 的基板導銷21。導齒97、98各自沿著密封環固持器94、 96的周向配置於各個位置。導齒97、98在自由端附近各 自有在内周面上的錐形表面97a、98a。當基板W被第一固 持構件11及第二固持構件12固持時，基板W的外周緣與 錐形表面97a、98a保持接觸及引導以使基板w就定位。 第20圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之鍍覆電流實施例的陰極電流密 度與時間關係圖。供給於基板w反面與面對基板？反面的 不溶陽極52之間的鍍覆電流係與供給於基板w正面與面對 基板W正面的不溶陽極52之間的鍍覆電流保持同步。不 過，該等鍍覆電流彼此不需同步化，因而本發明應不受限 於以上鍍覆電流是否同步。對於供給於基板w表面與面對 基板W表面的不溶陽極52之間的鍍覆電流，第2〇圖圖示 17 323761 201231738 陰極電流密度與時間的關係。 第20圖的實施例係交替重覆以下兩種製程：鍍覆製， 程A，其係供給脈衝電流於基板w表面與不溶陽極52之間、 用以鑛覆基板W表面持續一段預定時段；以及逆向電解製 程B，其供給電流方向係與在鍍覆製程a時供給於基板评 表面與不;谷陽極5 2之間的電流相反。因此，實施鑛覆製程 A的預定時段在5〇至1〇〇毫秒的範圍内，例如，以及實施 逆向電解製程B的預定時段在〇.丨至1〇毫秒的範圍内，或 〇. 5至1毫秒的範圍内為較佳。 如第20圖的虛線所示，在逆向電解製程b之後、鍵 覆製程A之前可插入例如〇.05毫秒的靜止期（quiescent period)C’此時在基板w表面與不溶陽極52之間沒有電流 供給。靜止期C可均勻化穿孔内之鍍覆液Q的金屬離子分 布用以有效率地將鍍覆膜填入穿孔。在以下所述的其他實 施例中插入靜止期C是有利的。 在第20圖的實施例中，實施鍍覆製程A使用有以下 交替重覆之周期的PR脈衝電流：正常電解周期，例如脈衝 間距為P,，鍍覆電流正向流動（亦即，鍍覆方向），正值陰 極電流密度Di在1至3 ASD(A/dm)之間；以及逆向電解周 期，例如脈衝間距為Pz，鍍覆電流逆向流動，負值陰極電 流密度D2在-〇. 〇5至-4 ASD之間。例如，PR脈衝電流之逆 向電解周期的脈衝間距P2為0· 5毫秒。例如，逆向電解製 程B用脈衝間距P3在〇. 1至10毫秒之間（0·5至1毫秒為 較佳）以及負值陰極電流密度D3在-30至-40 ASD之間的單When the first holding member 11 and the second holding member 12 are overlapped by the pivoting mechanism U 323761 11 201231738 ί=: Γ, that is, when the substrate holding member 10 is closed, the left and right holding members 11 and the second holding member 12 are clamped left and right. Fine 15, 16 15, i: left and right jaw grooves 15a, 16a made of two synthetic resin (for example, 'HTPVC) for accommodating the two sides of the first holding member 11 and the second holding member 12 which overlap each other The edge is in it. Left =: The lower ends are each angularly moved to the lower ends of the opposite sides of the first holding member 11 by the latches. As shown in Fig. 7, the seal ring 19 is mounted on the surface of the first holding member 12 in the first holding member u, and extends around the hole 11a. As shown in Fig. 9, the seal ring 2 is on the surface of the second holding member 12 facing the first fixing member 11, and is wound around the hole, and is made of rubber. ,% oxygen rubber (silieQne rubber). 〇% 29 is mounted on the surface of the second holding member 12 facing the first holding member, and extends around the sealing ring 20. Each of the sealing rings 19, 2 having a rectangular cross-sectional shape has its inner peripheral diameter The ridges 19a, 20a projecting and extending inwardly. When the first holding member 11 and the second holding member 12 overlap each other with the substrate w interposed therebetween, the ridges 19a, 20a each press the surface of the substrate w and In order to maintain contact with the 'feature', the watertight space without the plating solution Q is defined between the 〇ί衣 29 and the ridges iga, 2〇a radially outside the holes 11 a, i2a. As shown in Fig. 7 and Fig. As shown, the eight substrate guide pins 21 for positioning the substrate 1 are attached to the surface of the first holding member 11 facing the second holding member 12, radially outside the hole Ua, and projecting through the sealing ring 19 As shown in FIG. 7, FIG. 12 and FIG. 12, six conductive plates 22 are wound around 323761 12 201231738 • A hole 1 la is mounted on the surface of the first holding member 11 facing the second holding member 12. As shown in Fig. 11, three of the six conductive plates 22 pass through one of the conductive pins 23 and one of the substrates W (for example, positive The seed layer 1〇4 (refer to FIGS. 1A to 1D) remains electrically contacted. As shown in FIG. 12, the other three conductive plates 22 pass through the conductive pins 23 and on the other side of the substrate W (eg, 'reverse side' The seed layer 1〇4 remains in electrical contact. It is in electrical contact with the seed layer 1〇4 on one of the substrates (eg, the front side). 3 conductive plates 22 extend through the wire slot 25 (refer to the 13th) The insulated covered wires 26 of FIG. 6 are each electrically connected to the electrode terminals 27a, 27b, 27c provided on the terminal block 27 of the pylon 14 (refer to FIG. 4). On the other side of the substrate W (for example, the reverse side) The other three conductive plates 22 on which the upper seed layer 1 4 is in electrical contact are electrically connected to the other of the hangers 14 through the insulated covered wires 26 extending through the wire slots 25 (refer to FIG. 13). The electrode terminal on the terminal block 28 is torn, 28c (refer to Fig. 4). As shown in Figs. 7 and 13, the insulated covered electric wire is made of a wire loss device made of synthetic resin (for example, 'pvc). 3. The operation of the substrate holding member 1Q is as follows: when the first holding member 11 the second holding member 12 is called the mechanism 13 When the center is rotated and separated from each other, that is, when the field substrate holder 10 is opened, the substrate W is located in the region of the first holding member 11 surrounded by the faces 21 & The substrate W is fixed on the first holding member U μ 此时 at this time. The first holding member 11 and the second holding 檨徕 12 are turned to the other side with the pivoting mechanism 13 as the center of the weighing member d, that is, the substrate is held closed. Then, 'left, female + Λ 件 10 10 right tongs 15, 16 around the pins 17, 18 to prepare for the first holding structure η 月 11 and the second holding member 12 on both sides of the edge 323761 201231738 The grooves 15a, 16a of the left and right clamps 15, 16 are inserted. The substrate W fixed to the first holding member 11 is now sandwiched between the first holding member 11 and the second holding member 12. The annulus 29 together with the ridges 19a, 20a of the seal rings 19, 20 define a watertight space in which there is no plating solution Q therebetween. At this time, the outer peripheral edge region of the substrate W (radially outside the ridges 19a, 20a) is located in the watertight space, and the surface regions of both surfaces of the substrate w (the holes of the first holding member 丨丨 and the second holding member 丨 2) 11a, 12a coextensive) exposed to the holes iia, i2a. Among the six conductive plates 22, three conductive plates 22 that are in electrical contact with the seed layer 1〇4 on one side of the substrate W are electrically connected to the electrode terminals 27a provided on the terminal plate 27 of the cymbal cymbal 4, 27b, 27c, and the other three conductive plates 22 that are in electrical contact with the seed layer i〇4 on the other side of the substrate w are electrically connected to the electrode terminals 28a, 28b, 28c provided on the terminal block 28 of the pylon 14. . Fig. 15 is a front elevational view showing the anode holder 58 in which the insoluble anode 52 is held in the electroplating apparatus of Fig. 2, and Fig. 16 is a cross-sectional view of Fig. 15. In this embodiment, in order to prevent the anode from being dissolved by the additive (or several) of the liquid, the anode body is made of titanium and coated with an insoluble anode 52 such as ruthenium oxide. As shown in Figs. 15 and 16, each of the anode holders 58 includes a center hole 7〇& a holder main body 70 defined therein, and a sealing member disposed on the reverse side of the holder main body 7G and closing the center hole 7Qa. _ 72, disposed in the central hole 70a of the holder main body π) and holding the insoluble anode 52 on the surface thereof so that the non-pole 52 is located on the circular support plate 74 of the towel, and is mounted on the solid body 7 ( ) Front and encircling 323761 14 201231738 - Shaped anode shield 76. The support plate 74 has a passage 74a defined therein, and the passage 74a accommodates a conductive plate 78 electrically connected to the electric wire 61a extending from the plated power source 53 therein. Conductive plate 78 extends to a central region of support plate 74 where electrically conductive plate 78 is electrically coupled to insoluble anode 52. The barrier film in the form of a neutral film is configured to cover the surface of the insoluble anode 52 located at the center hole 7〇a of the holder body 70. The separator 80 has a periphery sandwiched by the holder main body 70 and the anode shield π, and is fixed to the holder main body 70. The anode shield 76 is fixed to the holder main body 70' by screws 82, and the closing plate 72 is also screwed to the holder main body 70. When the anode holder 58 is immersed in the plating solution Q, the plating solution q enters a gap between the insoluble anode 52 and the support plate 74 in the center hole 70a of the holder main body 70. The reason for using the insoluble anode 52 and the separator 80 is as follows: The additive to be added to the plating solution Q contains a component for promoting formation of a monovalent steel, which may impair the function of other additives because it causes oxidative decomposition of other additives. As a result, a soluble anode cannot be used. When an insoluble anode is used, the insoluble anode generates helium gas in the vicinity thereof, and the generated oxygen is partially dissolved in the plating solution q to increase the concentration of dissolved oxygen. The increased production of dissolved oxygen tends to cause oxidative decomposition of the additive. Therefore, it is desirable to arrange the insulating thin layer 8形式 in the form of a neutral film in a covering relationship with the surface of the insoluble anode crucible to prevent adverse effects on the additives of the additive near the substrate w even if they are in the insoluble anode Near 52 is subjected to oxidative decomposition. Another desirable way is to supply the vias with air or nitrogen (for example, through the 323761 15 201231738 air tube 'not shown) to fill the plating solution Q near the insoluble anode 52 with bubbles or gas to prevent the dissolved oxygen concentration from being The side of the insoluble anode 52 is improperly raised. - the insoluble anode 52 & held by the anode held by the anode 58 & the surface covered with the separator film 8G, the insoluble anode 52 system & is disposed to allow the barrier film to be held by the substrate holder 1G and disposed in the plating tank 51 The substrate W is filled with bubbles and gas in the Wei coating Q. It is possible to prevent oxygen from being generated near the anode 52 and to dissolve the plating solution to prevent the concentration of dissolved oxygen in the plating solution Q from increasing. * The operation of the electric ore equipment 50 constructed in this manner is as follows: the base (4) holding member 1G holding the bases of the front and the back is placed in the key coating Q of the (four) groove 51 such that the surface of the substrate W (for example, the front surface) The other side of the insoluble anode 52 and the other side of the substrate W (e.g., the reverse side) face the other insoluble anode 52. The chain is covered with lightning; the circumference of the original 53 is between the front surface of the substrate w and the non-anode 52 facing the substrate w, and between the opposite side of the substrate w and the surface facing the substrate (8) = the insoluble anode 52, the supply control The recording and control of the device 59 controls the front and back sides of the substrate W. If necessary, the slurry 62 is moved back in parallel with the substrate W at the front and back sides to agitate the plating solution Q. As shown, the money film 106 will grow in the definition = 1st to 1D 筮17 in the substrate W perforation l〇〇a. Cross section green: to the other first = the substrate solid earth temple pieces. FIG. 17 to FIG. 19 == The difference from the above substrate holder is as follows: the n-th plate holder includes elastic conduction in which the proximal ends are respectively fixed to the first-holding member 323761 201231738 11 and the second holding member 12. The plates 90, 92 are instead of the conductive pins 22, 23 of Figures 11 and 12. When the substrate W is held by the first holding member 11 and the second holding member 12, the distal free ends of the elastic conductive plates 90, 92 are elastically opposed to the front and back surfaces of the substrate W and the front and back surfaces of the substrate w, respectively. The seed layer 104 (refer to FIGS. 1A through 1D) maintains electrical contact. As shown in Figs. 18 and 19, the substrate holder also includes seal ring holders 94, 96 for holding the seal rings 19, 20, respectively. The seal ring holders 94, 96 are each fixed to the first holding member 11 and the second holding member 12. The seal ring retainers 94, 96 each have an array of alternating guide teeth 97, 98 for positioning the substrate W, rather than the substrate guide pins 21 illustrated in Figures 7 and 1 . The guide teeth 97, 98 are each disposed at each position along the circumferential direction of the seal ring holders 94, 96. The guide teeth 97, 98 each have a tapered surface 97a, 98a on the inner peripheral surface near the free end. When the substrate W is held by the first holding member 11 and the second holding member 12, the outer peripheral edge of the substrate W is kept in contact with and guided by the tapered surfaces 97a, 98a to position the substrate w. Figure 20 is a graph showing cathode current density versus time for an embodiment of a plating current supplied between the surface of the substrate w and the insoluble anode 52 (which is disposed to face the surface of the substrate W). Is it supplied to the opposite side of the substrate w and facing the substrate? The plating current between the insoluble anodes 52 is synchronized with the plating current supplied between the front surface of the substrate w and the insoluble anode 52 facing the front surface of the substrate W. However, the plating currents need not be synchronized with each other, and thus the present invention should not be limited to whether or not the above plating currents are synchronized. For the plating current supplied between the surface of the substrate w and the insoluble anode 52 facing the surface of the substrate W, the second graph shows the relationship between the cathode current density and time of 17 323761 201231738. The embodiment of Fig. 20 alternately repeats the following two processes: plating, process A, which supplies a pulse current between the surface of the substrate w and the insoluble anode 52, and serves to cover the surface of the substrate W for a predetermined period of time; And a reverse electrolysis process B, the direction of the supply current is opposite to the current supplied to the substrate during the plating process a; the current between the valley anodes 52 is opposite. Therefore, the predetermined period of time during which the ore-covering process A is performed is in the range of 5 〇 to 1 〇〇 milliseconds, for example, and the predetermined period of time during which the reverse electrolytic process B is performed is in the range of 〇.丨 to 1 〇 millisecond, or 〇. 5 to A range of 1 millisecond is preferred. As shown by the broken line in Fig. 20, a quiescent period C' of, for example, 〇.05 msec can be inserted after the reverse electrolysis process b and before the bonding process A, at this time, there is no between the surface of the substrate w and the insoluble anode 52. Current supply. The stationary phase C can homogenize the metal ion distribution of the plating solution Q in the perforations for efficiently filling the plating film into the perforations. It is advantageous to insert a stationary phase C in other embodiments described below. In the embodiment of Fig. 20, the plating process A is performed using a PR pulse current having the following alternating repetition periods: a normal electrolysis cycle, for example, a pulse pitch of P, and a plated current is positively flowing (i.e., plated) Direction), the positive cathode current density Di is between 1 and 3 ASD (A/dm); and the reverse electrolysis period, for example, the pulse spacing is Pz, the plating current is reverse flow, and the negative cathode current density D2 is -〇. 5 to -4 ASD. For example, the pulse pitch P2 of the reverse electrolysis period of the PR pulse current is 0.5 mm. For example, the reverse electrolysis process B uses a pulse pitch P3 between 11 to 10 milliseconds (0. 5 to 1 millisecond is preferred) and a negative cathode current density D3 between -30 and -40 ASD.
323761 201231738 •一脈衝實施。 由於逆向電解製程B在鍍覆製程A後用例如在-30至 一40 ASD之間的負值陰極電流密度D3實施，如第21圖的虛 線所示’容易沉積於穿孔l〇〇a轉角的鍍覆膜1〇6a會溶入 鍵覆液Q’從而允許鍍覆膜106優先在穿孔1〇〇3轉角沿著 深度方向成長，如第21圖的實線所示。 如示意圖示於第22圖，在鍍覆製程，鍍覆膜1〇6微 觀表面上的異常沉積容易產生精細不規則性l〇6b。不過， 例如’根據第20圖的實施例，用負值陰極電流密度d2在 -0· 05至-4 ASD之間的逆向電解周期，可防止精細不規則 性106b產生。由異常沉積引起的精細不規則性1〇6b會以 其他方式相互連結而在鍍覆膜中形成精細空洞。 第23圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之另一鏟覆電流實施例的陰極電 流密度與時間關係圖。第23圖的實施例與第20圖實施例 不同的地方在於在施加正向鍍覆電流的正常電解周期之前 及之後用脈衝間距P4在〇· 1至1〇毫秒之間（〇 5至1 〇毫 秒為較佳）的兩個脈衝實施逆向電解製程^。 負值陰極電流密度D3在-30至-40 ASD之間的逆向電 解製程B，如第20圖所示，用單一脈衝實施，其脈衝間距 P3在〇. 1至10毫秒之間。如果脈衝間距Pa大於1毫秒， 則如第24A圖所示，鍍覆膜106會過度溶入鍍覆液而形成 過度溶解區112。如第24B圖所示，過度溶解區112使開 端被封閉而容易在埋入穿孔ll〇a的鍍覆膜1〇6内產生猶眼 19 323761 201231738 空洞（cat-eyed void) 114。因此，脈衝間距p3在〇. 1至i. 〇 毫秒的範圍内為較佳，在〇. 5至1. 0毫秒的範圍内更佳。 不過，取決於定義於基板W之穿孔的高深寬比，根據 逆向電解製程，用脈衝間距小於1· 〇毫秒的單一脈衝優先 在穿孔中心沿著深度方向理想地嵌入鍍覆膜可能為無法實 現的理想嵌入製程。如第23圖所示，藉由施加脈衝間距 Ρ4都小於1. 0毫秒的兩個脈衝來實施的逆向電解製程βι使 得有可能理想地將鍍覆膜填入此一穿孔。 第25圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之又一鍍覆電流實施例的陰極電 流密度與時間關係圖。第25圖的實施例包括3個不同鍍覆 製程，亦即，鍍覆製程（第一鍍覆製程）Αι是在第一區沿著 穿孔100a深度方向直到穿孔1〇〇a的鍍覆膜1〇6在中心處 實質連結，如第1A圖至第ic圖所示，鍍覆製程（第二鍍覆 製程）a2是在第二區用以在穿孔1〇〇a的凹處1〇8散入鑛覆 膜106至預定厚度，如第lc圖與帛1D圖所示，以及錢覆 製程（第三錄覆製程）A3在第三區是在第1]}圖的階段後減 少夾止（pinch-off)的危險。 在第25圖中’第一鍍覆製程Αι，第二鍍覆製程^及 第二鍵覆製程A3係圖示成在逆向電解製程B(參考第別圖） 之前及之後各實施-次。不過，第一鑛覆製程八丨，第二鍵 覆製程A2及第三鑛覆製程八3中之每一實際上在 前及之後可實施數次。這也應㈣以下所述的其他 貫施例。 323761 20 201231738 在第25圖的實施例中，第一鍍覆製程Al，第二鍍覆 製程A2及第二鑛覆製程I中之每一的實施是用開/關脈衝 電流，其係交替重覆地供給及不供給正向流動（亦即，鍍覆 方向）的鍵覆電流’以及有例如在1至3 ASD之間的正值陰 極電流密度D!。第一鍍覆製程Al的開/關脈衝電流的脈衝 間距Ps小於第二鍍覆製程尨之開/關脈衝電流的脈衝間距 Ρ6(Ρ5<Ρ〇，以及第二鍍覆製程Az之開/關脈衝電流的脈衝 間距P6小於第三鍍覆製程Aa之開/關脈衝電流的脈衝間距 p7(p6<p7)。第一、第二及第三鍍覆製程Ai、A2、A3的開/關 脈衝電流有彼此相等的關機間距（d〇wntime pi 、p9、323761 201231738 • One pulse implementation. Since the reverse electrolytic process B is carried out after the plating process A with a negative cathode current density D3 of, for example, between -30 and 40 ASD, as indicated by the broken line in Fig. 21, it is easily deposited on the corner of the perforated l〇〇a. The plating film 1〇6a is dissolved in the keying solution Q' to allow the plating film 106 to preferentially grow in the depth direction at the corner of the perforation 1〇〇3 as shown by the solid line in FIG. As shown in Fig. 22, in the plating process, the abnormal deposition on the 1〇6 microscopic surface of the plating film is liable to produce fine irregularities l〇6b. However, for example, according to the embodiment of Fig. 20, the fine irregularity 106b can be prevented from being generated by the reverse electrolysis period of the negative cathode current density d2 between -0·05 and -4 ASD. Fine irregularities 1〇6b caused by abnormal deposition are otherwise connected to each other to form fine voids in the plating film. Figure 23 is a graph showing cathode current density versus time for another embodiment of a shroud current supplied between the surface of the substrate w and the insoluble anode 52 (configured to face the surface of the substrate W). The difference between the embodiment of Fig. 23 and the embodiment of Fig. 20 is that the pulse pitch P4 is between 〇·1 and 1 〇 milliseconds before and after the normal electrolysis cycle in which the forward plating current is applied (〇5 to 1 〇). The two pulses of milliseconds are preferred to carry out the reverse electrolysis process. The reverse electrolysis process B of the negative cathode current density D3 between -30 and -40 ASD, as shown in Fig. 20, is carried out with a single pulse with a pulse pitch P3 between 〇1 and 10 msec. If the pulse pitch Pa is larger than 1 msec, as shown in Fig. 24A, the plating film 106 is excessively dissolved in the plating solution to form the excessive dissolution region 112. As shown in Fig. 24B, the excessively soluble region 112 causes the open end to be closed to easily generate a cat-eyed void 114 in the plating film 1〇6 buried in the perforation 11〇a. Therefore, the pulse pitch p3 is preferably in the range of 〇. 1 to i. 毫秒 milliseconds, more preferably in the range of 〇. 5 to 1.0 milliseconds. However, depending on the high aspect ratio of the perforations defined on the substrate W, it may not be possible to preferentially embed the plating film along the depth direction at the center of the perforation with a single pulse having a pulse pitch of less than 1·〇 milliseconds according to the reverse electrolysis process. Ideal for embedded processes. As shown in Fig. 23, the reverse electrolysis process βι which is carried out by applying two pulses each having a pulse pitch Ρ4 of less than 1.0 msec makes it possible to ideally fill the perforation with the plating film. Figure 25 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate w and the insoluble anode 52 (which is disposed to face the surface of the substrate W). The embodiment of Fig. 25 includes three different plating processes, that is, the plating process (first plating process) is a plating film 1 in the first region along the depth direction of the perforation 100a until the perforation 1〇〇a 〇6 is substantially joined at the center, as shown in Figures 1A to ic, the plating process (second plating process) a2 is used in the second zone for the recesses 1穿孔8 of the perforations 1〇〇a The ore film 106 is to a predetermined thickness, as shown in Figures lc and 帛1D, and the money-covering process (third recording process) A3 is in the third zone after the stage of the 1]} diagram to reduce the pinch ( The danger of pinch-off). In Fig. 25, the first plating process Αι, the second plating process, and the second bonding process A3 are shown as being performed before and after the reverse electrolysis process B (refer to the figure). However, each of the first mine cover process, the second bond process A2 and the third mine process process 8 can be implemented several times before and after. This should also be followed by (4) other examples as described below. 323761 20 201231738 In the embodiment of Fig. 25, each of the first plating process A1, the second plating process A2 and the second ore process I is performed by using an on/off pulse current, which is alternately heavy The overlying current supply does not supply a forward current flow (ie, a plating direction) and a positive cathode current density D!, for example, between 1 and 3 ASD. The pulse pitch Ps of the on/off pulse current of the first plating process A1 is smaller than the pulse pitch Ρ6 of the on/off pulse current of the second plating process Ρ (Ρ5<Ρ〇, and the on/off of the second plating process Az The pulse pitch P6 of the pulse current is smaller than the pulse pitch p7 of the on/off pulse current of the third plating process Aa (p6 < p7). The on/off pulses of the first, second, and third plating processes Ai, A2, and A3 The currents have equal shutdown intervals (d〇wntime pi, p9,
Pi〇(P8=P9=P1Q)。因此，陰極電流密度的平均值逐步增加。 替換地，陰極電流密度的平均值可線性遞增。 由於開/關脈衝電流提供整個鏡覆製程不供給鍍覆電 流的非鍍覆時段，穿孔内鍍覆液的金屬離子濃度會在非鍍 覆時段恢復’從而防止鍍覆膜形成諸如空洞之類的缺陷。 在鍍覆製程中，隨著穿孔逐漸填滿鑛覆膜，穿孔的實質高 深寬比也跟著改變。當穿孔的實質高深寬比改變時，藉由 遞增鐘覆製程的平均陰極電流密度有可能以與穿孔的實質 高深寬比變化匹配的方式來有效率地將鍍覆膜填入穿孔。 結果’可進一步縮短鍍覆基板所需要的時間。 隨著鍍覆製程的進展而逐步增加鍍覆電流密度為本 技藝所習知。不過，在鍵覆電流密度由低鍍覆電流密度至 高鍍覆電流密度的整個範圍内難以抑制單價銅的產生。根 據此實施例’由於陰極電流密度有恆定的峰值以抑制單價 323761 21 201231738 銅的產生，因此可防止鑛覆液劣化。 第26圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之另一鍍覆電流實施例的陰極電 流密度與時間關係圖。第26圖的實施例與第25圖實施例 不同的地方在於藉由施加脈衝間距Pa各在〇. 1至1〇毫秒 之間（在0 · 5至1. 0毫秒之間為較佳）的兩個脈衝來實施圖 示於第23圖的逆向電解製程Bl，而不是用例如脈衝間距 P3在0· 1至10毫秒之間（〇. 5至1毫秒之間為較佳）的單一 脈衝來實施第25圖逆向電解製程b。 第27圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之又一鍍覆電流實施例的陰極電 流密度與時間關係圖。第27圖的實施例與第25圖實施例 不同的地方在於第一、第二及第三鍍覆製程Αι、a2、^有 彼此相等的加工時間，第一鍍覆製程Αι之開/關脈衝電流 的脈衝間距Ps小於第二鍍覆製程A2之開/關脈衝電流的脈 衝間距P6(P5<P6)，第二鍍覆製程Az之開/關脈衝電流的脈 衝間距P6小於第三鍍覆製程A3之開/關脈衝電流的脈衝間 距P7(P6<P7)，第一鍍覆製程Al之開/關脈衝電流的關機間 距Ρβ大於第二鍍覆製程A2之開/關脈衝電流的關機間距 Ρ9(Ρβ>Ρ9)，以及第二鍍覆製程Αζ之開/關脈衝電流的關機 間距Ρ9大於第二鍍覆製程L之開/關脈衝電流的關機間距 ΡΗ)(Ρ9>Ρ1β)。因此，陰極電流密度的平均值會逐步增加。 第28圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之另一鍍覆電流實施例的陰極電 22 323761 201231738 •流密度與時間關係圖。第28圖的實施例與第25圖實施例 不同的地方在於使用組合脈衝式電源來供給例如正值陰極 電流抵度Di在1至3 ASD之間的第一鑛覆電流，以及例如 正值陰極電流密度D4在0.1至0.5 ASD之間的第二鍛覆電 流’而不是藉由重覆地供給及不供給正向流動（亦即，鍛覆 方向）以及正值陰極電流密度〇,在1至3 ASD之間的 電流來供給開/關脈衝電流的電源。 由於組合脈衝式電源用來持續地供給例如在〇丨至 0 · 5 ASD之間的弱電流，而不是停止供給鍍覆電流，，覆 膜在鍍覆製程中會持續成長。因此，可防止鍍覆膜溶入鐵 覆製程的鍍覆液。 & 第29圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之又一鍍覆電流實施例的陰極電 流密度與時間關係圖。第29圖的實施例與第25圖實施例 不同的地方在於PR脈衝電流的供給係藉由重覆實施例如 正值陰極電密度Di在1至3 ASD之間的正常電解周期， 以及例如負值陰極電流密度j)2在_〇· 〇5至ASD之間的逆 向電解周期’而不是藉由重覆供給及不供給例如正值陰極 電流密度在1至3 ASD之間的鍍覆電流來供給開/關脈衝電 流。 第30圖圖示供給於基板w表面與不溶陽極52(經配置 成面對著基板W表面）間之另一鍍覆電流實施例的陰極電 流密度與時間關係圖。第3〇圖的實施例與第25圖實施例 不同的地方在於它藉由供給例如正值陰極電流密度〇1在1 23 323761 201231738 至3 ASD之間的直流鑛覆電流來依序實施第一、第二及第 三鍵覆製程Ai、A2、As ’第一、第二及第三艘覆製程、 A2、A3有依序加長的加工時間（Al<A2<A3)。 取決於穿孔的高深寬比’鍍覆底層的結構，鍍覆液的 本質、等等’在逆向電解製程之間可能不需要提供靜止期。 如果不需要靜止期’則基板W表面、不溶陽極52可供給錢 覆電流以實現第3 0圖中陰極電流密度與時間的關係從而 縮短完成鍵覆製程所需時間以有效率地將錄覆膜填入穿 孑L β 第31圖圖示供給於基板W表面、不溶陽極52(經配置 成面對著基板W表面）間之又一錢覆電流實施例的陰極電 流密度與時間關係圖。第31圖的實施例與第20圖實施例 不同的地方在於當鍍覆膜106穿孔i〇〇a的凹處1〇8嵌入預 疋厚度時，如第1D圖所示，藉此減少夾止的危險，例如， 逆向電解製程B之後，藉由供給例如正值陰極電流密度 在1至3 ASD之間的直流鍍覆電流來實施鍍覆製程八4。在 減少夾止危險的階段，大體完成鍍覆膜嵌入基板w的穿孔 l〇〇a，如第1D圖所示，以及最終要填滿留在基板表面上的 凹窩（dimple)。此時，不需要供給直流鍍覆電流以使陰極 電流密度與先前的脈衝尖峰電流密度相等，但是可供給直 流鍍覆電流以使陰極電流密度高於先前脈衝尖峰電流密 度，從而縮短完成鑛覆製程所需時間。 第32圖圖示供給於基板W表面與不溶陽極52(經配置 成面對著基板W表面）間之另一鍍覆電流實施例的陰極電 24 323761 201231738 一 ’"，》·岔度與時間關係圖。帛32 β的實施例與第27圖實施例 …不同的地方在於藉由供給例如正值陰極電流密度匕们至 -3 ASD之間的直流鑛覆電流來進行第三鑛覆製程A3，從而 縮短完成鑛覆製程所需時間。 儘管已圖示及詳述本發明的一些較佳具體實施例，然 而應瞭解’仍可做出各種改變及修改而不脫離隨附申請專 利範圍的範疇。 【圖式簡單說明】 、第1A圖至第1D圖所示的製程步驟序列係圖解說明用 、將鍍覆膜填人疋義於基板之穿孔以於其中形成通孔的方 法； 第2圖的垂直剖面正視圖示意圖示用於實施本發明電 錢方法的電鍍設備； 第3圖為第2圖電鍍設備中之基板固持件的正視圖； 第4圖為第2圖電鍍設備中之基板固持件的平面圖； 第5圖為第2圖電鍍設備中之基板固持件的仰視圖； 弟6圖為沿者第3圖之直線K-K繪出的橫截面圖； 第7圖圖示以第6圖之箭頭人為視線繪出的基板固持 件； 第8圖圖示以第6圖之箭頭β為視線繪出的基板固持 件； ' 第9圖圖示以第6圖之箭頭c為視線繪出的基板固持 件； ' 第10圖為沿著第7圖之直線D-D緣出的橫截面圖； 323761 25 201231738 第11圖為沿著第7圖之直線e_e繪出的橫截面圖 第12圖為沿著第3圖之直線F_F繪出的橫戴面圖 第13圖為沿著第7圖之直線G-G繪出的橫截面圖 第14圖為沿著第8圖之直線H_H繪出的橫戴面圖； 第15圖的正視圖圖示第2圖電鍍設備中固持不溶陽 極於其中的陽極固持器； 第16圖的橫截面圖圖示第2圖電鍍設備中固持不溶 陽極於其中的陽極固持器； '备 第Π圖的放大橫截面圖圖示另一基板固持件的主 部份； 第18圖的放大橫截面圖圖示第17圖之基板固持件的 主要部份； 第19圖的放大橫截面圖圖示第17圖之基板固持件的 主要部份； 第20圖圖示供給於基板表面、陽極間之錢覆電流實 施例的陰極電流密度與時間關係圖； 第21圖的放大局部橫截面圖圖示在鐘覆製程後執行 逆向電解製程時在穿孔沿著深度方向的中央處優先成長鍍 覆膜的方式； & 第22圖的放大局部橫截面圖示意圖示鍍覆製程中由 鍍覆膜微觀表面之異常沉積產生的精細不規則性； 第23圖圖示供給於基板表面與陽極間之另一鍍覆電 流實施例的陰極電流密度與時間關係圖； 第24A圖與第24B圖的放大局部橫截面圖示意圖示嵌Pi〇 (P8=P9=P1Q). Therefore, the average value of the cathode current density is gradually increased. Alternatively, the average value of the cathode current density can be linearly increased. Since the on/off pulse current provides a non-plating period in which the entire mirror coating process does not supply the plating current, the metal ion concentration of the plating solution in the perforation is restored during the non-plating period, thereby preventing the plating film from being formed, such as a void. defect. In the plating process, as the perforations gradually fill the mineral film, the substantial aspect ratio of the perforations also changes. When the substantial aspect ratio of the perforations is changed, it is possible to efficiently fill the perforations of the plating film by matching the average aspect ratio of the perforations with the average cathode current density of the incremental clocking process. As a result, the time required for plating the substrate can be further shortened. It is well known in the art to gradually increase the plating current density as the plating process progresses. However, it is difficult to suppress the generation of monovalent copper in the entire range of the bond current density from the low plating current density to the high plating current density. According to this embodiment, since the cathode current density has a constant peak to suppress the generation of the unit price 323761 21 201231738 copper, the deterioration of the ore coating can be prevented. Figure 26 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate w and the insoluble anode 52 (which is disposed to face the surface of the substrate W). The difference between the embodiment of Fig. 26 and the embodiment of Fig. 25 is that the application of the pulse pitch Pa is between 1 and 1 milliseconds (preferably between 0.5 and 1.0 milliseconds). Two pulses are used to implement the reverse electrolysis process B1 shown in Fig. 23, instead of using a single pulse such as a pulse pitch P3 between 0. 1 and 10 msec (preferably between 0.5 and 1 msec). The reverse electrolysis process b of Fig. 25 is carried out. Figure 27 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate w and the insoluble anode 52 (which is disposed to face the surface of the substrate W). The difference between the embodiment of Fig. 27 and the embodiment of Fig. 25 is that the first, second, and third plating processes Αι, a2, and ^ have processing times equal to each other, and the first plating process is turned on/off. The pulse pitch Ps of the current is smaller than the pulse pitch P6 of the on/off pulse current of the second plating process A2 (P5 < P6), and the pulse pitch P6 of the on/off pulse current of the second plating process Az is smaller than the third plating process The pulse pitch P7 of the on/off pulse current of A3 (P6 < P7), the turn-off interval Ρβ of the on/off pulse current of the first plating process A1 is larger than the turn-off interval of the on/off pulse current of the second plating process A2 Ρ9 (Ρβ>Ρ9), and the shutdown interval Ρ9 of the on/off pulse current of the second plating process Ρ is larger than the shutdown interval 开 of the on/off pulse current of the second plating process L) (Ρ9>Ρ1β). Therefore, the average value of the cathode current density is gradually increased. Figure 28 illustrates cathodic electricity supplied to another plated current embodiment between the surface of the substrate w and the insoluble anode 52 (configured to face the surface of the substrate W) 22 323761 201231738 • Flow density versus time. The embodiment of Fig. 28 differs from the embodiment of Fig. 25 in that a combined pulsed power supply is used to supply, for example, a first ore cover current having a positive cathode current resistance Di between 1 and 3 ASD, and for example a positive cathode The second forging current of the current density D4 is between 0.1 and 0.5 ASD' instead of being supplied by the repeated supply and not supplying the forward flow (ie, the forging direction) and the positive cathode current density 〇, at 1 to 3 Current between ASDs to supply power to the on/off pulse current. Since the combined pulsed power supply is used to continuously supply a weak current, for example, between 〇丨 and 0.5 ASD, rather than stopping the supply of the plating current, the coating continues to grow during the plating process. Therefore, it is possible to prevent the plating film from being dissolved in the plating solution of the iron coating process. & Figure 29 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate w and the insoluble anode 52 (which is disposed to face the surface of the substrate W). The difference between the embodiment of Fig. 29 and the embodiment of Fig. 25 is that the supply of the PR pulse current is repeated by, for example, performing a normal electrolysis cycle of a positive cathodic electrical density Di between 1 and 3 ASD, and for example, a negative value. The cathode current density j)2 is reversed in the period between _〇·〇5 and ASD' rather than by re-feeding and not supplying a plating current such as a positive cathode current density between 1 and 3 ASD. On/off pulse current. Figure 30 is a graph showing cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate w and the insoluble anode 52 (which is disposed to face the surface of the substrate W). The difference between the embodiment of Fig. 3 and the embodiment of Fig. 25 is that it is implemented first by supplying a DC ore current, for example, a positive cathode current density 〇1 between 1 23 323761 201231738 and 3 ASD. The second and third bonding processes Ai, A2, As 'the first, second and third coating processes, A2 and A3 have sequential processing times (Al<A2<A3). Depending on the high aspect ratio of the perforations, the structure of the plated underlayer, the nature of the plating solution, etc., it may not be necessary to provide a stationary period between the reverse electrolysis processes. If the stationary period is not required, the surface of the substrate W and the insoluble anode 52 can supply a current to achieve the relationship between the cathode current density and the time in FIG. 30, thereby shortening the time required to complete the keying process to efficiently record the film. Filling through the 孑L β Figure 31 illustrates a graph of cathode current density versus time for an embodiment of a further current applied between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). The difference between the embodiment of Fig. 31 and the embodiment of Fig. 20 is that when the recess 1〇8 of the perforation i〇〇a of the plating film 106 is embedded in the pre-thickness, as shown in Fig. 1D, the pinching is reduced. The danger, for example, after the reverse electrolysis process B, is carried out by supplying a DC plating current such as a positive cathode current density between 1 and 3 ASD. At the stage of reducing the risk of pinching, the perforation l〇〇a of the plating film embedded in the substrate w is substantially completed, as shown in Fig. 1D, and finally filled with dimples remaining on the surface of the substrate. At this time, it is not necessary to supply a DC plating current to make the cathode current density equal to the previous pulse peak current density, but a DC plating current can be supplied to make the cathode current density higher than the previous pulse peak current density, thereby shortening the completion of the ore-covering process. Time required. Figure 32 illustrates a cathode electricity supply to another substrate current between the surface of the substrate W and the insoluble anode 52 (configured to face the surface of the substrate W). 24 323761 201231738 A '", 岔度与Time diagram. The difference between the embodiment of 帛32β and the embodiment of Fig. 27 is that the third ore-covering process A3 is performed by supplying a direct current cover current of, for example, a positive cathode current density to -3 ASD, thereby shortening The time required to complete the mine cover process. While the preferred embodiment of the present invention has been shown and described, it is understood that various changes and modifications may be made without departing from the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The process sequence sequence shown in FIGS. 1A to 1D illustrates a method of filling a plating film with a perforation of a substrate to form a via hole therein; 1 is a front view of a substrate holder in the electroplating apparatus of FIG. 2; FIG. 5 is a bottom view of the substrate holder in the electroplating apparatus of FIG. 2; FIG. 6 is a cross-sectional view taken along line KK of FIG. 3; The arrow of the figure is the substrate holder drawn by the line of sight; the figure 8 shows the substrate holder drawn by the arrow β of Fig. 6; 'Fig. 9 is drawn with the arrow c of Fig. 6 as the line of sight a substrate holder; 'Fig. 10 is a cross-sectional view taken along line DD of Fig. 7; 323761 25 201231738 Fig. 11 is a cross-sectional view taken along line e_e of Fig. 7 The cross-sectional view taken along line F_F of Fig. 3 is a cross-sectional view taken along line GG of Fig. 7. Figure 14 is a cross-sectional view taken along line H_H of Figure 8; a front view of Figure 15 is an illustration of the anode holder in which the insoluble anode is held in the electroplating apparatus of Figure 2; 2 is a diagram showing an anode holder in which an insoluble anode is held in an electroplating apparatus; FIG. 2 is an enlarged cross-sectional view showing a main portion of another substrate holder; an enlarged cross-sectional view of FIG. The main part of the substrate holder of Fig. 17 is shown; the enlarged cross-sectional view of Fig. 19 shows the main part of the substrate holder of Fig. 17; and Fig. 20 shows the money supplied to the surface of the substrate and between the anodes. FIG. 21 is an enlarged partial cross-sectional view showing the manner in which the plating film is preferentially grown at the center of the perforation along the depth direction when the reverse electrolysis process is performed after the clock-coating process & An enlarged partial cross-sectional view of Fig. 22 shows fine irregularities caused by abnormal deposition of the microscopic surface of the plating film in the plating process; Fig. 23 illustrates another supply between the surface of the substrate and the anode A plating current embodiment Cathode current density versus time; FIG. 24A and the second enlarged partial cross sectional view of FIG. 24B shows a schematic view of the insert
323761 26 201231738 入穿孔之鍍覆膜過度溶入鍍覆液直到最終在鍍覆膜中形成 空洞的方式； 第25圖圖示供給於基板表面與陽極間之又一鍍覆電 流實施例的陰極電流密度與時間關係圖； 第26圖圖示供給於基板表面與陽極間之另一鍍覆電 流實施例的陰極電流密度與時間關係圖； 第27圖圖示供給於基板表面與陽極間之又一鍍覆電 流實施例的陰極電流密度與時間關係圖； 第28圖圖示供給於基板表面與陽極間之另一鍍覆電 流實施例的陰極電流密度與時間關係圖； 第29圖圖示供給於基板表面與陽極間之又一鍍覆電 流實施例的陰極電流密度與時間關係圖； 第30圖圖示供給於基板表面與陽極間之另一鍍覆電 流實施例的陰極電流密度與時間關係圖； 第31圖圖示供給於基板表面與陽極間之又一鍍覆電 流實施例的陰極電流密度與時間關係圖；以及 第32圖圖示供給於基板表面與陽極間之另一鍍覆電 流實施例的陰極電流密度與時間關係圖。 【主要元件符號說明】 10 基板固持件 11 第一固持構件 1 la、12a 圓孔 12 第二固持構件 13 柩接機構 13-1 釣 13-2 鉤鎖 14 T形掛架 15、16 夾钳 15a、 16a 凹槽 27 323761 201231738 17、18 插銷 19、20 密封環 19a ' 20a 隆脊 21 基板導銷 22 導電板 23 導電針腳 25 電線插槽 26 絕緣包覆電線 27、28 端子板 27a 、 27b | 、 27c 、 28a 、 28b 、28c 電極端子 29 0環 30 電線爽持 50 電鍍設備 51 鍍覆槽 52 不溶陽極 53 鍍覆電源 54 鍍覆液循環泵 55 恆溫單元 56 渡器 57 外槽 58 陽極固持器 59 控制器 60 調整板 61a、 61b 電線 62 攪拌漿 70 固持器主體 70a 中心孔 72 封閉板 74 圓形支撐板 74a 通道 76 環形陽極遮蔽物 78 導電板 80 隔離薄膜 82 螺絲 90、92 彈性導電板 94、 96 密封環固持器 97、98 導齒 97a、 98a 錐形表面 100 基部 100a 垂直穿孔 102 阻障層 104 種子層 106、106a 鍍覆膜 108 凹處 112 過度溶解區 114 貓眼空洞 28 323761 201231738323761 26 201231738 The manner in which the perforated plating film is excessively dissolved into the plating solution until a void is finally formed in the plating film; FIG. 25 illustrates the cathode current of another plating current applied to the substrate surface and the anode. Diagram of density vs. time; Figure 26 is a graph showing cathode current density versus time for another plating current supplied between the surface of the substrate and the anode; Figure 27 is a diagram showing another supply between the surface of the substrate and the anode. Cathode current density versus time for a plated current embodiment; Figure 28 is a graph showing cathode current density vs. time for another plated current embodiment supplied between the substrate surface and the anode; Figure 29 illustrates the supply to Diagram of cathode current density versus time for another plated current between the substrate surface and the anode; Figure 30 illustrates cathode current density versus time for another plated current embodiment supplied between the substrate surface and the anode Figure 31 is a graph showing the cathode current density versus time for another embodiment of the plating current supplied between the surface of the substrate and the anode; and Figure 32 is a diagram showing the supply to the substrate. A graph of cathode current density vs. time for another plated current embodiment between a face and an anode. [Main component symbol description] 10 substrate holder 11 first holding member 1 la, 12a circular hole 12 second holding member 13 splicing mechanism 13-1 fishing 13-2 hook lock 14 T-shaped hanger 15, 16 clamp 15a , 16a groove 27 323761 201231738 17, 18 pin 19, 20 sealing ring 19a ' 20a ridge 21 substrate guide pin 22 conductive plate 23 conductive pin 25 wire slot 26 insulated covered wire 27, 28 terminal plate 27a, 27b | 27c, 28a, 28b, 28c Electrode terminal 29 0 ring 30 Wire holding 50 Plating equipment 51 Plating tank 52 Insoluble anode 53 Plating power supply 54 Plating liquid circulation pump 55 Thermostatic unit 56 Ferrule 57 Outer tank 58 Anode holder 59 Controller 60 adjustment plate 61a, 61b wire 62 agitating slurry 70 holder body 70a central hole 72 closing plate 74 circular support plate 74a channel 76 annular anode shield 78 conductive plate 80 isolating film 82 screw 90, 92 elastic conductive plate 94, 96 seal ring holder 97, 98 guide teeth 97a, 98a tapered surface 100 base 100a vertical perforation 102 barrier layer 104 seed layer 106, 106a plating film 108 recess 112 Degree dissolution zone 114 cat's eye cavity 28 323761 201231738
Al 、八2 、 A3鑛覆製程 Bx 逆向電解製程 Di 正值陰極電流密度 d2 負值陰極電流密度 d3 負值陰極電流密度 d4 正值陰極電流密度 L 水平面 Pl_P7 脈衝間距 Pe-PlO 關機間距 Q 鍍覆液 w 基板 29 323761Al, 八2, A3 ore-covering process Bx reverse electrolysis process Di positive value cathode current density d2 negative value cathode current density d3 negative value cathode current density d4 positive value cathode current density L horizontal plane Pl_P7 pulse spacing Pe-PlO shutdown spacing Q plating Liquid w substrate 29 323761