TWI374502B - Method of manufacturing semiconductor device to decrease defect number of plating film - Google Patents

Description

1374502 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of fabricating a semiconductor device. In particular, the present invention relates to a method of fabricating a semiconductor device which is used to reduce the number of defects of a wiring or via including a plating film. [Prior Art]

In modern semiconductor devices, device performance has been limited by the signal transmission delay of the wiring. The delay of the wiring is expressed as the product of the wiring resistance and the capacitance between the wirings. In order to reduce wiring resistance to promote device operation, since Cu has a small resistance coefficient, Cu is generally used for wiring materials. In addition, the wiring width is relatively narrowed because the cracking feature is miniaturized in response to the demand for high integration in recent years. Therefore, the defect of the wiring layer not only causes an increase in the wiring resistance but also causes a serious influence of the open circuit. For this kind of _, the shape is not lacking. _ High material requires the formation of a Cu multilayer interconnection from the AI 萄 珉 method. Included: a film formation process of an insulating film on a substrate (in the case of a wiring layer, a wiring trench, or in a liter i: Cu fm (Cu i , a etched electrode of the etched electrode _ set step; 1 chemical mechanical polishing of barrier metal and Cu outside the concave portion ((10) broadly forming step anode by = crystal on the substrate; in the method of electric ore, the cross-sectional shape of the household and the quality of the film depends on the method of the conductor device The electroplating step is roughly divided into: a step of filling a narrower than about ^1, 5,374,502 (hereinafter referred to as a filling step); and a step of filling the wiring and in the 丄 = film (hereinafter referred to as a region film forming step). Such as 曰 biased cattle two 幵:?! 2 1-2 1 208 No. 208 for surface flattening, the reverse: t: Li 2 ΐ ' film formation step is the regional step into the process. Note bias refers to the direction of the bias relative to the direction of the growth of the electric power. The sputum film, the current value of the step, usually make the # higher than the rail step of the electric country profit 第 6140241 and the US patent 63i983i -Bi No. Knife In addition, in order to improve the flatness of the electric ore film in the recess, the dream lies in: The bias is biased so that the promoter located in the recess is dispersed into the electric s ΐ ΐ 续 续 电 电 电 电 电 电 电 电 电 电 电 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( 四 四 四 四 四 四 四 四 四 四〇 04·270028 '*. In Japanese Patent Laid-Open Publication No. 11-2387Q3, a anatomical step or a zone film forming step is disclosed, in which a reverse bias and a (cJhing) i-soil surface removal inhibitor are applied a plurality of times Inhibition of humiliation or dishing, however, the prior art described in the above documents is improved for the following points, although by inserting a reverse bias as a flattening step, etc. There are still many defects in the film. The defects here refer to the holes and cracks in the soil of the 曰 quot 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The inventor wholeheartedly at the same time, the current distribution in the electro-needle area, the quantity, for example, the electric power after the chemical mechanical polishing step, is only disclosed in the Japanese Patent Laid-Open No. Japanese Patent Publication No. 3_268s ^ ^ 11-238703 ^ 2〇〇1.2172〇8 ^ and the method described in U.S. Patent No. 6319831_B1, there are still many defects after the chemical mechanical research step 6. The filling and the __ into steps: Good to ^ ρ ^ 旦性士' 1 Once in the chemical film after chemical mechanical grinding, there is still a lack of 'i domain ttt Lee public bulletin * __27 () () No. 28 ' although in the filling step The inter-intrusion-time reversal is 1', but there is a problem that there are many defects in the electroplated film after the chemical 'grinding'. In the step-by-step bulletin No. 11-238703, it is described in the regional film shape 'Sudden addendum-human reverse hemiplegia, but this reverse bias is exposed by removing the inhibitor to increase the fine wiring waste Ui# Membrane residence effectively inhibits rot 1 insect, but this also raises the problem of causing the chemical research 11-23870^ and dish. Further, in the Japanese Laid-Open Patent Publication, since the current polarity is reversed, the current distribution passes through the current value.

Sii it force, 'So it is impossible to promote carbon impurities and electricity mines as described below. Therefore, 'after chemical mechanical polishing, the number of defects in the electrodeposited film is generated according to (4) in the above case, and provides a distribution of the film flow in the region to produce an electrically wrought film having almost no defects. [Invention] The present invention provides A method of fabricating a semiconductor device, comprising: forming a seed layer on a substrate, the substrate having a first recess and a second recess, the width of the second recess being wider than the width of the first recess; a plating solution comprising an accelerator and an inhibitor, wherein the plating layer and the cathode perform a plating step to fill the recesses, wherein the step of performing electroplating further comprises: performing the first electric ore step to a first current density fills the recess of the first 1374502 by the electric ore; performing a first reverse biasing step, after the end of the filling of the first recess, at a second current density, the application is different from the first plating step Current of a polarity of the current; performing a second electroplating step to perform electroplating at a third current density that is the same as the polarity of the current used in the first electroplating step; a second reverse biasing step of applying a current at a fourth current density, the current having a phase, a polarity of the current used in the first reverse biasing step; and performing a second plating step to be the same as the first The fifth current density of the current polarity used in the electrowinning step is electroplated, wherein the difference between the second current density and the fourth current density is greater than the difference between the first current density and the second current density. In the method of fabricating a semiconductor device of the present invention, in the performing the second reverse bias step, the promoter in the plating solution is decomposed. In the method of manufacturing a semiconductor device of the present invention, the second key step The second current density in the first plating step may be greater than the first current density in the first plating step. Further, in the method of fabricating the semiconductor device of the present invention, the fourth current density of the second reverse bias step may be equal to the first The second current density of the reverse biasing step, and the application time of the second reverse biasing step may be equal to the application time of the first reverse biasing step. Further, the amount of integrated current of the second reverse biasing step The absolute value may be greater than the absolute value of the integrated current amount of the first reverse bias step. The present invention provides a method of fabricating a semiconductor device that is used to reduce chemical current polishing by controlling the current distribution of the film formation step. The number of defects of the plating film after that. [Embodiment] (First Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to Figs. 1 to 3. 8 1374502

1 is a view for explaining a method of manufacturing the semiconductor device of the present embodiment by manufacturing the semiconductor device of the present embodiment, having the following steps: (S101), a seed layer forming step (sl〇3), and a first-electrode step. Pressing step _7), second weir step (), second reversal (° and third electro-penetration step (S113); and including a series of two, two steps [) current distribution concept map for each electro-mine procedure Shown as shown in Figure 3. Further, the step of manufacturing the semiconductor device of the embodiment of the present invention will be described as a step of forming a wiring in the inner insulating film 206. In Fig. 2 +, although the single metal inlay engraving method is used for the miscellaneous order, the present embodiment can be applied to the dual-in-one 2〇0 including: the stone substrate 2〇2' in which the transistor is formed, etc.; An inner layer, a tantalum film 204, formed on the stone substrate 2〇2, and a second inner insulating film 206 formed on the insulating film 2〇4. The wiring and the dielectric layer f (vi , the insulating film 204 and the second inner insulating film 2 〇 6 are in the inner shield. First, the second inner insulating film 2 〇 6 formed on the substrate by the selective I insect, The recess is formed (FIG. 2A). Although the recess is, for example, a wiring trench, it may be not only a wiring trench but also a contact hole, a via hole, etc. As shown in FIG. 2A, the wiring trench 208, 210, 212, 214, 216, 218, and 22 lions are formed in the first inner insulating film 206. The wiring trenches 21, 212, 214, 216, and 218' are formed in a fine pattern to generate, for example, 〇_3 Wiring width below /xm. Wiring trenches 2〇8 and 220 are wider than the above-described wiring trenches formed in a fine pattern. For example, 5, in such a fine pattern and in a wider range than such fine patterns The procedure for forming a thin film on the wiring trench is as follows. In the present embodiment, the wiring metal is buried by electroplating. First, the barrier metal film is formed in the concave portion of the second inner insulating film 206 (not shown). Regarding the barrier metal film, we can use a Ta film shape, a stacked film on a TaN film, etc. A barrier metal film as a general copper wiring. Next, a seed layer for electroplating is formed on the barrier layer. Here, the seed layer may be made of, for example, a copper (Cu) film or the like. The film system is formed by a chemical vapor deposition (CVD, 9 1374502 chemical vapor deposition) method or the like. In addition to Cu, five p is used for the material selected from the group below to serve as a seed layer, which is packaged; 1. mg, Te, and Tc' are used as the main components. Further, although the shovel is formed into a barrier metal film and a layer of 曰a for ΐf is subsequently formed on the barrier film, this is sufficient _ metal as a seed crystal and directly here. When the barrier metal is used as a seed crystal in this way, 'we can use the same material of the two-layer Ru seed layer material as the barrier metal. By using the above seed layer as a cathode, and applying a bias voltage between the cathode and the cathode, and performing a step of filling the recess with copper, the cu is disposed in the electric button liquid. The electrode is used as a sun and the seed layer is made (4) as a cathode. The promotion and suppression are included in Further, in the present embodiment, the plating step includes the steps of filling the fine pattern wiring trenches 210, 212, 214, 216, and 218 having the specific lower portions with a low current, and filling the width with a current higher than the first plating step. The second and third steps of the wiring trench of the fine pattern wiring trench and the 22Q. The actual plating process performs the deposition from bottom to top. Here, the wire degree is obtained by flowing the current value from the anode into the cathode. The value obtained by dividing the area of the substrate. First, the f-plating step of filling the recess formed in the fine pattern at the first current density (filling step XS105) is performed. When the first electrode film is formed due to the filling of the fine pattern At 230 o'clock, the first electro-mine procedure is completed (Fig. 2B). Next, a first reverse biasing step is performed at a second current density. In the first reverse, pressing step, a motor having a polarity different from that used in the first plating step is applied. At the end of the first plating step, a first reverse biasing step is performed, i.e., between the filling step and the subsequent region film forming step. Specifically, the first reverse=bias step is inserted after the first plating step (S105) and before the second plating step (si〇9). An advantageous plating film planarization effect is obtained by inserting a first reverse bias step between the first and second plating steps. Next, a second plating step (region film forming step) for forming a ruthenium film (sl 〇 9) is performed at a third current density greater than the first current density. In the second electroplating step, 1374502, film formation is performed in the same manner as the current of the current polarity used in the first electroplating step and the current density greater than the first electric, density. We can shorten the plating time by using a second current density greater than the first current density. Next, at a fourth current density, a second reverse bias step of applying a current having the same polarity as that used in the first reverse bias step is performed. In the second reverse, the pressing step (Sill) applies a current having a polarity different from that of the first-second step. That is, as shown in Fig. 3, between the first and third plating steps in which the thin films are formed by the third and fifth currents, respectively, a biasing step of inverting the current direction is inserted. Further, the fourth current density may be different from or different from the second current density. In the present embodiment, the fourth current density is equal to the second current density. Further, the difference between the third current density and the fourth current density in the present example is larger than the difference between the first current density and the second current density. Although the timing of performing the second reverse bias step is not limited, only the middle of the film formation step performed by the current in the filling step is preferably grown in the plating thickness to a desired plating thickness. The thin 10 to 200 nm drought time point then 'the second reverse bias step is performed. After that, the current direction is reversed again without going through the unbiased step, and the third plating step (SU3) is performed at the flow density. The step used in the third electroplating step: ==牛^2_private five_execution of the actual electro-mine procedure (S109) electric step ffG5), the first-reverse biasing step (drain), the second electroplating Step j_the factory reverse bias step (sill), and the third plating step (SU3). The intermediate 'reverse biasing step' is performed between the first and second electroforming steps to form a bovine plating step, that is, in the area membrane 2: the substrate produced by the conventional method is after chemical mechanical polishing Still, the method of forming is to insert a reverse bias only between the filling step of the fine pattern and the area-to-area. S, this will reduce the reliability of the device. Further, the present invention was created by finding the value of the current 11 1374502 in the film formation step of the control region to reduce the number of defects of the plating film after the chemical mechanical polishing. Therefore, the second reverse bias step is inserted halfway through the area film forming step. • Here, by applying a reverse current in the middle of the area film forming step, the accelerating agent contained in the plating liquid is formed, and the film forming step in this region forms a film with a current higher than the fine pattern filling step. Further, in the present embodiment, the difference between the third current density and the fourth current density is greater than the difference between the first current density and the second current density. Therefore, the accelerator is substantially decomposed. Further, after the reverse biasing step, the current value is reversed again to flow the forward current, so that the accelerator decomposed in the reverse biasing step is combined with the plating film as a carbon impurity. In the present embodiment, the defects after the chemical mechanical polishing step are lowered by the defect suppressing effect of the combination of the carbon impurities and the plating film. Here, the defect refers to a pit, a crack, or the like of a key film (wiring or via window) generated by a chemical mechanical polishing step. Similarly, when the reverse bias step is inserted in the middle of the first plating step (i.e., the fine pattern filling step), the impurities are combined with the plating film. However, since the width of the filled wiring is small, the influence of the impurities on the film becomes too large. Therefore, there is a problem that the wiring resistance is increased. In addition, since the inhibitor present on the surface of the electrodeposite film is removed, the film quality becomes less detailed and the number of defects is increased. On the other hand, in the case of the area film forming step, the wiring width is wide, and since the impurities are moderately bonded, the effect of reducing the number of defects of the electric φ ore can be obtained after the chemical mechanical polishing. Therefore, in the present embodiment, the reverse bias step is not inserted in the middle of the plating step of filling the fine pattern with the first current density. - ★ Again, it is preferred to reverse the direction of the current without going through the unbiased step. Preferred system,

The second reverse bias step is inserted between the second and third plating steps without a stable unbiased step. The steady state unbiased step in this specification means that the unbiased &amplified state lasts for a predetermined period of time. Therefore, when the current polarity is reversed, the transient unbiased state of the unbiased state at which the distribution is instantaneous is not included. That is, when the same current polarity is changed from the third current density to the fourth current density, the polarity is reversed once at a point where the steady flow value does not exist. Therefore, the accelerator is substantially dissolved. Similarly, when changing from the fourth current density to the fifth current density, at the point when the current value of the steady J 12 1374502 is not present, the bias step case T is determined by the reverse bias step ===. If you do not pass the object, it will immediately be combined with electricity. In addition, the rate of decomposition of the decomposition/promoter will be large. The step of the value of the capture value is zero. The operation will also become longer, and Lang will be able to shoot the patent publication No. 11_238703 at a time. Current distribution

If the flow value is stable to zero, the unpowered state cannot be promoted as described by < Impure and read_, so the number of defects in the plating film will still increase after chemical mechanical polishing. However, there is a special restriction on the first - current density, but the current density, but

== positive ^ into the negative direction of the positive direction, the substrate current is in the degree f 0.1 A / dm to 2 A / dm ' and better, it is 02 ship "to J dm. Here" current The density is a value obtained by accumulating the current flowing from the anode to the cathode. To: Although the time of the first key step is not particularly limited, it is 2 sec., and the second and third electroplating steps are respectively used. The third and fifth current capacitances are greater than the first current density. Preferably, the third and fifth current densities are from 3 A/dm to 6A7dm2' and more preferably '4A/dm2 to 5A/dm2. And the third and fifth current densities used in the second electro-penetration step may be the same or may be different. In the present embodiment, the third and fifth current densities are equal. Further, although there is no particular limitation on the second The time of the electroplating step, but it is from 1 second to 100 seconds. Although the time of the third electroplating step is not particularly limited, it is from αι seconds to 10 seconds. In the present embodiment, the first reverse bias step is used. The second current density is substantially the same as the fourth current used in the second reverse bias step The degrees are equal. With respect to the second and fourth current densities, in the case where the direction from the anode to the cathode is positive, the current density of the base 13 1374502 plate is preferably -4 A/dm2 to -i A/dm2, and A / dm2 to -1.5 A / dm2. And better, it is, 2.5 In addition, although the first reverse bias is not particularly limited (U seconds to 5 seconds. Better, this application time is jade 'But, secondly, when the biasing surface is executed within the above range, the sword is forced to perform the reverse bias step for the purpose of removing the inhibitor, while maintaining the advantageous effect of, for example, flattening: paying for suppression In the reverse bias step, when the plating film biasing step exhibits a high current density and a long time becomes longer, the productivity is lowered. For the flow density, the time is set in the accelerator. In the electric chain liquid "and r 2 above the outline towel, the electric money and the storage current value H plate area and the sound r value. In addition 'may include applying a fixed voltage U before the first plating step. The voltage here can be Voltage between the cathode and the anode, or between the electrode and the cathode Setting the step of performing the entry into the bath, i, can be a current density in the range of 1 to 6 A/dm2. The defects of the Cu plating film after chemical mechanical polishing are generally classified into: due to poor plating filling. Defects; and defects formed in subsequent heat treatment steps and chemical mechanical processes, which may cause defects in the subsequent steps due to the quality of the film, the stress of the electrical insulation, the type of mechanical polishing liquid, and the like. On the one hand, it is known that carbon impurities in the Cu film suppress the formation of vacancies under stress. The defects formed in the latter step are inhibited by the formation of vacancies, although the formation of vacancies is affected by impurities. The mechanism of inhibition is not solved but it can be understood as follows. That is, when heat treatment is applied after electroplating, Cu thermally expands, but because it does not completely rebound, the body of the Cu film after the heat treatment is 1374502, the crucible becomes smaller than the volume before the heat treatment, and therefore, internal stress is generated. The carbon impurities will stabilize the grain boundaries due to deposition on the grain boundaries and limit the occurrence of the (10) stress. The formation of vacancies = although this may become lower due to high impurity purity. Stress is caused by the formation, but this is considered to be an advantageous effect of mitigating the influence of stress. Similarly, when the reverse bias step is inserted midway through the first electro-mine procedure (i.e., filling = step), impurities are combined with the electrodeposited film. However, the effect of the impurities on the film becomes too large due to the filling degree ’ί. Therefore, the problem is increased. In addition, since it is present on the surface of the money film, the film quality becomes less detailed and the number of defects is increased. On the other hand, in the case of the film formation step, the wiring width = because the impurity is moderately combined, so After chemical mechanical polishing, we can pay for the reduction in the number of defects in the electrode film. Therefore, in the present embodiment, the electroplating step of inserting the fine pattern with the first current density is applied to the bias step, and in the embodiment, the electric clock liquid can be manufactured to contain the inhibitor and the timing. The materials used to form the plating film are the same. This embodiment is, for example, sulfuric acid, steel, or gas. In addition, the plating solution may also have other additives, such as a separate agent. Inhibitors inhibit the growth of electroplating, and = such as: inhibition - two = polypropylene glycoUf 〇 ^ 5 The beneficial effect of the growth of the electric ore. Although it is specific to the embodiment, it can be exemplified, for example, that an organic acid salt is used, for example, when the current density is completed, the third-valve conductive material is passed through the recess of the fine needle to fill the straight beam. The determination of whether to end the filling may be made based on the elapsed time. For the second example, the step of filling the fine pattern can be filled to a region of about 2 () to 2 (8) seconds to 100 seconds. These processing times are exemplary and can be appropriately set to obtain a desired film thickness. 1Tan also grinds the tempering process and exposes the wiring trench by chemical mechanical polishing. The number of defects after the yak is flattened in this embodiment can be lowered. Then, by seizing film formation, recess formation, and metal film formation, we can make an example of this, and various other modifications besides the above are explained in the above method. The rm two of the bias processing: two, five inserts more than three times of reverse bias processing to replace twice. Second, after the end of the first plating step or after the insertion of the reverse bias, it is not inserted in the middle of the fine pattern filling step, and (example 1) * Lei ^ two households ^ 7! current distribution (this is Called current distribution c), Cu plating is performed. Ϊ́ί 2 Continuously perform the following steps: H forging step, with the first electric current = two r =: i = i & ^ 'The first current density (6) is set in the range of 0.2 A/dm2 to 1 AAW. The direction of the current from the anode to the cathode is defined. The current density (in terms of ω, it is set between 13745〇2 for l and Λ, dry circumference. In addition, the first reverse bias At the time of the step, the third is two. In addition, the direction is positive from the 1^ pole to the cathode, and it is set in the range of 4 to 5. This a) The time is from 10 seconds to 100 seconds. In addition, the second current density or the like is set to be performed, and the application_ is also set to phase and flute-ΐ, the second motor twist (13) and the fifth current density (15) are set equal, and the second The plating step takes from 0.1 second to 1 second.

= Estimate the number of defects in the film after plating to make the defect evaluation equipment = lack of P with (4) Lai, this equipment is electronically analyzed with a snail mirror and identifies pattern defects. 1 gauge (Comparative Example 1-1), with the current distribution shown in Fig. 5 (this is called current distribution A), Cu plating was performed. = current distribution A, a first plating step (S1〇|5) using a first current density (Ι1) and a second plating step (S10) using a third current density (13) are continuously performed. As the example 1 'the first current density (6) is the same as the third current density (13). The evaluation of the number of defects is performed by the same method as in the example 1. (Comparative Example 1-2) Cu plating was performed with the current distribution shown in Fig. 6 (this is called current distribution B). With the current distribution B, the first plating step (S105) using the first current density (I1), the first reverse bias step (S101) using the second current density (?2), and the use are continuously performed. The second current demand (the second electro-penetration step of D (S1 〇 9). As in Example 1, the first current density (I丨), the second current density (y, and the third current density (?3) are the same Value. μ The evaluation of the number of defects was performed by the same method as in Example 1. The defect number evaluation in Example 1, Comparative Example 1-1, and Comparative Example 1-2 is shown in Fig. 7. By way of example The number of defects of the current distribution C of 1 is standardized as a standard' and shows the number of defects of the current distribution Α to C of Fig. 7. Fig. 7 shows that the number of defects of the current distribution C is greatly reduced, and this current distribution includes the film formation step in the region The second reverse bias step in the middle. (Second Embodiment) 〃 17 1374502 A flowchart showing a method of manufacturing the semiconductor device of the present embodiment and a step sectional view showing a step of producing the semiconductor device are the same as those of the first embodiment. However, its difference from the first embodiment is The absolute value of the integrated current amount of the second reverse bias step is greater than the absolute value of the integrated current amount of the first reverse bias step. Therefore, after the chemical mechanical polishing step, the number of defects of the plating film is further reduced. The following 'this embodiment' will be described with respect to features different from the first embodiment.

Fig. 8 is a conceptual diagram showing the current distribution of the plating step of the present embodiment. The first plating step, the second plating step, and the third plating step are set to the same conditions as in the first embodiment. These preferred ranges are the same as in the first embodiment. In the present embodiment, the absolute value of the integrated current amount of the second reverse bias step is set to be larger than the absolute value of the integrated current amount of the first reverse bias step. For the current density used in the first reverse bias step, the current density of the substrate is preferably _4 A/dm2 to 4 A/dm2' and more preferably in the case where the direction from the anode to the cathode is positive. , which is up to 5 A/dm2. Further, although the time of the first reverse bias step is not particularly limited, it is preferably 0.1 second to 5 seconds. More preferably, the application time is from leap seconds to 3 seconds. When the current density and time used in the first reverse bias step are in the above-mentioned range: we can obtain a sufficient planarization effect. In addition, we can suppress the hole and the middle becomes too high. When the concentration of the holes becomes too high, since a brain that cannot escape toward the surface is generated, and a mesh is formed at the edge of the substrate, the reading is corrected. 'J7. ', the reverse bias step makes (4) the current density, the positive current density of the substrate is preferably _4 A/dm2 to .A/dm, and more preferably, in the case where the direction from the anode to the 3 ί is positive. For · to ^ to ^ 5A / dm2. However, there is no second-counter second. Better, this application time is from leap seconds to 3ίΓ. When the second reverse bias step is performed in the right circle, the amount of defects after the chemical mechanical polishing can be removed due to the accelerator. In addition, in order to perform the reverse step for the purpose of the 她· 的, she is 18 l3745 〇 2 = public, 11-238703 f tiger, when the second reverse bias step is performed within the above range while maintaining becomes possible: suppression of electricity The defect of the value and the absolute value of the value of the current: by setting (in the integrated current of the second reverse bias step) / (= - the amount of integrated current in the reverse bias step) > i, increasing the defect reduction effect . The integrated current amount A1 of the fish reverse biasing step (hereinafter referred to as A1) The integrated current amount A2 of the reverse biasing step (hereinafter referred to as Μ is eight-step < 丄 的 carbon impurity concentration C2 (hereinafter referred to as C2) It becomes a carbon impurity concentration α (hereinafter referred to as C1) which is larger than the substrate (C2/C1 2: = silk of the nucleus of the vertical boundary). In the case of 2^<!, C2/ can be maintained. C1> i. Therefore, the film surface 曰曰 = , the effect of the female 疋 会 will be greater than the effect close to the substrate. This is more important: reduce the stability of the surface side of the missing substrate 'the grain boundary here is easy to become In the case of uneasiness Α 2 / Α 1 < Λ, the substrate side is more stable, and the hole on the surface side. 3 Ϊ will ^ ° hole will spread toward the inside and tend to be on the substrate side such as HA2 / A1 > In the case of 'the hole is diffused to the side, the vacancy group cannot be easily formed. For the above reasons, the β-measurement is reduced by setting Α2/Α1> 1. The defect reduction effect is shown by =9, when Α2/Α1 When the ratio becomes higher, the number of defects will decrease. =: The effect is saturated. This is the absolute value of Α2. Should be greater than the absolute value of A1 and the inside = is specifically limited 'But in order to more effectively reduce the effect of the defect, A2 is preferably less than 2 V times of the system, and 2.4 times or less of the 5 best system A1. By setting such A2 /Ai, rate 'We can prevent the quality of the right because the impurities are excessively increased in the electricity levy and the number of deniers: m, the reproducibility of the defects caused by the defects'. We can judge that when the defects are low, the force is 20/〇, it is Therefore, Α2 is preferably U times more than αι 1374502, and more preferably 7 times or more of A1. I understand that ♦ by (4)° = f(2) The absolute value of A2 can be made larger. The s, the use, or both of them are better because the ratio of the A2 ratio A1 is increased by decreasing the absolute value for not losing the planarization effect.大日士^&The best system is to change the absolute value of A2 by making the high current

=2) Under the circumstances, the hunting is performed by a long time (4) to make the integrated current amount Α ==== direction; the r time is set at the minimum of the accelerator at ί, and by using a higher current to make Α2 - In this case, in the second reverse bias step, the current value may not be 岐, and as shown in FIG. 10: a plurality of f-mixes may be changed and used. Furthermore, in the second reverse bias two: multiple reverse bias. However, since the film formation time becomes long due to the smart reverse bias, it is preferable to perform a reverse bias in the second reverse bias step. Furthermore, in the embodiment of m, it is preferable to reverse the current direction without going through the unbiased step in the reverse bias step of this embodiment. This reason has been explained. y In the above description, the current density refers to a value obtained by dividing the anode current value by the substrate area. Additionally, a step of applying a fixed voltage prior to the first plating step to perform the entry into the bath may be included. The voltage here may be between the cathode and the anode or may be the voltage between the reference electrode and the cathode in the plating bath. We can set the voltage to perform the step of entering the bath to a current density in the range of UA/dm2 to 6A/dm2. Also in this embodiment, the plating solution can be manufactured with the inhibitor and accelerator and in general The material used to form the plating film is the same when the copper wiring is formed. The plating solution of the present embodiment may further contain, for example, sulfuric acid, copper, or gas. In addition, the battery liquid may also contain other additives such as a homogenizer. The agent suppresses the growth of electroplating and has an advantageous effect. Although (4) the present embodiment uses a finely-organized alcohol (4) and a system, the accelerator has an advantageous promoter for promoting electroplating growth. There is no particular limitation, and the specific sulfonate of the present embodiment can be used. For example, an organic sulfonate is listed, for example, when the second plating film 232 is formed and

In the case of a sudden period of time, after a series of times of the second and second 222 steps of the electric ore, the time of the second time may be based on the elapsed time. For example, the step of filling the fine pattern may be performed. It takes about 10 to 100 seconds. These processing times are broken and the thickness of the film is _ film thickness. At the end of the Wei step reading, the fine fire treatment, and the field from the chemical mechanical research U to remove the electricity line flattening, so that the wiring trench is exposed. In the semiconductor device of the present embodiment, the amount of bribes after flattening is low. Then, by repeating the formation of the inner insulating film, the formation of the concave portion, and the formation of the metal film in two steps, a multilayer wiring structure can be obtained. The above description is an example of the embodiment, and various modifications other than the above are possible. '" Capricorn column (Example 2-1) Cu plating was performed with the current distribution shown in Fig. 8. In the current distribution of the present example, the following steps are continuously performed: a first plating step of filling the fine pattern with the first current density (6); a first reverse biasing step of the second current density (i2) after the end of the fine pattern filling Applying a current; a second plating step using a third current density (i3); a second reverse biasing step applying a current at a second current density (i2); and a third plating step 'using a third current density (i3) . 21 !3745〇2 Lai Wei R± Ρ问/>, Ά έ έ 。. Further, the time (6) of the 'first electric clock step' is 20 seconds to 200 seconds. The second current density (i2) is set to be 2 s from the anode flow mode, and is positive to 5 squares. Also two === and . Further, the fourth current density (i4) is set within _2 5 and the application time 〇 4) is from i seconds to 3 seconds. · ^ = current density (6) is set equal, third power 44; = reverse ίί = product, first - evaluate the number of defects in the plating film after plating. Using the evaluation of the number of defects = the number of defects in the line, the device uses an optical microscope to "see the flaws and identify pattern defects. The evaluation of the number of defects is shown in the biasing step." The absolute value of the integrated current is greater than the flattening step) The ratio of the absolute value of the integrated current amount. The number of defects is normalized by the number of defects when the defect reduction step is equal to the squared integrated current amount, and is represented by 0 (Example 2-2). In this embodiment, In addition to the ratio of the integrated electric current of the second reverse biasing step to the integrated current amount (i2 X t2) of the first reverse biasing step, the Cu electric ore is performed in the example 2]. The evaluation is shown in Fig. 9. (Comparative example) In this comparative example, in addition to the second reverse bias step, the integral of the 穑-than-reverse step is _(12 X t is 丨 = = 22 Perform Cu plating in Example 2-1. The evaluation of the number of traps is shown in Figure 9. Anti-Heart - Low defect number. When the ratio of (t2) is greater than 1, it will be further reduced [Simplified illustration] 1 series shows the flow chart of the electric ore program that is not the first to make up; Figure 3 is a schematic diagram showing the current distribution of the first embodiment; Figure 4 is a schematic diagram showing the current distribution c of the plating step of the example ;; Figure 5 is a comparison showing A schematic diagram of the current distribution a of the electroplating step of the example; FIG. 6 is a schematic diagram showing the current distribution b of the electroplating step of the comparative example 丨_2; and FIG. 7 is a graph showing the number of defects of the current distributions A to C in the example 1-1. Figure 8 is a schematic diagram showing the current distribution of the second embodiment; Figure 9 is a graph showing the relationship between the absolute value ratio of the integrated current amount of the reverse bias step and the number of defects; and the figure shows the first implementation Schematic diagram of the current distribution of the modified example. [Main element symbol description] S101 concave portion forming step S103 seed layer forming step S105 first electric boat step S107 first reverse bias step S109 second plating step sill second reversal Biasing step S113 third plating step 200 semiconductor device 23 1374502 202 矽 substrate 204 first inner insulating film... 206 second inner insulating film. 208 wiring trench 210 wiring trench 212 A wiring groove 214 groove 216 groove wiring a wiring groove 1218: 220 _ 230 a first wiring groove 232 of the second plating film plating film

Claims (1)

1374502 August 16th, 2011 Revision replacement page 97117436 (without line) 卞 Patent Application Range: 1. A method of fabricating a semiconductor device comprising: forming a seed layer on a substrate having a first recess and a first recess and a width of the first recess Width is wider than the width of the first recess; and an electric forging solution comprising an accelerator and an inhibitor is used, and the plating layer is used as a cathode to perform a plating step to fill the recesses, wherein the plating is performed The step further comprises: - a concave row - a - first step, filling the first execution-first reverse biasing step by electroplating with a current density, after the end of the filling of the first recess, using a second current The density 'applied with a current different from the polarity of the first electric current; % performs a second electroplating step, electroplating with a third current density similar to the electric current used in the first electroplating step Performing a second reverse bias step of applying a current at a fourth current density, the polarity of the current used in the first reverse step, and a second plating step to Same as the first Electroplating is performed at a fifth current density of the electrode used in the electroplating step, so that the difference between the third current density and the fourth current density is greater than the difference between the degree and the second current density, The first electro-pneumatic step 5 does not provide an unbiased period between the electrical steps, and no unbiased period is provided between the second electroplating step and the second electromotive step. 2. If _ please patent scope! A method of manufacturing a semiconductor device, wherein in the first reverse biasing step, the promoter of the plating solution t is decomposed. People 3. If you apply for the patent scope! The method of manufacturing a conductor device, wherein the third current density in the clock 2 is greater than the first current density in the first step. 25 1374502 2: (6 innocent two replacement page 4. If applying for refining the third method of manufacturing a semiconductor device, step; = fourth current; degree is equal to the first-reverse; bias # is the first The application time of the reverse bias step. ', equal 5. The method of manufacturing a semiconductor device according to claim 3, wherein the third current density in the bean forging is equal to the current of the third Wei step The method of manufacturing a semiconductor device according to claim 3, wherein the fourth current density in the second reverse bias step is _4 A/dm 2 to _1 A/dm 2 , the anode A current direction to the cathode is defined as a positive direction. A method of fabricating a semiconductor device according to claim 3, wherein the second reverse bias step and the second plating step Between the second reverse biasing step and the third plating step, the polarity of the current is reversed without a steady state unbiased step. 8. As claimed in claim 3 A method of fabricating a semiconductor device, wherein a plating thickness is greater than a desired thickness When 1 〇 to 2 〇〇 mn, the second plating step is ended, and then the second reverse bias step is performed, and in the second reverse bias step, the fourth current density is -4 A/dm 2 To -1 A/dm2 and applying a current for 0.1 second to 5 seconds, wherein a current direction from the anode to the cathode is defined as a positive direction. 9. Manufacturing of a semiconductor device according to claim 3 The method, wherein the promoter comprises an organic hydrogenate. 10. The method of fabricating a semiconductor device according to claim 3, wherein the second 26 1^74502 97117436 (without a scribe line) reverse biasing step integration current The absolute value of the quantity is greater than the absolute value of the integrated current amount of the first reverse bias - I. The method of manufacturing a semiconductor device according to the '10th aspect of the patent, wherein the second bias step The absolute value of the fourth current density is greater than the absolute value of the second current density of the first reverse bias step. The method of manufacturing a semiconductor device according to the ig patent scope ig, * the second bias The absolute value of the fourth current density of the pressure f is greater than the first The absolute value of the second current density to the bias voltage and the sigma time of the second reverse bias step are longer than the application time of the first reverse bias step. The method of the device, wherein the absolute value of the integrated current amount of the second biasing step is u to 3 times the absolute value of the integrated current amount of the first reverse biasing step. 申!f patent range $1G A method of fabricating a semiconductor device, wherein the fourth current density in the second pressing step is -4 A/dm 2 to -1 A/dm 2 , and wherein a direction of current flow from the anode to the cathode is defined as a Positive direction. The third semiconductor current density in the second electroplating step is equivalent to the fifth electric wire density of the third electrowinning step. 16. Shen Qili's scope is second. The method of fabricating a semiconductor device, wherein between the second bias step and the second plating step, and between the second reverse bias and the third plating step, without an unbiased Reverse the polarity of the current. 27 ΟΙ . 8 8 8 8 ; ; ; ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 97 97 97 97 97 97 97 97 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ When the 2G is fine 1, the second key step is ended, and the second reverse bias step is performed, and in the second reverse dusting step, the = stream density is 4 AAW to the woven fabric. The current is applied for 〇] seconds to 5 seconds, and the direction of the flow from the anode to the cathode is defined as the - positive direction. = with m (four) ω (four) boat _, (four) promote Η * First, the pattern: