JP2009296014A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To raise electromigration resistance of wiring. <P>SOLUTION: When Al wiring 40 is formed, a first Al film is formed under a first condition so that Al particles 40a may have a first average particle diameter on a barrier metal 41. Then, a second Al film is formed under a second condition so that the Al particles 40a may have a second average particle diameter smaller than the first average particle diameter. After that, a barrier metal 42 is formed on the second Al film, and after the formation, the barrier metals 41, 42 and the first and the second Al films are processed into a wiring pattern. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a process for producing a semiconductor device having a metallic wire.

  With the high integration of silicon (Si) semiconductor devices and the reduction in chip size, miniaturization of wirings formed therein and multilayer wiring are also progressing. For example, in a 65 nm node device, the minimum wiring width is about 100 nm. When a current is passed through such a fine wiring, electromigration may occur in which the metal atoms of the wiring move. Electromigration causes voids and hillocks in the wiring, which cause an increase in resistance, disconnection, short circuit, and the like of the wiring, thereby reducing the reliability of the circuit.

  By the way, in the advanced Si semiconductor device, Cu wiring formed by using a so-called damascene method is generally used for the wiring. In the damascene method, for example, after a groove is first formed in an insulating film using lithography and etching techniques, a barrier metal and a seed Cu film are formed on the entire surface using a sputtering method, and an electrolytic plating method is formed thereon. A Cu wiring is formed by forming a Cu film, filling the trench, and removing excess Cu film and barrier metal on the insulating film by CMP (Chemical Mechanical Polishing). Further, a cap film such as silicon nitride (SiN) is formed on the surface of the Cu wiring using a CVD (Chemical Vapor Deposition) method or the like for the purpose of suppressing the diffusion of Cu atoms in the Cu wiring, as in the case of the barrier metal. (For example, refer to Patent Document 1).

  In the Cu wiring formed in this way, the periphery thereof is covered with the barrier metal and the cap film, but the adhesion force at the interface with the cap film is weaker than the interface with the barrier metal. This is because the interface between the Cu wiring and the barrier metal is formed by bonding between metals, whereas the interface between the Cu wiring and the cap film is formed by bonding between the insulating film and the metal. It is considered that the diffusion of Cu atoms in the Cu wiring is likely to occur from the interface with the cap film having weak adhesion, and in fact, there is a high probability that voids are scattered at this interface.

  As a method for increasing the electromigration resistance, for example, when forming a cap film, a predetermined pretreatment is performed prior to the film formation, and then the film is formed to improve the interface between the cap film and the Cu wiring. A method for improving the quality is proposed (for example, see Non-Patent Document 1). As another method for increasing electromigration resistance, a method using a metal such as cobalt tungsten phosphorus (CoWP) for the cap film has also been proposed (see Non-Patent Document 2, for example).

JP 2005-317835 A

Reliability Physics Symposium Proceedings, IEEE, April 2004, p. 246 Journal of Applied Physics, January 2003, Vol. 93, No. 3, p. 1417-1421

  In the future, as the generation progresses, the wiring width will become thinner, and at the 45 nm node, the minimum wiring width will be about 70 nm. In such a situation, in addition to considering the material of the cap film, there is a possibility that electromigration cannot be sufficiently suppressed only by using the above-described method of modifying the interface between the cap film and the Cu wiring. For example, when SiN is used for the cap film, the adhesion with the Cu wiring is stronger than when silicon carbide (SiC) or silicon carbonitride (SiCN) is used. However, SiN has a higher dielectric constant than SiC and SiCN, and the use of SiN for the cap film hinders the speeding up of the Cu wiring.

  In addition, when a metal cap film is used as described above, a strong adhesion with the Cu wiring can be obtained, and diffusion of Cu atoms can be suppressed. Such a metal cap film needs to be selectively formed on the wiring, but it is not possible to selectively form the metal cap film on the narrow pitch wiring as in the next generation semiconductor device. The current situation is that it is not always easy, and problems remain in terms of mass productivity.

  By the way, electromigration can occur in aluminum (Al) wiring in addition to the above Cu wiring. In a general Al wiring, electron transport is dominant in the vicinity of the interface with the barrier metal, and therefore electromigration is likely to occur in such a region.

According to one aspect of the present invention, in a method of manufacturing a semiconductor device including an Al wiring, a step of forming a first barrier metal on a first insulating film, and Al particles on the first barrier metal A first Al film is formed under a first condition so as to have a first average particle diameter, and then under a second condition so as to have a second average particle diameter smaller than the first average particle diameter. A step of forming a second Al film; a step of forming a second barrier metal on the second Al film; and the first and second barrier metals and the first and second Al films. A method for manufacturing a semiconductor device is provided, which includes a step of processing into a wiring pattern and a step of covering the wiring pattern with a second insulating film .

According to the disclosed method for manufacturing a semiconductor device, the Al wiring is more likely to flow in the center than in the upper part, so that electromigration from the upper part can be suppressed. Therefore, a semiconductor device provided with highly reliable Al wiring can be realized. In addition, since the Al wiring having such a configuration can be stably formed without complicating the process, it becomes possible to stably mass-produce a semiconductor device including a highly reliable Al wiring. .

It is a figure which shows the relationship between the wiring width of Cu wiring, and a resistivity. It is explanatory drawing of the particle size distribution in Cu wiring. It is a principal part cross-section schematic diagram which shows the structural example of Cu wiring. It is a principal part cross-sectional schematic diagram after a CMP process. It is a principal part cross-sectional schematic diagram of an ion implantation process. It is a principal part cross-sectional schematic diagram of a 1st electrolytic plating process. It is a principal part cross-sectional schematic diagram of a heat processing process. It is a principal part cross-sectional schematic diagram of a 2nd electrolytic plating process. It is a principal part cross-sectional schematic diagram which shows the structural example of Al wiring. It is a principal part cross-sectional schematic diagram of the formation process of an interlayer insulation film and a hard mask. It is a principal part cross-sectional schematic diagram of a groove | channel formation process. It is a principal part cross-sectional schematic diagram of formation processes, such as a barrier metal. It is a principal part cross-sectional schematic diagram of an electroplating process. It is a principal part cross-sectional schematic diagram of a 1st CMP process. It is a principal part cross-sectional schematic diagram of formation processes, such as a 1st cap film. It is a principal part cross-sectional schematic diagram of the formation process of a via hole and a groove | channel. It is a principal part cross-sectional schematic diagram after an electroplating process. It is a principal part cross-sectional schematic diagram of a 2nd CMP process. It is a principal part cross-sectional schematic diagram of formation processes, such as a 2nd cap film.

First, the configuration and characteristics of the Cu wiring will be described.
First, Cu wires having various shapes were formed and the resistance thereof was measured accurately, and further, the wiring width and wiring height of those Cu wires were measured precisely to calculate the resistivity. Further, the grain size (grain size) of the Cu particles constituting the Cu wiring was changed by changing the Cu film formation conditions, the wiring width of the Cu wiring, and the wiring height at the time of forming the Cu wiring. The particle size was measured using a TEM (Transmission Electron Microscope) or an EBSP (Electron Back Scattering Pattern) method.

  FIG. 1 is a diagram showing the relationship between the wiring width and resistivity of a Cu wiring. In FIG. 1, the horizontal axis represents the wiring width (nm), and the vertical axis represents the resistivity (μΩ · cm). FIG. 1 also shows fitting curves A, B, and C obtained by fitting using a model to be described later.

  From FIG. 1, it was found that the resistivity of the Cu wiring does not depend on the particle size of the Cu particles constituting the Cu wiring, but the wiring width starts to increase from several hundred nm, and the increase becomes remarkable when it becomes 100 nm or less. . Here, the average particle size is changed to roughly three types (average particle size of about 213 nm, 230 nm, and 256 nm (however, the average particle size at a wiring width of 1 μm)), but even if the wiring width is the same, It was found that the smaller the particle size, the higher the resistivity.

  In order to analyze this result, the particle size dependence of the resistivity was measured using the surface scattering model of thin films (FS Model; EH Sondheimer, “The Mean Free Path of Electron in Metals”, Adv. Phys. (1952)) and crystals. Model that incorporates grain boundary scattering (MS Model; AF Mayadas, "Electrical-Resistivity Model for Polycrystalline Films: the Case of Arbitrary Reflection at External Surfaces", Phys. Rev. B (1970), Vol.1, p. 1382) was used for the fitting. Among the parameters necessary for these fittings, the actual particle diameter measured for the formed Cu wiring was used. FIG. 1 also illustrates these fitting curves A, B, and C.

  When the wiring width of the Cu wiring is 100 nm or less, the ratio of the peripheral interface increases with respect to the cross-sectional area, and the electron scattering contribution increases, so that the resistivity increases. On the other hand, the resistivity increases as the particle size decreases, but it has been found that the change in resistivity is almost explained by taking this into account. That is, it was found that the resistivity depends on the particle size because the electron scattering effect at the grain boundary works greatly in addition to the reflection of electrons at the interface in the fine wiring of 100 nm or less. Such a phenomenon becomes prominent when the particle size is reduced to around 40 nm, which is a free electron scattering process.

Based on this result, for example, when there is a particle size distribution in the fine wiring, electricity tends to flow through a region having a low resistance, so that it flows selectively in a region having a relatively large particle size.
FIG. 2 is an explanatory diagram of the particle size distribution in the Cu wiring.

When the Cu wiring 1 is formed by the damascene method, first, a hard mask 3 such as SiN is formed on the interlayer insulating film 2 such as silicon oxide (SiO ₂ ), and a groove is formed in a region where the Cu wiring 1 is to be formed. Form. Thereafter, a sputtering method is used to form a barrier metal 4 using a refractory metal such as tantalum (Ta), titanium (Ti), or tantalum nitride (TaN) over the entire surface, and a seed Cu film (not shown). ) And a Cu film is formed thereon by electrolytic plating to fill the groove. Then, the Cu wiring 1 is formed by removing excess Cu film, barrier metal 4 and the like on the hard mask 3 by CMP. A cap film 5 such as SiC or SiN is formed thereon using a CVD method or the like, and an upper interlayer insulating film 6 such as SiO ₂ is further formed thereon.

  In such a method, usually, the current density is lowered at the initial stage of electrolytic plating to slow down the formation rate of the Cu film. This is to ensure that the lower and lower side wall portions are reliably buried regardless of the wiring width of the Cu wiring 1, and so that the seed Cu film is not dissolved by a sudden current change at the start of plating. It is to do. Thus, at the initial stage of electroplating with a low current density and a slow Cu film formation rate, more impurities are taken into the formed Cu film. As a result, the subsequent heat treatment generates a large number of Cu particles 1a with the large number of impurities as nuclei. In other words, the large number of impurities inhibits the generation of large Cu particles 1a. There exists a tendency for the particle size of the particle | grains 1a to become small.

  On the other hand, the current density is increased to increase the Cu film formation rate from the middle to the later stage of electroplating for embedding the upper part from the central part of the Cu wiring 1. At this time, contrary to the case where the process is performed at a low current density, the impurities taken into the formed Cu film are reduced, and the particle diameter of the Cu particles 1a tends to be increased.

  Since the Cu wiring 1 is formed by such electrolytic plating, as shown in FIG. 2, the particle size of the Cu particles 1a is relatively small in the lower and lower side wall portions, and from the central portion to the upper portion, The particles 1a are formed with a structure having a relatively large particle size.

  In the Cu wiring 1 having such a structure, as can be seen from the result of FIG. 1 above, the current flowing through the Cu wiring 1 is concentrated in a region from the central portion to the upper portion having a relatively large particle size and low resistivity. To flow into. In electromigration, since Cu atoms move by the flow of electrons, the influence of the flow of electrons on Cu atoms in the Cu wiring 1 increases from the center to the upper region.

  Further, it is known that the Cu wiring 1 is in contact with the cap film 5 on the upper surface of the Cu wiring 1, and when the cap film 5 is an insulating film, the adhesive strength of the portion is weak. That is, when electromigration occurs, the reason why the diffusion of Cu atoms at the upper interface of the Cu wiring 1 in contact with the cap film 5 is dominant is in addition to the weak adhesion with the cap film 5 at the upper interface. It can be said that a relatively large amount of electrons flow from the central portion to the upper portion of the Cu wiring 1 to increase the electromigration driving force.

From the above, the Cu wiring is configured such that the Cu particles are relatively large in the center and the Cu particles are relatively small in the periphery.
FIG. 3 is a schematic cross-sectional view of an essential part showing a configuration example of a Cu wiring.

The Cu wiring 10 shown in FIG. 3 is formed by using the damascene method in the same manner as the Cu wiring 1 shown in FIG. 2, and a groove provided in the interlayer insulating film 11 such as SiO ₂ and the hard mask 12 such as SiN is formed. The structure is embedded with a Cu film through a barrier metal 13 using Ta, Ti, TaN or the like. The Cu wiring 10 is formed by first forming a barrier metal 13 and a seed Cu film (not shown) on the entire surface after forming the groove, forming a Cu film using an electrolytic plating method, and performing CMP up to the hard mask 12. ,It is formed. A cap film 14 such as SiC or SiN is formed on the Cu wiring 10, and an upper interlayer insulating film 15 such as SiO ₂ is further formed thereon.

  The Cu wiring 10 shown in FIG. 3 has a configuration in which the Cu particles 10a at the center are relatively large, and the lower, side wall, and upper Cu particles 10a around it are relatively small. In the Cu wiring 10 having such a configuration, the Cu particles 10a are relatively large and the resistivity is low, the current is relatively easy to flow through the central portion, the Cu particles 10a are relatively small, and the resistivity is high. The current is relatively difficult to flow through. As a result, the electromigration driving force is weakened at the interface between the upper portion of the Cu wiring 10 having weak adhesion and the cap film 14.

  In general, the higher the frequency of the signal flowing through the wiring, the more current is concentrated on the surface. This phenomenon is called the skin effect. In the state-of-the-art devices, signals in the order of GHz flow, and the skin effect cannot be ignored for general objects. The depth through which the current flows is called the skin depth δ, and the skin depth δ is expressed by the following equation (1).

In Equation (1), μ is the absolute permeability of the conductor, which is 4π × 10 ⁻⁷ (H / m), σ is the conductivity, and ω is the angular frequency of the current. Assuming here that the conductor is Cu, for example, the skin depth δ at a frequency of 1 GHz is 2.09 μm. That is, at such a frequency, all the usual Cu wirings on the order of μm may be regarded as the surface, and current does not flow only on the surface of the Cu wiring due to the skin effect.

Therefore, like the Cu wiring 10 shown in FIG. 3, it can be said that current flow path control is possible by forming a predetermined particle size distribution therein.
The particle size distribution in the Cu wiring 10 can be controlled, for example, by controlling the current density during electroplating when forming the Cu film.

  Specifically, a low current density is set at the initial stage of electrolytic plating, that is, when forming a lower side portion or a lower side wall portion of the Cu wiring 10, and the current density is increased at the time when the middle portion of the middle Cu wiring 10 is formed. The low current density is restored again when the upper part of the Cu wiring 10 is formed. By controlling the current density during electroplating in this way, a Cu wiring 10 having relatively large Cu particles 10a at the center and relatively small Cu particles 10a around the center can be obtained.

  The current density at the time of electrolytic plating is, for example, gradually increased during the initial period to the middle period, and gradually decreased during the intermediate period to the latter period. In addition, it is also possible to continuously change the current density from the initial period to the middle period and from the intermediate period to the latter period. The current density may be set such that no voids or the like are generated in the obtained Cu wiring 10.

  According to such a method, it is possible to form the Cu wiring 10 having electromigration resistance, in which the current flows through the central portion relatively easily only by controlling the current density at the time of electrolytic plating. In order to form 10, it is not necessary to introduce a new manufacturing apparatus.

  Moreover, in order to control the particle size distribution in the Cu wiring, in addition to the method of controlling the current density at the time of electrolytic plating as described above, a method using ion implantation, such as the following, A method of performing a plurality of times under different conditions can also be used.

4 and 5 are explanatory views of a Cu wiring forming method using ion implantation. FIG. 4 is a schematic cross-sectional view of a main part after the CMP process, and FIG. 5 is a schematic cross-sectional view of a main part in the ion implantation process.
First, grooves are formed in the interlayer insulating film 21 such as SiO ₂ and the hard mask 22 such as SiN, and after forming a barrier metal 23 and a seed Cu film (not shown) using Ta, Ti, TaN or the like, A Cu film is formed by electrolytic plating. At the time of electrolytic plating, a Cu film is formed using a conventional method in which the current density is lowered in the initial stage and the current density is increased from the middle period to the latter stage. Thereafter, CMP is performed up to the hard mask 22 to form a Cu wiring 20. Thereby, a state as shown in FIG. 4 is obtained.

  After the Cu wiring 20 is formed in this manner, before the cap film is formed, a halogen such as argon (Ar), neon (Ne), xenon (Xe) or the like is formed on the Cu wiring 20 as shown in FIG. The element of the genus is ion-implanted with the energy adjusted appropriately, and a predetermined heat treatment is performed as necessary, so that only the upper portion of the Cu wiring 20 is made polycrystalline or amorphous. A cap film or the like is formed after such processing. In addition, in FIG. 5, the case where it polycrystallizes is shown typically.

  Also by such a method, for example, when the upper part of the Cu wiring 20 is polycrystallized, the Cu particles 20a on the upper part become smaller, so that the resistivity of the upper part can be increased. Also, when the upper portion of the Cu wiring 20 is made amorphous, the resistivity of the upper portion can be increased. Therefore, like the Cu wiring 10 of FIG. 3, the current is relatively easy to flow through the central portion of the Cu wiring 20 and is relatively difficult to flow in the upper portion where the adhesion with the cap film is weak. It will increase.

  As an element to be ion-implanted, for example, elements such as carbon (C), oxygen (O), and nitrogen (N) that form a compound with Cu can be used in addition to the above-described halogen group elements. Since any compound formed when such an element is used has a higher resistance than pure Cu, the same effect as when the upper portion of the Cu wiring 20 is made polycrystalline or amorphous can be obtained. It becomes possible.

  6 to 8 are explanatory views of a Cu wiring forming method in which electrolytic plating is performed a plurality of times. FIG. 6 is a schematic cross-sectional view of the main part of the first electrolytic plating process. FIG. FIG. 8 is a schematic cross-sectional view of an essential part of the second electrolytic plating process.

In this method, first, as shown in FIG. 6, after a groove is formed in an interlayer insulating film 31 such as SiO ₂ and a hard mask 32 such as SiN, a barrier metal 33 using Ta, Ti, TaN or the like and a seed are formed. A Cu film (not shown) is formed, and the first electrolytic plating is performed with a low current density in the initial stage and a high current density in the middle period to form the Cu film 34. Before the trench is completely filled with the Cu film 34, the first electrolytic plating is finished. In the Cu film 34 thus obtained, the Cu particles 30a are relatively small at the lower part and the side wall part of the groove, and the Cu particles 30a are relatively large from the center part to the upper part.

Next, as shown in FIG. 7, for example, heat treatment is performed at about 350 ° C. for about several minutes in an N ₂ atmosphere or a vacuum atmosphere. Thereby, the Cu particles 30a constituting the Cu film 34 become larger as a whole.

  Then, after the predetermined heat treatment, as shown in FIG. 8, second electrolytic plating is performed at a constant low current density to form a Cu film 35. The groove is completely buried by this second electrolytic plating.

Thereafter, CMP is performed up to the hard mask 32, and a cap film or the like is formed thereon.
By such a method, it is possible to form a Cu wiring in which the Cu particles 30a are relatively large in the central portion and the Cu particles 30a are relatively small in the upper portion in contact with the cap film, and the electromigration resistance can be increased.

  In addition, although the case where the electroplating was performed twice was illustrated here, it can also be performed three times or more. It is clear that Cu wiring with a more controlled grain size can be formed by finely dividing the electrolytic plating and further performing heat treatment under predetermined conditions between them. The conditions for each electroplating (current density, etc.) and the conditions for the heat treatment (temperature, time, etc.) may be set appropriately according to the particle size of the Cu particles to be formed. However, it should be noted that increasing the number of times of electrolytic plating in this way can increase the number of manufacturing steps and increase the cost.

  In addition, the method of performing electroplating in a plurality of times as described above is not particularly limited in the wiring width of the Cu wiring to be formed. For example, in addition to the formation of a Cu wiring having a relatively narrow wiring width of about 150 nm, for example, about 1 μm. The present invention can be similarly applied to the formation of a Cu wiring having a relatively large wiring width, and in any case, a similar particle size distribution can be obtained.

  In the above description, the Cu wiring has been described as an example. However, the present invention can be similarly applied to other metal wirings such as an Al wiring mainly composed of aluminum (Al) polycrystal.

FIG. 9 is a schematic cross-sectional view of an essential part showing a configuration example of an Al wiring.
In the Al wiring 40 shown in FIG. 9, barrier metals 41 and 42 using a refractory metal such as Ta, Ti, or TaN are laminated on the lower layer and the upper layer.

Such an Al wiring 40 is formed as follows, for example. First, on the interlayer insulating film 43 such as SiO ₂ , a refractory metal film, an Al film (including a film containing Al as a main component), and a refractory metal film are sequentially stacked by sputtering. Then, by processing them by dry etching or the like, a three-layer structure of barrier metal 41, Al wiring 40, and barrier metal 42 as shown in FIG. 9 can be obtained. Thereafter, an interlayer insulating film 44 such as SiO ₂ is formed so as to cover the three-layer structure including the Al wiring 40.

  When the Al film is formed by sputtering, the Al particles 40a are relatively small when forming the initial and latter stages, that is, the lower and upper portions of the Al wiring 40, and the Al particles 40a are formed when forming the middle stage, that is, the middle part of the Al wiring 40. Sputtering conditions that are relatively large are set. Specifically, the particle size of the Al particles 40a may be controlled by adjusting the plasma voltage during sputtering or controlling the introduced gas. By forming the Al film in this way, after the processing, the Al wiring 40 having a relatively small lower and upper Al particles 40a and a relatively large middle Al particle 40a can be obtained. Therefore, it is possible to obtain the same effect as described for the Cu wiring.

  In a general Al wiring, electron transport is dominant in the vicinity of the interface with the upper and lower barrier metals, and therefore electromigration is likely to occur in such a region. On the other hand, if the particle size of the Al particles 40a in the vicinity of the interface with the barrier metal is reduced as in the Al wiring 40 described above, the resistivity of the region increases, so that the current flows relatively easily through the central portion. It is possible to suppress the occurrence of such electromigration.

Here, the configuration in which the barrier metals 41 and 42 are provided on the upper and lower layers of the Al wiring 40 is illustrated, but a configuration in which only the lower barrier metal 41 is provided is also possible.
As described above, the metal wiring having electromigration resistance can be formed by appropriately controlling the formation conditions using the apparatus conventionally used for manufacturing the semiconductor device, and has such a high reliability. A semiconductor device provided with metal wiring can be realized stably.

Examples will be described below.
(Example 1)
Here, an example using a method for controlling the current density condition during electrolytic plating will be described. Cross-sectional views of each process for forming the Cu wiring are shown in FIGS. Note that illustration of the transistor portion is omitted. Each process will be described in turn.

FIG. 10 is a schematic sectional view showing an important part of an interlayer insulating film and hard mask forming process.
First, a low dielectric constant (Low-k) film of silicon carbide oxide (SiOC) having a film thickness of about 250 nm is deposited on the underlying insulating film 51 of SiO ₂ formed on the Si substrate 50 by using a CVD method. Then, an interlayer insulating film 52 was formed. A hard mask 53 having a thickness of about 50 nm was formed on the interlayer insulating film 52.

FIG. 11 is a schematic cross-sectional view of the relevant part in the groove forming step.
After the formation of the interlayer insulating film 52 and the hard mask 53, a groove 54 for a lower layer Cu wiring having a width of 100 nm to 1000 nm penetrating the interlayer insulating film 52 and the hard mask 53 was formed by photolithography and etching.

FIG. 12 is a schematic cross-sectional view of an essential part of a barrier metal forming process.
After forming the groove 54, a Ta or TaN barrier metal 55 was formed by sputtering, and a seed Cu film (not shown) was further formed.

FIG. 13 is a schematic cross-sectional view of an essential part of the electrolytic plating process.
After the formation of the barrier metal 55 and the seed Cu film, a Cu film 56 was formed on the seed Cu film by electrolytic plating, and the groove 54 shown in FIGS. 11 and 12 was filled with the Cu film 56.

In the electroplating, the current density is set to about 3 mA / cm ^{2 at} the initial stage (when the lower and lower side wall portions of the groove 54 are embedded), and the current density is gradually increased from there to the middle period (the groove 54). When embedding the central part), it was set to about 20 mA / cm ² . Then, the current density was gradually decreased again and adjusted to be about 3 mA / cm ^{2 in} the latter period (when the upper portion of the groove 54 was buried).

The current density during the electrolytic plating, when raising from its initial 3mA / cm ² to a metaphase of 20 mA / cm ^2, as referred 5,7,9mA / cm ^2, as will increased stepwise did. Similarly, when lowering the mid 20 mA / cm ² to late 3mA / cm ^2, and so will stepped down.

FIG. 14 is a schematic sectional view showing an important part of the first CMP process.
After the formation of the Cu film 56 by electrolytic plating, planarization by CMP was performed in order to remove unnecessary portions of the Cu film 56 and the seed Cu film and barrier metal 55 thereunder. Thereby, a lower layer Cu wiring composed of the seed Cu film and the Cu film 56 was formed.

FIG. 15 is a schematic cross-sectional view of the relevant part in the process of forming the first cap film and the like.
After the CMP, a SiC cap film 57 having a film thickness of about 50 nm, which becomes a diffusion preventing film for Cu atoms in the Cu wiring, was formed by CVD. Thereafter, an SiOC interlayer insulating film 58 having a film thickness of about 450 nm was formed by using the CVD method, and a hard mask 59 having a film thickness of about 50 nm was further formed by using the CVD method.

FIG. 16 is a schematic cross-sectional view of the relevant part in the process of forming via holes and grooves.
After the formation of the cap film 57, the interlayer insulating film 58 and the hard mask 59, a via hole 60 leading to the lower layer Cu wiring and a groove 61 for the upper layer Cu wiring were formed by photolithography and etching using a dual damascene method.

Thereafter, electrolytic plating was performed in the same procedure as in the formation of the lower layer Cu wiring, and the groove 61 was buried.
FIG. 17 is a schematic cross-sectional view of the relevant part after the electrolytic plating process.

  After forming the groove 61 shown in FIG. 16, a barrier metal 62 and a seed Cu film (not shown) are formed by sputtering, and then a Cu film 63 is formed on the seed Cu film by electrolytic plating. .

In the electroplating, the current density is set to about 3 mA / cm ^{2 at} the initial stage (when the via hole 60 is embedded in the lower and lower side wall portions of the groove 61), and the current density is gradually increased from that to the middle period ( (When embedding the central portion of the groove 61), the current density is gradually reduced from about 20 mA / cm ^2, and then the current density is gradually decreased, and about 3 mA / cm ^{2 at} the later stage (when embedding the upper portion of the groove 61). It adjusted so that it might become. Here, the current density was changed stepwise as in the case of the lower Cu wiring.

FIG. 18 is a schematic cross-sectional view of the relevant part in the second CMP step.
After the formation of the Cu film 63 by electrolytic plating, CMP is performed up to the hard mask 59 to remove unnecessary portions of the Cu film 63 and the seed Cu film and barrier metal 62 thereunder, and thereby vias leading to the lower layer Cu wiring , And the upper layer Cu wiring were formed simultaneously.

FIG. 19 is a schematic cross-sectional view of the relevant part in the step of forming the second cap film and the like.
After the formation of the via and the upper layer Cu wiring, a SiC cap film 64 having a film thickness of about 50 nm was formed by CVD, and an SiOC interlayer insulating film 65 was formed thereon.

Through the steps as described above, a Cu wiring structure was formed. Thereafter, a predetermined number of wiring layers were formed in the same manner, and then a pad and a protective film were formed to complete the semiconductor device.
Moreover, the sample using the conventional manufacturing method was also produced as a sample for comparison. That is, in the sample by the conventional method, when the Cu film is embedded by electrolytic plating, the current density is set to about 3 mA / cm ² at the initial stage, and the current density is gradually increased to 20 mA / cm ^{2 at the} middle stage. Thereafter, film formation was performed without changing the current density until the groove was completely filled. Other process conditions were the same as in Example 1 above.

  When a large number of cross sections of the Cu wiring formed by the method of Example 1 were observed using the TEM and EBSP methods, the average particle size of the Cu particles in the lower, upper, and side walls of the Cu wiring cross section was about 0.1 μm. It was found that the thickness was about 0.5 μm at the center. On the other hand, when the cross section of the Cu wiring of the sample to be compared was observed in the same way using the TEM and EBSP methods, the average particle size of the Cu particles in the lower part and the side wall part was about 0.1 μm, and the central part It was found that the average particle diameter of the Cu particles from the top to the top was about 0.5 μm, and that the upper part was larger.

Furthermore, an electromigration test was performed on each of the Cu wiring formed by the electrolytic plating technique used in Example 1 and the Cu wiring formed by the conventional electrolytic plating technique applied to the above-described comparative sample. Each test pattern had a two-layer Cu wiring structure. The lower layer Cu wiring had a wiring width of about 300 nm and a length of about 100 μm, and vias were connected to both ends thereof, and an upper layer Cu wiring was connected to each via. Each upper layer Cu wiring had a wiring width of about 1000 nm, and a pad was directly formed on the upper layer Cu wiring. Then, at a test temperature of about 300 ° C., a current corresponding to ² MA / cm ² was passed from one upper layer Cu wiring to one via, lower layer Cu wiring, the other via, and the other upper layer Cu wiring. As a result of such a test, the life of the electrolytic plating method used in Example 1 is about twice as long as that of the conventional electrolytic plating method applied to the comparative sample. I understood it.

(Example 2)
Here, a method using ion implantation will be described.
The formation process of the Cu wiring is the same up to the processes of FIGS. 10 to 12 shown in the first embodiment. In the subsequent electroplating process of FIG. 13 for forming the lower layer Cu wiring, the conventional method is used here. A Cu film 56 was formed using the same. That is, at the initial stage of electrolytic plating for embedding the lower and lower side wall portions of the groove 54 shown in FIG. 12, the current density is set to about 3 mA / cm ² , and the current density is gradually increased to bury the central portion of the groove 54. In the middle period, it was set to 20 mA / cm ^2, and thereafter, film formation was performed without changing the current density until the groove 54 was completely filled.

  Next, planarization by CMP was performed in the same manner as shown in FIG. 14, and then ion implantation was performed before the formation of the cap film 57 shown in FIG. Ar was used for the implanted ions, and the acceleration voltage at the time of implantation was about 50 keV to 100 keV. Thereby, the lower layer Cu wiring was formed.

  After such ion implantation, as in the first embodiment, as shown in FIGS. 15 to 19, the dual damascene method was used to simultaneously form vias leading to the lower Cu wiring and upper Cu wiring. At that time, in the electrolytic plating step shown in FIG. 17 for forming the via and the upper layer Cu wiring, the Cu film 63 is formed by using the conventional method similarly to the lower layer Cu wiring, and the CMP shown in FIG. After the process, Ar was ion-implanted at an acceleration voltage of about 50 keV to 100 keV.

After the formation of such a Cu wiring structure, a predetermined number of wiring layers were formed in the same manner, and then a pad and a protective film were formed to complete the semiconductor device.
As described above, by performing ion implantation when forming the lower layer Cu wiring and the upper layer Cu wiring, Ar enters between the crystal lattices of the Cu films 56 and 63 formed by electrolytic plating, and the crystallinity is disturbed. The implanted region has an amorphous structure. By controlling the ion implantation conditions, the Ar implantation depth can be controlled. Here, Ar is implanted into the upper portions of the lower layer Cu wiring and the upper layer Cu wiring, respectively.

  When a large number of cross sections of the Cu wiring formed in this way were observed using the TEM and EBSP methods, the surface layer portion was amorphous in the cross section of the Cu wiring, and the average grain size of about 0. Small polycrystals of 1 μm or less were observed. However, in the central part where the ion-implanted element was not reached, it was found that the average particle diameter of Cu particles was about 0.5 μm, as in the comparative sample (see Example 1 above).

As in Example 1, the electromigration test was performed on the Cu wiring formed using the ion implantation method as in Example 2 and the Cu wiring that did not use the ion implantation method as in the comparative sample. did. The test pattern had the same structure (two-layer Cu wiring structure) as described in Example 1 above, and the test conditions (test temperature about 300 ° C., current about 2 MA / cm ² ) were the same. As a result of such a test, it was found that the life when the ion implantation method was used was about 1.5 times longer than when the ion implantation method was not used.

  Although the case where the upper portion of the Cu wiring is made amorphous by ion implantation of Ar is illustrated here, as described above, other halogen group elements can also be used. Been formed.

  It is also possible to ion-implant elements such as C, O, and N to form a higher resistance compound on the Cu wiring. In this case, after ion implantation, heat treatment is performed as necessary to form a predetermined compound. Note that heat is sufficiently applied even in the process after ion implantation (for example, during the formation of an interlayer insulating film), and thus heat treatment for the purpose of forming a compound after ion implantation is not necessarily required. In any case, since the compound is formed by the heat applied after the ion implantation, the acceleration voltage at the time of ion implantation can be set low, and damage such as lattice defects given to the Cu wiring can be reduced.

(Example 3)
Here, a method of performing electrolytic plating in two steps will be described.
The process for forming the Cu wiring is the same up to the processes shown in FIGS. 10 to 12 shown in the first embodiment, and the conditions differ in the electrolytic plating process shown in FIG. 13 for forming the lower layer Cu wiring. Two electrolytic platings were performed.

First, in the first electrolytic plating, the current density is about 3 mA / cm ^{2 in the} initial stage, and the current density is gradually increased to 20 mA / cm ^{2 in the} middle period. The electrode was buried up to the center of 54, and the electroplating was finished at that time. Then, heat treatment at a temperature of about 350 ° C. was performed in such a buried state. Thereby, Cu particle | grains grew and the particle size became large. After the heat treatment, the second electrolytic plating was performed to completely fill the groove 54. This second electrolytic plating was performed at a current density of about 5 mA / cm ² and a constant low current density.

Thereafter, a lower layer Cu wiring was formed through the CMP process shown in FIG.
After the formation of the lower layer Cu wiring, as shown in FIGS. 15 to 19, vias leading to the lower layer Cu wiring and upper layer Cu wiring were simultaneously formed as shown in FIGS. At that time, in the electrolytic plating process shown in FIG. 17 for forming the via and the upper layer Cu wiring, first, the current density is about 3 mA / cm at the initial stage of filling the lower and lower side walls of the groove 61 from the via hole 60. ² and gradually increasing the current density to 20 mA / cm ² to fill the center of the groove 61 (first electrolytic plating), and after heat treatment at a temperature of about 350 ° C., electrolytic plating with a constant current density of about 5 mA / cm ² ( The second electrolytic plating) was performed to completely fill the groove 61. Thereafter, vias and upper-layer Cu wirings were formed through the CMP process shown in FIG.

After the formation of such a Cu wiring structure, a predetermined number of wiring layers were formed in the same manner, and then a pad and a protective film were formed to complete the semiconductor device.
When a large number of cross sections of the Cu wiring formed in this way were observed using the TEM and EBSP methods, the average particle size of the Cu particles on the lower, side and upper portions of the Cu wiring cross section was about 0.1 μm, It was found to be about 0.6 μm at the center. By this method, it was confirmed that the lower layer Cu wiring and the upper layer Cu wiring in which the particle size of the Cu particles is relatively large in the central portion and the particle size of the Cu particles is relatively small can be formed around the center portion.

  Similarly to Example 1 above, when an electromigration test was performed on a Cu wiring formed using the method of performing electrolytic plating in two steps as in Example 3, a conventional electrolytic plating method was used. It was found that the lifetime was about twice as long as the case.

(Example 4)
Here, a method for forming an Al wiring will be described.
A SiO ₂ film was formed on a Si substrate, and a barrier metal made of Ti or titanium nitride (TiN) having a thickness of about 80 nm was formed thereon by sputtering. On the barrier metal, an Al film having a thickness of 450 nm containing about 0.5 wt% of Cu was formed by sputtering.

  During the formation of the Al film, the sputtering conditions were changed halfway. That is, up to about 50 nm in the initial stage of film formation, the sputtering power is increased from an appropriate value to increase the film formation speed to 1 μm / min, and at about 50 nm or more, the film formation speed is reduced to 0.2 μm / min, The value of about 50 nm was also increased from the appropriate value to 1 μm / min. In the case of Al film formation, since particle nucleation determines the particle size, the larger the film formation rate, the smaller the particle size. Utilizing this fact, the film formation rate was increased at the initial and later stages to reduce the Al particles, and the film formation speed was decreased at the intermediate stage to increase the Al particles.

  After the formation of the Al film, a barrier metal made of Ti or TiN and having a thickness of about 50 nm was again formed by sputtering. Then, a pattern having a width of about 0.5 μm was formed using photolithography, and an unnecessary metal portion was removed by RIE. As a result, a lower Al wiring having a wiring width of about 0.5 μm and barrier metals formed on the upper and lower sides was formed.

Thereafter, an SiO ₂ film was deposited on the entire surface to form a tungsten (W) via leading to the Al wiring, and the same process was repeated to form an upper Al wiring.
After the formation of such an Al wiring structure, a predetermined number of wiring layers were formed in the same manner, and then a pad and a protective film were formed to complete the semiconductor device.

When a large number of cross sections of the Al wiring thus formed were observed using the TEM and EBSP methods, Al particles were observed at the lower part (near the lower barrier metal) and the upper part (near the upper barrier metal). The average particle diameter was about 0.2 μm, and it was confirmed that the average particle diameter of Al particles was about 0.5 μm at the center. Since the Al wiring is formed by dry etching, the average particle diameter of the Al particles is equal to that of the central portion in the vicinity of the side wall portion, that is, the interface in contact with the SiO ₂ film.

An electromigration test was performed on the Al wiring formed by such a technique and the Al wiring formed without switching the conventional technique, that is, sputtering conditions in the middle. Each test pattern had a two-layer Al wiring structure, W vias were connected to both ends of the lower Al wiring, upper Al wiring was connected to each via, and a pad was formed on each upper Al wiring. At a test temperature of about 250 ° C., a current corresponding to 1.5 MA / cm ² was passed from one upper layer Al wiring to one W via, lower layer Al wiring, the other via, and the other upper layer Al wiring. As a result of such a test, it was found that the Al wiring formed by using the above-described method has a life approximately 1.5 times longer than that of the Al wiring formed by using the conventional method.

  In the case of Al wiring, the transport of electrons is predominant at the interface with the upper and lower barrier metals. It is considered that the Al particle particle size in the vicinity of them is reduced, so that the resistivity of the region is increased and the current flows in a relatively central portion, thereby improving the electromigration resistance.

In this example, the grain size of the Al wiring is controlled by changing the film formation rate during sputtering. However, for example, the film formation temperature during sputtering can be changed, It is also possible to control by introducing a small amount of hydrogen (H ₂ ) gas or oxygen (O ₂ ) gas sometimes. That is, when the film formation temperature at the time of sputtering is high, diffusion on the film formation surface is promoted, so the particle size of the Al particles increases, and when the film formation temperature is low, nucleus growth is promoted. Therefore, the particle size of the Al particles is reduced. Further, introduction of a trace amount of H ₂ gas or O ₂ gas changes the particle size by reducing or oxidizing the Al particles. Therefore, it is possible to control the particle size of the Al particles by using such methods, and it is possible to improve the electromigration resistance.

  As described above, when forming a metal wiring using Cu, Al or the like, the particle size inside is controlled. In particular, by reducing the particle size of the metal particles in the region where metal transport is most likely to occur in electromigration relative to other regions, the electron flow in that region is reduced and resistance to electromigration phenomenon is improved. Improve. Moreover, the metal wiring having such a configuration can be stably formed by setting the electrolytic plating conditions and the sputtering conditions optimally. Therefore, a semiconductor device including a highly reliable metal wiring having electromigration resistance can be stably manufactured.

  In the above description, the material, size, formation method, and the like of each component of the semiconductor device are not limited to the above example, and can be arbitrarily set according to the required characteristics of the semiconductor device to be formed. It is.

(Additional remark 1) In a semiconductor device provided with metal wiring,
The metal wiring has a top surface covered with a film, and an upper portion in the vicinity of an interface with the film covering the top surface has a higher resistance than a central portion.

(Additional remark 2) The said metal wiring is a semiconductor device of Additional remark 1 characterized by the average particle diameter of the said upper metal particle being formed smaller than the average particle diameter of the metal particle of the said center part.
(Supplementary note 3) The semiconductor device according to supplementary note 1, wherein the metal wiring has an amorphous upper portion.

  (Supplementary note 4) The semiconductor according to supplementary note 1, wherein the metal wiring further has a lower resistance in the vicinity of the interface with the film covering the lower surface of the metal wiring, as compared with the central portion. apparatus.

(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the metal wiring has a lower surface and side surfaces covered with a refractory metal film and an upper surface covered with an insulating film.
(Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 4, wherein the metal wiring has an upper and lower surface covered with a refractory metal film and a side surface covered with an insulating film.

(Additional remark 7) In the manufacturing method of a semiconductor device provided with metal wiring,
Forming a groove in the insulating film;
Forming a barrier metal on the insulating film in which the trench is formed;
Forming a metal film under a high current density condition using a plating method, then forming a metal film under a low current density condition, and embedding the groove with the metal film;
Forming a cap film on the metal film formed in the groove;
A method for manufacturing a semiconductor device, comprising:

(Additional remark 8) Before forming a metal film on the conditions of the said high current density, a metal film is formed on the conditions of a low current density, The manufacturing method of the semiconductor device of Additional remark 7 characterized by the above-mentioned.
(Supplementary note 9) The method for manufacturing a semiconductor device according to supplementary note 8, wherein when the plurality of times of plating are performed and the groove is filled with the metal film, heat treatment is performed between each time of plating.

(Additional remark 10) In the manufacturing method of a semiconductor device provided with metal wiring,
Forming a groove in the insulating film;
Forming a barrier metal on the insulating film in which the trench is formed;
Filling the groove with a metal film using a plating method under conditions of high current density;
Introducing a predetermined element into the upper part of the metal film formed in the groove;
Forming a cap film on the metal film introduced with the predetermined element;
A method for manufacturing a semiconductor device, comprising:

(Supplementary Note 11) In the step of introducing the predetermined element into the upper part of the metal film formed in the groove,
12. The method of manufacturing a semiconductor device according to appendix 10, wherein a halogen element is introduced as the predetermined element to polycrystallize or amorphize the upper portion of the metal film.

(Supplementary Note 12) In the step of introducing the predetermined element into the upper part of the metal film formed in the groove,
11. The method of manufacturing a semiconductor device according to appendix 10, wherein an element that forms a compound with the metal film is introduced as the predetermined element.

  (Additional remark 13) When introducing the said element which forms the said metal film and the said compound as said predetermined element, after the process of introduce | transducing the said element, the heat processing which forms the said compound is performed. The manufacturing method of the semiconductor device of description.

(Additional remark 14) In the manufacturing method of a semiconductor device provided with metal wiring,
Forming a first barrier metal on the first insulating film;
Forming a metal film on the first barrier metal under the condition that the average particle size of the lower and upper metal particles is smaller than the average particle size of the central metal particles;
Forming a second barrier metal on the metal film;
Processing the first and second barrier metals and the metal film into a wiring pattern;
Covering the wiring pattern with a second insulating film;
A method for manufacturing a semiconductor device, comprising:

(Additional remark 15) On the said 1st barrier metal, the said metal film is formed on the conditions that the average particle diameter of the said metal particle of the said lower part and the said upper part becomes smaller than the average particle diameter of the metal particle of the said center part. In the process
By changing the forming speed, forming temperature, or introduced gas when forming the metal film, the average particle size of the lower and upper metal particles is made smaller than the average particle size of the metal particles in the central portion. 15. The method of manufacturing a semiconductor device according to appendix 14, wherein the metal film is formed.

1, 10, 20 Cu wiring 1a, 10a, 20a, 30a Cu particles 2, 6, 11, 15, 21, 31, 43, 44, 52, 58, 65 Interlayer insulating films 3, 12, 22, 32, 53, 59 Hard mask 4, 13, 23, 33, 41, 42, 55, 62 Barrier metal 5, 14, 57, 64 Cap film 34, 35, 56, 63 Cu film 40 Al wiring 40a Al particle 50 Si substrate 51 Base insulation Film 54, 61 Groove 60 Via hole

Claims (3)

In a method for manufacturing a semiconductor device including an Al wiring,
Forming a first barrier metal on the first insulating film;
On the first barrier metal, a first Al film is formed under a first condition so that Al particles have a first average particle diameter, and then a second smaller than the first average particle diameter. Forming a second Al film under a second condition so as to have an average particle diameter;
Forming a second barrier metal on the second Al film;
Processing the first and second barrier metals and the first and second Al films into a wiring pattern;
Covering the wiring pattern with a second insulating film;
A method for manufacturing a semiconductor device, comprising: A third Al film is formed under the third condition so as to have a third average particle size smaller than the first average particle size under the first Al film formed under the first condition. the method of manufacturing a semiconductor device according to claim 1, comprising the step of forming. Wherein the 1, Al film formed between the second barrier metal, a manufacturing method of a semiconductor device according to claim 1 or 2, characterized in that it is formed by sputtering.

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