JP2000114263A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve electromigration resistance of an Al alloy wiring. SOLUTION: A laminated film, consisting of a lower layer Ti film 9a wherein Ti (002) orientation, is relatively storing, a TiN film 9b where TiN (111) orientation is relatively strong and an upper layer Ti film 9c is interposed on a plug electrode 8 constituted of a W film 7 for forming an Al alloy wiring 11 where Al (111) orientation is relatively strong. Furthermore, the grain diameter of the Al alloy wiring 11 is made as small as about 0.2 to 1.0 μm and the dispersion of the grain diameter is made relatively small. As a result, the electromigration resistance of the Al alloy wiring 11 is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same, and more particularly, to aluminum (A)
1) The present invention relates to a technique which is effective when applied to a semiconductor integrated circuit device having a wiring constituted by an alloy film.

[0002]

2. Description of the Related Art Wiring constituted by an Al alloy film formed by a sputtering method (hereinafter, abbreviated as Al alloy wiring) is becoming a limit in obtaining good coverage, and high integration of a semiconductor integrated circuit device is being achieved. However, it is becoming difficult to apply the method to through holes having a high aspect ratio due to miniaturization. Therefore, a technique of burying a tungsten (W) film in a through hole, forming a plug electrode made of the W film, and then forming an Al alloy wiring has been studied.

However, in the Al alloy wiring using the plug electrode, there is a problem that Al flows from the Al alloy wiring to the plug electrode and a part of the Al alloy wiring disappears. Therefore, titanium nitride (Ti
N) Al alloy / TiN in which film is arranged as barrier metal
Stacked wiring is employed.

[0004] The Al alloy / TiN laminated wiring is described in, for example, “Monthly Semiconductor World” published by Press Journal, January 1995.
It is described in the February issue, p150-p155 and the like.

[0005]

However, according to studies made by the present inventors, the following problems remain in the Al alloy / TiN laminated wiring.

That is, the electromigration resistance of an Al alloy wiring depends on its crystal orientation, and Al (1
11) Good electromigration resistance is obtained in the oriented Al alloy wiring. However, the Al alloy film formed on the TiN film is made of Al (111), Al (20).
0) and Al (311) orientation, the electromigration resistance may be deteriorated in the Al alloy / TiN laminated wiring.

Further, the electromigration resistance of the Al alloy wiring is inversely proportional to the square of the standard deviation of the grain size of the Al alloy film. Therefore, it was considered that the electromigration resistance would be improved by reducing the particle size of the Al alloy film and reducing its variation. However, in order to obtain good coverage, the Al alloy film formed by the sputtering method must be formed by heating the semiconductor substrate to about 350 ° C. As a result, the particle size of the Al alloy film Becomes as large as about 0.5 to 4 μm, and its variation also increases.

An object of the present invention is to provide a technique capable of improving the electromigration resistance of an Al alloy wiring.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention has a structure in which a lower titanium (Ti) film, a Ti
It has an Al alloy wiring connected through a laminated film composed of an N film and an upper Ti film, and the lower Ti film has a Ti (0
02) orientation is relatively strong, and the TiN film is TiN (11
1) The orientation is relatively strong.
1) The orientation is relatively strong, and the grain size of the Al alloy wiring is about 1.0 μm or less.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the semiconductor device is connected to a plug electrode formed of a W film via a laminated film including a lower Ti film, a TiN film and an upper Ti film. When forming the Al alloy wiring to be performed,
After forming an interlayer insulating film on the semiconductor substrate on which the lower wiring is formed, a through hole reaching the lower wiring is formed in the interlayer insulating film, and then a barrier layer and a W film are sequentially deposited on the semiconductor substrate. Next, the surface of the W film and the exposed surface of the barrier layer are flattened by a chemical mechanical polishing method, and the barrier layer and the W film are buried in the through holes. Then, at least the lower Ti film and the TiN film are formed on the semiconductor substrate. After successive deposition without opening to the atmosphere, the upper layer Ti
A film is deposited, and then an Al alloy film is formed on a semiconductor substrate maintained at a temperature from room temperature to 150 ° C. by a sputtering method.

According to the above means, the Al alloy film is formed with the lower Ti film having relatively strong Ti (002) orientation and the TiN film having relatively strong TiN (111) orientation interposed therebetween, whereby the Al alloy film is formed. The Al (200) orientation or the Al (311) orientation of the alloy film is suppressed, and an Al alloy film having a relatively strong Al (111) orientation is formed. Furthermore, Al
By forming the alloy film by sputtering at a relatively low temperature from room temperature to 150 ° C., the growth rate of the grain size of the Al alloy film is suppressed, and the grain size is reduced to about 0.2 to 1.0 μm, Since the variation is reduced, the electromigration resistance of the wiring constituted by the Al alloy film is improved.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a sectional view of a principal part of a semiconductor substrate showing a multilayer wiring having an Al alloy wiring according to an embodiment of the present invention.

An interlayer insulating film 2 is formed on a semiconductor substrate 1 on which a semiconductor element (not shown) is formed, and a lower wiring 3 is formed on the interlayer insulating film 2. Further, an interlayer insulating film 4 is formed to cover the lower wiring 3, and a through hole 5 penetrating through the interlayer insulating film 4 and reaching the lower wiring 3 is formed in the interlayer insulating film 4. A barrier layer 6 and a W film 7 are sequentially buried in the through hole 5, and the W film 7 forms a plug electrode 8.

On the upper layer of the interlayer insulating film 4, a lower Ti film 9
a, a TiN film 9b and an upper Ti film 9c are sequentially deposited to form a laminated film, and the lower Ti film 9a is formed of Ti (0
02), the TiN film 9b is relatively strongly oriented to TiN (111). On this laminated film, copper (Cu) is added to a thickness of 0.
An Al alloy wiring 11 composed of an Al alloy film 10 containing 5 wt% is formed. The grain size of the Al alloy wiring 11 is about 0.2 to 1.0 μm, and the Al alloy wiring 11 is oriented relatively strongly to Al (111). On the Al alloy wiring 11, a Ti film 12a and a Ti film
N films 12b are sequentially deposited.

FIG. 2 shows the diffraction intensity of Al (111) in the X-ray diffraction result of the Al alloy film formed on the laminated film composed of the Ti film, the TiN film and the Ti film, and the sputtering on the TiN film. Al (1) in the X-ray diffraction results of the Al alloy film formed by the
11) shows the diffraction intensity. Ti film, TiN film and Ti
Al (1) of the Al alloy film formed on the laminated film
The diffraction intensity of 11) is about five times the diffraction intensity of Al (111) of the Al alloy film formed on the TiN film,
By forming an Al alloy film on the laminated film, A
It can be seen that the Al (111) orientation of the 1 alloy film is improved.

Next, a method of manufacturing an Al alloy wiring according to the present embodiment will be described with reference to cross-sectional views of essential parts of a semiconductor substrate shown in FIGS.

First, as shown in FIG. 3, after an interlayer insulating film 2 is formed on a semiconductor substrate 1 on which a semiconductor element (not shown) is formed, a lower wiring 3 is formed on the interlayer insulating film 2. Then, an interlayer insulating film 4 is formed above the lower wiring 3. The lower wiring 3 is, for example, a lower refractory metal film 3.
a, an aluminum alloy film 3b and an upper refractory metal film 3c. Lower refractory metal film 3
a and the upper refractory metal film 3c are, for example, a W film, Ti
An N film, a tungsten titanium (TiW) film, or a molybdenum silicide (MoSi ₂ ) film. Next, the interlayer insulating film 4 is etched using the resist pattern as a mask to form a through hole 5 reaching the lower wiring 3.

Next, as shown in FIG. 4, after forming a barrier layer 6 on the semiconductor substrate 1 by a sputtering method,
CVD (Chemical Vapor Deposition) on the semiconductor substrate 1
A high melting point metal film, for example, a W film 7 is deposited by the method. The barrier layer 6 is provided to enhance the electrical contact between the lower wiring 3 and the W film 7 and to prevent a reaction gas when forming the W film 7 from entering the lower wiring 3. .

The barrier layer 6 is composed of a Ti film, a TiN film, a W film, a cobalt (Co) film, or a laminated film composed of these films. Further, the high melting point metal film is not limited to the W film 6 formed by the CVD method, but may be an Al alloy film formed by the CVD method,
Alternatively, a W film formed by a sputtering method, T
It may be composed of an iN film, a Ti film or an Al alloy film.

Next, as shown in FIG. 5, the surface of the W film 7 and the exposed surface of the barrier layer 6 are chemically and mechanically polished (Ch
The barrier layer 6 and the W film 7 are buried in the through holes 5 by planarization by emical mechanical polishing (CMP) technology, and the W film 7 forms a plug electrode 8. However, a surface reaction layer 13 made of a component of the polishing liquid, for example, alumina or the like adheres to the surfaces of the interlayer insulating film 4 and the W film 7 after the CMP. Therefore, thereafter, as shown in FIG. 6, first, N ₂ , O ₂ , H ₂ O, etc. adsorbed on the surface of the semiconductor substrate 1 are removed by heat treatment using a high vacuum device. 13 is removed by sputter etching.

Next, as shown in FIG. 7, a lower Ti film 9a, a TiN film 9b and an upper Ti film 9c are successively deposited on the semiconductor substrate 1 successively by a sputtering method without opening to the atmosphere. The thicknesses of the lower Ti film 9a, the TiN film 9b, and the upper Ti film 9c are 5 to 20 nm and 30 to 7, respectively.
0 nm and 5-20 nm. By continuously forming a film without opening to the atmosphere, high purity Ti (002)
The lower Ti film 9a having a strong orientation can be formed, and the lower Ti film 9a having a strong Ti (002) orientation can be formed.
Is the TiN (11) of the TiN film 9b formed thereon.
1) Strengthen the orientation. As a result, the crystal orientation of the Al alloy film formed on the upper Ti film 9c can be improved.

The lower Ti film 9a, the TiN film 9b and the upper Ti film 9c may be formed continuously in the same chamber by switching the gas introduced into the chamber, or may be formed separately in different chambers. May be.

Then, as shown in FIG. 8, an Al alloy film having a thickness of about 0.4 to 2 μm is formed on the semiconductor substrate 1 set at a temperature of room temperature to 150 ° C. without opening to the atmosphere. 1
0 is deposited by a sputtering method. Al alloy film 1
0 contains Cu, and its concentration is, for example, 0.5 wt%.
It is.

The Al alloy film 10 formed on the upper Ti film 9c has a strong Al (111) orientation whose lattice spacing is close to the Ti (002) orientation of the upper Ti film 9c.
By forming the film at a temperature of 0 ° C., the particle size of the Al alloy film 10 is reduced to about 0.2 to 1.0 μm, and at the same time,
Variations in particle size are also relatively small.

When a thick wiring of 0.5 μm or more in which the size of the grain or the variation of the grain size does not greatly affect the electromigration characteristics is formed of the Al alloy film 10, the temperature of 150 ° C. or more is used. An Al alloy film 10 may be formed on the semiconductor substrate 1.

Next, as shown in FIG. 9, a Ti film 12a and a TiN film 12b are successively deposited on the semiconductor substrate 1 by a sputtering method without opening to the atmosphere. Ti
The thicknesses of the film 12a and the TiN film 12b are, for example, about 10 nm and about 80 nm, respectively.

Then, using the photoresist pattern as a mask, the TiN film 12b, the Ti film 12a, the Al alloy film 1
0, upper Ti film 9c, TiN film 9b and lower Ti film 9
By successively etching a, the multilayer wiring shown in FIG. 1 is formed.

In the first embodiment, the lower Ti film 9a, the TiN film 9b, and the upper Ti film 9c are continuously formed by the sputtering method, but may be continuously deposited by the CVD method. 9a and the upper Ti film 9c are made of a source gas containing Ti, for example, titanium tetrachloride (T
The TiN film 9b is formed by using an iCl ₄ ) gas or a titanium tetraiodide (TiI ₄ ) gas, and the TiN film 9b is made of a source gas containing Ti, for example, a TiCl ₄ gas or TiI ₄ gas, and a source gas containing N, for example, NH ₃ It is formed using a mixed gas with a gas.

Further, at least one of the lower Ti film 9a, the TiN film 9b and the upper Ti film 9c may be deposited by a CVD method.

The lower Ti film 9a and the TiN film 9b
May be continuously formed by a sputtering method or a CVD method, and then opened to the atmosphere, and then the upper Ti film 9c may be formed by a sputtering method or a CVD method.

The lower Ti film 9a is, for example, about 60 to
After being formed to a thickness of about 120 nm, a heat treatment at 500 to 900 ° C. is performed on the semiconductor substrate 1 in an atmosphere containing a nitriding gas to nitride the surface of the lower Ti film 9a, thereby forming a laminated film of the lower Ti film 9a and the TiN film 9b. After the formation, the upper Ti film 9c is formed by a sputtering method or a CVD method, so that the lower Ti film 9a, the TiN film 9b and the upper Ti film 9 are formed.
A laminated film made of c may be formed.

Further, in the first embodiment, the lower layer Ti
A laminated film composed of the film 9a, the TiN film 9b, and the upper Ti film 9c is provided below the Al alloy film 10, but has a thickness of about 30 to 50.
A Ti single layer film having a thickness of about nm may be provided below the Al alloy film 10.

In the first embodiment, the Al alloy film 10 is formed by the sputtering method.
May be formed by a CVD method using a source gas containing.

Next, a complementary MISFET (Complementary Metal Ion FET) to which Al alloy wiring according to the first embodiment is applied.
FIG. 10 is a cross-sectional view of a main part of a semiconductor substrate showing an Insulator Semiconductor FET (CMISFET). Qn is an n-channel type MISFET, and Qp is a p-channel type MISFET.
SFET.

A p-type well 15 and an n-type well 16 are formed on the semiconductor substrate 14, and the p-type well 15 and the n-type well 16 are separated from each other via a field insulating film 17.

The p-type well 1 formed on the semiconductor substrate 14
5, an n-channel MISFET Qn is formed, and an n-type well 16 is formed with a p-channel MISFET Qp.

The n-channel MISFET Qn mainly includes a pair of n-type semiconductor regions (source and drain) 18 formed in the p-type well 15, a gate oxide film 19 formed on the surface of the p-type well 15, Oxide film 19
And the gate electrode 20 formed thereon. p
The channel type MISFET Qp mainly has an n-type well 1
6, a pair of p-type semiconductor regions (source and drain) 21, a gate oxide film 19 formed on the surface of the n-type well 16, and a gate electrode 20 formed on the gate oxide film 19. It is configured. The gate electrode 20
For example, it is composed of a polycide film in which a tungsten silicide film is laminated on an n-type polycrystalline silicon film.

For example, a silicon oxide film 22 is formed on the gate electrode 20, and a sidewall spacer 23 made of a silicon oxide film is formed on a side wall. Silicon oxide film 22 and sidewall spacer 23
Are the gate electrode 20 and the wiring (25
a to 25d).

First-layer wirings 25 a to 25 d are formed above the n-channel MISFET Qn and the p-channel MISFET Qp via a silicon oxide film 24. The wiring 25a is connected to an n-channel MISFE through a connection hole 26a opened in the silicon oxide film 24.
TQn is electrically connected to one n-type semiconductor region 18, and wiring 25b is electrically connected to the other n-type semiconductor region 18 of n-channel MISFET Qn through connection hole 26b. The wiring 25c is connected to the connection hole 26c.
Is electrically connected to one p-type semiconductor region 21 of the p-channel MISFET Qp, and the wiring 25d is electrically connected to the other p-type semiconductor region 21 of the p-channel MISFET Qp through the connection hole 26d.

Second-layer wirings 28a and 28b are formed above the first-layer wirings 25a to 25d via an interlayer insulating film 27 made of a silicon oxide film or the like. The wiring 28a has a connection hole 29a formed in the interlayer insulating film 27.
Is electrically connected to the first-layer wiring 25a through the plug electrode 30 embedded in the wiring, and the wiring 28b is connected to the connection hole 29.
It is electrically connected to the first-layer wiring 25d through the plug electrode 30 embedded in b.

The first-layer wirings 25a to 25d are composed of a laminated film composed of a lower refractory metal film, an Al alloy film and an upper refractory metal film, and are composed of a lower refractory metal film and an upper refractory metal film. Are, for example, W film, TiN film, T
It is an iW film or a MoSi ₂ film.

The plug electrode 30 is composed of a refractory metal film such as a W film, an Al alloy film, a TiN film or a Ti film, and a Ti film, a TiN
A barrier layer composed of a film, a W film, a Co film, or a stacked film including these films is provided.

The wirings 28a and 28b of the second layer are formed of a laminated film in which the lower Ti film, the TiN film and the upper Ti film of the first embodiment are sequentially deposited, and Cu formed on the laminated film. It is composed of an Al alloy wiring containing 0.5 wt% and a laminated film in which a Ti film and a TiN film formed on the Al alloy wiring are sequentially deposited. The lower Ti film under the Al alloy wiring is Ti (002), and the TiN film is TiN.
(111) is oriented relatively strongly, and further, Al
The alloy film is relatively strongly oriented to Al (111) and has a particle size of about 0.2 to 1.0 μm.

A passivation film 31 composed of a laminated film of a silicon oxide film and a silicon nitride film is formed on the wirings 28a and 28b.

As described above, according to the first embodiment, T
i (002) orientation relatively lower Ti film 9a, Ti
By forming the Al alloy film 10 with the TiN film 9b having a relatively strong N (111) orientation interposed therebetween, the Al (200) or Al (311) orientation of the Al alloy film 10 is suppressed, and the Al (111) orientation is suppressed. 3.) An Al alloy film 10 having a relatively strong orientation is formed. Further, by forming the Al alloy film 10 at a relatively low temperature from room temperature to 150 ° C. by the sputtering method, the growth rate of the grain size of the Al alloy film 10 is suppressed, and the grain size becomes about 0.2 to 1 About 0.0μm,
Since the variation is reduced, the electromigration resistance of the Al alloy wiring 11 composed of the Al alloy film 10 is improved.

(Embodiment 2) A method of manufacturing an Al alloy wiring according to another embodiment of the present invention will be described with reference to cross-sectional views of essential parts of a semiconductor substrate shown in FIGS.

First, in the first embodiment, FIG.
A through hole 5 is formed in the interlayer insulating film 4 in the same manner as in the manufacturing method described with reference to FIG.
A barrier layer 32 and a W film 7 are sequentially deposited on the semiconductor substrate 1. The barrier layer 32 includes a Ti film 32a and a TiN film 3
2b.

Next, the surface of the W film 7 is flattened by an etch back method, a plug electrode 8 composed of the W film 7 is formed in the through hole 5, and a Ti electrode is formed on the interlayer insulating film 4.
The film 32a and the TiN film 32b are left.

Thereafter, as shown in FIG. 12, a Ti film 33 is formed on the semiconductor substrate 1 by a sputtering method or a CVD method, and then an Al film is formed on the semiconductor substrate 1 by the same manufacturing method as in the first embodiment. Alloy film 10, Ti film 12a
After the TiN film 12b and the TiN film 12b are sequentially deposited, the TiN film 12b and the Ti film 1 are
2a, the Al alloy film 10, the Ti film 33, the TiN film 32b, and the Ti film 32a are sequentially etched. Thereby, the Al alloy wiring 1 composed of the Al alloy film 10 is formed.
1 is formed.

As described above, according to the second embodiment, when the plug electrode 8 composed of the W film 7 is formed in the through hole 5, the Ti film 32a and the TiN film 32b are formed on the interlayer insulating film 4. And a Ti film 32 for improving the crystal orientation of the Al alloy film 10 only by forming the Ti film 33.
a, a laminated film composed of the TiN film 32b and the Ti film 33 can be formed, so that an increase in the number of steps is minimized and the Al alloy film 1 having a relatively strong Al (111) orientation is formed.
0 can be formed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the barrier layer formed on the Al alloy film is a laminated film in which a Ti film and a TiN film are sequentially deposited.
When an alloy film is formed, the barrier layer formed on the Al alloy film may be constituted only by the TiN film.

[0056]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the Al (11
1) Since the orientation becomes relatively strong, the growth rate of the grain size of the Al alloy film is suppressed, and the grain size is reduced to about 1.0 μm or less, and its variation is also reduced. The electromigration resistance of the wiring is improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing an Al alloy wiring according to an embodiment of the present invention.

FIG. 2 shows a diffraction intensity of an Al (111) diffraction peak in X-ray diffraction of an Al alloy film formed on a laminated film including a Ti film, a TiN film and a Ti film, and an Al alloy film formed on a TiN film. FIG.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an Al alloy wiring according to an embodiment of the present invention.

4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device having the Al alloy wiring subsequent to FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device having the Al alloy wiring continued from FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device having the Al alloy wiring continued from FIG. 5;

7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device having the Al alloy wiring subsequent to FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device having the Al alloy wiring subsequent to FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device having the Al alloy wiring subsequent to FIG. 8;

FIG. 10 is a sectional view of a principal part of a semiconductor substrate showing a CMISFET to which an Al alloy wiring according to an embodiment of the present invention is applied;

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device having an Al alloy wiring according to another embodiment of the present invention.

12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device having the Al alloy wiring subsequent to FIG. 11;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 interlayer insulating film 3 lower wiring 3a upper refractory metal film 3b aluminum alloy film 3c lower refractory metal film 4 interlayer insulating film 5 through hole 6 barrier layer 7 tungsten (W) film 8 plug electrode 9a lower titanium (Ti) ) Film 9b titanium nitride (TiN) film 9c upper titanium (Ti) film 10 aluminum (Al) alloy film 11 aluminum (Al) alloy wiring 12a titanium (Ti) film 12b titanium nitride (TiN) film 13 surface reaction layer 14 semiconductor substrate Reference Signs List 15 p-type well 16 n-type well 17 field insulating film 18 n-type semiconductor region 19 gate oxide film 20 gate electrode 21 p-type semiconductor region 22 silicon oxide film 23 sidewall spacer 24 silicon oxide film 25a wiring 25b wiring 25c wiring 25d wiring 26a Connection hole 26b Connection 26c connecting holes 26d connecting hole 27 interlayer insulating film 28a wiring 28b wiring 29a connecting hole 29b connecting hole 30 plug electrodes 31 a passivation film 32 barrier layer 32a of titanium (Ti) film 32b titanium nitride (TiN) film 33 of titanium (Ti) film

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hideo Aoki 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. 4M104 AA01 BB18 CC01 GG10 5F033 HH09 HH18 HH33 JJ18 JJ19 JJ33 KK09 KK19 KK23 KK29 KK33 LL07 LL08 MM08 MM13 NN06 NN07 PP03 PP04 PP06 PP15 QQ08 QQ09 QQ31 QQ37 QQ48 QQ73 QQ78 QQ98 VV04 VV05 WW02 WW03 XX05

Claims (10)

[Claims] 1. A semiconductor integrated circuit device having an aluminum alloy wiring connected to a plug electrode formed of a high melting point metal film via a laminated film including a lower titanium film, a titanium nitride film and an upper titanium film. The lower titanium film has a relatively strong Ti (002) orientation, the titanium nitride film has a relatively strong TiN (111) orientation,
A semiconductor integrated circuit device according to claim 1, wherein said aluminum alloy wiring has a relatively strong Al (111) orientation. 2. The semiconductor integrated circuit device according to claim 1, wherein said aluminum alloy wiring has a grain size of about 1.0 μm or less. 3. The semiconductor integrated circuit device according to claim 1, wherein the lower titanium film has a thickness of 5 to 20 nm, the titanium nitride film has a thickness of 30 to 70 nm, and the upper titanium film has a thickness of 5 to 70 nm. A semiconductor integrated circuit device having a thickness of 20 nm. 4. A semiconductor integrated circuit device having an aluminum alloy wiring connected on a plug electrode formed of a high melting point metal film with a first titanium film interposed therebetween,
A second titanium film, a titanium nitride film, and the first titanium film are provided between the aluminum alloy wiring and an interlayer insulating film thereunder.
A laminated film in which titanium films are sequentially deposited is formed,
A semiconductor integrated circuit device, wherein the thickness of the first titanium film is 5 to 15 nm. 5. A semiconductor integrated circuit device having an aluminum alloy wiring connected via a titanium film on a plug electrode formed of a high melting point metal film, wherein the thickness of the titanium film is 30 to 70 nm. A semiconductor integrated circuit device. 6. A semiconductor integrated circuit device in which an aluminum alloy wiring connected to a plug electrode composed of a high melting point metal film via a laminated film including a lower titanium film, a titanium nitride film and an upper titanium film is formed. (A) forming an interlayer insulating film on a semiconductor substrate on which a lower wiring is formed, and then forming a through hole reaching the lower wiring in the interlayer insulating film; (b) After sequentially forming the barrier layer and the high-melting-point metal film on the semiconductor substrate, the surface of the high-melting-point metal film and the exposed surface of the barrier layer are flattened by a chemical mechanical polishing method. Embedding the barrier layer and the refractory metal film, and (c) depositing at least the lower titanium film and the titanium nitride film on the semiconductor substrate sequentially without opening to the atmosphere, Depositing the upper titanium film on the semiconductor substrate; (d) forming an aluminum alloy film by a sputtering method on the semiconductor substrate maintained at a temperature of room temperature to 150 ° C., or on the semiconductor substrate. Forming an aluminum alloy film by a CVD method. 7. A semiconductor integrated circuit device in which an aluminum alloy wiring connected to a plug electrode formed of a high melting point metal film via a laminated film including a lower titanium film, a titanium nitride film and an upper titanium film is formed. (A) forming an interlayer insulating film on a semiconductor substrate on which a lower wiring is formed, and then forming a through hole reaching the lower wiring in the interlayer insulating film; (b) After sequentially forming the barrier layer and the high-melting-point metal film on the semiconductor substrate, the surface of the high-melting-point metal film and the exposed surface of the barrier layer are flattened by a chemical mechanical polishing method. Embedding the barrier layer and the refractory metal film; and (c) forming a titanium film having a thickness of about 60 to 120 nm on the semiconductor substrate, and then subjecting the semiconductor substrate to heat treatment in a nitrogen atmosphere. (E) nitriding the surface of the titanium film by applying a treatment to form the lower titanium film and the titanium nitride film; and (d) forming the upper titanium film on the semiconductor substrate; Forming an aluminum alloy film by a sputtering method on the semiconductor substrate maintained at a temperature of from room temperature to 150 ° C., or forming an aluminum alloy film by a CVD method on the semiconductor substrate. Of manufacturing a semiconductor integrated circuit device. 8. A method for manufacturing a semiconductor integrated circuit device, comprising forming an aluminum alloy wiring connected to a plug electrode formed of a high melting point metal film with a first titanium film interposed therebetween, comprising: Forming an interlayer insulating film on the semiconductor substrate on which the lower wiring is formed, and then forming a through hole reaching the lower wiring in the interlayer insulating film; and (b) forming a second titanium on the semiconductor substrate. After sequentially forming a film, a titanium nitride film and the refractory metal film, the surface of the refractory metal film is planarized by an etch-back method, and the second titanium film, the titanium nitride film and the Burying the refractory metal film while leaving the second titanium film and the titanium nitride film on the upper surface of the interlayer insulating film; and (c) a thickness of about 5 to 15 nm on the semiconductor substrate. The first of Forming a titanium film of (d). Forming an aluminum alloy film by a sputtering method on the semiconductor substrate maintained at a temperature of room temperature to 150 ° C., or an aluminum alloy film by a CVD method on the semiconductor substrate Forming a semiconductor integrated circuit device. 9. A method of manufacturing a semiconductor integrated circuit device, comprising forming an aluminum alloy wiring connected to a plug electrode formed of a high melting point metal film with a titanium film interposed therebetween, comprising: (a) lower wiring; Forming an interlayer insulating film on the semiconductor substrate on which is formed, and then forming a through hole reaching the lower wiring in the interlayer insulating film; (b) a barrier layer and the refractory metal on the semiconductor substrate. After sequentially forming films, flattening the surface of the refractory metal film and the exposed surface of the barrier layer by a chemical mechanical polishing method, and embedding the barrier layer and the refractory metal film in the through-hole; (C) forming the titanium film having a thickness of about 30 to 70 nm on the semiconductor substrate, and (d) forming the titanium film on the semiconductor substrate maintained at a temperature of from room temperature to 150 ° C. by a sputtering method. The method of manufacturing a semiconductor integrated circuit device characterized by a step of forming an aluminum alloy film, or an aluminum alloy film by CVD on the semiconductor substrate. 10. An aluminum alloy wiring having a width of 0.5 μm or more connected to a plug electrode formed of a high melting point metal film via a laminated film composed of a lower titanium film, a titanium nitride film and an upper titanium film. A method of manufacturing a semiconductor integrated circuit device, comprising: (a) forming an interlayer insulating film on a semiconductor substrate having a lower wiring formed thereon, and then forming a through hole reaching the lower wiring in the interlayer insulating film; (B) after sequentially forming a barrier layer and the refractory metal film on the semiconductor substrate, flattening the surface of the refractory metal film and the exposed surface of the barrier layer by a chemical mechanical polishing method. Embedding the barrier layer and the refractory metal film in the through holes; and (c) without exposing at least the lower titanium film and the titanium nitride film on the semiconductor substrate to the atmosphere. Forming the upper titanium film on the semiconductor substrate after the sequential deposition; and (d) forming an aluminum alloy film by sputtering on the semiconductor substrate maintained at a temperature of 150 to 450 ° C. A method for manufacturing a semiconductor integrated circuit device, comprising: