JPH05114599A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05114599A JPH05114599A JP27578091A JP27578091A JPH05114599A JP H05114599 A JPH05114599 A JP H05114599A JP 27578091 A JP27578091 A JP 27578091A JP 27578091 A JP27578091 A JP 27578091A JP H05114599 A JPH05114599 A JP H05114599A
- Authority
- JP
- Japan
- Prior art keywords
- crystal grain
- metal layer
- grain size
- based metal
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、半導体装置及びその
製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.
【0002】[0002]
【従来の技術】半導体の微細化が進むに連れて配線膜
(特にAl合金膜)のエレクトロマイグレーション(E
M)、ストレスマイグレーション(SM)等による信頼
性の低下が大きな問題になって来ている。従来のEM対
策として、Al中に他の金属不純物(例えばCu,T
i,Pd等)を混入させることや、結晶粒系を大きくし
て所謂竹の節(バンブー)構造の結晶粒界を形成するこ
とが考えられている。又、SM対策としては勿論配線膜
を覆う絶縁膜の低ストレス化と共に材料側の対策として
EM対策と同様金属不純物の混入や結晶粒径の抑制等が
考えられている。2. Description of the Related Art As semiconductors become finer, wiring film (especially Al alloy film) electromigration (E
M), stress migration (SM), and the like have reduced reliability, which has become a serious problem. As a conventional EM countermeasure, other metal impurities (such as Cu and T) are contained in Al.
(i, Pd, etc.) or by increasing the size of the crystal grain system to form a crystal grain boundary having a so-called bamboo knot (bamboo) structure. Further, as SM countermeasures, of course, reduction of stress of the insulating film covering the wiring film is considered, and as countermeasures on the material side, mixing of metal impurities and suppression of crystal grain size are considered as in EM countermeasures.
【0003】さらにAl合金と高融点金属の積層膜やA
lの成膜中に一度装置の外に出し表面に薄い酸化膜を付
けてその上に更にAlを堆積する方法等が考えられてい
る。Further, a laminated film of Al alloy and refractory metal or A
A method has been considered in which, during the film formation of l, the film is taken out of the apparatus once, a thin oxide film is attached to the surface thereof, and Al is further deposited thereon.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、不純物
を混入させたAl系合金の配線層では、腐食や不均一析
出の影響で機械的強度が弱くなる問題があり、EM対策
の竹の節構造の結晶粒界を有する配線層ではSM耐性が
悪くなるという問題がある。この発明は、上記問題を解
決するためになされたものであって、腐食がなく工程を
複雑化することなく、EM、SMのいずれにも耐性を有
する高信頼性のAl系金属が具備されてなる半導体装置
及びその製造方法を提供しようとするものである。However, the wiring layer made of an Al-based alloy containing impurities has a problem that the mechanical strength becomes weak due to the influence of corrosion and uneven deposition. The wiring layer having crystal grain boundaries has a problem that the SM resistance deteriorates. The present invention has been made to solve the above problems, and is provided with a highly reliable Al-based metal that is resistant to both EM and SM without corrosion and without complicating the process. Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof.
【0005】[0005]
【課題を解決するための手段】この発明によれば、半導
体基板上に、絶縁層を介して大きい結晶粒径のAl系金
属層と小さい結晶粒径のAl系金属層との2層以上の積
層体からなる配線層が具備されてなる半導体装置が提供
される。この発明においては、半導体基板上に、絶縁膜
を介して配線層が配置される。According to the present invention, two or more layers of an Al-based metal layer having a large crystal grain size and an Al-based metal layer having a small crystal grain size are provided on a semiconductor substrate through an insulating layer. There is provided a semiconductor device including a wiring layer formed of a laminated body. In the present invention, the wiring layer is arranged on the semiconductor substrate via the insulating film.
【0006】上記半導体基板は、通常シリコン基板が用
いられる。また、この半導体基板は、通常予め素子が形
成される。上記絶縁膜は、半導体基板のコンタクト領域
以外の領域と配線層とを絶縁するためのものであって、
例えば酸化シリコン、窒化シリコン等によって形成され
る。A silicon substrate is usually used as the semiconductor substrate. In addition, elements are usually formed in advance on this semiconductor substrate. The insulating film is for insulating a region other than the contact region of the semiconductor substrate from the wiring layer,
For example, it is formed of silicon oxide, silicon nitride, or the like.
【0007】上記配線層は、半導体装置に高い信頼性を
もって信号の入出力を行うためのものであって、腐食が
なく、製造工程を複雑にすることなくEMとSMのいず
れにも耐性を有するものがよく、大きい結晶粒径のAl
系金属層と小さい結晶粒径のAl系金属層との2層以上
の積層体からなる。大きい結晶粒径のAl系金属層は、
結晶粒径がEMを抑制しうる程度に大きいのがよく通常
5000Å以上好ましくは10000Å以上である。ま
たこの膜厚は、通常0.2〜1.0μmである。The above wiring layer is for inputting / outputting signals to / from the semiconductor device with high reliability, has no corrosion, and has resistance to both EM and SM without complicating the manufacturing process. Good quality, large grain size Al
It is composed of a laminate of two or more layers of a system metal layer and an Al system metal layer having a small crystal grain size. The Al-based metal layer having a large crystal grain size is
The crystal grain size is preferably large enough to suppress EM, and is usually 5000 Å or more, preferably 10,000 Å or more. The film thickness is usually 0.2 to 1.0 μm.
【0008】小さい結晶粒径のAl系金属層は、結晶粒
径がSMを抑制しうる程度に小さいのがよく通常100
00Å以下好ましくは3000Å以下である。またこの
膜厚は、通常0.2〜1.0μmである。上記積層体
は、大きい結晶粒径のAl系金属層と小さい結晶粒径の
Al系金属層とを任意に配置することができるが、絶縁
膜が形成された半導体基板上にまずEM耐性の大きい結
晶粒径のAl系金属層が配置され、この上に任意に小さ
い結晶粒径のAl系金属層と大きい結晶粒径のAl系金
属層とがくり返し積層され、積層体の上部を覆う絶縁層
に接する層にSM耐性の小さい結晶粒径のAl系金属層
が配置されるのが好ましい。The Al-based metal layer having a small crystal grain size preferably has a crystal grain size small enough to suppress SM.
It is not more than 00Å, preferably not more than 3000Å. The film thickness is usually 0.2 to 1.0 μm. In the above-mentioned laminated body, an Al-based metal layer having a large crystal grain size and an Al-based metal layer having a small crystal grain size can be arbitrarily arranged, but the EM resistance is first large on the semiconductor substrate on which the insulating film is formed. An Al-based metal layer having a crystal grain size is disposed, and an Al-based metal layer having an arbitrarily small crystal grain size and an Al-based metal layer having a large crystal grain size are repeatedly stacked on the insulating layer, and an insulating layer covering the upper part of the laminated body. It is preferable to dispose an Al-based metal layer having a small crystal grain size having a small SM resistance in a layer in contact with.
【0009】この発明の半導体装置は、例えば次のよう
にして製造することができる。すなわち、半導体基板
に、絶縁膜を形成し、次いでAl系金属を蒸発源としス
パッタ法を用いて第1の温度で結晶粒径の大きいAl系
金属層を形成し、第1の温度より低い第2の温度で前記
より結晶粒径の小さいAl系金属層を形成し、任意に更
に結晶粒径の大きいAl系金属層と小さいAl系金属層
とをくり返し積層し配線層を形成して半導体装置を製造
する。The semiconductor device of the present invention can be manufactured, for example, as follows. That is, an insulating film is formed on a semiconductor substrate, an Al-based metal layer having a large crystal grain size is formed at a first temperature by using a sputtering method using an Al-based metal as an evaporation source, and a first lower temperature than the first temperature is formed. An Al-based metal layer having a smaller crystal grain size is formed at a temperature of 2, and an Al-based metal layer having a larger crystal grain size and an Al-based metal layer having a smaller crystal grain size are repeatedly laminated to form a wiring layer, thereby forming a semiconductor device. To manufacture.
【0010】上記Al系金属は、例えばAl、Al−S
i、Al−Si−Pd、Al−Si−Cu、Al−Si
−Ti等を挙げることができる。上記第1の温度は、ス
パッタ法によって基板上にEMを抑制しうる結晶粒径の
Al系金属層を形成するための基板温度であって、通常
150°C以上好ましくは300°C以上である。The Al-based metal is, for example, Al or Al-S.
i, Al-Si-Pd, Al-Si-Cu, Al-Si
-Ti etc. can be mentioned. The first temperature is a substrate temperature for forming an Al-based metal layer having a crystal grain size capable of suppressing EM on the substrate by a sputtering method, and is usually 150 ° C or higher, preferably 300 ° C or higher. ..
【0011】上記第2の温度は、スパッタ法によってE
Mを抑制しうる結晶粒径のAl系金属層の上にSMを抑
制しうる結晶粒径のAl系金属層を形成するための基板
温度であって、通常100°C以下好ましくは50°C以
下である。この発明においては、上記配線層が形成され
た半導体基板上に絶縁層を形成して半導体装置を製造す
ることができる。The second temperature is E by the sputtering method.
A substrate temperature for forming an Al-based metal layer having a crystal grain size capable of suppressing SM on an Al-based metal layer having a crystal grain size capable of suppressing M, usually 100 ° C. or lower, preferably 50 ° C. It is below. In the present invention, the semiconductor device can be manufactured by forming the insulating layer on the semiconductor substrate on which the wiring layer is formed.
【0012】[0012]
【作用】基板温度300°C以上で積層した大きい結晶
粒径のAl系金属層がエレクトロマイグレーションを抑
制し、基板温度50°C以下で積層した小さい結晶粒径
のAl系金属層がストレスマイグレーションを抑制す
る。[Function] An Al-based metal layer having a large crystal grain size laminated at a substrate temperature of 300 ° C or higher suppresses electromigration, and an Al-based metal layer having a small crystal grain size laminated at a substrate temperature of 50 ° C or less causes stress migration. Suppress.
【0013】[0013]
【実施例】以下に図面を用いてこの発明の実施例を示
す。この実施例によって本発明の適用範囲が限定される
ものではない。図1(a)に示すように、表面に絶縁膜
2が形成されたシリコン基板1をスパッタ装置内に配置
して400°Cに加熱しAl−Si−Pdを蒸発源とし
てスパッタ法によって膜厚0.4μmのAl−Si−P
d膜3を形成する。Al−Si−Pd膜3を構成するA
l−Si−Pdの結晶粒径は、20000〜40000
Åである。Embodiments of the present invention will be described below with reference to the drawings. The scope of application of the present invention is not limited by this embodiment. As shown in FIG. 1A, a silicon substrate 1 having an insulating film 2 formed on its surface is placed in a sputtering apparatus and heated to 400 ° C., and Al—Si—Pd is used as an evaporation source to form a film with a sputtering method. 0.4 μm Al-Si-P
The d film 3 is formed. A that constitutes the Al-Si-Pd film 3
The crystal grain size of 1-Si-Pd is 20000 to 40,000.
It is Å.
【0014】次に図1(b)に示すようにAl−Si−
Pd膜3が形成された基板の温度を25°Cに下げ、再
びスパッタ法によって膜厚0.4μmのAl−Si−P
d膜4を形成する。Al−Si−Pd膜4を構成するA
l−Si−Pdの結晶粒径は1000〜3000Åであ
る。次にAl−Si−Pd膜3及びAl−Si−Pd膜
4をフォトリソグラフィ法によって所定のパターンにエ
ッチングして配線層を形成し、半導体装置を作製する。Next, as shown in FIG. 1B, Al--Si--
The temperature of the substrate on which the Pd film 3 is formed is lowered to 25 ° C., and again the Al-Si-P film having a thickness of 0.4 μm is formed by the sputtering method.
The d film 4 is formed. A that constitutes the Al-Si-Pd film 4
The crystal grain size of l-Si-Pd is 1000 to 3000Å. Next, the Al-Si-Pd film 3 and the Al-Si-Pd film 4 are etched into a predetermined pattern by photolithography to form a wiring layer, and a semiconductor device is manufactured.
【0015】[0015]
【発明の効果】この発明によれば、工程を複雑化するこ
となく、エレクトロマイグレーションとストレスマイグ
レーションのいずれにも耐性を有する高信頼性のAl系
配線層が具備された半導体装置及びその製造方法を提供
することができる。According to the present invention, a semiconductor device provided with a highly reliable Al-based wiring layer having resistance to both electromigration and stress migration without complicating the process and a method for manufacturing the same are provided. Can be provided.
【図1】この発明の実施例で作製した半導体装置の製造
工程の説明図である。FIG. 1 is an explanatory diagram of a manufacturing process of a semiconductor device manufactured in an example of the present invention.
【符号の簡単な説明】1 シリコン基板 2 絶縁膜 3 Al−Si−Pd膜 4 Al−Si−Pd膜[Brief description of symbols] 1 silicon substrate 2 insulating film 3 Al-Si-Pd film 4 Al-Si-Pd film
Claims (2)
結晶粒径のAl系金属層と小さい結晶粒径のAl系金属
層との2層以上の積層体からなる配線層が具備されてな
る半導体装置。1. A wiring layer comprising a laminate of two or more layers of an Al-based metal layer having a large crystal grain size and an Al-based metal layer having a small crystal grain size is provided on a semiconductor substrate via an insulating layer. Semiconductor device.
Al系金属を蒸発源としスパッタ法を用いて第1の温度
で結晶粒径の大きいAl系金属層を形成し、第1の温度
より低い第2の温度で前記より結晶粒径の小さいAl系
金属層を形成し、任意に更に結晶粒径の大きいAl系金
属層と小さいAl系金属層とをくり返し積層し配線層を
形成してなる請求項1の半導体装置の製造方法。2. An insulating film is formed on a semiconductor substrate, and then an Al-based metal layer having a large crystal grain size is formed at a first temperature by a sputtering method using an Al-based metal as an evaporation source. An Al-based metal layer having a smaller crystal grain size is formed at a lower second temperature, and an Al-based metal layer having a larger crystal grain size and an Al-based metal layer having a smaller crystal grain size are repeatedly laminated to form a wiring layer. The method for manufacturing a semiconductor device according to claim 1, wherein
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27578091A JPH05114599A (en) | 1991-10-23 | 1991-10-23 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27578091A JPH05114599A (en) | 1991-10-23 | 1991-10-23 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05114599A true JPH05114599A (en) | 1993-05-07 |
Family
ID=17560301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27578091A Pending JPH05114599A (en) | 1991-10-23 | 1991-10-23 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05114599A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100917823B1 (en) * | 2007-12-28 | 2009-09-18 | 주식회사 동부하이텍 | Method of manufacturing metal line of the semiconductor device |
JP2009296014A (en) * | 2009-09-18 | 2009-12-17 | Fujitsu Ltd | Method for manufacturing semiconductor device |
CN102237299A (en) * | 2010-04-27 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming aluminum thin film |
-
1991
- 1991-10-23 JP JP27578091A patent/JPH05114599A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100917823B1 (en) * | 2007-12-28 | 2009-09-18 | 주식회사 동부하이텍 | Method of manufacturing metal line of the semiconductor device |
US7659195B2 (en) | 2007-12-28 | 2010-02-09 | Dongbu Hitek Co., Ltd. | Method for forming metal line of semiconductor device |
JP2009296014A (en) * | 2009-09-18 | 2009-12-17 | Fujitsu Ltd | Method for manufacturing semiconductor device |
CN102237299A (en) * | 2010-04-27 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming aluminum thin film |
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