TWI515909B - Thin-film field-effect transistor and method for manufacturing the same - Google Patents

Description

Thin film field effect transistor and manufacturing method thereof

The present invention relates to a thin film field effect transistor using an amorphous oxide semiconductor and a method for fabricating the same, and more particularly to a thin film field effect transistor having an etch barrier layer, good TFT characteristics, and high reliability. Its manufacturing method.

At present, field effect transistors are widely used as semiconductor memory bulk circuits, high frequency signal amplification elements, and the like.

Further, in a field effect transistor, a thin film field effect transistor (hereinafter also referred to as a TFT) is used as a planar thin pattern of a liquid crystal display device (LCD), an electroluminescence display device (EL), and a field emission display (FED). A switching element such as a display device (Flat Panel Display: FPD). A TFT used in FPD is formed with an amorphous germanium film or a polycrystalline germanium film as an active layer on a glass substrate.

The above-described TFT using an amorphous germanium film or a polycrystalline germanium film in the active layer requires a higher temperature thermal process. Therefore, although a glass substrate can be used for a TFT, it is difficult to use a resin substrate having low heat resistance.

Further, in the case of FPD, further reduction in thickness, weight reduction, and breakage resistance are required, and it has been studied to use a lightweight and flexible resin substrate instead of a glass substrate. Therefore, development of a TFT using an amorphous oxide which can form a film at a low temperature has been actively carried out.

A TFT using an amorphous oxide has a substrate, a gate electrode, a gate insulating film, an active layer composed of an amorphous oxide semiconductor, a source electrode, and a drain electrode, and is active. A source and a drain are formed on the layer.

In a TFT using an amorphous oxide, a source and a drain are formed by etching a conductive film. Therefore, in the case where an etching stopper layer for protecting the active layer is not formed, the active layer may be etched sometimes when the source and the drain are formed, and the characteristics and characteristics of the TFT sometimes occur. Unstable. In extreme cases, the active layer is completely etched and sometimes the TFT characteristics are not displayed. In view of the above, a TFT having an etching stopper or the like for protecting the active layer is proposed (for example, refer to Japanese Patent Laid-Open No. 2008-166716, Japanese Patent Laid-Open No. 2009-21612, and Japanese Patent Laid-Open No. 2009-141342 Bulletin).

A bottom gate type thin film transistor having a gate electrode, a first insulating film as a gate insulating film, and an oxide semiconductor layer as a channel layer on the substrate (Japanese Patent Publication No. 2008-166716) Corresponding to the active layer), the second insulating film as a protective layer, the source and the drain. In the thin film transistor, the oxide semiconductor layer contains an oxide containing at least one of In, Zn, and Sn, and the second insulating film includes an amorphous oxide insulator formed next to the oxide semiconductor layer and contains greater than or equal to The detached gas observed as oxygen was analyzed by 380 × 10 ¹⁹ /cm ³ by temperature rise.

The second insulating film functions as an etching stopper which is provided to cover a part of the channel region, preferably covering the entire channel region.

In addition, the second insulating film is made of amorphous SiO _x , amorphous bismuth oxynitride, or amorphous alumina.

A channel protection type thin film transistor is disclosed in Japanese Laid-Open Patent Publication No. 2009-21612. In the thin film transistor, a gate is formed on a substrate, and a first gate insulating film is formed to cover the gate, and a second gate insulating film is formed on the first gate insulating film. Further, an oxide semiconductor film (corresponding to an active layer) is formed on the second gate insulating film to cover the gate. A channel protective film is formed on the oxide semiconductor film in a region overlapping the gate. Further, a source electrode and a drain are formed on the oxide semiconductor film.

The channel protective film prevents etching of the semiconductor layer of the channel portion when forming the source and the drain. The channel protective film is made of yttrium oxide (SiO _x ), tantalum nitride (SiN _x ), yttrium oxynitride (SiO _x N _y ) (x>y), yttrium oxynitride (SiN _x O _y ) (x>y). And so on.

Japanese Laid-Open Patent Publication No. 2009-141342 describes a thin film field effect transistor (TFT) having at least a gate, a gate insulating film, an active layer containing an amorphous oxide semiconductor, a source, and a germanium on a substrate. pole. In the thin film field effect transistor, the root mean square thickness of the interface between the gate insulating film and the active layer is less than 2 nm, the carrier concentration of the active layer is greater than or equal to 1×10 ¹⁵ /cm ³ , and the film thickness of the active layer is greater than or equal to 0.5. Nm is less than 20 nm. Further, a low carrier concentration layer formed of an amorphous oxide semiconductor layer having a carrier concentration of 10 ¹⁶ /cm ³ or less is present next to the active layer. The low carrier concentration layer functions as a protective film that protects the active layer from the environment (moisture, oxygen).

As described above, in the gate thin film transistor described in Japanese Laid-Open Patent Publication No. 2008-166716, a second insulating film that functions as an etching stopper is provided. Further, a film protective film for preventing etching of a semiconductor layer in a channel portion is also provided in the film transistor of Japanese Laid-Open Patent Publication No. 2009-21612. In the above, Japanese Laid-Open Patent Publication No. 2008-166716 and Japanese Patent Laid-Open No. 2009-21612 are provided with a layer as an etching stopper.

As described above, an etch barrier layer is formed over the active layer, and a source and a drain are also formed over the active layer. Therefore, when forming the source and the drain, it is necessary to process the etching stopper.

However, when an etching stopper layer is formed of amorphous SiO _x , SiO ₂ or the like as described in Japanese Laid-Open Patent Publication No. 2008-166716, or Japanese Patent Laid-Open Publication No. 2009-21612, it is necessary to perform processing by dry etching or In the case of wet etching, it is necessary to use buffered hydrofluoric acid for processing, and processing of the etching stopper layer is difficult to perform.

Further, when an SiO ₂ film or a SiN _x film is formed as an etching stopper on the active layer, the active layer is damaged. Due to this damage, the active layer sometimes has a low resistance, the threshold of the TFT becomes a negative value, or the TFT does not exhibit TFT operation without being turned off.

In the case where an SiO ₂ film as an etching stopper layer is formed by a sputtering method in a high-concentration oxygen atmosphere, the reduction in resistance of the active layer can be prevented depending on the film formation conditions. Thus, even if low resistance can be avoided, the back channel of the underlying active layer is damaged by oxygen ions. When the active layer is damaged by oxygen ions, the threshold shift is large when the reliability of the TFT is evaluated.

In Japanese Laid-Open Patent Publication No. 2009-141342, a low carrier concentration layer having the same composition as that of the active layer is formed as a layer that also functions as a protective film. However, the low carrier concentration layer is sometimes etched to the active layer depending on the etching conditions at which the source and the drain are formed. As a result, characteristics of the TFT and characteristics may be unstable or the reliability of the TFT may be lowered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film field effect transistor having excellent TFT characteristics and high reliability and a method of manufacturing the same based on the above problems in the prior art.

In order to achieve the above object, a first aspect of the present invention provides a thin film field effect transistor having at least a gate electrode, an insulating film, an active layer, an etch barrier layer, a source electrode, and a drain electrode formed on the active layer. Forming the etch stop layer, the source and the drain are formed on the etch stop layer, and the thin film field effect transistor is characterized in that the etch stop layer comprises In, Ga, and Zn having a Zn concentration of less than 20%. The amorphous oxide is composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and the Zn concentration is higher than the Zn concentration of the etching stopper.

Here, in the present invention, the Zn concentration in the active layer means the atomic concentration of Zn contained in the amorphous oxide semiconductor film other than the oxygen atom. As a method of calculating the Zn concentration, Zn concentration = [the amount of Zn atoms contained in the amorphous oxide semiconductor film / (the amount of In atoms contained in the amorphous oxide semiconductor film + the amorphous oxide semiconductor film) can be used. The amount of Ga atoms contained + the amount of Zn atoms contained in the amorphous oxide semiconductor film)]. The In concentration and the Ga concentration in the active layer are also the same as the definition of the Zn concentration, and the In concentration and the Ga concentration are also calculated in the same manner as the Zn concentration.

In the present invention, the Zn concentration, the In concentration, and the Ga concentration in the etching stopper layer are the same as the definitions of the Zn concentration, the In concentration, and the Ga concentration of the active layer, and the Zn concentration and the In concentration in the active layer. In the definition and calculation method of the Ga concentration, the "amorphous oxide semiconductor" may be replaced by an "amorphous oxide film".

The etching stopper layer preferably has an In concentration of 40% or more and a Ga concentration of 37% or more.

Further, the source and the above-mentioned drain are preferably made of molybdenum or a molybdenum alloy, and particularly preferably molybdenum.

Further, the above thin film field effect transistor may be any of a top contact type bottom-gate structure or a top contact type top-gate structure.

Further, the above active layer and the above-described etching stopper layer preferably have the same shape.

A second aspect of the present invention provides a method of fabricating a thin film field effect transistor, wherein the thin film field effect transistor has at least a gate, an insulating film, an active layer, an etch stop layer, a source, and a drain formed on the substrate. And forming the etching stopper layer on the active layer, wherein the source electrode and the drain electrode are formed on the etching stopper layer, and the manufacturing method is characterized in that a mixed acid aqueous solution containing phosphoric acid, acetic acid and nitric acid is used as an etching liquid. a process for forming the source and the drain, wherein the etch barrier layer is composed of an amorphous oxide containing In, Ga, and Zn having a Zn concentration of less than 20%, and the active layer is made of a non-In, Ga, and Zn. The crystalline oxide semiconductor is composed, and the Zn concentration is higher than the Zn concentration of the etching stopper layer.

In this case, the etching stopper layer preferably has an In concentration of 40% or more and a Ga concentration of 37% or more.

Further, the mixed acid aqueous solution preferably contains 70% by mass to 75% by mass of phosphoric acid, 5% by mass to 10% by mass of acetic acid, and 1% by mass to 5% by mass of nitric acid.

Preferably, before the process of forming the source and the drain, a process of forming the gate on the substrate; and forming the insulating film on the substrate to cover the gate; a process for forming the active layer on the insulating film; and a process for forming the etch stop layer on the active layer, wherein the source and the ruthenium are formed on the substrate in a process of forming the source and the drain The pole is covered to cover a portion of the etch stop layer described above.

Further, preferably, after the process of forming the source and the drain, a process of forming a protective layer on the substrate to cover the etching stopper, the source, and the drain is performed.

Further, in another aspect, preferably, before the process of forming the source and the drain, a process of forming the active layer on the substrate; and forming the etching on the active layer is performed a process for forming a barrier layer, wherein the source and the drain are formed on the substrate to cover a portion of the etch stop layer in a process of forming the source and the drain, and forming the source and the drain After the process, a process of forming the insulating film on the substrate to cover the etching stopper layer, the source and the drain, and a process of forming the gate on the insulating film is performed.

Further, it is preferable that the active layer has the same shape as the etching stopper layer. Further, each of the above processes is preferably carried out at a temperature of 200 ° C or less.

Based on the above, according to the present invention, an etching barrier layer is formed by using an amorphous oxide containing In, Ga, and Zn having a Zn concentration of less than 20%, and an active layer composed of an amorphous oxide semiconductor containing In, Ga, and Zn. The composition is similar, the active layer is not damaged, and low resistance does not occur. Therefore, a thin film field effect transistor in which the threshold does not become a negative value and exhibits a good TFT operation can be obtained.

Further, by making the etching stopper layer have the above composition, the etching rate ratio of the source and the drain electrode to the etching stopper layer can be made larger than the mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid for forming the source and the drain. big enough. Therefore, when the source and the drain are formed, the active layer is protected by the etching stopper, and the active layer is not damaged. Thereby, a thin film field effect transistor having excellent TFT characteristics and high reliability can be obtained.

Further, the etching stopper layer of the present invention is similar in composition to the active layer, and etching can be performed using the same etching solution as the active layer. Therefore, the etching stopper layer can be easily processed as compared with the case where the SiO ₂ film is used in the etching stopper layer. Further, even if an etching stopper layer is provided, the active layer is not damaged and the resistance is not reduced. Therefore, it is not necessary to perform sputtering in a high-concentration oxygen atmosphere, and a TFT having a small threshold shift and good reliability can be provided. .

The above described features and advantages of the present invention will be more apparent from the following description.

Hereinafter, the thin film field effect transistor of the present invention will be described in detail based on a suitable embodiment shown in the drawings.

FIG. 1 is a schematic cross-sectional view showing a thin film field effect transistor according to a first embodiment of the present invention.

The thin film field effect transistor 10 (hereinafter simply referred to as TFT 10) shown in FIG. 1 has a substrate 12, a gate electrode 14, a gate insulating film 16, an active layer 18 functioning as a channel layer, and an etching stopper (hereinafter referred to as ES). Layer 30, source 20a, drain 20b, and protective layer 22. The TFT 10 is an active device and has a function of applying a voltage to the gate 14 to control the current flowing into the active layer 18 and switching the current between the source 20a and the drain 20b. The TFT 10 shown in Fig. 1 is a TFT which is generally referred to as a top contact type lower gate structure.

In the TFT 10, a gate electrode 14 is formed on the surface 12a of the substrate 12, and a gate insulating film 16 is formed on the surface 12a of the substrate 12 to cover the gate electrode 14. An active layer 18 is formed on the surface 16a of the gate insulating film 16. An ES layer 30 is provided on the surface 18a of the active layer 18.

A source electrode 20a is formed on the surface 16a of the gate insulating film 16 to cover a surface 18a of the active layer 18 and a portion of the surface 30a of the ES layer 30. Further, on the surface 16a of the gate insulating film 16, a drain 20b which is opposed to the source 20a is formed opposite to the source 20a so as to cover a surface 18a of the active layer 18 and a part of the surface 30a of the ES layer 30. That is, the source 20a and the drain 20b are formed above the surface 30a of the ES layer 30 so as to cover the surface 18a of the active layer 18 and a part of the surface 30a of the ES layer 30. A protective layer 22 is formed to cover the source 20a, the ES layer 30, and the drain 20b.

The substrate 12 is not particularly limited. In the substrate 12, for example, YSZ (zirconia stabilized niobium) and an inorganic material such as glass can be used. In addition, polyesters such as polyethylene terephthalate (PET), polybutylene terephthalate (PBT), polyethylene naphthalate (PEN), and the like can be used in the substrate 12; Organic materials such as synthetic resins such as ethylene, polycarbonate, polyether oxime, polyarylate, allyl diglycol carbonate, polyimine, polycycloolefin, norbornene resin, poly(chlorotrifluoroethylene) .

When an organic material is used for the substrate 12, it is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulating properties, workability, low air permeability, and low moisture absorption.

Further, when glass is used for the substrate 12, in order to reduce eluted ions from the glass, it is preferred to use an alkali-free glass. In the case where soda-lime glass is used for the substrate 12, it is preferable to use a soda lime glass to which a barrier coat such as ceria is applied.

A flexible substrate can also be used for the substrate 12. The flexible substrate preferably has a thickness of 50 μm to 500 μm. This is because when the thickness of the flexible substrate is less than 50 μm, it is difficult for the substrate itself to maintain sufficient flatness. When the thickness of the flexible substrate exceeds 500 μm, the flexibility of the substrate itself becomes insufficient, and it is difficult to freely bend the substrate itself.

As the flexible substrate, an organic plastic film having a high transmittance is preferable. As the organic plastic film, for example, polyester such as polyethylene terephthalate (PET), polybutylene phthalate (PBT), polyethylene naphthalate (PEN), or polyphenylene is used. A plastic film of ethylene, polycarbonate, polyether oxime, polyarylate, polyimide, polycycloolefin, norbornene resin, or poly(chlorotrifluoroethylene).

When a plastic film or the like is used for the substrate 12, if the electrical insulating property is insufficient, an insulating layer is formed and used.

In the substrate 12, a moisture-proof layer (gas barrier layer) may be provided on the surface or the reverse surface to prevent the passage of water vapor and oxygen.

As a material of the moisture-proof layer (gas barrier layer), an inorganic substance such as tantalum nitride or ruthenium oxide is suitably used. The moisture-proof layer (gas barrier layer) can be formed, for example, by a high-frequency sputtering method or the like.

In addition, when a thermoplastic substrate is used, a hard coat layer, a lower coat layer, or the like may be further provided as needed.

The gate 14 is made of, for example, a metal such as Al, Mo, Cr, Ta, Ti, Au or Ag or an alloy thereof, an alloy such as Al-Nd or APC, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), or oxidation. It is formed by a metal oxide conductive material such as indium zinc (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof. As the gate 14, it is preferable to use Mo, a Mo alloy or Cr from the viewpoint of reliability of TFT characteristics. The thickness of the gate 14 is, for example, 10 nm to 1000 nm.

The method of forming the gate electrode 14 is not particularly limited. The gate electrode 14 is formed by a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an Ion Plating method, or a chemical vapor deposition (CVD). It is formed by a chemical method such as a slurry CVD method. In view of the suitability of the material constituting the gate 14, an appropriate formation method is selected from the above methods. For example, when a gate electrode 14 is formed using Mo or a Mo alloy, a DC sputtering method is employed. When an organic conductive compound is used in the gate 14, a wet film forming method is used.

As the gate insulating film 16, an insulator such as SiO ₂ , SiN _x , SiON, Al ₂ O ₃ , YsO ₃ , Ta ₂ O ₅ or HfO ₂ or a mixed crystal compound containing at least two or more of the above compounds is used. Further, a polymer insulator such as polyimide may be used in the gate insulating film 16.

The thickness of the gate insulating film 16 is preferably 10 nm to 10 μm. In order to reduce leakage current and improve voltage resistance, the gate insulating film 16 must have a certain thickness. However, if the film thickness of the gate insulating film 16 is increased, the driving voltage of the TFT 10 is increased. Therefore, when it is an inorganic insulator, the thickness of the gate insulating film 16 is more preferably 50 nm to 1000 nm; and when it is a polymer insulator, the thickness of the gate insulating film 16 is more preferably 0.5 μm to 5 μm.

In the case where a high dielectric constant insulator such as HfO ₂ is used for the gate insulating film 16, the transistor can be driven at a low voltage even if the film thickness is increased. Therefore, it is particularly preferable that the gate insulating film 16 is used. Use a high dielectric constant insulator.

As the source 20a and the drain 20b, for example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag or an alloy thereof, an alloy such as Al-Nd or APC, tin oxide, zinc oxide, indium oxide, or indium oxide is used. It is formed of a metal oxide conductive material such as tin (ITO) or indium zinc oxide (IZO).

As the source 20a and the drain 20b, it is preferable to use Mo or a Mo alloy, and particularly preferably Mo, from the viewpoint of the reliability of the TFT characteristics and the etching rate ratio of the ES layer 30. It should be noted that the thickness of the source 20a and the drain 20b is, for example, 10 nm to 1000 nm.

The source electrode 20a and the drain electrode 20b are formed by forming the above-described film, forming a photoresist pattern on the film by photolithography, and then etching the film to form.

In addition, the method of forming the film constituting the source 20a and the drain 20b is not particularly limited. The film is formed by, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD.

For example, when the source 20a and the drain 20b are formed using Mo or a Mo alloy, for example, a Mo film or a Mo alloy film is formed by a DC sputtering method.

Then, a photoresist pattern is formed on the Mo film or the Mo alloy film by photolithography, and the Mo film or the Mo alloy film is etched by an etching solution to form the source electrode 20a and the drain electrode 20b.

As the etching liquid, a mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid is used. The mixed acid aqueous solution contains, for example, 70% by mass to 75% by mass of phosphoric acid, 5% by mass to 10% by mass of acetic acid, and 1% by mass to 5% by mass of nitric acid, and the balance is water.

The active layer 18 is composed of an amorphous oxide semiconductor containing In, Ga, and Zn. The Zn concentration of the active layer 18 is higher than the Zn concentration of the ES layer 30.

In the active layer 18, when the total atomic weight other than oxygen is 100%, it is preferable that the Zn concentration (Zn/(Zn+In+Ga)) is 20% to 50%.

The ES layer 30 protects the active layer 18 such that the active layer 18 is not etched when the source 20a and the drain 20b are formed. The ES layer 30 is composed of an amorphous oxide containing In, Ga, and Zn.

In the ES layer 30, when the total atomic weight other than oxygen is 100%, the Zn concentration (Zn/(Zn+In+Ga)) is less than 20%. In the ES layer 30, it is further preferred that the In concentration (In/(Zn + In + Ga)) is 40% or more and the Ga concentration (Ga / (Zn + In + Ga)) is 37% or more.

As described above, the Zn concentration in the active layer 18 and the ES layer 30 herein refers to the atomic concentration of Zn contained in the amorphous oxide semiconductor film or the amorphous oxide film other than the oxygen atom.

As a method of calculating the Zn concentration in the active layer 18 and the ES layer 30, Zn concentration = [amount of Zn atom contained in the amorphous oxide semiconductor film (amorphous oxide film) / (amorphous oxide semiconductor film) The amount of In atoms contained in the (amorphous oxide film) + the amount of Ga atoms contained in the amorphous oxide semiconductor film (amorphous oxide film) + the inclusion in the amorphous oxide semiconductor film (amorphous oxide film) The amount of Zn atom)). The In concentration and the Ga concentration in the active layer 18 and the ES layer 30 are also the same as the definition of the Zn concentration, and the In concentration and the Ga concentration are also calculated in the same manner as the Zn concentration.

In addition, the Zn atom amount, the In atom amount, and the Ga atom amount in the amorphous oxide semiconductor film (amorphous oxide film) are values obtained by XRF (fluorescence X-ray analysis).

The Zn concentration, the In concentration, and the Ga concentration in the ES layer 30 may be the concentration in the entire ES layer 30, or may be the concentration of the surface 30a of the ES layer 30 in contact with the source 20a and the drain 20b, or the concentration above.

It is to be noted that the Zn concentration of the ES layer 30 is preferably 5% or more and less than 20%. This is because when the Zn concentration is less than 5%, the amorphous form of the oxide semiconductor film is deteriorated, and crystallization tends to occur.

The In concentration of the ES layer 30 is preferably 40% to 58%, and the Ga concentration of the ES layer 30 is preferably 37% to 55%.

When the mixed acid aqueous solution is used as the etching liquid to form the source 20a and the drain 20b made of Mo or Mo alloy, the ES layer 30 is also in contact with the etching liquid. At this time, if the ES layer 30 is not resistant to the etching liquid, the ES layer 30 is also etched. Therefore, in the present invention, the etching rate of the ES layer 30 with respect to the mixed acid aqueous solution is lowered, so that the ES layer 30 is not etched. That is, the ES layer 30 is sufficiently high in the etching rate ratio (selection ratio) to Mo constituting the source 20a and the drain 20b.

In the present invention, when the Zn concentration of the ES layer 30 is less than 20%, as shown in FIG. 2, the etching rate ratio with molybdenum exceeds 10 with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid. Therefore, when the source electrode 20a and the drain electrode 20b are formed, the etching of the active layer 18 is suppressed. If the Ga concentration of the ES layer 30 is 37% or more, as shown in FIG. 3, the mixed acid containing phosphoric acid, acetic acid, and nitric acid is mixed. An aqueous solution having an etching rate ratio of more than 10 to molybdenum. Therefore, when the source 20a and the drain 20b are formed, the etching of the ES layer 30 is suppressed.

Even if the In concentration of the ES layer 30 is 40% or more, as shown in FIG. 3, the etching rate ratio with molybdenum exceeds 10 with respect to the mixed acid aqueous solution containing phosphoric acid, acetic acid, and nitric acid. Therefore, when the source 20a and the drain 20b are formed, the etching of the ES layer 30 is suppressed.

Thus, in the present invention, the composition of the ES layer 30 is adjusted so that the Zn concentration is less than 20% so as to be sufficiently high, for example, more than 10, with respect to the etching rate of the mixed acid aqueous solution with the source 20a and the drain 20b. Thereby, when the source electrode 20a and the drain electrode 20b are formed, etching of the ES layer 30 can be suppressed, and the function as an etching stopper can be fully exhibited.

It is to be noted that, with respect to the composition of the ES layer 30, by making the Zn concentration less than 20%, and making the In concentration 40% or more and the Ga concentration 37% or more, the source and the aqueous solution with respect to the mixed acid can be further sufficiently increased. Etching rate ratio of pole 20a and drain 20b. Thereby, the etching of the ES layer 30 can be more reliably suppressed.

The protective layer 22 is formed to protect the active layer 18, the ES layer 30, the source 20a, and the drain 20b from deterioration by the atmosphere, and is insulated from the electronic device fabricated on the transistor.

The protective layer 22 of the present embodiment is formed, for example, by heat-hardening a photosensitive acrylic resin under a nitrogen atmosphere.

In addition to the above-mentioned photosensitive acrylic resin, the protective layer 22 may be, for example, MgO, SiO, SiO ₂ , Al ₂ O ₃ , GeO, NiO, CaO, BaO, Fe ₂ O ₃ , Y ₂ O ₃ , Ga ₂ O. ₃ or a metal oxide such as TiO ₂ ; a metal nitride such as SiN _x or SiN _x O _y ; a metal fluoride such as MgF ₂ , LiF, AlF ₃ or CaF ₂ ; polyethylene, polypropylene, polymethyl methacrylate, poly a copolymer of ruthenium, polyurea, polytetrafluoroethylene, polychlorotrifluoroethylene, polydichlorodifluoroethylene, chlorotrifluoroethylene and dichlorodifluoroethylene, comprising tetrafluoroethylene and at least one comonomer A copolymer obtained by copolymerizing a monomer mixture, a fluorine-containing copolymer having a cyclic structure in a copolymerization main chain, a water-absorbent substance having a water absorption of 1% or more, a moisture-proof substance having a water absorption of 0.1% or less, or the like.

The method of forming the protective layer 22 is not particularly limited. The protective layer 22 can be, for example, a vacuum deposition method, a sputtering method, a reactive sputtering method, an MBE (molecular ray epitaxy) method, a cluster ion beam method, an ion plating method, or a plasma polymerization method (high-frequency excitation ion plating method). , plasma CVD method, laser CVD method, thermal CVD method, gas source CVD method, coating method, printing method, or transfer method.

Next, a method of manufacturing the TFT 10 of the present embodiment will be described with reference to FIGS. 4a to 4c.

First, as the substrate 12, for example, a glass substrate is prepared.

Next, a molybdenum film (not shown) having a thickness of, for example, 40 nm is formed on the surface 12a of the substrate 12 by DC sputtering.

Next, a photoresist film (not shown) is formed on the molybdenum film, and a photoresist pattern is formed by photolithography.

Next, for example, a mixed acid aqueous solution containing 70% by mass to 75% by mass of phosphoric acid, 5% by mass to 10% by mass of acetic acid, 1% by mass to 5% by mass of nitric acid, and the balance of water is used to etch the molybdenum film. . Thereafter, the photoresist film is peeled off. Thereby, as shown in FIG. 4a, a gate electrode 14 made of molybdenum is formed on the surface 12a of the substrate 12.

Next, an SiO ₂ film (not shown) as a gate insulating film 16 is formed on the entire surface of the surface 12a of the substrate 12 by RF sputtering, for example, at a thickness of 200 nm to cover the gate electrode 14.

Next, a first IGZO film (not shown) as the active layer 18 is formed on the surface of the SiO ₂ film by a DC sputtering method, for example, at a thickness of 30 nm.

Next, a second IGZO film (not shown) as the ES layer 30 was formed on the surface of the first IGZO film by a DC sputtering method under a pressure of 0.37 Pa, for example, at a thickness of 20 nm. Thus, the SiO ₂ film, the first IGZO film, and the second IGZO film are successively formed on the substrate 12 in this order.

Next, a photoresist film (not shown) was formed on the second IGZO film. Then, a photoresist pattern is formed by photolithography. Thereafter, the second IGZO film and the first IGZO film are etched, for example, using 5% oxalic acid water. Thereafter, the photoresist film is peeled off. Thereby, the active layer 18 is formed.

Next, a photoresist film (not shown) was formed on the second IGZO film. Then, a photoresist pattern is formed by photolithography. Thereafter, for example, only 5% of oxalic acid water is used to etch only the second IGZO film. Thereafter, the photoresist film is peeled off. Thereby, the ES layer 30 is formed.

A photoresist film (not shown) was formed on the SiO ₂ film/first IGZO film/second IGZO film again, and a photoresist pattern was formed by photolithography. Then, the SiO ₂ film is etched, for example, using buffered hydrofluoric acid. Thereafter, the photoresist film is peeled off. In this manner, as shown in FIG. 4b, a pattern of the ES layer 30, the active layer 18, and the gate insulating film 16 is formed.

In addition, the first IGZO film constituting the active layer 18 contains In, Ga, and Zn, and the Zn concentration is 20% or more, which is higher than the Zn concentration of the ES layer 30.

The second IGZO film constituting the ES layer 30 contains In, Ga, and Zn, and has a Zn concentration of less than 20%. Preferably, the In concentration is 40% or more and the Ga concentration is 37% or more.

In addition, when the first IGZO film and the second IGZO film are formed by the DC sputtering method, the composition of the first IGZO film and the second IGZO film is obtained by using a target having a composition adjusted in advance.

Next, a molybdenum film (not shown) as a source 20a and a drain 20b is formed on the surface 16a of the gate insulating film 16 by a DC sputtering method at a pressure of 0.37 Pa, for example, as a source 20a and a drain 20b. To cover the ES layer 30 and the active layer 18.

Next, a photoresist film (not shown) is formed on the molybdenum film, and a photoresist pattern is formed by photolithography in the same manner as the gate electrode 14. Thereafter, for example, a molybdenum film is etched using a mixed acid aqueous solution containing 70% by mass to 75% by mass of phosphoric acid, 5% by mass to 10% by mass of acetic acid, 1% by mass to 5% by mass of nitric acid, and the balance being water. Incidentally, the etching is preferably carried out at a liquid temperature of the mixed acid aqueous solution at the time of etching of 35 ° C or less, and more preferably at a liquid temperature of 15 ° C to 25 ° C. After etching, the photoresist film is peeled off. Thereby, as shown in FIG. 4c, the source 20a and the drain 20b which are formed so as to cover a part of the surface 30a of the ES layer 30 and a part of the surface 18a of the active layer 18 are obtained.

Next, for example, a photosensitive acrylic resin is applied to cover the ES layer 30, the source 20a, and the drain 20b. Then, an acrylic resin film pattern is formed by photolithography. In addition, the curing conditions of the acrylic resin at the time of pattern formation are, for example, a temperature of 180 ° C for 30 minutes.

Next, post annealing was performed for 1 hour under a nitrogen atmosphere at a temperature of 180 °C. As described above, the TFT 10 shown in Fig. 1 can be formed.

In the TFT 10 of the present embodiment, even if the ES layer 30 which protects the active layer 18 from being etched is provided on the surface 18a of the active layer 18, since the composition of the ES layer 30 and the active layer 18 is similar, the active layer 18 does not If it is damaged, it will not cause low resistance. Therefore, the threshold of the TFT 10 does not become a negative value, but shows a good TFT operation.

Further, the etching rate of the source layer 20a and the drain electrode 20b and the ES layer 30 with respect to the etching liquid is made higher than 10 or 10, and the etching resistance of the ES layer 30 is improved. Thereby, etching of the underlying ES layer 30 is reduced during etching at the time of forming the source 20a and the drain 20b, and does not cause any damage to the underlying active layer 18. Therefore, the TFT 10 which exhibits good TFT characteristics and has high reliability can be formed uniformly in the plane.

Further, in the manufacturing process of the TFT 10, the ES layer 30 can be etched by the same etching solution as that of the active layer 18, and the ES layer 30 can be easily processed as compared with the case of using an SiO ₂ film as an etching stopper. Further, even if the ES layer 30 is provided, the active layer 18 is not damaged or reduced in resistance, so that it is not necessary to form the ES layer by sputtering in a high-concentration oxygen atmosphere, and the threshold shift can be made small and reliable. Good TFT.

Further, in the manufacturing process of the TFT 10, the formation of the photoresist film, the formation of the photoresist pattern, the formation of various films, and the formation of the protective layer 22 are all performed at a temperature of 200 ° C or lower. In this way, since each process is performed at a temperature of 200 ° C or less, for example, PET, PEN, or the like having low heat resistance can be used for the substrate 12 . Since these PET and PEN have flexibility, a flexible transistor can be obtained.

Next, a second embodiment will be described.

FIG. 5 is a schematic cross-sectional view showing a thin film field effect transistor according to a second embodiment of the present invention.

In the present embodiment, the same components as those of the TFT 10 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The TFT 10a shown in FIG. 5 is different from the TFT 10 shown in FIG. 1 in that the ES layer 32 has the same shape as the active layer 18, and the other configuration is the same as that of the TFT 10 shown in FIG. It should be noted that the ES layer 32 is the same as the ES layer 30 of the first embodiment except for the shape, and thus detailed description thereof will be omitted.

Next, a method of manufacturing the TFT 10a of the present embodiment will be described.

6a to 6c are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a second embodiment of the present invention in a process sequence.

In the method of manufacturing the TFT 10a, the same processes as those of the TFT 10 of the first embodiment shown in FIGS. 4a to 4c will be omitted.

In the manufacturing method of the TFT 10a of the present embodiment, the manufacturing process of the TFT layer 10 of the first embodiment is the same as the manufacturing process of the TFT 10 of the first embodiment, except that the manufacturing process of the TFT layer 32 is different from that of the TFT 10 of the first embodiment. Therefore, the detailed description of the processes of FIGS. 6a and 6c except for the formation process of the ES layer 32 will be omitted.

In the method of manufacturing the TFT 10a of the present embodiment, first, the same operation as in the first embodiment is performed, and as shown in FIG. 6a, the gate electrode 14 is formed on the surface 12a of the substrate 12.

Then, in the same manner as in the first embodiment, the SiO ₂ film as the gate insulating film 16 , the first IGZO film (not shown) as the active layer 18, and the ES layer are successively formed on the substrate 12 in this order. The second IGZO film of 32 (not shown).

Next, a photoresist film (not shown) was formed on the second IGZO film. Then, a photoresist pattern is formed by photolithography, and then the second IGZO film and the first IGZO film are etched. Thereafter, the photoresist film is peeled off. Thereby, the ES layer 32 and the active layer 18 are formed.

A photoresist film (not shown) was formed again on the second IGZO film, and then a photoresist pattern was formed by photolithography. Then, the SiO ₂ film is etched. Thereafter, the photoresist film is peeled off. Thereby, as shown in FIG. 6b, a pattern of the ES layer 32 and the active layer 18 is formed on the surface 16a of the gate insulating film 16. At this time, the ES layer 32 formed on the surface 18a of the active layer 18 is formed in the same shape as the active layer 18.

In addition, etching of the gate insulating film 16, the ES layer 32, and the active layer 18 can be performed similarly to the first embodiment.

Further, the second IGZO film constituting the ES layer 32 has the same composition as that of the second IGZO film constituting the ES layer 30 of the first embodiment.

In the same manner as in the first embodiment, when the first IGZO film and the second IGZO film are formed by the DC sputtering method, a target having a composition adjusted in advance is used.

Next, in the same manner as in the first embodiment, a molybdenum film (not shown) as a source electrode 20a and a drain electrode 20b is formed on the surface 16a of the gate insulating film 16 to cover the ES layer 32 and the active layer 18. Then, a photoresist pattern is formed by photolithography. Thereafter, the molybdenum film was etched using the same mixed acid aqueous solution as that of the first embodiment. Thereby, as shown in FIG. 6c, the source 20a and the drain 20b which are formed so as to cover a part of the surface 32a of the ES layer 32 are obtained.

Next, the same operation as in the first embodiment is performed to form the protective layer 22 covering the ES layer 32, the source 20a, and the drain 20b. As described above, the TFT 10a shown in Fig. 5 can be formed.

It should be noted that although the ES layer 32 and the active layer 18 are collectively formed at one time, it is not limited thereto. The photoresist pattern may be formed by photolithography, followed by etching to form the ES layer 32 and the active layer 18, respectively.

In the present embodiment, even if the ES layer 32 and the active layer 18 have the same shape, the composition of the ES layer 32 and the active layer 18 are similar, and the ES layer 32 also functions as an active layer to operate as a TFT.

By making the ES layer 32 the same shape as the active layer 18, the ES layer 32 and the active layer 18 can be formed using a photoresist pattern formed with the same mask. Thereby, the number of masks required to form the photoresist pattern can be reduced, the cost can be reduced, and the manufacturing process can be simplified. In this way, productivity can also be improved.

In addition, in the present embodiment, the same effects as those of the TFT 10 of the first embodiment and the method of manufacturing the same can be obtained. Therefore, the threshold value of the TFT 10a of the present embodiment does not become a negative value, but shows a good TFT operation. Further, the TFT 10a which exhibits good TFT characteristics and high reliability can be formed uniformly in the plane.

Further, the ES layer 32 can be easily formed as compared with the prior art, and the processing can be easily performed.

Further, in the manufacturing process of the TFT 10a, the formation of the photoresist film, the formation of the photoresist pattern, the formation of various films, and the formation of the protective layer 22 are also performed at a temperature of 200 ° C or lower. In this way, since each process is performed at a temperature of 200 ° C or less, a substrate 12 having low heat resistance such as PET or PEN can be used. Thereby, a flexible transistor can be obtained.

Next, a third embodiment will be described.

FIG. 7 is a schematic cross-sectional view showing a thin film field effect transistor according to a third embodiment of the present invention.

In the present embodiment, the same components as those of the TFT 10 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The TFT 10b shown in Fig. 7 is generally a TFT called a top contact type upper gate structure. The TFT 10b is different from the TFT 10 shown in FIG. 1 in that the arrangement position of the gate electrode 14 and the arrangement positions of the ES layer 30 and the active layer 18 and the source electrode 20a and the drain electrode 20b are reversed, and the like. The configuration is the same as that of the TFT 10 shown in Fig. 1 .

The TFT 10b shown in FIG. 7 has an active layer 18 formed on the surface 12a of the substrate 12. An ES layer 30 is formed on the surface 18a of the active layer 18. A source electrode 20a is formed on the surface 12a of the substrate 12 to cover a surface 18a of the active layer 18 and a portion of the surface 30a of the ES layer 30. Further, on the surface 12a of the substrate 12, a drain 20b which is opposed to the source 20a is formed to face the source 20a so as to cover a surface 18a of the active layer 18 and a part of the surface 30a of the ES layer 30. An insulating film 24 is formed on the substrate 12 to cover the ES layer 30 and the active layer 18, and the source 20a and the drain 20b. A gate electrode 14 is formed on the surface 24a of the insulating film 24. A protective layer 22 is formed on the surface 24a of the insulating film 24 to cover the gate 14.

In addition, the insulating film 24 is used to insulate the ES layer 30 and the active layer 18, and the source 20a and the drain 20b from the gate 14. Since the insulating film 24 has the same configuration as that of the gate insulating layer 16 of the TFT 10 shown in FIG. 1, the detailed description thereof will be omitted.

Next, a method of manufacturing the TFT 10b of the present embodiment will be described.

8a to 8d are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a third embodiment of the present invention in a process sequence.

In the method of manufacturing the TFT 10b, the same processes as those of the TFT 10 of the first embodiment shown in FIGS. 4a to 4c will be omitted.

In the method of manufacturing the TFT 10b of the present embodiment, first, for example, a glass substrate is prepared as the substrate 12.

Next, a first IGZO film (not shown) as the active layer 18 is formed on the surface 12a of the substrate 12 by a DC sputtering method, for example, at a thickness of 30 nm.

Next, a second IGZO film (not shown) as the ES layer 30 is formed on the surface of the first IGZO film by a DC sputtering method under a pressure of 0.37 Pa, for example, at a thickness of 20 nm. Thus, the first IGZO film and the second IGZO film are continuously formed.

Next, a photoresist film (not shown) was formed on the second IGZO film. Then, a photoresist pattern is formed by photolithography, and then the second IGZO film and the first IGZO film are etched using, for example, 5% oxalic acid water. Thereafter, the photoresist film is peeled off.

A photoresist film (not shown) was formed again on the second IGZO film, and then a photoresist pattern was formed by photolithography. Then, for example, only the second IGZO film is etched using 5% oxalic acid water. Thereafter, the photoresist film is peeled off. Thereby, as shown in Fig. 8a, the active layer 18 is formed on the surface 12a of the substrate 12, and the ES layer 30 is formed on the surface 18a thereof.

Next, a molybdenum film (not shown) as a source electrode 20a and a drain electrode 20b is formed on the surface 12a of the substrate 12 by a DC sputtering method at a thickness of 100 nm by a DC sputtering method to cover the ES. Layer 30 and active layer 18.

Next, a photoresist film (not shown) is formed on the molybdenum film, and a photoresist pattern is formed by photolithography. Then, the molybdenum film was etched using the same mixed acid aqueous solution as that of the first embodiment. After etching, the photoresist film is peeled off. Thereby, as shown in FIG. 8b, the source 20a and the drain 20b formed so as to cover the surface 30a of the ES layer 30 and a part of the surface 18a of the active layer 18 are obtained.

Next, as shown in FIG. 8c, an SiO ₂ film (not shown) having a thickness of 200 nm as the insulating film 24 is formed by RF sputtering to cover the active layer 18, the source 20a, and the drain 20b. A photoresist film (not shown) is formed on the SiO ₂ film, and then a photoresist pattern is formed by photolithography. Then, the SiO ₂ film is etched, for example, using buffered hydrofluoric acid to form the insulating film 24.

Next, a molybdenum film (not shown) as a gate electrode 14 having a thickness of 40 nm is formed on the surface 24a of the insulating film 24 by a DC sputtering method.

Next, a photoresist film (not shown) was formed on the molybdenum film, and then a photoresist pattern was formed by photolithography.

Next, the molybdenum film was etched using the same mixed acid aqueous solution as the component of the first embodiment. Thereafter, the photoresist film is peeled off. Thereby, as shown in Fig. 8d, a gate electrode 14 made of molybdenum is formed on the surface 24a of the insulating film 24.

Next, a photosensitive acrylic resin is applied on the surface 24a of the insulating film 24, for example, to cover the gate electrode 14. Then, an acrylic resin film pattern is formed by photolithography. In addition, the curing conditions of the acrylic resin at the time of pattern formation are, for example, a temperature of 180 ° C for 30 minutes.

Next, post-annealing was performed for 1 hour under a nitrogen atmosphere at a temperature of 180 °C. As described above, the TFT 10b shown in Fig. 7 can be formed.

Also in the present embodiment, the same effects as those of the TFT 10 of the first embodiment and the method of manufacturing the same can be obtained. Therefore, in the TFT 10b of the present embodiment, the threshold value does not become a negative value, but a good TFT operation is exhibited. Further, the TFT 10b which exhibits good TFT characteristics and high reliability can be formed uniformly in the plane.

Further, the ES layer 32 can be easily formed as compared with the prior art, and the processing can be easily performed.

In the manufacturing process of the TFT 10b of the present embodiment, the formation of the photoresist film, the formation of the photoresist pattern, the formation of various films, and the formation of the protective layer 22 are all performed at a temperature of 200 ° C or lower. In this way, since each process is performed at a temperature of 200 ° C or less, a substrate 12 having low heat resistance such as PET or PEN can be used. Thereby, a TFT having flexibility can be obtained.

Next, a fourth embodiment will be described.

FIG. 9 is a schematic cross-sectional view showing a thin film field effect transistor according to a fourth embodiment of the present invention.

In the present embodiment, the same components as those of the TFT 10b of the third embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The TFT 10c shown in FIG. 9 is different from the TFT 10b shown in FIG. 7 in that the ES layer 32 has the same shape as the active layer 18, and the other configuration is the same as that of the TFT 10b shown in FIG. It should be noted that the ES layer 32 has the same composition as the ES layer 30 of the first embodiment as described above. Therefore, the detailed description is omitted.

Next, a method of manufacturing the TFT 10c of the present embodiment will be described.

10a to 10d are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a fourth embodiment of the present invention in a process sequence.

In the method of manufacturing the TFT 10c, the same processes as those of the method of manufacturing the TFT 10b of the third embodiment shown in FIGS. 8a to 8d will be omitted.

In the manufacturing method of the TFT 10c of the present embodiment, the manufacturing process of the TFT 10b of the third embodiment is the same as the manufacturing process of the TFT 10b of the third embodiment, except that the manufacturing process of the ES layer 32 is different from that of the third embodiment. Therefore, the detailed description of the processes of FIGS. 10b to 10d other than the formation process of the ES layer 32 will be omitted.

In the method of manufacturing the TFT 10c of the present embodiment, first, the same operation as in the third embodiment is performed, and a first IGZO film (not shown) as the active layer 18 is continuously formed on the surface 12a of the substrate 12, and A second IGZO film (not shown) as the ES layer 32 is formed on the surface of the first IGZO film.

Next, a photoresist film (not shown) was formed on the second IGZO film, and then a photoresist pattern was formed by photolithography. Thereafter, the second IGZO film and the first IGZO film are etched, for example, using 5% oxalic acid water. Thereafter, the photoresist film is peeled off. Thereby, as shown in FIG. 10a, the pattern of the ES layer 32 and the active layer 18 is formed. At this time, the ES layer 32 formed on the surface 18a of the active layer 18 is formed in the same shape as the active layer 18.

In addition, the composition of the second IGZO film constituting the ES layer 32 is the same as that of the second IGZO film constituting the ES layer 30 of the first embodiment.

In the same manner as in the third embodiment, when the first IGZO film and the second IGZO film are formed by the DC sputtering method, a target having a composition adjusted in advance is used.

Next, in the same manner as in the third embodiment, a molybdenum film (not shown) as a source electrode 20a and a drain electrode 20b is formed on the surface 12a of the substrate 12 to cover the ES layer 32 and the active layer 18. Then, a photoresist pattern is formed by photolithography. Thereafter, in the same manner as in the third embodiment, the molybdenum film was etched using the same mixed acid aqueous solution as the components of the first embodiment. Thereby, as shown in FIG. 10b, the source 20a and the drain 20b which are formed so as to cover a part of the surface 32a of the ES layer 32 are obtained.

Next, the same operation as in the third embodiment is performed, and as shown in FIG. 10c, an insulating film 24 covering the ES layer 32, the source 20a, and the drain 20b is formed.

Next, the same operation as in the third embodiment is performed, as shown in Fig. 10d, a gate electrode 14 made of molybdenum is formed on the surface 24a of the insulating film 24, and then a protective layer is formed on the surface 24a of the insulating film 24. 22 to cover the gate 14. Thereafter, post-annealing was performed for 1 hour under a nitrogen atmosphere at a temperature of 180 ° C to form the TFT 10c.

It should be noted that although the ES layer 32 and the active layer 18 are collectively formed at one time, it is not limited thereto. The photoresist pattern may be formed by photolithography, followed by etching to form the ES layer 32 and the active layer 18, respectively.

In the present embodiment, even if the shape of the ES layer 32 and the active layer 18 are the same, the composition of the ES layer 32 and the active layer 18 is similar, and the ES layer 32 functions as an active layer to operate as a TFT.

Further, by making the shape of the ES layer 32 and the active layer 18 the same, the ES layer 32 and the active layer 18 can be formed using the photoresist pattern formed with the same mask. Thereby, the number of masks required to form the photoresist pattern can be reduced, the cost can be reduced, and the manufacturing process can be simplified. In this way, productivity can also be improved.

In addition, in the present embodiment, as in the third embodiment, the same effects as those of the TFT 10 of the first embodiment and the method of manufacturing the same can be obtained. Therefore, the threshold of the TFT 10c does not become a negative value, but shows a good TFT operation. Further, the TFT 10c which exhibits good TFT characteristics and high reliability can be formed uniformly in the plane.

Further, the ES layer 32 can be easily formed as compared with the prior art, and the processing can be easily performed.

Further, in the manufacturing process of the TFT 10c, the formation of the photoresist film, the formation of the photoresist pattern, the formation of various films, and the formation of the protective layer 22 are also performed at a temperature of 200 ° C or lower. In this way, since each process is performed at a temperature of 200 ° C or less, a substrate 12 having low heat resistance such as PET or PEN can be used. Thereby, a TFT having flexibility can be obtained.

The invention is basically as described above. The present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

[Example 1]

Hereinafter, examples of the thin film field effect transistor of the present invention will be specifically described.

In the present Example, the TFTs shown in the following Example 1, Example 2, and Comparative Example 1 to Comparative Example 3 were produced, and the TFTs of Example 1, Example 2, and Comparative Example 1 to Comparative Example 3 were produced. Evaluation. In the TFTs of Example 1, Example 2, and Comparative Example 1 to Comparative Example 3, the TFT 10 having the configuration shown in FIG. 1 was used.

Each of the TFTs of Example 1, Example 2, and Comparative Example 1 to Comparative Example 3 was basically produced by the above-described manufacturing method shown in Figs. 4a to 4c.

In each of the TFTs of Example 1, Example 2, Comparative Example 1, and Comparative Example 2, the gate electrode 14 was formed by forming a molybdenum film having a thickness of 40 nm by DC sputtering, and then photolithographically coating the molybdenum film. The resist pattern was formed thereon, and it was formed by etching using a mixed acid aqueous solution (liquid temperature: 35 ° C) containing 73 mass% of phosphoric acid, 7 mass% of acetic acid, 3% by mass of nitric acid, and the remainder being water.

Next, an SiO ₂ film having a thickness of 200 nm as the gate insulating film 16 was formed by RF sputtering. Next, a first IGZO film having the following composition as the active layer 18 was formed on the surface of the SiO ₂ film by a DC sputtering method at a thickness of 30 nm. A second IGZO film having the following composition as the ES layer 30 was formed on the surface of the first IGZO film by a DC sputtering method at a thickness of 30 nm. Then, a photoresist pattern is formed on the second IGZO film by photolithography. Then, the second IGZO film and the first IGZO film were formed by using 5% oxalic acid water to form.

The active layer 18 has a Zn concentration (Zn/In+Ga+Zn) of 26.9%, a Ga concentration (Ga/In+Ga+Zn) of 34.6%, and an In concentration (In/In+Ga+Zn) of 38.5%. 1 IGZO film. Incidentally, the concentration analysis of the first IGZO film was carried out by XRF analysis as described above.

The ES layer 30 is formed by forming a photoresist pattern on the second IGZO film by photolithography after the active layer 18 is formed. Then, the ES layer 30 is formed by etching only the second IGZO film using 5% oxalic acid water.

The gate insulating film 16 is formed by forming a photoresist pattern on the SiO ₂ film / the first IGZO film / the second IGZO film by photolithography, and then etching the SiO ₂ film using buffered hydrofluoric acid to form the gate insulating film 16.

The source electrode 20a and the drain electrode 20b were formed by forming a molybdenum film with a thickness of 100 nm under a condition of a pressure of 0.37 Pa by a DC sputtering method. A photoresist pattern is formed on the molybdenum film by photolithography. Then, a molybdenum film was formed by using an aqueous mixed acid solution (liquid temperature: 25 ° C) containing 73% by mass of phosphoric acid, 7% by mass of acetic acid, 3% by mass of nitric acid, and the remainder being water, to form a molybdenum film.

A photosensitive acrylic resin (PC405G (manufactured by JSR Co., Ltd.)) was applied to the protective layer 22 so as to cover the active layer 18, the source 20a, and the drain 20b, and then an acrylic resin film pattern was formed by photolithography. The curing conditions of the acrylic resin at the time of pattern formation were as follows: temperature: 180 ° C, 30 minutes. Thereafter, post-annealing was performed for 1 hour under a nitrogen atmosphere at a temperature of 180 ° C to form a TFT 10.

In Example 1, the ES layer used a Zn concentration (Zn/In+Ga+Zn) of 14.6%, a Ga concentration (Ga/In+Ga+Zn) of 41.6%, and an In concentration (In/In+Ga+Zn). It is 43.8% of the 2nd IGZO film. Incidentally, the concentration analysis of the second IGZO film was carried out by XRF analysis as described above.

In the first embodiment, the ES layer and the constituent source and the ruthenium are formed by using the etching liquid (73 mass% phosphoric acid, 7 mass% acetic acid, and 3% by mass aqueous mixed acid solution of nitric acid (liquid temperature: 25 ° C)). The etch rate ratio of the molybdenum is (1:1: IGZO:Mo). Embodiment 1 corresponds to the symbol A shown in Fig. 2 .

In Example 2, the ES layer used a Zn concentration (Zn/In+Ga+Zn) of 19.2%, a Ga concentration (Ga/In+Ga+Zn) of 38.8%, and an In concentration (In/In+Ga+Zn). It is 42.0% of the 2nd IGZO film.

In the second embodiment, the ES layer and the constituent source and the ruthenium are formed by using the etching liquid (73 mass% phosphoric acid, 7 mass% acetic acid, and 3% by mass aqueous mixed acid solution of nitric acid (liquid temperature: 25 ° C)). The etch rate ratio of the molybdenum (IGZO:Mo) is 1:10.6. Embodiment 2 corresponds to the symbol B shown in FIG.

In Comparative Example 1, a SiO ₂ film having a thickness of 20 nm was used as the ES layer. In Comparative Example 1, the same as Example 1 except that the configuration and the formation method of the ES layer were different. In Comparative Example 1, an ES layer was formed as follows.

In Comparative Example 1, after the first IGZO film was formed, a pattern of the active layer 18 was formed. Thereafter, a SiO ₂ film having a thickness of 20 nm was formed on the surface 16a of the gate insulating film 16 by RF sputtering to cover the active layer 18. Next, a photoresist pattern was formed on the SiO ₂ film, and the SiO ₂ film was etched using buffered hydrofluoric acid to form an ES layer.

In Comparative Example 2, the ES layer used a Zn concentration (Zn/In+Ga+Zn) of 34.7%, a Ga concentration (Ga/In+Ga+Zn) of 30.3%, and an In concentration (In/In+Ga+Zn). It is 35.0% of the 2nd IGZO film.

In Comparative Example 2, the ES layer and the constituent source and the ytterbium were formed by the above etching liquid (73 mass% phosphoric acid, 7 mass% acetic acid, and 3% by mass aqueous mixed acid solution of nitric acid (liquid temperature: 25 ° C)). The etch rate ratio of the molybdenum (IGZO:Mo) is 1:3.1. Comparative Example 2 corresponds to the symbol C shown in Fig. 2 .

In Comparative Example 3, the ES layer used a Zn concentration (Zn/In+Ga+Zn) of 25.1%, a Ga concentration (Ga/In+Ga+Zn) of 36.5%, and an In concentration (In/In+Ga+Zn). It is 35% of the 2nd IGZO film.

In Comparative Example 3, the ES layer and the constituent source and the ruthenium were formed by using the above etching liquid (73 mass% phosphoric acid, 7 mass% acetic acid, and 3% by mass aqueous mixed acid solution of nitric acid (liquid temperature: 25 ° C)). The etch rate ratio of the molybdenum (IGZO:Mo) is 1:9.0. Comparative Example 3 corresponds to the symbol D shown in Fig. 2 .

The mobility of each of the transistors of Example 1, Example 2, and Comparative Example 1 to Comparative Example 3 was measured. As a result, the mobility of the transistor of Example 1 and Example 2 was 10 cm ² /Vs or more, and the uniformity of TFT characteristics was good.

On the other hand, in Comparative Example 1, the active layer of the underlayer was also etched by the etching in the formation of the ES layer, and the contact with the source and the drain was insufficient, and the on-current was deteriorated, and even in the reliability test, it was obtained. The results were inferior to those of Example 1 and Example 2.

Further, in Comparative Example 2, the ES layer did not function, and the etching occurred when the source and the drain were formed, the active layer disappeared, the TFT could not be formed, and the TFT operation was not performed. In Comparative Example 3, the ES layer function was insufficient, and although the TFT operation was performed, the in-plane uniformity of the TFT characteristics was poor.

[Embodiment 2]

In the present Example, the TFTs shown in the following Examples 3 and 4 were produced, and the TFTs of Examples 3 and 4 were evaluated. In the TFTs of Example 3 and Comparative Example 4, the TFT 10a having the configuration shown in FIG. 5 was used.

In the present embodiment, the ES layer and the active layer have the same shape as the first embodiment, and the same as the first embodiment, the detailed description thereof will be omitted.

In Example 3, the ES layer and the active layer formed the same shape. This embodiment 3 is the same as the first embodiment of the first embodiment except that the ES layer and the active layer form the same shape.

In Comparative Example 4, the ES layer and the active layer formed the same shape. This Comparative Example 4 is the same as Comparative Example 1 of the first embodiment except that the ES layer and the active layer have the same shape.

The mobility of each of the TFTs of Example 3 and Comparative Example 4 was measured. As a result, the mobility of the TFT of Example 3 was 10 cm ² /Vs or more, and the uniformity of TFT characteristics was good. Comparative Example 4 did not show TFT operation.

It should be noted that since the embodiment 3 can form the ES layer and the active layer using the same mask, the number of masks can be reduced, and the cost can be reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 10a, 10b, 10c. . . Thin film field effect transistor (TFT)

12. . . Substrate

12a, 16a, 18a, 24a, 30a, 32a. . . surface

14. . . Gate

16. . . Gate insulating film

18. . . Active layer

20a. . . Source

20b. . . Bungee

twenty two. . . The protective layer

twenty four. . . Insulating film

30, 32. . . Etch barrier (ES layer)

FIG. 1 is a schematic cross-sectional view showing a thin film field effect transistor according to a first embodiment of the present invention.

2 is a view showing an IGZO film related to Zn concentration relative to molybdenum when a mixed acid aqueous solution containing 73% by mass of phosphoric acid, 7% by mass of acetic acid, 3% by mass of nitric acid, and a temperature of 25 ° C is used in the etching solution. A graph of the etching speed ratio.

3 is a view showing the relative relationship between the IGZO film and the In concentration and the Ga concentration when a mixed acid aqueous solution containing 73% by mass of phosphoric acid, 7% by mass of acetic acid, 3% by mass of nitric acid and having a temperature of 25° C. is used in the etching solution. A graph of the etching rate ratio of molybdenum.

4a to 4c are schematic cross-sectional views showing a method of manufacturing the thin film field effect transistor according to the first embodiment of the present invention in a process sequence.

FIG. 5 is a schematic cross-sectional view showing a thin film field effect transistor according to a second embodiment of the present invention.

6a to 6c are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a second embodiment of the present invention in a process sequence.

FIG. 7 is a schematic cross-sectional view showing a thin film field effect transistor according to a third embodiment of the present invention.

8a to 8d are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a third embodiment of the present invention in a process sequence.

FIG. 9 is a schematic cross-sectional view showing a thin film field effect transistor according to a fourth embodiment of the present invention.

10a to 10d are schematic cross-sectional views showing a method of manufacturing a thin film field effect transistor according to a fourth embodiment of the present invention in a process sequence.

10. . . Thin film field effect transistor (TFT)

12. . . Substrate

12a, 16a, 18a, 30a. . . surface

14. . . Gate

16. . . Gate insulating film

18. . . Active layer

20a. . . Source

20b. . . Bungee

twenty two. . . The protective layer

30. . . Etch barrier (ES layer)

Claims (13)

A thin film field effect transistor having at least a gate electrode, an insulating film, an active layer, an etch stop layer, a source and a drain formed on the substrate, and the etch stop layer is formed on the active layer The source and the drain are formed on the etch barrier layer, and the thin film field effect transistor is characterized in that the etch barrier layer is made of non-In, Ga, and Zn containing a Zn concentration of less than or equal to 14.6%. The crystalline oxide is composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and the Zn concentration is higher than the Zn concentration of the etching stopper. The thin film field effect transistor according to claim 1, wherein the etching barrier layer has an In concentration of 40% or more and a Ga concentration of 37% or more. The thin film field effect transistor of claim 1, wherein the source and the drain are composed of molybdenum or a molybdenum alloy. The thin film field effect transistor of claim 1, wherein the active layer and the etch stop layer have the same shape. The thin film field effect transistor according to any one of claims 1 to 4, wherein the thin film field effect transistor is a top contact type lower gate structure. The thin film field effect transistor according to any one of claims 1 to 4, wherein the thin film field effect transistor is a top contact type upper gate structure. Method for manufacturing thin film field effect transistor, said thin film field effect electric Forming at least a gate, an insulating film, an active layer, an etch stop layer, a source, and a drain on the substrate, and forming the etch stop layer on the active layer to form on the etch stop layer The source and the drain, the manufacturing method characterized by having a process of forming the source and the drain using an aqueous mixed acid solution containing phosphoric acid, acetic acid, and nitric acid as an etching solution; The etch barrier layer is composed of an amorphous oxide containing In, Ga, and Zn having a Zn concentration of less than or equal to 14.6%; the active layer is composed of an amorphous oxide semiconductor containing In, Ga, and Zn, and the Zn concentration is higher than The Zn concentration of the etch barrier layer. The method for producing a thin film field effect transistor according to claim 7, wherein the etching barrier layer has an In concentration of 40% or more and a Ga concentration of 37% or more. The method for producing a thin film field effect transistor according to claim 7, wherein the mixed acid aqueous solution comprises 70% by mass to 75% by mass of phosphoric acid, 5% by mass to 10% by mass of acetic acid, and 1% by mass to 55%. Mass % of nitric acid. The method of producing a thin film field effect transistor according to claim 7, wherein the active layer and the etch barrier layer form the same shape. The method for producing a thin film field effect transistor according to any one of the preceding claims, wherein, before the process of forming the source and the drain, the process is as follows: Forming the gate on the substrate; forming on the substrate a process of forming the insulating film to cover the gate; a process of forming the active layer on the insulating film; and a process of forming the etch stop layer on the active layer; forming the source And in the process of the drain, the source and the drain are formed on the substrate to cover a portion of the etch barrier. The method of manufacturing a thin film field effect transistor according to claim 11, wherein after the process of forming the source and the drain, a protective layer is formed on the substrate to cover the etching a process of blocking the layer, the source, and the drain. The method for producing a thin film field effect transistor according to any one of the preceding claims, wherein, before the process of forming the source and the drain, the process is as follows: a process of forming the active layer on the substrate; and a process of forming the etch stop layer on the active layer; forming a process on the substrate in a process of forming the source and the drain The source electrode and the drain electrode cover a portion of the etch barrier layer; after the process of forming the source electrode and the drain electrode, having a process of forming the insulating film on the substrate, a process of covering the etch stop layer, the source and the drain; and a process of forming the gate on the insulating film.