TWI508259B - Stacked multi-chip package structure - Google Patents

Stacked multi-chip package structure Download PDF

Info

Publication number
TWI508259B
TWI508259B TW100103398A TW100103398A TWI508259B TW I508259 B TWI508259 B TW I508259B TW 100103398 A TW100103398 A TW 100103398A TW 100103398 A TW100103398 A TW 100103398A TW I508259 B TWI508259 B TW I508259B
Authority
TW
Taiwan
Prior art keywords
chip package
spacer
package structure
wafer block
stacked multi
Prior art date
Application number
TW100103398A
Other languages
Chinese (zh)
Other versions
TW201201352A (en
Inventor
Tae-Shin Kang
Seung-Yup Yoo
Sang-Hak Chung
Original Assignee
Fci Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fci Inc filed Critical Fci Inc
Publication of TW201201352A publication Critical patent/TW201201352A/en
Application granted granted Critical
Publication of TWI508259B publication Critical patent/TWI508259B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Description

堆疊多晶片封裝結構Stacked multi-chip package structure

本發明涉及一種在以疊層方式進行佈局的多晶片封裝結構中插入隔片作為其中疊層的堆疊多晶片封裝結構。The present invention relates to a stacked multi-chip package structure in which a spacer is interposed in a multi-chip package structure laid out in a stacked manner.

一般情況下,藉由將晶片塊整齊地進行佈局的形式與以堆疊(stack)進行佈局的形式等,製作出多種形態的多晶片封裝(multi-chip Package)形式的封裝產品,但在實現疊層形式的結構時,會出現因打線接合而引起的各種問題。In general, a package product in the form of a multi-chip package of various forms is produced by neatly laying out a wafer block in a form of layout and stacking in a stack, etc. In the case of a layer-form structure, various problems due to wire bonding occur.

其中最大的問題就是將比下部(bottom)晶片塊的尺寸小很多的晶片塊堆成疊層的情況下,在打線接合上部(top)晶片塊時,用於接合的打線的長度變長,且打線接合的角度變小,因此在打線接合後的程序,即成型(mold)程序中,會產生打線偏移(sweeping)等的問題,由此對多晶片封裝的製作及量產上造成困難。The biggest problem of this is that in the case of stacking wafer blocks which are much smaller than the size of the bottom wafer block, the length of the wire for bonding becomes long when wire bonding the top wafer block, and Since the angle of the wire bonding is small, there is a problem in the process of wire bonding, that is, a molding process, such as sweeping, which causes difficulty in production and mass production of the multi-chip package.

而且,隨著打線接合時用於接合的打線長度變長會造成組裝單價上升的問題,並且接合的打線變長所引起的電阻(resistance)及電感(inductance)的增加,會在導致晶片電氣性能下降的問題。Moreover, as the length of the wire for joining at the time of wire bonding becomes longer, the problem of an increase in the unit price of the assembly, and the increase in resistance and inductance caused by the lengthening of the bonding wire may cause deterioration of electrical properties of the wafer. The problem.

換言之,將比下部晶片塊的尺寸小很多的晶片塊疊置於上部時,在打線接合上部晶片塊時的打線長度會變長,由此會出現各種問題。In other words, when the wafer block which is much smaller than the size of the lower wafer block is stacked on the upper portion, the length of the wire bonding when the upper wafer block is bonded by wire bonding becomes long, and various problems occur.

圖1至3顯示存在問題的現有技術的多晶片封裝結構之示意圖。1 to 3 show schematic views of a prior art multi-chip package structure in question.

圖1為現有的堆疊多晶片封裝結構的截面圖;圖2為圖1的結構的平面圖;圖3為顯示進行打線接合時的問題的平面圖及截面圖。1 is a cross-sectional view of a conventional stacked multi-chip package structure; FIG. 2 is a plan view of the structure of FIG. 1; and FIG. 3 is a plan view and a cross-sectional view showing a problem when wire bonding is performed.

如圖1至圖3所示,堆疊多晶片封裝結構,其底部的封裝印刷電路板(PCB)10上面的一個點80與下部晶片塊20及上部晶片塊30上面的一個點通過打線70接合而進行電氣連接,其中與下部晶片塊20的打線接合不存在問題,但與尺寸最小的上部晶片塊30進行打線接合時,打線70的長度會變得過長,從而變長的打線70的偏移(sweeping)現象會引起上述各種問題。As shown in FIGS. 1 through 3, a stacked multi-chip package structure has a dot 80 on the bottom of the package printed circuit board (PCB) 10 and a point on the lower wafer block 20 and the upper wafer block 30 joined by a wire 70. Electrical connection is made in which there is no problem in the wire bonding with the lower wafer block 20, but when the wire bonding is performed with the smallest wafer block 30 having the smallest size, the length of the wire 70 becomes too long, so that the length of the wire 70 is shifted. The phenomenon of "sweeping" causes various problems as described above.

為了解決上述的現有的問題,本發明的主要目的在於提供一種堆疊多晶片封裝結構,在將尺寸小於下部晶片塊的上部晶片塊進行堆疊的情況下進行打線接合時,能夠解決由於打線長度增加而引起的現有的多晶片封裝結構所存在的問題。In order to solve the above-mentioned problems, it is a primary object of the present invention to provide a stacked multi-chip package structure capable of solving an increase in wire length when wire bonding is performed in a case where an upper wafer block having a size smaller than that of a lower wafer block is stacked. The resulting problems with existing multi-chip package structures.

用於解決上述現有的問題,且達成本發明的技術課題的堆疊多晶片封裝結構,是從底部將封裝PCB、下部晶片塊(bottom die)、上部晶片塊(top die)進行堆疊,並進行打線接合以用於層間的電氣連接,所述堆疊多晶片封裝(multi-chip package)結構,其特徵在於,在所述下部晶片塊上面形成具有金屬層的隔片,所述隔片一方面與所述封裝PCB進行打線接合,另一方面與所述上部晶片塊進行打線接合。A stacked multi-chip package structure for solving the above-mentioned problems and achieving the technical problem of the present invention is to stack a package PCB, a bottom die, and a top die from the bottom, and perform wire bonding. Bonded for electrical connection between layers, the stacked multi-chip package structure, characterized in that a spacer having a metal layer is formed on the lower wafer block, the spacer being on the one hand The package PCB is wire bonded and, on the other hand, wire bonded to the upper wafer block.

其中所述隔片使用FR4材質的PCB或仿真矽。The spacer is made of FR4 material PCB or simulation 矽.

又,為了可以在所述下部晶片塊的上面一側進行打線接合的操作,使所述隔片的大小大於所述上部晶片塊而小於所述下部晶片塊。Further, in order to perform a wire bonding operation on the upper surface side of the lower wafer block, the size of the spacer is made larger than the upper wafer block and smaller than the lower wafer block.

此外,為了能改善接合特性,在所述金屬層進行鍍金(gold plating)。Further, in order to improve the bonding characteristics, gold plating is performed on the metal layer.

甚且,使用防焊料而使得需要所述鍍金(gold plating)的部分達到最小化,實現程序的優化。Moreover, the use of anti-solder minimizes the need for the gold plating portion to achieve program optimization.

再者,所述隔片的上面形成有接地(GND)接合面及信號跟蹤網(signal trace net)的路由(routing)圖案。Furthermore, a grounding (GND) bonding surface and a routing pattern of a signal trace net are formed on the upper surface of the spacer.

如上所述根據本發明形成的堆疊多晶片封裝結構,在結構上的效果在於:改善打線接合的長度及接合角度,從而可以適用原本不能以疊層方式製作的小尺寸晶片塊,且在打線接合後的成型(mold)程序時對於打線接合的偏移現象具有改善效果。The stacked multi-chip package structure formed according to the present invention as described above has a structural effect in that the length of the wire bonding and the bonding angle are improved, so that a small-sized wafer block which cannot be fabricated in a laminated manner can be applied, and the wire bonding is performed. The subsequent mold process has an effect of improving the offset phenomenon of the wire bonding.

在電氣性能上的改善效果在於:藉由形成偽接地(GND)金屬層而減少接地(ground)電感及電阻,對於信號線(signal line)方面也能實現阻抗的控制及遮罩(shielding)的功效。The improvement in electrical performance is to reduce the ground inductance and resistance by forming a pseudo ground (GND) metal layer, and to achieve impedance control and shielding for the signal line. efficacy.

以下將參照附圖對根據本發明的堆疊多晶片封裝結構的實施例進行詳細說明。Embodiments of the stacked multi-chip package structure according to the present invention will be described in detail below with reference to the accompanying drawings.

圖4為疊置有根據本發明的隔片的多晶片封裝結構的一實施例;圖5為使用根據本發明的隔片作為接地(GND)面時的電阻改善效果的示意圖;圖6為使用根據本發明的隔片作為GND面時的電感改善效果的示意圖;圖7為顯示將根據本發明的隔片上面作為路由而使用的情況下,信號網(signal net)具有20%的電阻改善效果的示意圖;圖8為顯示將根據本發明的隔片上面作為路由而使用的情況下,信號(signal)具有15%的電感改善效果的示意圖;圖9為將根據本發明的隔片的整個上面作為GND金屬而使用的情況下的堆疊多晶片封裝結構的平面圖及截面圖;圖10為將根據本發明的隔片上面作為路由及GND面而使用的多晶片封裝結構的平面圖及截面圖。4 is an embodiment of a multi-chip package structure in which a spacer according to the present invention is stacked; FIG. 5 is a schematic view showing an effect of improving resistance when a spacer according to the present invention is used as a ground (GND) surface; A schematic diagram of the effect of improving the inductance of the spacer according to the present invention as a GND plane; and FIG. 7 is a diagram showing a signal net having a resistance improvement effect of 20% in the case where the upper surface of the spacer according to the present invention is used as a route. FIG. 8 is a schematic diagram showing a signal having a 15% inductance improvement effect in the case where the spacer according to the present invention is used as a route; FIG. 9 is the entire upper surface of the spacer according to the present invention; A plan view and a cross-sectional view of a stacked multi-chip package structure in the case of being used as a GND metal; and FIG. 10 is a plan view and a cross-sectional view of a multi-chip package structure used as a route and a GND plane of the spacer according to the present invention.

首先參照圖4,對根據本發明的多晶片封裝(multi-chip package)結構的一實施例進行詳細說明。Referring first to Figure 4, an embodiment of a multi-chip package structure in accordance with the present invention will be described in detail.

如圖所示,從底面依次疊置有封裝印刷電路板(PCB)100、下部晶片塊(bottom die)200、上部晶片塊(top die)300,且實施了用於電氣連接的打線接合,構成一般的堆疊多晶片封裝結構,其中,本發明在所述下部晶片塊200上形成一隔片400,所述隔片形成有金屬層410。即,隔片以板狀的形狀位於下部晶片塊200與上部晶片塊300之間。As shown in the figure, a package printed circuit board (PCB) 100, a bottom die 200, an upper die 300 are stacked in this order from the bottom surface, and a wire bonding for electrical connection is implemented. A typical stacked multi-chip package structure in which the present invention forms a spacer 400 on the lower wafer block 200, the spacer being formed with a metal layer 410. That is, the spacer is located between the lower wafer block 200 and the upper wafer block 300 in a plate shape.

所述隔片400一方面與所述封裝PCB 100進行打線接合,另一方面與所述上部晶片塊300進行打線接合。此乃本發明的核心技術思想,其能解決現有技術中對封裝PCB 100與上部晶片塊300進行打線接合時,因接合打線700的長度過長而出現的問題。The spacer 400 is wire bonded to the package PCB 100 on the one hand and to the upper wafer block 300 on the other hand. This is the core technical idea of the present invention, which solves the problem that the length of the bonding wire 700 is too long when the package PCB 100 and the upper wafer block 300 are wire bonded in the prior art.

其中,疊置的所述隔片400的材質較佳使用FR4材質的PCB或者仿真矽。The material of the stacked spacers 400 is preferably a FR4 PCB or a dummy 矽.

並且,為了可以在所述下部晶片塊200的上側進行打線接合的操作,所述隔片400的大小大於所述上部晶片塊300而小於所述下部晶片塊200,佈局及構成要確保與所述下部晶片塊200打線接合的區域。Moreover, in order to perform the wire bonding operation on the upper side of the lower wafer block 200, the size of the spacer 400 is larger than the upper wafer block 300 and smaller than the lower wafer block 200, and the layout and composition are to be ensured and The lower wafer block 200 is wire bonded.

另一方面,為了增進打線接合的特性,較佳為在所述金屬層410上實施鍍金(gold plating),從而提高電氣連接效率,改善電氣性能。On the other hand, in order to improve the characteristics of the wire bonding, gold plating is preferably performed on the metal layer 410 to improve electrical connection efficiency and improve electrical performance.

其中,當所述鍍金(gold plating)量較多的情況下,較佳為使用防焊料而使需要鍍金的部分達到最小化,從而實現電鍍優化。Wherein, in the case where the amount of the gold plating is large, it is preferable to minimize the portion requiring gold plating by using the anti-solder, thereby achieving electroplating optimization.

據此,將所述隔片400對封裝PCB 100與下部晶片塊200以打線接合程序進行連接,從而可以縮短接合於上部晶片塊300的打線700的長度,從而可以改善現有接合程序上的問題,且電氣性能也可以倍增。Accordingly, the spacer 400 is connected to the package PCB 100 and the lower wafer block 200 by a wire bonding process, so that the length of the wire bonding 700 bonded to the upper wafer block 300 can be shortened, so that problems in the existing bonding process can be improved. And the electrical performance can also be multiplied.

圖5至圖8為採用根據本發明的多晶片封裝結構時在電氣性能上的改善效果示意圖。5 to 8 are schematic views showing an improvement in electrical performance when a multi-chip package structure according to the present invention is employed.

如圖5所示,使用隔片400作為接地(GND)面時平均可帶來70%的電阻改善,圖6為顯示使用隔片400作為GND面時平均可帶來70%的電感改善效果的示意圖。As shown in FIG. 5, when the spacer 400 is used as the ground (GND) plane, the average resistance can be improved by 70%, and FIG. 6 shows that the average improvement of the inductance can be 70% when the spacer 400 is used as the GND plane. schematic diagram.

即,可以知道藉由打線接合隔片而進行電氣連接時,其電氣特性與現有的堆疊多晶片封裝結構相比具有較大的改善。That is, it can be known that when the electrical connection is made by bonding the spacers by wire bonding, the electrical characteristics thereof are greatly improved as compared with the conventional stacked multi-chip package structure.

圖7中可以確認在將隔片400的上面作為路由(routing)而使用的情況下,對信號網(signal net)具有20%的電阻改善效果,圖8中可以確認在將隔片400的上面作為路由而使用的情況下,對信號(signal)具有15%的電感改善效果。In Fig. 7, it can be confirmed that when the upper surface of the spacer 400 is used as a routing, the signal net has a resistance improvement effect of 20%, and in Fig. 8, it can be confirmed that the spacer 400 is on the upper side. When used as a route, it has a 15% inductance improvement effect on a signal.

如上所述,將隔片400疊置於下部晶片塊200上的結構,可以使電氣特性倍增,這能解決被打線接合的打線700長度變長所引起的現有的堆疊多晶片封裝結構存在的缺點。As described above, the structure in which the spacers 400 are stacked on the lower wafer block 200 can multiply the electrical characteristics, which can solve the disadvantages of the existing stacked multi-chip package structure caused by the lengthening of the wire bonding wires 700 being lengthened.

接著,參照圖9至圖10,對根據本發明的堆疊多晶片封裝結構的實施例進行說明。Next, an embodiment of a stacked multi-chip package structure according to the present invention will be described with reference to FIGS. 9 to 10.

首先,準備一大小不會對下部晶片塊200的打線接合程序產生問題的隔片400。這是為了露出下部晶片塊200的接合區域,從而使得封裝PCB 100的接合端子800與下部晶片塊200的上面一點能進行打線接合。First, a spacer 400 of a size that does not cause a problem with the wire bonding process of the lower wafer block 200 is prepared. This is to expose the bonding region of the lower wafer block 200 so that the bonding terminal 800 of the package PCB 100 and the upper surface of the lower wafer block 200 can be wire bonded.

在一般情況下,較佳而言,所製作的隔片與打線接合板相比存在300 μm至500 μm的小偏移量(offset),且其厚度越薄越好。In general, it is preferable that the spacer produced has a small offset of 300 μm to 500 μm as compared with the wire bonding plate, and the thinner the thickness, the better.

接下來,為了能對該隔片400進行打線接合,在隔片400上形成金屬。在這種情況下,為了提高接合特性,一般在金屬層410上進行鍍金(gold plating)的操作,而此鍍金(gold plating)的厚度越厚越好。Next, in order to enable wire bonding of the spacer 400, metal is formed on the spacer 400. In this case, in order to improve the bonding characteristics, a gold plating operation is generally performed on the metal layer 410, and the thickness of the gold plating is as thick as possible.

另一方面,在需要鍍金(gold plating)的量較多的情況下,較佳為使用防焊料來使得需要鍍金的部分達到最小化,從而實現電鍍的優化。On the other hand, in the case where a large amount of gold plating is required, it is preferable to use anti-solder to minimize the portion requiring gold plating, thereby achieving optimization of electroplating.

參照圖9與圖10,對根據所述本發明的堆疊多晶片封裝結構的實施例進行說明。An embodiment of a stacked multi-chip package structure according to the present invention will be described with reference to FIGS. 9 and 10.

作為一實施例,如果僅以金屬層410作為接地強化之目的時,如圖9所示,在隔片400的整個上面形成金屬,並將所述金屬作為接地面而使用。As an embodiment, if only the metal layer 410 is used for the purpose of grounding reinforcement, as shown in FIG. 9, a metal is formed on the entire upper surface of the spacer 400, and the metal is used as a ground plane.

作為另一實施例,需要同時改善信號線及打線接合的角度(angle)的情況下,如圖10所示,在隔片400上面形成GND接合面及信號跟蹤網(signal trace net)的路由圖案900。As another embodiment, in the case where it is necessary to simultaneously improve the angle of the signal line and the wire bonding, as shown in FIG. 10, a routing pattern of the GND bonding surface and the signal trace net is formed on the spacer 400. 900.

如上所述的本發明雖然是依據被限定的實施例與附圖而進行了說明,但對本說明書及請求保護範圍中所使用的術語和詞語的解釋不能被限於通常的意義和詞典上的意義,應以符合本發明的技術思想的意義和概念來進行解釋。The invention as described above has been described in terms of the limited embodiments and the drawings, but the explanation of the terms and words used in the specification and the claims are not limited to the ordinary meaning and the meaning of the dictionary. The meaning and concept of the technical idea of the present invention should be explained.

從而,本說明書中所記載的實施例與附圖中所示意的結構僅為本發明的最佳實施例,並不能代表本發明的整個技術思想,因此需要瞭解的是從本申請的角度出發有多種等同物和變換的事例可以代替上述實施例。Therefore, the embodiments described in the present specification and the drawings are merely preferred embodiments of the present invention, and are not representative of the entire technical idea of the present invention. Therefore, it is necessary to understand that from the perspective of the present application. A variety of equivalents and variants can be substituted for the above embodiments.

10...封裝印刷電路板(PCB)10. . . Package printed circuit board (PCB)

20...下部晶片塊20. . . Lower wafer block

30...上部晶片塊30. . . Upper wafer block

40...隔片40. . . bead

70...打線70. . . Line

80‧‧‧點80‧‧‧ points

100‧‧‧封裝印刷電路板(PCB)100‧‧‧Package Printed Circuit Board (PCB)

200‧‧‧下部晶片塊200‧‧‧lower wafer block

300‧‧‧上部晶片塊300‧‧‧Upper wafer block

400‧‧‧隔片(spacer)400‧‧‧Separator (spacer)

410‧‧‧金屬層410‧‧‧metal layer

700‧‧‧打線(wire)700‧‧‧wire

800‧‧‧接合端子800‧‧‧Join terminal

圖1為現有的堆疊多晶片封裝結構的截面圖;1 is a cross-sectional view of a conventional stacked multi-chip package structure;

圖2為圖1的結構的平面圖;Figure 2 is a plan view of the structure of Figure 1;

圖3為用於顯示打線接合的問題的平面圖及截面圖;Figure 3 is a plan view and a cross-sectional view for showing a problem of wire bonding;

圖4為顯示疊置有根據本發明的隔片的多晶片封裝結構的一實施例;4 is an embodiment showing a multi-chip package structure in which a spacer according to the present invention is stacked;

圖5為使用根據本發明的隔片作為接地面時的電阻改善效果的示意圖;Figure 5 is a schematic view showing the effect of improving electric resistance when the separator according to the present invention is used as a ground plane;

圖6為使用根據本發明的隔片作為接地面時的電感改善效果的示意圖;Figure 6 is a schematic view showing the effect of improving the inductance when the spacer according to the present invention is used as a ground plane;

圖7為顯示將根據本發明的隔片上面作為路由而使用的情況下,信號網(signal net)具有20%的電阻改善效果的示意圖;Figure 7 is a view showing a signal net having a resistance improvement effect of 20% in the case where the spacer according to the present invention is used as a route;

圖8為顯示將根據本發明的隔片上面作為路由而使用的情況下,信號(signal)具有15%的電感改善效果的示意圖;Figure 8 is a view showing a signal having a 15% inductance improvement effect in the case where the spacer according to the present invention is used as a route;

圖9為顯示將根據本發明的隔片的整個上面作為接地金屬而使用的情況下的堆疊多晶片封裝結構的平面圖及截面圖;Figure 9 is a plan view and a cross-sectional view showing a stacked multi-chip package structure in the case where the entire upper surface of the spacer according to the present invention is used as a ground metal;

圖10為將根據本發明的隔片上面作為路由及接地面而使用的多晶片封裝結構的平面圖及截面圖。Figure 10 is a plan view and a cross-sectional view of a multi-chip package structure used as a routing and ground plane on the top of the spacer according to the present invention.

10...封裝印刷電路板(PCB)10. . . Package printed circuit board (PCB)

20...下部晶片塊20. . . Lower wafer block

30...上部晶片塊30. . . Upper wafer block

40...隔片40. . . bead

70...打線70. . . Line

Claims (6)

一種堆疊多晶片封裝結構,從底部起疊置有封裝印刷電路板(PCB)、下部晶片塊(bottom die)、上部晶片塊(top die),並實施了用於層間電氣連接的打線接合,所述堆疊多晶片封裝(multi-chip package)結構,其特徵在於:在所述下部晶片塊形成一隔片,所述隔片形成有金屬層,所述隔片一方面與所述封裝PCB的上面進行打線接合,另一方面與所述上部晶片塊的上面進行打線接合。 A stacked multi-chip package structure in which a package printed circuit board (PCB), a bottom die die, an upper die die are stacked from the bottom, and wire bonding for interlayer electrical connection is implemented. A stacked multi-chip package structure, characterized in that a spacer is formed on the lower wafer block, the spacer is formed with a metal layer, and the spacer is on the one hand and the upper surface of the package PCB Wire bonding is performed, and on the other hand, wire bonding is performed on the upper surface of the upper wafer block. 如申請專利範圍第1項所述的堆疊多晶片封裝結構,其中所述隔片使用FR4材質的PCB或者仿真(dummy)矽。 The stacked multi-chip package structure of claim 1, wherein the spacer uses a FR4 material PCB or a dummy 矽. 申請專利範圍第2項所述的堆疊多晶片封裝結構,其中為了可以在所述下部晶片塊的上側進行打線接合的操作,所述隔片的大小係大於所述上部晶片塊而小於所述下部晶片塊。 The stacked multi-chip package structure of claim 2, wherein the spacer is larger in size than the upper wafer block than the lower portion in order to perform wire bonding operation on an upper side of the lower wafer block Wafer block. 如申請專利範圍第1至3項其中任一項所述的堆疊多晶片封裝結構,其中為了能改善接合特性,對所述金屬層進行鍍金(gold plating)。 The stacked multi-chip package structure according to any one of claims 1 to 3, wherein the metal layer is gold plated in order to improve bonding characteristics. 如申請專利範圍第4項所述的堆疊多晶片封裝結構,其中使用防焊料而使得需要鍍金的部分達到最小化,從而實現電鍍的優化。 The stacked multi-chip package structure of claim 4, wherein the use of solder resisting minimizes the need for gold plating to optimize plating. 如申請專利範圍第5項所述的堆疊多晶片封裝結構,其中在所述隔片的上面形成接地(GND)接合面及信號跟蹤網(signal trace net)的路由(routing)圖案,從而改善信號線(signal line) 及打線接合的角度(angle)。 The stacked multi-chip package structure of claim 5, wherein a ground (GND) bonding surface and a signal trace net routing pattern are formed on the spacer to improve the signal. Signal line And the angle at which the wire is joined.
TW100103398A 2010-06-18 2011-01-28 Stacked multi-chip package structure TWI508259B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100057946A KR20110137926A (en) 2010-06-18 2010-06-18 Stacked multi chip package structure

Publications (2)

Publication Number Publication Date
TW201201352A TW201201352A (en) 2012-01-01
TWI508259B true TWI508259B (en) 2015-11-11

Family

ID=45336674

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100103398A TWI508259B (en) 2010-06-18 2011-01-28 Stacked multi-chip package structure

Country Status (3)

Country Link
KR (1) KR20110137926A (en)
CN (1) CN102290401A (en)
TW (1) TWI508259B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040140552A1 (en) * 2003-01-22 2004-07-22 Renesas Technology Corp. Semiconductor device
US20040195667A1 (en) * 2003-04-04 2004-10-07 Chippac, Inc Semiconductor multipackage module including processor and memory package assemblies
US20080174000A1 (en) * 2007-01-19 2008-07-24 Yu-Ren Chen Zigzag-stacked package structure
US20080220563A1 (en) * 2005-06-20 2008-09-11 Marcos Karnezos Module having stacked chip scale semiconductor packages
US20090294941A1 (en) * 2008-05-30 2009-12-03 Oh Jihoon Package-on-package system with heat spreader

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002217354A (en) * 2001-01-15 2002-08-02 Shinko Electric Ind Co Ltd Semiconductor device
CN1295766C (en) * 2003-05-29 2007-01-17 财团法人工业技术研究院 Electronic sealer with three-dimensional stack and assembling method thereof
US7528494B2 (en) * 2005-11-03 2009-05-05 International Business Machines Corporation Accessible chip stack and process of manufacturing thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040140552A1 (en) * 2003-01-22 2004-07-22 Renesas Technology Corp. Semiconductor device
US20040195667A1 (en) * 2003-04-04 2004-10-07 Chippac, Inc Semiconductor multipackage module including processor and memory package assemblies
US20080220563A1 (en) * 2005-06-20 2008-09-11 Marcos Karnezos Module having stacked chip scale semiconductor packages
US20080174000A1 (en) * 2007-01-19 2008-07-24 Yu-Ren Chen Zigzag-stacked package structure
US20090294941A1 (en) * 2008-05-30 2009-12-03 Oh Jihoon Package-on-package system with heat spreader

Also Published As

Publication number Publication date
CN102290401A (en) 2011-12-21
TW201201352A (en) 2012-01-01
KR20110137926A (en) 2011-12-26

Similar Documents

Publication Publication Date Title
JP6958525B2 (en) Inductor parts
TWI297184B (en) A semiconductor device and a method of manufacturing the same
JP2005175434A5 (en)
TWI570877B (en) Multi-component chip package structure
US9999125B2 (en) Method for fabricating ceramic insulator for electronic packaging
JP2006253289A5 (en)
JP2012054264A5 (en)
KR102064073B1 (en) Inductor
JPWO2015178136A1 (en) Coil component and module including the coil component
CN103650135B (en) Semiconductor device
JP2021009938A5 (en)
JP2011181697A (en) Semiconductor package, and method of manufacturing the same
JP6245249B2 (en) Electronic component package
WO2020224480A1 (en) Package capable of preventing layered channeling of tin and manufacturing method therefor
WO2014203739A1 (en) Semiconductor device and method for manufacturing same
TWI508259B (en) Stacked multi-chip package structure
CN104465580A (en) Semiconductor package
CN102244972A (en) Circuit board and application thereof
US7919715B2 (en) Circuit board ready to slot
JP2015225869A (en) Semiconductor device
TW201822322A (en) Flip-chip package rectification/protection diode element with multiple chip stacks capable of reducing the height of diode element and extending the number of flip-chips based on voltage resistance requirements
CN105870025A (en) Electronic packaging structure making method
US20240063107A1 (en) Crack arrest features for miultilevel package substrate
CN103137498B (en) Semiconductor package and preparation method thereof
KR102512587B1 (en) Inductor and its manufacturing method

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees