CN105870025A - Method for manufacturing electronic packaging structure - Google Patents
Method for manufacturing electronic packaging structure Download PDFInfo
- Publication number
- CN105870025A CN105870025A CN201510026897.XA CN201510026897A CN105870025A CN 105870025 A CN105870025 A CN 105870025A CN 201510026897 A CN201510026897 A CN 201510026897A CN 105870025 A CN105870025 A CN 105870025A
- Authority
- CN
- China
- Prior art keywords
- preparation
- insulating barrier
- bearing part
- package structure
- line layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 9
- 238000004100 electronic packaging Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000004888 barrier function Effects 0.000 claims description 37
- 238000002360 preparation method Methods 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 239000000084 colloidal system Substances 0.000 claims description 18
- 238000012856 packing Methods 0.000 claims description 17
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000009747 press moulding Methods 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 6
- 238000005336 cracking Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 241000218202 Coptis Species 0.000 description 1
- 235000002991 Coptis groenlandica Nutrition 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Electroplating Methods And Accessories (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A method for preparing electronic package structure includes plating multiple conductive columns on a carrying element, forming insulating layer on said carrying element and said conductive columns, forming circuit layer on said insulating layer, setting electronic element on said circuit layer, removing said carrying element, forming said conductive columns by plating growth mode to obtain more precise fine-spacing and strong-structure circuit layer and to reduce problem of cracking of said insulating layer caused by uneven stress.
Description
Technical field
The present invention relates to a kind of encapsulation technology, the preparation method of a kind of electron package structure.
Background technology
Flourish along with electronic industry, electronic product is the most gradually marched toward multi-functional, high-performance
Trend.Need to meet the encapsulation of semiconductor package part miniaturization (miniaturization)
Ask, towards the thickness development of the base plate for packaging reducing bearing wafer.
Figure 1A to Fig. 1 F is the semiconductor package part 1 of existing seedless central layer (coreless)
The cross-sectional schematic of preparation method.
As shown in Figure 1A, it is provided that just like the metal support plate 10 of copper, this metal support plate 10 has phase
To the first side 10a and the second side 10b.
As shown in Figure 1B, carry out half-etching processing procedure, remove the of this metal support plate 10 with etching
The part material of side 10a, to form multiple groove 100 and relative conductive pole 11.
As shown in Figure 1 C, in this groove 100, fill the first packing colloid 12, and make those lead
Electricity post 11 exposes to this first packing colloid 12.
As shown in figure ip, on this first packing colloid 12 with conductive pole 11, plating forms a line
Road floor 13, forms a surface-treated layer 14, wherein, this line layer on this line layer 13
13 have and multiple put brilliant pad 131 and multiple electric connection pads 130.
As referring to figure 1e, semiconductor wafer 15 is connect and is placed in this and puts on brilliant pad 131, and profit
It is electrically connected with this semiconductor wafer 15 and this electric connection pad 130 with multiple bonding wires 16.Afterwards,
On this first packing colloid 12 and this line layer 13, form this semiconductor wafer 15 of cladding and be somebody's turn to do
Second packing colloid 17 of a little bonding wires 16.
As shown in fig. 1f, etching removes the material of the second side 10b of this metal support plate 10, with
Expose outside on the downside of those conductive poles 11 and on the downside of this first packing colloid 12.Afterwards, in respectively should
Plant multiple soldered ball 18 on the downside of conductive pole 11, and carry out singulation operation.
But, in the preparation method of existing semiconductor package part 1, half-etching processing procedure cannot be produced
The line layer 13 of more accurate thin space (fine pitch), and after half-etching processing procedure, enter
When row makes this first packing colloid 12, this first packing colloid 12 wayward is inserted each
The amount of individual groove 100, so the problem that unbalanced stress can occur and rupture (crack).
Therefore, how to overcome the variety of problems of above-mentioned prior art, become to desire most ardently solution at present in fact
Problem.
Summary of the invention
In view of the disadvantages of above-mentioned prior art, the present invention provides a kind of electron package structure
Preparation method, to obtain more accurate thin space and the strong line layer of structure, and can reduce this insulating barrier
There is unbalanced stress and the problem that ruptures.
The preparation method of the electron package structure of the present invention includes: plate out multiple conductive pole in a bearing part
On；Formation insulating barrier is on this bearing part with those conductive poles, and this insulating barrier has relative
First surface and second surface, and be incorporated on this bearing part with this second surface；Form circuit
Layer is on the first surface of this insulating barrier, and this line layer is electrically connected with those conductive poles；Arrange
At least one electronic component is on this line layer, and this electronic component is electrically connected with this line layer；With
And remove this bearing part, make the end face of this conductive pole expose to the second surface of this insulating barrier.
In aforesaid preparation method, after removing this bearing part, form a surface-treated layer in this conduction
On the end face of post.
The present invention also provides for the preparation method of a kind of electron package structure, including: plate out multiple conductive pole
On a bearing part；Formation insulating barrier is on this bearing part with those conductive poles, and this insulating barrier
There is relative first surface and second surface, and be incorporated on this bearing part with this second surface；
Formation line layer is on the first surface of this insulating barrier, and this line layer is electrically connected with those conductions
Post；Remove this bearing part, make the end face of this conductive pole expose to the second surface of this insulating barrier；
And setting at least one electronic component is on this line layer, and this electronic component is electrically connected with this line
Road floor.
In aforesaid preparation method, before this electronic component is set, forms a surface-treated layer and lead in this
On the end face of electricity post.
In aforesaid two kinds of preparation methods, this bearing part has a plate body, to be respectively arranged on this plate body relative
The first metal layer of both sides and the second metal level.
In aforesaid two kinds of preparation methods, this insulating barrier is to mold the packing colloid that processing procedure makes.
In aforesaid two kinds of preparation methods, the other end of this conductive pole flushes the first table of this insulating barrier
Face.
In aforesaid two kinds of preparation methods, also it is included in before this electronic component is set, forms a surface
Reason layer is on this line layer.
In aforesaid two kinds of preparation methods, also include forming packing colloid in the first surface of this insulating barrier
On, to be coated with this electronic component.
It addition, in aforesaid two kinds of preparation methods, be also included in after removing this bearing part, arrange multiple
Conducting element is on the second surface of this insulating barrier, and respectively this is led to make those conducting elements be electrically connected with
Electricity post.
From the foregoing, it will be observed that in the preparation method of the electron package structure of the present invention, mainly by plating out growth
Mode forms this conductive pole, to obtain more accurate thin space and the strong line layer of structure, and can
The problem reducing this insulating barrier generation unbalanced stress and rupture.
Accompanying drawing explanation
Figure 1A to Fig. 1 F is the section view signal of the preparation method of the semiconductor package part of existing seedless central layer
Figure；And
Fig. 2 A to Fig. 2 F is the cross-sectional schematic of the preparation method of the electron package structure of the present invention；Its
In, Fig. 2 D ' and the cross-sectional schematic of another embodiment that Fig. 2 E ' is Fig. 2 D and Fig. 2 E.
Symbol description
1 semiconductor package part
10 metal support plates
10a the first side
10b the second side
100 grooves
11,21 conductive poles
12 first packing colloids
13,23 line layers
130,230 electric connection pads
131 put brilliant pad
14,24,24 ' surface-treated layers
15 semiconductor wafers
16 bonding wires
17 second packing colloids
18 soldered balls
2 electron package structures
20 bearing parts
200 plate bodys
201 the first metal layers
202 second metal levels
21a upper surface
21b lower surface
22 insulating barriers
22a first surface
22b second surface
231 conductive traces
25 electronic components
26 conductive projections
27 packing colloids
28 conducting elements.
Detailed description of the invention
By particular specific embodiment, embodiments of the present invention, art technology are described below
Personnel can be understood other advantages and the merit of the present invention easily by content disclosed in the present specification
Effect.
It should be clear that structure depicted in this specification institute accompanying drawings, ratio, size etc., the most only use
In coordinating the content disclosed in description, for understanding and the reading of those skilled in the art, and
Non-for limiting the enforceable qualifications of the present invention, so not having technical essential meaning,
The modification of any structure, the change of proportionate relationship or the adjustment of size, do not affecting institute of the present invention
Under the effect that can produce and the purpose that can reach, all should still fall in disclosed technology
In the range of content obtains and can contain.Meanwhile, in this specification cited as " on ", D score,
Terms such as " first ", " second " and " one ", is also only and is easy to understanding of narration, rather than
For limiting the enforceable scope of the present invention, being altered or modified of its relativeness, without essence
Under change technology contents, when being also considered as the enforceable category of the present invention.
Fig. 2 A to Fig. 2 F is the cross-sectional schematic of the preparation method of the electron package structure 2 of the present invention.
As shown in Figure 2 A, it is provided that a bearing part 20, this bearing part 20 have a plate body 200,
It is respectively arranged on the first metal layer 201 and second metal level 202 of these upper and lower both sides of plate body 200.
In the present embodiment, the material of this plate body 200 is glass material (such as FR4), and this
One and second metal level 201,202 be Copper Foil, make this bearing part 20 as copper clad laminate (Copper
Clad laminate, is called for short CCL).Of a great variety about copper clad laminate, and for industry institute
Know, so repeating no more.
As shown in Figure 2 B, on this first metal layer 201, form patterning photoresistance (figure is slightly),
In this patterning photoresistance plating or the multiple conductive pole 21 such as copper post of formation of deposits in this first
On metal level 201
As shown in Figure 2 C, after removing photoresistance, form an insulating barrier 22 in this first metal layer
201, with on those conductive poles 21, then form a line layer 23 on this insulating barrier 22, and should
Line layer 23 is electrically connected with those conductive poles 21.
In the present embodiment, this insulating barrier 22 is to mold the encapsulation that (molding) processing procedure makes
Colloid, and this insulating barrier 22 has relative first surface 22a and a second surface 22b, and with
This second surface 22b is incorporated on this first metal layer 201.
Additionally, in forming this insulating barrier 22 to cover this first metal layer 201 and those conductive poles
After on 21, can pass through and grind this insulating barrier 22, make those conductive poles 21 expose to this insulating barrier
The first surface 22a of 22, and the upper surface 21a of this conductive pole 21 flushes this insulating barrier 22
First surface 22a.
Also, this line layer 23 has multiple conductive trace 231 and multiple electric connection pads 230.
As shown in Figure 2 D, an electronic component 25 is set on this line layer 23, and this electronics unit
Part 25 is electrically connected with those electric connection pads 230.Then, packing colloid 27 is formed in this insulation
On the first surface 22a of layer 22, to be coated with this electronic component 25.
In the present embodiment, this electronic component 25 is electric by multiple conductive projections 26 such as soldered ball
Property connects those electric connection pads 230.In other embodiments, this electronic component 25 also can mat
It is electrically connected with those electric connection pads 230 by routing (i.e. gold thread, figure is slightly).
Additionally, this electronic component 25 is active member, passive device or a combination thereof person, and this is main
Dynamic element is such as semiconductor wafer, and this passive device is such as resistance, electric capacity and inductance.
In this, this electronic component 25 is active member.
Also, a surface-treated layer 24 can be initially formed on this line layer 23, then this electronics is set
Element 25 is on this line layer 23.
It addition, this surface-treated layer 24 welds film (Organic Solderability for organic guarantor
Preservatives, is called for short OSP), nickel, palladium, gold or silver layer etc..
As shown in Figure 2 E, remove this bearing part 20, make the lower surface 21b of those conductive poles 21
Expose to the second surface 22b of this insulating barrier 22.
In other embodiments, after forming this line layer 23, it is possible to first remove this bearing part
20, as shown in Fig. 2 D ', then form a surface-treated layer 24,24 ' respectively in this line layer 23
With on the lower surface 21b of this conductive pole 21, this electronic component 25 is the most just set and is somebody's turn to do with being formed
Packing colloid 27, as shown in Fig. 2 E '.
As shown in Figure 2 F, multiple conducting element 28 such as soldered ball is set in respectively this conductive pole 21
On the 21b of lower surface.
The preparation method of the present invention plates out conductive pole 21 by such as plating or depositional mode, can make respectively that this is led
Distance between electricity post 21 is less, to obtain more accurate thin space (fine pitch) and structure
Strong line layer 23, and this insulating barrier 22 can be reduced unbalanced stress occurs and the problem that ruptures.
It addition, this line layer 23 can coordinate the pin requirement of this electronic component 25, to design
More preferably wiring (layout).
Above-described embodiment is only used for principle and effect thereof of the illustrative present invention, not for
Limit the present invention.Any those skilled in the art all can be in the spirit and the scope without prejudice to the present invention
Under, above-described embodiment is modified.Therefore the scope of the present invention, should be such as right
Listed by claim.
Claims (10)
1. a preparation method for electron package structure, is characterized by, this preparation method includes:
Plate out multiple conductive pole on a bearing part；
Formation insulating barrier is on this bearing part with those conductive poles, and wherein, this insulating barrier has phase
To first surface and second surface, and be incorporated on this bearing part with this second surface；
Formation line layer is on the first surface of this insulating barrier, and makes the electric connection of this line layer be somebody's turn to do
A little conductive poles；
Setting at least one electronic component is on this line layer, and makes the electric connection of this electronic component be somebody's turn to do
Line layer；And
Remove this bearing part, make the end face of this conductive pole expose to the second surface of this insulating barrier.
2. a preparation method for electron package structure, is characterized by, this preparation method includes:
Plate out multiple conductive pole on a bearing part；
Formation insulating barrier is on this bearing part with those conductive poles, and wherein, this insulating barrier has phase
To first surface and second surface, and be incorporated on this bearing part with this second surface；
Formation line layer is on the first surface of this insulating barrier, and makes the electric connection of this line layer be somebody's turn to do
A little conductive poles；
Remove this bearing part, make the end face of this conductive pole expose to the second surface of this insulating barrier；
And
Setting at least one electronic component is on this line layer, and makes the electric connection of this electronic component be somebody's turn to do
Line layer.
The preparation method of electron package structure the most according to claim 1 and 2, is characterized by,
This bearing part has a plate body, the first metal layer being respectively arranged on this plate body opposite sides and second
Metal level.
The preparation method of electron package structure the most according to claim 1 and 2, is characterized by,
The packing colloid that this insulating barrier is formed with press moulding mode.
The preparation method of electron package structure the most according to claim 1 and 2, is characterized by,
The other end of this conductive pole flushes the first surface of this insulating barrier.
The preparation method of electron package structure the most according to claim 1 and 2, is characterized by,
This preparation method is also included in before arranging this electronic component, forms a surface-treated layer on this line layer.
The preparation method of electron package structure the most according to claim 1, is characterized by, this system
Method is also included in after removing this bearing part, forms a surface-treated layer on the end face of this conductive pole.
The preparation method of electron package structure the most according to claim 2, is characterized by, this system
Method is also included in before arranging this electronic component, forms a surface-treated layer in the end face of this conductive pole
On.
The preparation method of electron package structure the most according to claim 1 and 2, is characterized by,
This preparation method also include formed packing colloid on the first surface of this insulating barrier, to be coated with this electronics
Element.
The preparation method of electron package structure the most according to claim 1 and 2, is characterized by,
This preparation method is also included in after removing this bearing part, arranges multiple conducting element in the of this insulating barrier
On two surfaces, those conducting elements are made to be electrically connected with respectively this conductive pole.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104100214 | 2015-01-06 | ||
| TW104100214A TWI566330B (en) | 2015-01-06 | 2015-01-06 | Method of fabricating an electronic package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105870025A true CN105870025A (en) | 2016-08-17 |
Family
ID=56622833
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510026897.XA Pending CN105870025A (en) | 2015-01-06 | 2015-01-20 | Method for manufacturing electronic packaging structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105870025A (en) |
| TW (1) | TWI566330B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107768320A (en) * | 2016-08-18 | 2018-03-06 | 恒劲科技股份有限公司 | Electronic packing piece and its preparation method |
| CN109004036A (en) * | 2017-06-06 | 2018-12-14 | 财团法人工业技术研究院 | Photoelectric cell packaging body |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140160688A1 (en) * | 2012-12-06 | 2014-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for Package with Interposers |
| CN103871998A (en) * | 2012-12-13 | 2014-06-18 | 珠海越亚封装基板技术股份有限公司 | Single Layer Coreless Substrate |
| US20140290057A1 (en) * | 2013-03-29 | 2014-10-02 | Kinsus Interconnect Technology Corp. | Method of manufacturing a stacked multilayer structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300686B1 (en) * | 1997-10-02 | 2001-10-09 | Matsushita Electric Industrial Co., Ltd. | Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection |
| US20010038140A1 (en) * | 2000-04-06 | 2001-11-08 | Karker Jeffrey A. | High rigidity, multi-layered semiconductor package and method of making the same |
| US8704350B2 (en) * | 2008-11-13 | 2014-04-22 | Samsung Electro-Mechanics Co., Ltd. | Stacked wafer level package and method of manufacturing the same |
| TWI555166B (en) * | 2013-06-18 | 2016-10-21 | 矽品精密工業股份有限公司 | Stack package and method of manufacture |
-
2015
- 2015-01-06 TW TW104100214A patent/TWI566330B/en active
- 2015-01-20 CN CN201510026897.XA patent/CN105870025A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140160688A1 (en) * | 2012-12-06 | 2014-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and Apparatus for Package with Interposers |
| CN103871998A (en) * | 2012-12-13 | 2014-06-18 | 珠海越亚封装基板技术股份有限公司 | Single Layer Coreless Substrate |
| US20140290057A1 (en) * | 2013-03-29 | 2014-10-02 | Kinsus Interconnect Technology Corp. | Method of manufacturing a stacked multilayer structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107768320A (en) * | 2016-08-18 | 2018-03-06 | 恒劲科技股份有限公司 | Electronic packing piece and its preparation method |
| CN109004036A (en) * | 2017-06-06 | 2018-12-14 | 财团法人工业技术研究院 | Photoelectric cell packaging body |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI566330B (en) | 2017-01-11 |
| TW201626500A (en) | 2016-07-16 |
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Application publication date: 20160817 |
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