CN107768320A - Electronic package and manufacturing method thereof - Google Patents

Abstract

The present invention discloses an electronic package and a method for manufacturing the same. The electronic package includes an insulating layer, electronic components and conductive bumps embedded in the insulation, and a circuit structure formed on the insulating layer and electrically connected to the conductive bumps. The board body of the known packaging substrate is avoided to reduce the overall thickness of the electronic package and meet the demand for thinness and lightness.

Description

Electronic package and its manufacturing method

technical field

The invention relates to a semiconductor package technology, in particular to an electronic package and a manufacturing method thereof.

Background technique

With the evolution of semiconductor packaging technology, different packaging types have been developed for semiconductor devices, and flip chip technology has been developed to improve electrical functions and save packaging space.

FIG. 1 is a schematic cross-sectional view of a known semiconductor package 1 . As shown in FIG. 1, the manufacturing method of the semiconductor package 1 firstly provides a package substrate 10 having a board body 10a and a circuit structure 10b, and then combines a semiconductor element 11 on the circuit structure 10b by a flip-chip method, and then forms a package. The glue 13 is on the packaging substrate 10 to cover the semiconductor device 11 .

Specifically, the semiconductor element 11 has an opposite active surface 11a and a non-active surface 11b, the active surface 11a has a plurality of electrode pads 110, so as to electrically connect the electrode pads 110 and the circuit structure through a plurality of solder bumps 12 10b, and the encapsulant 13 is also formed between the semiconductor element 11 and the package substrate 10 to cover the above-mentioned solder bumps 12 .

However, in the known manufacturing process of the semiconductor package 1, when the semiconductor element 11 is of large size or high pin count (high pin count), the flow of the encapsulant 13 is not easy to fill the semiconductor element 11 and the packaging substrate 10 The space between the semiconductor elements 11 and the package substrate 10 creates a void 14, so in the subsequent curing process of the encapsulant 13, the void 14 is prone to popcorn effect, lead to a decline in product yield.

In addition, in the known semiconductor package 1 , since the package substrate 10 has a plate body 10 a, it is difficult to effectively reduce the overall thickness of the semiconductor package 1 , which cannot meet the demand for thinner and lighter electronic products today.

Therefore, how to overcome the defect of the prior art is actually a technical problem that all walks of life desire to solve urgently.

Contents of the invention

In view of the above-mentioned defects in the prior art, the present invention provides an electronic package and a manufacturing method thereof, so as to reduce the overall thickness of the electronic package and meet the demand for thinner and lighter.

The electronic package of the present invention includes: an insulating layer; an electronic component combined with a plurality of conductive bumps embedded in the insulating layer, and part of the surface of the conductive bumps is exposed to the insulating layer; and a circuit structure, It is formed on the insulating layer and the conductive bump is exposed on a part of the surface of the insulating layer and is electrically connected to the conductive bump.

The present invention also provides a method for manufacturing an electronic package, which includes the following steps: setting an electronic component combined with a plurality of conductive bumps on a carrier; forming an insulating layer on the carrier, so that the insulating layer Covering the electronic component, and exposing part of the surface of the conductive bump to the insulating layer; forming a circuit structure on the insulating layer and the part of the surface of the conductive bump exposed on the insulating layer, and making the circuit structure electrically connecting the conductive bump; and removing the carrier.

In the aforementioned electronic package and its manufacturing method, the electronic component has an opposite active surface and a non-active surface, and the active surface is combined with the conductive bump so that the electronic component is electrically connected to the conductive bump. For example, after the carrier is removed, the non-active surface of the electronic component is exposed to the insulating layer; or, the non-active surface of the electronic component is combined with a heat sink.

In the aforementioned electronic package and its manufacturing method, after the carrier is removed, the electronic component is exposed on the insulating layer.

In the aforementioned electronic package and its manufacturing method, the conductive bumps are solder bumps.

The aforementioned electronic package and its manufacturing method also include forming a plurality of conductive elements on the circuit structure.

In addition, the aforementioned electronic package and its manufacturing method also include forming a plurality of conductive pillars in the insulating layer, and the conductive pillars are electrically connected to the circuit structure. For example, after the carrier is removed, the end surfaces of the conductive pillars are exposed to the insulating layer. Further, it also includes connecting an electronic device on the end surface of the conductive column.

It can be seen from the above that the electronic package and its manufacturing method of the present invention have the following advantages and beneficial effects: the electronic packaging of the present invention and its manufacturing method mainly cover the electronic component and the conductive bump with the insulating layer, and then The wiring structure is formed on the insulating layer, so the insulating layer does not need to flow between the electronic component and the wiring structure, so there will be no void between the electronic component and the wiring structure, so compared with the prior art, The invention can effectively improve product yield.

In addition, the electronic package of the present invention only forms a circuit structure without using a known package substrate. Therefore, compared with the prior art, the overall thickness of the electronic package can be greatly reduced to meet the demand for light and thin.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a known semiconductor package; and

2A to 2E are schematic cross-sectional views of the manufacturing method of the first embodiment of the electronic package of the present invention; wherein, FIG. 2E' and FIG. 2E" are different embodiments of FIG. 2E; and

3A to 3C are schematic cross-sectional views of the manufacturing method of the second embodiment of the electronic package of the present invention; wherein, FIG. 3C' is another embodiment of FIG. 3C.

Explanation of reference signs

1 Semiconductor package

10 Package Substrate

10a board body

10b,24,24’ line structure

100,240 line layer

11 Semiconductor components

11a, 21a Action surface

11b, 21b non-active surface

110,210 electrode pads

12 Solder bumps

13 Encapsulation colloid

14 hollow

2,3 Electronic packages

20 Carriers

200 metal layers

21 electronic components

22 Conductive bumps

22a top surface

23 insulation layer

23a first surface

23b Second surface

241 Conductor

242 dielectric layer

25 Conductive elements

26,26’ radiator

30 conductive pillars

30a, 30b end faces

31 Electronics

32 Connection bumps.

Detailed ways

Embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification, for those skilled in the art to understand and read, and are not used to limit the implementation of the present invention. Conditions, so it has no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size shall still fall within the scope of the present invention without affecting the effect and purpose of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "above", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall also be regarded as the implementable scope of the present invention if there is no substantial change in the technical content.

2A to 2E are schematic cross-sectional views of the manufacturing method of the first embodiment of the electronic package 2 of the present invention.

As shown in FIG. 2A , an electronic component 21 combined with a plurality of conductive bumps 22 is disposed on a carrier 20 .

In this embodiment, a metal layer 200 is formed on the surface of the carrier 20 . In this embodiment, the carrier 20 is a substrate, such as a copper foil substrate or other boards, but there is no particular limitation. In this embodiment, a copper foil substrate is used for illustration, with metal layers 200 on both sides thereof.

In addition, the electronic component 21 is a semiconductor component, which is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is a semiconductor wafer, which has an opposite active surface 21a and a non-active surface 21b. The active surface 21a has a plurality of electrode pads 210 to combine the above-mentioned conductive bumps 22, so that the conductive bumps 22 are electrically conductive. The electronic component 21 is connected, and the electronic component 21 is adhered to the metal layer 200 with its non-active surface 21b through a bonding layer (not shown).

Also, the conductive bumps 22 are solder bumps.

As shown in FIG. 2B , an insulating layer 23 is formed on the metal layer 200 of the carrier 20 so that the insulating layer 23 covers the electronic component 21 and the conductive bump 22 .

In this embodiment, the insulating layer 23 defines a first surface 23 a and a second surface 23 b opposite to each other, so that the second surface is bonded to the metal layer 200 of the carrier 20 .

In addition, the insulating layer 23 is an epoxy encapsulant, which can be formed on the carrier 20 by lamination or molding.

Moreover, the top surface 22 a of the conductive bump 22 is exposed from the insulating layer 23 . For example, the top surface 22 a of the conductive bump 22 can be flush with the first surface 23 a of the insulating layer 23 through a leveling process. Specifically, the leveling process can remove part of the material of the conductive bump 22 and part of the material of the insulating layer 23 by grinding.

As shown in FIGS. 2C to 2D , a circuit structure 24 is formed on the insulating layer 23 and the top surface 22 a of the conductive bump 22 , and the circuit structure 24 is electrically connected to the conductive bump 22 .

In this embodiment, the circuit structure 24 includes a circuit layer 240 disposed on the insulating layer 23 and the conductive bump 22, a plurality of conductors 241 disposed on the circuit layer 240, and a circuit layer covering the circuit layer. 240 and the dielectric layer 242 of the conductor 241 , and the circuit layer 240 is electrically connected to the conductive bump 22 , and exposes part of the surface of the conductor 241 to the dielectric layer 242 .

In addition, the circuit layer 240 is made of copper, and the conductor 241 is a copper cylinder.

Moreover, the dielectric layer 242 is formed on the insulating layer 23 by molding, coating or pressing, and the material for forming the dielectric layer 242 is molding compound (Molding Compound), primer (Primer) or such as Dielectric material of epoxy resin (Epoxy).

As shown in FIG. 2E , the carrier 20 and its metal layer 200 are removed so that the electronic component 21 is exposed on the insulating layer 23 to complete the electronic package 2 of the present invention.

In this embodiment, the non-active surface 21b of the electronic element 21 is exposed on the second surface 23b of the insulating layer 23, and a plurality of conductive elements 25 such as solder balls can be formed on the conductor 241 of the circuit structure 24, For subsequent placement of electronic devices such as circuit boards, packaging structures or other structures (such as another chip) (not shown).

In addition, as shown in FIG. 2E', the circuit structure 24' formed on the insulating layer 23 may also have a plurality of circuit layers 240 and a plurality of dielectric layers 242.

Also, as shown in FIG. 2E ", a heat sink 26 can also be combined on the non-active surface 21b of the electronic component 21 and the second surface 23b of the insulating layer 23. In one embodiment, as shown in FIG. 2A of the present invention The carrier used can be a metal plate, and only part of the carrier is removed during the manufacturing process, and the carrier corresponding to the non-active surface 21b of the electronic component 21 is reserved as the heat sink 26. The electronic package of the present invention The manufacturing method of component 2 is to cover the electronic component 21 and the conductive bump 22 with the insulating layer 23 first, and then form the circuit structure 24 on the insulating layer 23, so the insulating layer 23 does not need to flow through the electronic component 21 and the circuit structure 24. Therefore, when the electronic component 21 is large in size or has a high pin count, there will be no void between the electronic component 21 and the circuit structure 24, thereby avoiding the problem of moisture infiltration, There will be no popcorn effect, so it can effectively improve product yield.

In addition, the electronic package 2 of the present invention only forms the circuit structure 24 without making a known package substrate board, so compared with the prior art, the overall thickness of the electronic package 2 can be greatly reduced to meet the light and thin requirements. demand.

3A to 3C are schematic cross-sectional views of the manufacturing method of the second embodiment of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the addition of conductive pillars, and other manufacturing processes are substantially the same, so only the differences will be described below, and the similarities will not be repeated.

As shown in FIG. 3A , a plurality of conductive pillars 30 and an electronic component 21 combined with a plurality of conductive bumps 22 are disposed on a carrier 20 .

In this embodiment, the conductive pillar 30 is a copper pillar.

As shown in FIG. 3B , the process of FIG. 2B to FIG. 2D is performed to form the above-mentioned conductive pillar 30 in the insulating layer 23 , and the conductive pillar 30 is electrically connected to the circuit layer 240 of the circuit structure 24 .

In this embodiment, when performing the leveling process as shown in FIG. 2B , part of the material of the conductive pillar 30 can be removed, so that one end surface 30 a of the conductive pillar 30 is flush with the first surface 23 a of the insulating layer 23 .

In addition, after the carrier 20 is removed, the other end surface 30 b of the conductive column 30 is exposed on the second surface 23 b of the insulating layer 23 .

Also, as shown in FIG. 3C, a plurality of conductive elements 25 such as solder balls can be formed on the conductor 241 of the circuit structure 24 for subsequent placement such as circuit boards, packaging structures or other structures (such as another chip) electronic devices (not shown).

In addition, in the subsequent process, as shown in FIG. 3C , an electronic device 31 can be connected to the end surface 30 b of each conductive pillar 30 through the connection bump 32 , so that the electronic device 31 is electrically connected to each conductive pillar 30 . For example, the electronic device 31 is a package, an active component or a passive component.

It should be understood that, as shown in FIG. 3C', a heat sink 26' may also be combined on the non-active surface 21b of the electronic component 21. In one embodiment, the heat sink 26' can be a bearing (for example, a metal plate) that remains at the non-active surface 21b corresponding to the electronic component 21.

The present invention provides an electronic package 2 , 3 , which includes: an insulating layer 23 , an electronic component 21 having a plurality of conductive bumps 22 and a circuit structure 24 .

The insulating layer 23 has a first surface 23a and a second surface 23b opposite to each other.

The electronic components 21 and the conductive bumps 22 are embedded in the insulating layer 23 , so that part of the surface (top surface 22 a ) of the conductive bumps 22 is exposed on the first surface 23 a of the insulating layer 23 .

The circuit structure 24 is formed on the first surface 23 a of the insulating layer 23 and is electrically connected to the conductive bump 22 .

In one embodiment, the electronic component 21 has an opposite active surface 21 a and a non-active surface 21 b, and the active surface 21 a is combined with the above-mentioned conductive bump 22 .

In one embodiment, a heat sink 26, 26' is combined on the non-active surface 21b of the electronic component 21.

In one embodiment, the electronic component 21 is exposed on the insulating layer 23 . For example, the non-active surface 21 b of the electronic component 21 is exposed on the second surface 23 b of the insulating layer 23 .

In one embodiment, the conductive bump 22 is a solder bump.

In one embodiment, the electronic package 2 , 3 further includes a plurality of conductive elements 25 formed on the circuit structure 24 .

In one embodiment, the electronic package 3 further includes a plurality of conductive pillars 30 formed in the insulating layer 23 , and the conductive pillars 30 are electrically connected to the circuit structure 24 .

In one embodiment, the end surface 30 b of the conductive pillar 30 is exposed on the second surface 23 b of the insulating layer 23 .

In one embodiment, the electronic package 3 further includes an electronic device 31 connected to the end surface 30 b of the conductive pillar 30 .

To sum up, the electronic package and its manufacturing method of the present invention cover the electronic component and the conductive bump with the insulating layer first, and then form the circuit structure on the insulating layer, so the electronic component and the There will be no voids between the circuit structures, so the product yield can be effectively improved.

In addition, the electronic package of the present invention only forms a circuit structure without making a board body of a known package substrate, so the overall thickness of the electronic package can be greatly reduced to meet the demand for lightness and thinning.

The above-mentioned embodiments are only used to illustrate the principles and effects of the present invention, but not to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (10)

1. An electronic package, characterized in that the electronic package comprises: Insulation; An electronic component combined with a plurality of conductive bumps embedded in the insulating layer, with part of the surface of the conductive bumps exposed to the insulating layer; and The circuit structure is formed on the insulating layer and the conductive bump is exposed on a part of the surface of the insulating layer and is electrically connected to the conductive bump. 2. The electronic package as claimed in claim 1, wherein the electronic component has an opposite active surface and a non-active surface, and the active surface is combined with the conductive bump to electrically connect the electronic component the conductive bumps. 3. The electronic package as claimed in claim 1, wherein the conductive bump is a solder bump. 4. The electronic package as claimed in claim 1, further comprising a plurality of conductive pillars formed in the insulating layer, and the conductive pillars are electrically connected to the circuit structure. 5. The electronic package as claimed in claim 4, further comprising an electronic device connected to the end surface of the conductive post. 6. A method for preparing an electronic package, characterized in that the method comprises the following steps: disposing an electronic component combined with a plurality of conductive bumps on a carrier; forming an insulating layer on the carrier, so that the insulating layer covers the electronic component, and a part of the surface of the conductive bump is exposed to the insulating layer; forming a wiring structure on the insulating layer and the conductive bump exposed on a part of the surface of the insulating layer, and electrically connecting the wiring structure to the conductive bump; and Remove the carrier. 7. The method of manufacturing an electronic package as claimed in claim 6, wherein the electronic component has an opposite active surface and a non-active surface, and the active surface is combined with the conductive bump, so that the electronic component Electrically connect the conductive bump. 8. The method for manufacturing an electronic package as claimed in claim 6, wherein the conductive bumps are solder bumps. 9. The method for manufacturing an electronic package as claimed in claim 6, further comprising forming a plurality of conductive elements on the circuit structure. 10 . The method for manufacturing an electronic package as claimed in claim 9 , further comprising connecting an electronic device on the end surface of the conductive post. 11 .