CN1295766C - Electronic sealer with three-dimensional stack and assembling method thereof - Google Patents
Electronic sealer with three-dimensional stack and assembling method thereof Download PDFInfo
- Publication number
- CN1295766C CN1295766C CNB031239706A CN03123970A CN1295766C CN 1295766 C CN1295766 C CN 1295766C CN B031239706 A CNB031239706 A CN B031239706A CN 03123970 A CN03123970 A CN 03123970A CN 1295766 C CN1295766 C CN 1295766C
- Authority
- CN
- China
- Prior art keywords
- assembly
- packing piece
- column conductive
- electronic packing
- dimensional stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000012856 packing Methods 0.000 claims description 33
- 230000000149 penetrating effect Effects 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000004927 fusion Effects 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 4
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 abstract description 22
- 238000004100 electronic packaging Methods 0.000 abstract description 9
- 230000000712 assembly Effects 0.000 abstract description 6
- 238000000429 assembly Methods 0.000 abstract description 6
- 238000004377 microelectronic Methods 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 2
- 238000005538 encapsulation Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000012797 qualification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Wire Bonding (AREA)
Abstract
The present invention discloses a three-dimensional stacked electronic packaging member and an assembly method thereof. The present invention is designed by combining a columnar tin ball method and permeable holes of assemblies. Simultaneously, the upper layer assemblies and the lower layer assemblies are jointed, and the electric joint can be completed. Loading bodies can form columnar conductive convex blocks by the columnar tin ball method, and the columnar conductive convex blocks can pass through the permeable holes of the assemblies. The three-dimensional stacked electronic packaging member can be completed by assembling the assemblies on the loading bodies. The present invention reduces the cost of multiple chip packaging and simplifies packaging manufacture processes. The present invention can be used for the field of IC manufacture and the relevant manufacture of other microelectronics.
Description
Technical field
The present invention relates to a kind of electronic packing piece and assemble method thereof, particularly a kind of three-dimensional stacked electronic packing piece and assemble method thereof.
Background technology
Electronic Packaging (Electronic Packaging) is also referred to as electronic packaging, and its purpose is to give integrated circuit package (IC) institutional framework, makes it can bring into play set function.Therefore with the manufacture process of microelectronic product, Electronic Packaging belongs to the manufacturing technology of product back segment, and encapsulation often is considered to one of supporting role of ic manufacturing technology just.In fact, therefore the Electronic Packaging technology develops the importance of encapsulation technology not second to IC manufacturing technology and other microelectronics associated fabrication techniques for dominating electronic product size and cost.
According to combined I C core number in the encapsulation, Electronic Packaging can be divided into single-chip package, and (Single ChipPackages is SCP) with the encapsulation of multicore sheet (Multichip Packages, MCP) two big classes, multicore sheet encapsulation also comprise the multi-chip module encapsulation (Multichip Module, MCM).In order to reach the product demand of miniaturization, low cost, high density distribution and multifunction, the encapsulation of multicore sheet has become the main flow of current Electronic Packaging development, therefore how to reduce the cost of multicore sheet encapsulation and simplifies the research and development target that package fabrication process also becomes present semiconductor industry.
Wherein, the electric connection method of the chip chamber of general multicore sheet encapsulation is that (ball grid array, the BGA) end points that outwards connects as chip electrically connect to reach chip chamber at the chip manufacturing solder ball array.Yet, this manufacture method has comprised that assembling of many mask manufactures, light lithography, sputter, plating or the like related manufacturing process and back segment and solder ball array plant the manufacture process of ball, its manufacture process is quite complicated and influence the factor of manufacture process more and cause the manufacturing process instability, has relatively improved packaging cost.In addition, also the penetrating hole of made is used as the vertical conducting path of chip on the utilized chip, but in manufacture process, need the penetrating hole of contraposition chip and insert electric conducting material, the step of this contraposition and filling has suitable difficulty in practice, make qualification rate unstable and cause difficulty in the batch process.
Summary of the invention
The object of the present invention is to provide a kind of three-dimensional stacked electronic packing piece and assemble method thereof,, reach and simplify manufacture process and cost-effective purpose to solve the problem of above-mentioned known technology.
The present invention utilizes the penetrating hole design of stud bumps (stud bump) method and assembly itself, engages the levels assembly simultaneously and finishes electrical joint.Can reduce solder ball array in a large number and plant the relevant manufacture process of ball and producing lug two parts required many mask manufactures, light lithography, sputter or plating or the like, and the assembling manufacture process of back segment.
The assemble method of three-dimensional stacked electronic packing piece disclosed in this invention, its overview of steps is as follows: utilize stud bumps (stud bump) method to make several column conductive projections in the load-bearing surface of supporting body earlier; More than one assembly is provided, and it has several the penetrating holes corresponding to the column conductive projection, passes through so that several column conductive projections to be provided; Assemble aforesaid assembly and supporting body, make the column conductive projection aim at the penetrating hole of passing through assembly; So, promptly finish assembly and form electronic packing piece with engaging of supporting body.In addition, can utilize said method, utilize completed electronic packing piece, repeat above-mentioned steps to engage several assemblies as supporting body.According to the difference of circuit design, also can select the to get along well alignment of column conductive projection or the contact of electronic packing piece of ground floor of the position of the stud bumps that supporting body is follow-up.With the method can finish multicore sheet encapsulation (Multichip Packages, MCP) or multi-chip module encapsulation (Multichip Module, multi-level encapsulation such as MCM).Wherein, the present invention also is included in the assembly surface coating scolder of top around column conductive projection tail end, heats scolder that reflow makes fusion then along the step of the penetrating hole of column conductive projection by assembly with each layer assembly of connecting; Or replace aforesaid scolder with the conductive paste material, replace heating reflow manufacture process to solidify afterwards.
The assemble method that cooperates above-mentioned three-dimensional stacked electronic packing piece, the present invention also comprises the three-dimensional stacked electronic packing piece of producing with the method, its structure includes: a supporting body, its load-bearing surface have several column conductive projections; More than one assembly, it has several the penetrating holes corresponding to the column conductive projection, and the penetrating hole of several of each assembly is to aim at by several column conductive projections, makes more than one component groups be loaded on load-bearing surface.In addition, structure of the present invention also comprises along the scolder of column conductive projection by the penetrating hole of assembly.
Description of drawings
Figure 1A to Fig. 1 E is the making schematic flow sheet of first embodiment of the invention; And
Fig. 2 A to Fig. 2 D is the making schematic flow sheet of second embodiment of the invention.
Label declaration:
10 substrates, 11 column conductive projections
20 chips, 21 penetrating holes
30 septs, 31 scolders
Embodiment
For making purpose of the present invention, structural feature and function thereof are had further understanding, conjunction with figs. is described in detail as follows:
Please refer to Figure 1A to Fig. 1 E, it is the making schematic flow sheet of first embodiment of the invention.Shown in Figure 1A, utilize stud bumps (stud bump) method to make several column conductive projections 11 earlier in the load-bearing surface of substrate 10; Then, shown in Figure 1B, provide the chip 20 that has corresponding to several penetrating holes 21 of column conductive projection 11; Then, assembling chip 20 and substrate 10, shown in Fig. 1 C, the penetrating hole 21 that column conductive projection 11 is aimed at by each chip 20, the tail end of column conductive projection 11 exceeds chip 20 height; So, promptly joint chip 20 and substrate 10 are to form the electronic packing piece of ground floor.In addition, can utilize said method, shown in Fig. 1 D, utilize completed electronic packing piece as supporting body, utilize the load-bearing surface of stud bumps (stud bump) method above chip 20 to make several column conductive projections 11 equally, connect so that follow-up chip 20 to be provided; Then, can repeat above-mentioned steps to engage a plurality of chips 20, shown in Fig. 1 E, it is the schematic diagram of first embodiment of the invention.Wherein, the position of follow-up stud bumps can be formed at the tail end of the column conductive projection 11 that electronic packing piece exposed of ground floor; Perhaps, according to the difference of circuit design, the position of follow-up stud bumps also can be selected not contact with the column conductive projection that electronic packing piece exposed of ground floor.
The present invention also can utilize stud bumps (stud bump) method to make several highly higher column conductive projections in the load-bearing surface of supporting body; Make single column conductive projection several chips of can connecting.Please refer to Fig. 2 A to Fig. 2 D, it is the making schematic flow sheet of second embodiment of the invention.Shown in Fig. 2 A, utilize stud bumps (stud bump) method to make several column conductive projections 11 that highly are about 300 microns (μ m) earlier in the load-bearing surface of supporting body; Then, shown in Fig. 2 B, provide four chips 20 that have corresponding to several penetrating holes 21 of column conductive projection 11, the penetrating hole 21 that column conductive projection 11 is aimed at by each chip 20, assemble each chip 20 in regular turn in supporting body 10, and between chip 20, add sept 30.Be coated with again around column conductive projection 11 tail ends that scolder 31 exposes in chip 20 surfaces of top, please refer to Fig. 2 C; At last, shown in Fig. 2 D, the heating reflow makes scolder 31 fusions along the penetrating hole 21 of column conductive projection 11 by chip 20, makes it solidify each layer chip 20 of being connected afterwards.
In addition, also can the conducting resinl material replace scolder, the conducting resinl material of liquid state is coated around the column conductive projection tail end of chip surface of top, make it along the penetrating hole of conductive projection, and curing conductive glue material makes its each layer chip of connecting by chip.
Utilize the formed column conductive projection of stud bumps (stud bump) in the manufacture process of the present invention, its material can be utilized the metal material of high conductivity, and as gold, copper or aluminium etc., or the conductive material of other tool is to obtain better conductive properties.And chip can be selected semiconductor chip commonly used such as silicon, GaAs, indium phosphide or extension chip (epi-wafer), and supporting body can be organic substrate, pottery (ceramic), glass (glass), silicon and GaAs substrates such as (GaAs).And, supporting body can see through array pin position array packages (Pin Grid Array Package again, PGA), solder ball array, routing engage (Wire Bond), flip-chip (Flip-Chip), coil type engage automatically (Tape Automated Bonding, TAB) or lead frame modes such as (lead frame) be connected with other substrate or assembly.
Though preferred embodiment of the present invention openly as mentioned above; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when doing some variations and change, therefore scope of patent protection of the present invention is as the criterion with claim.
Claims (17)
1. the assemble method of a three-dimensional stacked electronic packing piece is characterized in that, step includes:
(a) provide a supporting body;
(b) utilize the stud bumps method to make several column conductive projections in a load-bearing surface of this supporting body;
(c) provide more than one assembly, it has several the penetrating holes corresponding to this column conductive projection, passes through so that this column conductive projection to be provided; And
(d) make this column conductive projection aim at this penetrating hole of passing through this assembly, assemble this assembly and this supporting body to form an electronic packing piece.
2. the assemble method of three-dimensional stacked electronic packing piece as claimed in claim 1 is characterized in that, also is included in this step (d) afterwards, as supporting body, repeats once above step (b) in regular turn to step (d) with this electronic packing piece.
3. the assemble method of three-dimensional stacked electronic packing piece as claimed in claim 1, it is characterized in that, this assembly surface that also is included in top is coated with a scolder around this column conductive projection tail end, and the heating reflow make fusion this scolder along this column conductive projection by the step of this penetrating hole with this assembly of each layer of connecting.
4. the assemble method of three-dimensional stacked electronic packing piece as claimed in claim 1, it is characterized in that, this assembly surface that also is included in top is coated with a conducting resinl material around this column conductive projection tail end, make this liquid conducting resinl material along this column conductive projection by the step of this penetrating hole with this assembly of each layer of connecting.
5. the assemble method of three-dimensional stacked electronic packing piece as claimed in claim 1 is characterized in that the material of this column conductive projection is a conductive metal.
6. the assemble method of three-dimensional stacked electronic packing piece as claimed in claim 1 is characterized in that, the material of this column conductive projection be selected from group that gold, copper and aluminium forms one of them.
7. the assemble method of three-dimensional stacked electronic packing piece as claimed in claim 1 is characterized in that, this assembly be selected from group that silicon, GaAs chip, indium phosphide chip and extension chip formed one of them.
8. the assemble method of three-dimensional stacked electronic packing piece as claimed in claim 1 is characterized in that, this supporting body be selected from group that organic substrate, ceramic substrate, glass substrate, silicon substrate and GaAs substrate formed one of them.
9. a three-dimensional stacked electronic packing piece is characterized in that, includes:
-supporting body, it has a load-bearing surface, and this load-bearing surface is to form several column conductive projections with the stud bumps method; And
More than one assembly, it has several the penetrating holes corresponding to this column conductive projection, and the penetrating hole of this of each this assembly is to aim at by this column conductive projection, makes each this assembly from bottom to top be assembled in this load-bearing surface.
10. three-dimensional stacked electronic packing piece as claimed in claim 9, it is characterized in that, this assembly is several, and this penetrating hole of aiming at each this assembly piles up to form a combination of components, make this penetrating hole by this column conductive projection to assemble this combination of components in this load-bearing surface.
11. three-dimensional stacked electronic packing piece as claimed in claim 10, it is characterized in that, also comprise a scolder, be coated on around this column conductive projection tail end of this assembly surface of top, and via the heating reflow with this scolder of fusion make its along this column conductive projection by this penetrating hole this assembly with each layer of connecting.
12. three-dimensional stacked electronic packing piece as claimed in claim 10, it is characterized in that, also comprising a conducting resinl material, is to be coated on around this column conductive projection tail end of this assembly surface of top, make its along this column conductive projection by this penetrating hole this assembly with each layer of connecting.
13. three-dimensional stacked electronic packing piece as claimed in claim 10 is characterized in that, also comprises a sept, is to be interval between this assembly of this assembly and adjacency.
14. three-dimensional stacked electronic packing piece as claimed in claim 9 is characterized in that, the material of this column conductive projection is a conductive metal.
15. three-dimensional stacked electronic packing piece as claimed in claim 9 is characterized in that, the material of this column conductive projection be selected from group that gold, copper and aluminium forms one of them.
16. three-dimensional stacked electronic packing piece as claimed in claim 9 is characterized in that, this assembly be selected from group that silicon, GaAs chip, indium phosphide chip and extension chip formed one of them.
17. three-dimensional stacked electronic packing piece as claimed in claim 9 is characterized in that, this supporting body be selected from group that organic substrate, ceramic substrate, glass substrate, silicon substrate and GaAs substrate formed one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031239706A CN1295766C (en) | 2003-05-29 | 2003-05-29 | Electronic sealer with three-dimensional stack and assembling method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031239706A CN1295766C (en) | 2003-05-29 | 2003-05-29 | Electronic sealer with three-dimensional stack and assembling method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1553490A CN1553490A (en) | 2004-12-08 |
| CN1295766C true CN1295766C (en) | 2007-01-17 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031239706A Expired - Fee Related CN1295766C (en) | 2003-05-29 | 2003-05-29 | Electronic sealer with three-dimensional stack and assembling method thereof |
Country Status (1)
| Country | Link |
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| CN (1) | CN1295766C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100409419C (en) * | 2006-09-01 | 2008-08-06 | 中国航天时代电子公司第七七一研究所 | Method for interconnecting and packaging 3-D multi-chip module |
| KR100920039B1 (en) | 2007-06-21 | 2009-10-07 | 주식회사 하이닉스반도체 | Stacked semiconductor package and method of manufacturing thereof |
| US8399973B2 (en) * | 2007-12-20 | 2013-03-19 | Mosaid Technologies Incorporated | Data storage and stackable configurations |
| KR20110137926A (en) * | 2010-06-18 | 2011-12-26 | (주)에프씨아이 | Stacked multi chip package structure |
| CN110335858B (en) * | 2019-06-27 | 2021-04-02 | 深圳第三代半导体研究院 | Vertical stacked packaging chip and preparation method thereof |
| CN111843276A (en) * | 2020-06-29 | 2020-10-30 | 上海邑和汽车科技有限公司 | Paste-free brazing process and combined solder |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6218731B1 (en) * | 1999-05-21 | 2001-04-17 | Siliconware Precision Industries Co., Ltd. | Tiny ball grid array package |
| US6266249B1 (en) * | 1998-10-20 | 2001-07-24 | Lsi Logic Corporation | Semiconductor flip chip ball grid array package |
| US6388333B1 (en) * | 1999-11-30 | 2002-05-14 | Fujitsu Limited | Semiconductor device having protruding electrodes higher than a sealed portion |
-
2003
- 2003-05-29 CN CNB031239706A patent/CN1295766C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6266249B1 (en) * | 1998-10-20 | 2001-07-24 | Lsi Logic Corporation | Semiconductor flip chip ball grid array package |
| US6218731B1 (en) * | 1999-05-21 | 2001-04-17 | Siliconware Precision Industries Co., Ltd. | Tiny ball grid array package |
| US6388333B1 (en) * | 1999-11-30 | 2002-05-14 | Fujitsu Limited | Semiconductor device having protruding electrodes higher than a sealed portion |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1553490A (en) | 2004-12-08 |
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