CN110335858B - Vertical stacked packaging chip and preparation method thereof - Google Patents
Vertical stacked packaging chip and preparation method thereof Download PDFInfo
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- CN110335858B CN110335858B CN201910567083.5A CN201910567083A CN110335858B CN 110335858 B CN110335858 B CN 110335858B CN 201910567083 A CN201910567083 A CN 201910567083A CN 110335858 B CN110335858 B CN 110335858B
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- 238000004806 packaging method and process Methods 0.000 title description 5
- 238000002360 preparation method Methods 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 135
- 239000011796 hollow space material Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 19
- 238000003466 welding Methods 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 230000000712 assembly Effects 0.000 claims description 10
- 238000000429 assembly Methods 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 7
- 239000003292 glue Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 239000012792 core layer Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims 6
- 238000004891 communication Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Combinations Of Printed Boards (AREA)
Abstract
A vertical stack package chip, comprising: a first substrate, a second substrate, … …, an nth substrate, said n > 1; and a plurality of connecting pieces interconnecting the adjacent substrates, wherein the connecting pieces are connecting pins or soft boards, and the hollow space between the adjacent substrates is adjusted by controlling the depth of the connecting pieces in the substrates or the height of the connecting pieces. The invention solves the technical problem of the limitation of the space of the original chip structure, fully utilizes the three-dimensional space of the substrate, realizes the interconnection communication among the multilayer substrates and improves the flexibility of the chip structure.
Description
Technical Field
The invention relates to the field of chip package interconnection, in particular to a system-on-chip package technology.
Background
In a diversified, high-density, hybrid integrated system-in-package (SiP), the size of the whole IC product is a very important consideration, and how to effectively realize the performance of the IC in the minimum three-dimensional space is a key consideration of modern circuit designers and package technicians, and from the viewpoint of the package technicians, the process implementation difficulty is more and more complex. Therefore, in many cases, the implementation of packaging technology becomes the key to diversified, high-density, hybrid integrated system-in-package.
Disclosure of Invention
In order to overcome the defects of the prior art and avoid the problem of space limitation of the original chip structure, the invention provides a vertical stacked packaged chip, which comprises:
a first substrate, a second substrate, … …, an nth substrate, said n > 1;
and a plurality of connectors interconnecting the adjacent substrates,
the hollow space between adjacent substrates is adjusted by controlling the depth of the connector placed in the substrate, or the height of the connector.
Preferably, the connecting piece is a connecting needle, and the connecting needle comprises a needle part with a first width and a first height and a supporting part with a second width and a second height; the second width is greater than the first width;
the needle portion and the support portion include copper, an electroplated nickel layer plated on a surface of the copper, and an electroplated gold layer plated on a surface of the electroplated nickel layer.
Preferably, the substrate comprises an assembly of a plurality of wiring layers covering a core layer,
the first substrate comprises a plurality of said assemblies connected by a first ink layer comprising a first horizontal layer of ink bridging the top and bottom of adjacent assemblies and a first vertical layer of ink filling the spaces between adjacent assemblies;
the second substrate to the nth substrate comprise a plurality of assemblies which are separately arranged, and the upper layer and the lower layer of the assemblies are coated with a second upper ink layer and a second lower ink layer which are shorter than the circuit layer in length.
Preferably, the connecting piece is a flexible board, and the flexible board comprises an ink portion, and a first welding portion and a second welding portion which are located on two sides of the ink portion.
A method for preparing a vertical stack package chip comprises the following steps:
step 1: preparing a plurality of substrates and connecting pieces;
step 2: welding a plurality of components on the substrate;
and step 3: vertically interconnecting the plurality of the substrates with a connector; a plurality of the substrates comprise height-adjustable hollow spaces therebetween;
and 4, sealing glue or attaching metal or an insulating cover.
Preferably, the connecting piece is a connecting needle, and the connecting needle comprises a needle part with a first width and a first height and a supporting part with a second width and a second height; the second width is greater than the first width. Preferably, the plurality of substrates are a first substrate, a second substrate … … and an nth substrate from bottom to top, wherein n >1, and a plurality of holes with a first width are formed on the second substrate to the nth substrate.
Preferably, the step 3 comprises: placing a plurality of the connecting needle supporting parts on a first substrate, and inserting the connecting needle parts into a second substrate; the step 4 comprises the following steps: adjusting the hollow space height between the first substrate and the second substrate, and fixing the supporting part and the first substrate, the needle part and the second substrate by adopting sealing glue or pasting metal or an insulating cover.
Preferably, the connecting piece is a flexible board, and the flexible board comprises an ink portion, and a first welding portion and a second welding portion which are located on two sides of the ink portion.
Preferably, the second substrate further comprises a plurality of copper columns located at the bottom, the bottoms of the plurality of copper columns are connected to the first substrate, the first welding portion of the soft board is connected with the first substrate, and the second welding portion of the soft board is connected with the second substrate.
The invention carries out structural design and assembly on two or more than two mutually independent substrates positioned in the cavity of the system-in-package structure, effectively solves the problem of the size of an IC product in the system-in-package, fully utilizes the three-dimensional space of the product and realizes the interconnection communication between the substrates.
Drawings
Fig. 1 is a side view of a second substrate of a multi-layer substrate and a method for making the same according to an embodiment.
Fig. 2 is a side view of a first substrate of a multi-layer substrate and a method for fabricating the same according to an embodiment.
Fig. 3 is a side view of a connection pin of a multi-layer substrate and a method for manufacturing the same according to an embodiment.
Fig. 4 is a side view of a vertical stack package chip according to an embodiment of the present invention.
Fig. 5 is a perspective view of a vertical stack package chip of the multi-layer substrate and a method for manufacturing the same according to an embodiment.
Fig. 6 is a side view of a connection pin of a multi-layered substrate and a method for manufacturing the same according to an embodiment.
Fig. 7 is a top view of a flexible printed circuit board of the multi-layered substrate and the method for manufacturing the same according to the second embodiment.
Fig. 8 is a perspective view of a vertical stack package chip of the multi-layer substrate and the method for manufacturing the same according to the second embodiment.
Fig. 9 is a perspective view of a vertical stack package chip of the multi-layer substrate and the method for manufacturing the same according to the second embodiment.
Fig. 10 is a substrate layout diagram of the multilayer substrate and the method for manufacturing the same according to the second embodiment.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, the following examples of which are intended to be illustrative only and are not to be construed as limiting the scope of the invention.
Example one
This example provides a multilayer substrate and a method of making the same, as shown in FIGS. 1-6. The multilayer substrate of this example was connected by connecting pins, and was prepared as follows:
1. designing and manufacturing a packaging interconnection structure:
1) manufacturing a substrate: FIG. 1 is a side view of a substrate A, including an upper ink layer 1-1a, a trace layer 1-2b, a lower ink layer 1-1b, and a core layer 1-3; the through hole annular welding disc 1-4, the connecting hole of the upper circuit layer and the lower circuit layer and the interconnecting pin hole 1-5 can be obtained by laser drilling or mechanical drilling.
FIG. 2 is a side view of a substrate B, including an upper ink layer 2-1a, a trace layer 2-2B, a lower ink layer 2-1B, and a core layer 2-3; the PCB comprises circular bonding pads 2-4, connecting holes 2-5 of upper and lower circuit layers and circular or square bonding pads 2-6, and is used for being connected with other PCBs.
2) Designing a connecting needle:
FIG. 3 is a side view of a connecting pin of a copper substrate cylindrical structure, which includes 3-1 copper, 3-2 electroplated nickel layer, 3-3 electroplated gold layer, nickel-gold plated on the surface of the copper pin mainly for preventing oxidation, the connecting pin having a pin portion with a first width and a first height and a support portion with a second width and a second height; the second width is greater than the first width. Through the connection of the substrate surface bonding pads and the connecting pins, signal transmission based on the connecting pins is realized on the basis of the interconnection of a plurality of vertical substrates.
3) Interconnection: the substrate A and the substrate B are interconnected through the connecting pins.
4) And (3) encapsulation: and (3) partially sealing and protecting the substrate A, the connecting pins and the upper-layer elements of the substrate B, or attaching a metal cover or an insulating cover on the substrate B to form a complete system packaging body.
5) And (3) packaging the whole process:
the first step is as follows: designing a circuit schematic diagram;
the second step is that: processing a substrate and manufacturing a connecting needle;
the third step: welding a component on the substrate;
the fourth step: the upper layer substrate and the lower layer substrate are interconnected through a connecting needle;
the fifth step: sealing glue or attaching a metal or insulating cover.
As shown in fig. 6, the present embodiment further provides a three-layer substrate interconnection structure, which includes a substrate C, a substrate B, a substrate a, a substrate C and a substrate B vertically arranged from top to bottom, wherein the substrate B and the substrate C are connected by a connection pin, a connection pin portion is disposed in the upper substrate, and a gap between adjacent substrates is adjusted by adjusting a length of the connection pin portion and the substrate.
Example two
This example provides a multilayer substrate and a method of making the same, as shown in FIGS. 7-10.
The multilayer substrate of this embodiment connects and realizes information transmission through the soft board, the soft board includes printing ink portion and is located the first welding point and the second welding point of printing ink portion both sides. The multilayer substrate comprises a substrate A located at the bottom, a substrate B located at the top, a plurality of connecting copper columns vertically arranged between the substrate B and the substrate A, and a flexible printed circuit board arranged between the substrate B and the substrate A, wherein a first welding point of the flexible printed circuit board is connected with the substrate B, a second welding point of the flexible printed circuit board is connected with the substrate A, and the area of the substrate B is different from that of the substrate A. The substrate B and the substrate A can be adjusted by adjusting the height of the copper pillar.
The whole packaging process through the soft board connection is as follows:
the first step is as follows: designing a circuit schematic diagram;
the second step is that: processing a substrate and processing a flexible board;
the third step: welding a component on the substrate;
the fourth step: the upper layer substrate and the lower layer substrate are interconnected through the flexible printed circuit board;
the fifth step: sealing glue or attaching a metal or insulating cover.
The multilayer substrate and the preparation method thereof provided by the invention can obtain the following technical effects:
1) high space utilization rate
By adopting the connecting pin interconnection structure, the utilization of the longitudinal space of the system-in-package product is increased, as shown in fig. 9, the structure can be expanded to a two-layer or multi-layer structure from the original one-layer structure, and the transverse area of the product is greatly reduced.
2) High degree of freedom in space
The height of the connecting pins is adjustable, and can be changed according to the height of the Top surface IC of the lower substrate; the connecting pins are flexible to use, and can be controlled according to the structural design of the substrate; the soft board can freely adjust the position and the height of the upper layer substrate relative to the lower layer substrate, and has flexibility.
Although exemplary embodiments of the present invention have been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, substitutions and the like can be made in form and detail without departing from the scope and spirit of the invention as disclosed in the accompanying claims, all of which are intended to fall within the scope of the claims, and that various steps in the various sections and methods of the claimed product can be combined together in any combination. Therefore, the description of the embodiments disclosed in the present invention is not intended to limit the scope of the present invention, but to describe the present invention. Accordingly, the scope of the present invention is not limited by the above embodiments, but is defined by the claims or their equivalents.
Claims (9)
1. A vertical stack package chip, comprising: a first substrate, a second substrate, … …, an nth substrate, said n >1, vertically distributed; and a plurality of connecting pieces interconnecting adjacent ones of the substrates, the connecting pieces being connecting pins, or flexible boards; controlling the hollow interval between adjacent substrates by defining the depth of the connecting pins in the substrate or the height of the connecting pins;
the substrate comprises an assembly of a plurality of circuit layers covering a core layer, the first substrate comprises a plurality of the assemblies connected by a first ink layer, the first ink layer comprises a first ink horizontal layer bridging the top and bottom of adjacent assemblies, and a first ink vertical layer filling the space between adjacent assemblies; the second substrate to the nth substrate comprise a plurality of assemblies which are separately arranged, and the upper layer and the lower layer of the assemblies are coated with a second upper ink layer and a second lower ink layer which are shorter than the circuit layer in length.
2. The vertical stack package chip of claim 1, wherein the connecting pins comprise pin portions having a first width and a first height, and support portions having a second width and a second height, the second width being greater than the first width; the hollow space between adjacent substrates is controlled by defining a second height of the connecting pins, and the pin portions and the supporting portions include copper, an electroplated nickel layer plated on the surface of the copper, and an electroplated gold layer plated on the surface of the electroplated nickel layer.
3. The vertical stack package chip of claim 1, wherein the connecting member is a flexible board, and the flexible board comprises an ink portion and a first solder portion and a second solder portion located on both sides of the ink portion.
4. A method for preparing the vertical stack package chip according to any one of claims 1 to 3, comprising: step 1: preparing a plurality of substrates and connecting pieces; step 2: welding a plurality of components on the substrate; and step 3: vertically interconnecting a plurality of the substrates using a connector; a plurality of the substrates comprise height-adjustable hollow spaces therebetween; and 4, sealing glue or attaching metal or an insulating cover.
5. The method of claim 4, wherein the connecting members are connecting pins, and the connecting pins comprise pin portions having a first width and a first height and support portions having a second width and a second height; the second width is greater than the first width.
6. The method of claim 4, wherein the plurality of substrates are a first substrate, a second substrate … … and an nth substrate from bottom to top, wherein n >1, and a plurality of holes with a first width are disposed from the second substrate to the nth substrate.
7. The method of claim 4, wherein the step 3 comprises: placing a plurality of the connecting needle supporting parts on a first substrate, and inserting the connecting needle parts into a second substrate; the step 4 comprises the following steps: adjusting the hollow space height between the first substrate and the second substrate, and fixing the supporting part and the first substrate, the needle part and the second substrate by adopting sealing glue or pasting metal or an insulating cover.
8. The method of claim 4, wherein the connecting member is a flexible board, and the flexible board includes an ink portion and a first solder portion and a second solder portion on two sides of the ink portion.
9. The method of claim 7, wherein the second substrate further comprises a plurality of copper pillars at a bottom, wherein the plurality of copper pillars are connected to the first substrate at the bottom, wherein the first solder portion of the flexible printed circuit board is connected to the first substrate, and wherein the second solder portion of the flexible printed circuit board is connected to the second substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910567083.5A CN110335858B (en) | 2019-06-27 | 2019-06-27 | Vertical stacked packaging chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910567083.5A CN110335858B (en) | 2019-06-27 | 2019-06-27 | Vertical stacked packaging chip and preparation method thereof |
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| Publication Number | Publication Date |
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| CN110335858A CN110335858A (en) | 2019-10-15 |
| CN110335858B true CN110335858B (en) | 2021-04-02 |
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| CN201910567083.5A Expired - Fee Related CN110335858B (en) | 2019-06-27 | 2019-06-27 | Vertical stacked packaging chip and preparation method thereof |
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| CN101221908A (en) * | 2008-01-29 | 2008-07-16 | 日月光半导体制造股份有限公司 | Substrate technique and structure with projection |
| CN102867786A (en) * | 2011-07-04 | 2013-01-09 | 三星电子株式会社 | Chip-stacked semiconductor package |
| CN106887415A (en) * | 2015-12-15 | 2017-06-23 | 半导体元件工业有限责任公司 | Semiconductor packaging system and correlation technique |
| CN106997876A (en) * | 2016-01-23 | 2017-08-01 | 重庆三峡学院 | A kind of three-dimensional PoP stack package structures and its manufacture method |
| CN107393422A (en) * | 2017-09-04 | 2017-11-24 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| KR20190031470A (en) * | 2019-03-19 | 2019-03-26 | 주식회사 경신 | Printed circuit boards jumping device |
-
2019
- 2019-06-27 CN CN201910567083.5A patent/CN110335858B/en not_active Expired - Fee Related
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1771399A (en) * | 2002-07-22 | 2006-05-10 | 远程接合技术公司 | Fastener for assembly and disassembly |
| CN1553490A (en) * | 2003-05-29 | 2004-12-08 | ���ŷ��˹�ҵ�����о�Ժ | Electronic sealer with three-dimensional stack and assembling method thereof |
| CN101188232A (en) * | 2007-12-19 | 2008-05-28 | 日月光半导体制造股份有限公司 | Laminated encapsulation structure and its making method |
| CN101221908A (en) * | 2008-01-29 | 2008-07-16 | 日月光半导体制造股份有限公司 | Substrate technique and structure with projection |
| CN102867786A (en) * | 2011-07-04 | 2013-01-09 | 三星电子株式会社 | Chip-stacked semiconductor package |
| CN106887415A (en) * | 2015-12-15 | 2017-06-23 | 半导体元件工业有限责任公司 | Semiconductor packaging system and correlation technique |
| CN106997876A (en) * | 2016-01-23 | 2017-08-01 | 重庆三峡学院 | A kind of three-dimensional PoP stack package structures and its manufacture method |
| CN107393422A (en) * | 2017-09-04 | 2017-11-24 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| KR20190031470A (en) * | 2019-03-19 | 2019-03-26 | 주식회사 경신 | Printed circuit boards jumping device |
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| CN110335858A (en) | 2019-10-15 |
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Effective date of registration: 20230403 Address after: No. 1088, Xueyuan Avenue, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Southern University of Science and Technology Address before: Taizhou building, 1088 Xueyuan Avenue, Xili University Town, Nanshan District, Shenzhen, Guangdong 518051 Patentee before: SHENZHEN THIRD GENERATION SEMICONDUCTOR Research Institute |
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