JPWO2013153717A1 - Electronic device and manufacturing method thereof - Google Patents

Electronic device and manufacturing method thereof Download PDF

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JPWO2013153717A1
JPWO2013153717A1 JP2014510026A JP2014510026A JPWO2013153717A1 JP WO2013153717 A1 JPWO2013153717 A1 JP WO2013153717A1 JP 2014510026 A JP2014510026 A JP 2014510026A JP 2014510026 A JP2014510026 A JP 2014510026A JP WO2013153717 A1 JPWO2013153717 A1 JP WO2013153717A1
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substrate
electronic component
electrode
semiconductor device
electronic device
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和之 川嶋
和之 川嶋
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract

電子機器（１００）は、基板（１０３）と、基板（１０３）上に実装される第１の電子部品（１０２）と、基板（１０３）と第１の電子部品（１０２）との間で、基板（１０３）と第１の電子部品（１０２）とを電気的に接続するとともに、基板（１０３）上に第１の電子部品（１０２）を支持する接続支持部（１０１）と、基板（１０３）と第１の電子部品（１０２）との間で、基板（１０３）上に実装される第２の電子部品（１０４）と、を備えることにより、実装面積の増大を防ぐことが可能となる。The electronic device (100) includes a substrate (103), a first electronic component (102) mounted on the substrate (103), and the substrate (103) and the first electronic component (102). The substrate (103) and the first electronic component (102) are electrically connected to each other, and the connection support portion (101) for supporting the first electronic component (102) on the substrate (103) and the substrate (103) ) And the first electronic component (102) and the second electronic component (104) mounted on the substrate (103), it is possible to prevent an increase in mounting area. .

Description

本発明は、電子機器及びその製造方法に関し、特に、基板に電子部品を実装する電子機器及びその製造方法に関する。   The present invention relates to an electronic device and a method for manufacturing the same, and more particularly to an electronic device for mounting electronic components on a substrate and a method for manufacturing the same.

近年、スマートフォンやタブレット端末等の高機能携帯機器が普及しており、このような電子機器には、ｅＭＭＣ（Embedded Multi Media Card）と呼ばれるメモリを内蔵した半導体装置が搭載されてきている。そして、電子機器の高機能化に伴い、内蔵されるメモリの容量が増加していることから、ｅＭＭＣのパッケージ外形の大型化が進んでいる。   In recent years, high-functional portable devices such as smartphones and tablet terminals have become widespread, and semiconductor devices incorporating a memory called an eMMC (Embedded Multi Media Card) have been mounted on such electronic devices. And since the capacity of the built-in memory has increased along with the higher functionality of electronic devices, the package size of eMMC has been increasing.

一方、ｅＭＭＣはＪＥＤＥＣ（Joint Electron Device Engineering Council）等により端子の配置を含むインタフェースが規定されている。例えば、半導体装置のインタフェースとして、端子の形状、サイズ、配列数やピッチなどが規格化されている。ｅＭＭＣでは、ＪＥＤＥＣの標準規格に規定された端子を使用することで、様々な電子機器にＭＭＣ（Multi Media Card）を組み込むことを可能としている。   On the other hand, for eMMC, an interface including terminal arrangement is defined by JEDEC (Joint Electron Device Engineering Council) or the like. For example, as the interface of a semiconductor device, the shape, size, number of arrays, pitch, and the like of terminals are standardized. In eMMC, it is possible to incorporate an MMC (Multi Media Card) into various electronic devices by using terminals defined in the JEDEC standard.

なお、半導体装置の実装に関連する技術として、特許文献１〜６が知られている。   Patent Documents 1 to 6 are known as techniques related to mounting of a semiconductor device.

特開平６−５０９８７号公報JP-A-6-50987 特開２００６−１２９２５５号公報JP 2006-129255 A 特開２００６−２９５１３６号公報JP 2006-295136 A 特開２００７−３２４３５４号公報JP 2007-324354 A 特開２０１０−２１９１８０号公報JP 2010-219180 A 特開２００９−０２６８４３号公報JP 2009-026843 A

上記のように、ｅＭＭＣのような半導体装置は、メモリ容量の増大とともにパッケージ外形が大型化しているとともに、半導体装置のインタフェースの規格化が進み様々な機器に実装されてきている。   As described above, the semiconductor device such as eMMC has been mounted on various devices as the memory size increases and the outer shape of the package increases and the standardization of the interface of the semiconductor device advances.

しかしながら、スマートフォンやタブレット端末等の電子機器では、高機能が要求されることに加えて小型化も要求されるため、大型化した半導体装置を実装することが困難な恐れがある。   However, in electronic devices such as smartphones and tablet terminals, in addition to high functionality, downsizing is also required, so that it may be difficult to mount a large semiconductor device.

特に、ｅＭＭＣのような半導体装置（第１の電子部品）を基板（親基板）に実装する場合、半導体装置近傍にバイパスコンデンサなどの周辺部品（第２の電子部品）を電気特性上実装する必要がある。例えば、上記特許文献１などの関連する技術では、半導体装置の周辺領域（ランド領域）に周辺部品を配置している。したがって、関連する技術のように、半導体装置の周辺に周辺部品を配置して実装すると、実装面積が増大するという問題がある。   In particular, when a semiconductor device (first electronic component) such as eMMC is mounted on a substrate (parent substrate), it is necessary to mount a peripheral component (second electronic component) such as a bypass capacitor in the vicinity of the semiconductor device in terms of electrical characteristics. There is. For example, in the related technology such as Patent Document 1 described above, peripheral components are arranged in the peripheral region (land region) of the semiconductor device. Therefore, there is a problem that the mounting area increases when peripheral components are arranged and mounted around the semiconductor device as in the related art.

すなわち、大型化した半導体装置のパッケージ周囲に周辺部品を配置することとなるため、実装基板に大きなパッケージ外形に加えて周辺部品を実装するための実装面積が必要となり、実装面積が増大してしまう。携帯電話に代表される、小型の実装基板を使用することが多い携帯電子機器の場合、実装面積を大きくすることは困難であり、実装面積の増大は大きな問題となる。   In other words, since peripheral components are arranged around the package of a large-sized semiconductor device, a mounting area for mounting peripheral components in addition to a large package outer shape is required on the mounting substrate, which increases the mounting area. . In the case of a portable electronic device such as a mobile phone that often uses a small mounting board, it is difficult to increase the mounting area, and an increase in the mounting area becomes a big problem.

本発明の目的は、このような問題を解決する電子機器及びその製造方法を提供することにある。   An object of the present invention is to provide an electronic device that solves such a problem and a method for manufacturing the same.

本発明に係る電子機器は、基板と、前記基板上に実装される第１の電子部品と、前記基板と前記第１の電子部品との間で、前記基板と前記第１の電子部品とを電気的に接続するとともに、前記基板上に前記第１の電子部品を支持する接続支持部と、前記基板と前記第１の電子部品との間で、前記基板上に実装される第２の電子部品と、を備えるものである。   An electronic apparatus according to the present invention includes a substrate, a first electronic component mounted on the substrate, and the substrate and the first electronic component between the substrate and the first electronic component. A connection support part for electrically connecting and supporting the first electronic component on the substrate, and a second electron mounted on the substrate between the substrate and the first electronic component And parts.

本発明に係る電子機器の製造方法は、基板に第１の電子部品を実装する電子機器の製造方法であって、前記基板上の第１の領域に、前記基板と前記第１の電子部品とを電気的に接続するとともに、前記基板上に前記第１の電子部品を支持するための接続支持部を、導電性接続材料を介して配置し、前記基板上の第２の領域に、導電性接続材料を介して第２の電子部品を配置し、前記接続支持部及び前記第２の電子部品の上方を含む領域で、前記接続支持部上に導電性接続材料を介して前記第１の電子部品を配置するものである。   A method for manufacturing an electronic device according to the present invention is a method for manufacturing an electronic device in which a first electronic component is mounted on a substrate, wherein the substrate, the first electronic component, And a connection support portion for supporting the first electronic component on the substrate is disposed via a conductive connection material, and the second region on the substrate is electrically conductive. A second electronic component is disposed via a connection material, and the first electron is disposed on the connection support portion via a conductive connection material in a region including the connection support portion and the upper side of the second electronic component. Parts are arranged.

本発明によれば、実装面積の増大を防ぐことが可能な電子機器及びその製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the electronic device which can prevent the increase in a mounting area, and its manufacturing method can be provided.

本発明に係る電子機器の特徴を説明するための概略断面図である。It is a schematic sectional drawing for demonstrating the characteristic of the electronic device which concerns on this invention. 実施の形態１に係る実装構造の構成を示す概略断面図である。1 is a schematic cross-sectional view showing a configuration of a mounting structure according to a first embodiment. 実施の形態１に係る実装構造の構成を示す拡大断面図である。2 is an enlarged cross-sectional view showing a configuration of a mounting structure according to Embodiment 1. FIG. 実施の形態１に係る子基板の製造方法を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment. 実施の形態１に係る子基板の製造方法を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment. 実施の形態１に係る子基板の製造方法を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment. 実施の形態１に係る子基板の製造方法を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment. 実施の形態１に係る子基板の製造方法を示す概略断面図である。FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment. 実施の形態１に係る実装構造の製造方法を示す概略断面図である。5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1. FIG. 実施の形態１に係る実装構造の製造方法を示す概略断面図である。5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1. FIG. 実施の形態１に係る実装構造の製造方法を示す概略断面図である。5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1. FIG. 実施の形態１に係る実装構造の製造方法を示す概略断面図である。5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1. FIG. 実施の形態１に係る子基板の構成を示す拡大断面図である。FIG. 3 is an enlarged cross-sectional view illustrating a configuration of a daughter board according to the first embodiment. 実施の形態２に係る実装構造の構成を示す概略断面図である。6 is a schematic cross-sectional view showing a configuration of a mounting structure according to Embodiment 2. FIG. 実施の形態２に係る実装構造の構成を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view illustrating a configuration of a mounting structure according to a second embodiment. 実施の形態２に係る子基板の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2. 実施の形態２に係る子基板の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2. 実施の形態２に係る子基板の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2. 実施の形態２に係る子基板の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2. 実施の形態２に係る実装構造の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment. 実施の形態２に係る実装構造の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment. 実施の形態２に係る実装構造の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment. 実施の形態２に係る実装構造の製造方法を示す概略断面図である。FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment. 実施の形態２に係る子基板の構成を示す拡大断面図である。FIG. 5 is an enlarged cross-sectional view showing a configuration of a daughter board according to a second embodiment. 実施の形態３に係る実装構造の構成を示す概略断面図である。FIG. 6 is a schematic cross-sectional view showing a configuration of a mounting structure according to a third embodiment. 実施の形態３に係る実装構造の構成を示す拡大断面図である。FIG. 6 is an enlarged cross-sectional view illustrating a configuration of a mounting structure according to a third embodiment. 実施の形態３に係る実装構造の製造方法を示す概略断面図である。FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment. 実施の形態３に係る実装構造の製造方法を示す概略断面図である。FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment. 実施の形態３に係る実装構造の製造方法を示す概略断面図である。FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment. 実施の形態３に係る実装構造の製造方法を示す概略断面図である。FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment. 実施の形態４に係る実装構造の構成を示す概略断面図である。FIG. 6 is a schematic cross-sectional view showing a configuration of a mounting structure according to a fourth embodiment.

（本発明の特徴）
本発明の実施の形態の説明に先立って、図１の概略断面図を用いて、本発明の特徴についてその概要を説明する。(Features of the present invention)
Prior to the description of the embodiment of the present invention, the outline of the features of the present invention will be described with reference to the schematic sectional view of FIG.

図１に示すように、本発明に係る電子機器（実装構造に相当）１００は、接続支持部（子基板や半田付けスペーサなどに相当）１０１、第１の電子部品（ｅＭＭＣなどの半導体装置に相当）１０２、基板（親基板に相当）１０３、バイパスコンデンサなどの第２の電子部品（周辺部品に相当）１０４を備えている。   As shown in FIG. 1, an electronic device (corresponding to a mounting structure) 100 according to the present invention includes a connection support portion (corresponding to a sub board and a soldering spacer) 101, a first electronic component (a semiconductor device such as eMMC). Equivalent) 102, a substrate (corresponding to a parent substrate) 103, and a second electronic component (corresponding to a peripheral component) 104 such as a bypass capacitor.

そして、基板１０３は実装面１０３ａを有し、第１の電子部品１０２は実装面１０３ａの上方に実装され、接続支持部１０１は、基板１０３と第１の電子部品１０２との間の領域で、基板１０３と第１の電子部品１０２とを電気的に接続するとともに、第１の電子部品１０２を基板１０３から所定の位置に支持し、第２の電子部品１０４は、基板１０３と第１の電子部品１０２との間の領域のうち接続支持部の配置領域１０５ａを外した配置領域１０５ｂで、実装面１０３ａに実装されている。すなわち、本発明に係る電子機器１００は、基板１０３と、基板１０３上に実装される第１の電子部品１０２と、基板１０３と第１の電子部品１０２との間で、基板１０３と第１の電子部品１０２とを電気的に接続するとともに、基板１０３上に第１の電子部品１０２を支持する接続支持部１０１と、基板１０３と第１の電子部品１０２との間で、基板１０３上に実装される第２の電子部品１０４と、を備えることを、本発明の主要な特徴としている。   The substrate 103 has a mounting surface 103a, the first electronic component 102 is mounted above the mounting surface 103a, and the connection support portion 101 is an area between the substrate 103 and the first electronic component 102. The substrate 103 and the first electronic component 102 are electrically connected, the first electronic component 102 is supported at a predetermined position from the substrate 103, and the second electronic component 104 is connected to the substrate 103 and the first electronic component 102. The mounting area 103b is mounted on the mounting surface 103a in an area 105b from which the connection support area 105a is removed. That is, the electronic device 100 according to the present invention includes the substrate 103, the first electronic component 102 mounted on the substrate 103, and the substrate 103 and the first electronic component 102. The electronic component 102 is electrically connected and mounted on the substrate 103 between the substrate 103 and the first electronic component 102, and the connection support unit 101 that supports the first electronic component 102 on the substrate 103. It is a main feature of the present invention that the second electronic component 104 is provided.

このように、本発明では、基板に実装される半導体装置等の第１の電子部品を接続支持部により接続及び支持するようにし、接続支持部が接続及び支持することにより形成される空間（領域１０５ｂ）に周辺部品等の第２の電子部品を実装することとした。これにより、第１の電子部品の周辺に第２の電子部品を並べて実装する場合と比べて、実装面積を削減できるため実装面積の増大を防ぐことができる。   Thus, in the present invention, the first electronic component such as a semiconductor device mounted on the substrate is connected and supported by the connection support portion, and the space (region) formed by the connection support portion connecting and supporting the space (region). A second electronic component such as a peripheral component is mounted on 105b). As a result, the mounting area can be reduced as compared with the case where the second electronic components are mounted side by side around the first electronic component, so that an increase in the mounting area can be prevented.

ところで、上記のように、ｅＭＭＣのような半導体装置では、メモリ容量の増大とともにパッケージ外形の大型化が進むとともに、端子の配置はＪＥＤＥＣなどの規格により規定されるため一定の制約がある。例えば、ＢＧＡパッケージなどの半導体装置では、半導体装置中央部に端子を配列するため、パッケージ外形が大きくなると、半導体装置中央部の端子とパッケージ外形端との距離が長くなる。   By the way, as described above, in a semiconductor device such as eMMC, as the memory capacity increases, the package outline size increases, and the terminal arrangement is defined by a standard such as JEDEC, and thus has certain restrictions. For example, in a semiconductor device such as a BGA package, since terminals are arranged in the central portion of the semiconductor device, the distance between the terminal in the central portion of the semiconductor device and the package outer edge increases as the package outer shape increases.

そうすると、ｅＭＭＣなどの大型化した半導体装置の周辺に周辺部品を並べて実装すると、半導体装置の端子と周辺部品とを接続する配線の配線長が長くなってしまう。このため、半導体装置の周辺に周辺部品を並べて実装すると、実装面積が増大するとともに、周辺部品によるノイズの低減効果が低くなるなど、特性が劣化するという問題があった。   Then, when peripheral components are mounted side by side around a large semiconductor device such as eMMC, the wiring length of the wiring connecting the terminals of the semiconductor device and the peripheral components becomes long. For this reason, when peripheral components are mounted side by side on the periphery of the semiconductor device, there is a problem that the mounting area increases and the effect of noise reduction by the peripheral components decreases, leading to deterioration of characteristics.

そこで、本発明では、特に、図１のように第１の電子部品の下の領域に第２の電子部品を配置する電子機器１００において、第２の電子部品１０４と第１の電子部品１０２とを接続支持部１０１を介して電気的に接続することも可能である。これにより、第２の電子部品を第１の電子部品の周辺に配置して接続する場合と比べて、第２の電子部品と第１の電子部品とを接続する配線長が短くなるため、特性の劣化を抑えることができる。   Therefore, in the present invention, particularly in the electronic device 100 in which the second electronic component is arranged in the region below the first electronic component as shown in FIG. 1, the second electronic component 104, the first electronic component 102, Can be electrically connected via the connection support portion 101. As a result, the wiring length connecting the second electronic component and the first electronic component is shortened as compared with the case where the second electronic component is arranged and connected around the first electronic component. Can be prevented.

なお、上記特許文献１〜６では、実装する半導体パッケージ（モジュール含む）として、専用の半導体パッケージが必要となるため、汎用的な半導体装置を使用することは困難である。これに対し、本発明では、ＪＥＤＥＣなどで標準化された半導体装置を適用することが可能である。これにより大幅なコスト削減を図ることができる。また、特許文献１〜６では、半導体装置の端子数が多くなると周辺部品の配置面積が減少、あるいは無くなるのに対し、本発明は端子数が決められた半導体装置を使用するため、周辺部品の配置面積が減少することはない。   In Patent Documents 1 to 6, since a dedicated semiconductor package is required as a semiconductor package (including a module) to be mounted, it is difficult to use a general-purpose semiconductor device. On the other hand, in the present invention, it is possible to apply a semiconductor device standardized by JEDEC or the like. As a result, significant cost reduction can be achieved. In Patent Documents 1 to 6, when the number of terminals of the semiconductor device increases, the arrangement area of the peripheral components decreases or disappears. On the other hand, the present invention uses a semiconductor device with a determined number of terminals. The layout area does not decrease.

また、上記特許文献２や３には、子基板の両面に周辺部品を実装できることが記載されている。特許文献２や３のように、例えば、周辺部品を実装した子基板を親基板上に実装し、子基板上に半導体装置を実装したとする。そうすると、半導体装置の実装高さに加え、子基板の厚みと周辺部品の実装高さ、および親基板と周辺部品とのクリアランスの合算値が全体の高さになるため、薄型化が困難である。   Patent Documents 2 and 3 describe that peripheral components can be mounted on both sides of the sub board. As in Patent Documents 2 and 3, for example, it is assumed that a child board on which peripheral components are mounted is mounted on a parent board, and a semiconductor device is mounted on the child board. Then, in addition to the mounting height of the semiconductor device, the total value of the thickness of the child board and the mounting height of the peripheral components, and the clearance between the parent substrate and the peripheral components is the total height, making it difficult to reduce the thickness. .

これに対し、本発明の構成では、半導体装置のボディ厚と周辺部品の実装高さ、及び両者のクリアランスの合算値が全体の高さとなるため、特許文献２や３よりも薄型化が可能である。   On the other hand, in the configuration of the present invention, the total thickness of the body thickness of the semiconductor device, the mounting height of the peripheral components, and the clearance between them is the total height, so that it can be made thinner than Patent Documents 2 and 3. is there.

また、上記特許文献４や５には、半導体パッケージを搭載する複数の基板間をそれぞれ中継基板を介して接続することが記載されている。しかしながら、特許文献４や５では、半導体パッケージの周囲に中継基板を配置する構成のため、半導体パッケージの大きさや端子数によっては、半導体パッケージを搭載する基板を大きくする必要がある（例えば特許文献４の図１の基板１３２など）。また、特許文献４や５では、複数の専用モジュール基板と複数の中継基板を用いており、コスト面に問題がある。   Patent Documents 4 and 5 describe that a plurality of substrates on which a semiconductor package is mounted are connected to each other via a relay substrate. However, in Patent Documents 4 and 5, since the relay substrate is arranged around the semiconductor package, the substrate on which the semiconductor package is mounted needs to be enlarged depending on the size of the semiconductor package and the number of terminals (for example, Patent Document 4). 1 and the like in FIG. In Patent Documents 4 and 5, a plurality of dedicated module substrates and a plurality of relay substrates are used, which causes a problem in cost.

これに対し、本発明の構成では、端子数が多い場合においても半導体装置２の投影面積に影響することなく子基板（スペーサ基板）の配置が可能であり、制約なく小型化が可能である。また、１枚の子基板（スペーサ基板）で構成されていることから、特許文献４や５に対しコスト面でも優位である。   On the other hand, in the configuration of the present invention, even when the number of terminals is large, the child substrate (spacer substrate) can be arranged without affecting the projected area of the semiconductor device 2, and the size can be reduced without restriction. Further, since it is composed of a single sub-substrate (spacer substrate), it is superior to Patent Documents 4 and 5 in terms of cost.

また、上記特許文献６には、サイズが異なる複数の半導体素子を積層し実装面積を縮小することが記載されている。しかしながら、特許文献６では、提案の構造を実現するために、実際の製造工程では接着材料の塗布、チップの搭載、接着材料の加熱硬化を複数回繰り返してチップを重ねた後、電気接続をワイヤーボンディングで１本１本行っており、製造工程が複雑である。また、スペーサチップは電気接続を伴わず、配線長の短縮に寄与していない。   Patent Document 6 describes that a plurality of semiconductor elements having different sizes are stacked to reduce the mounting area. However, in Patent Document 6, in order to realize the proposed structure, in the actual manufacturing process, after applying the adhesive material, mounting the chip, and heating and curing the adhesive material several times, the chips are stacked, and then the electrical connection is made by wire. Bonding is performed one by one, and the manufacturing process is complicated. In addition, the spacer chip does not involve electrical connection and does not contribute to shortening the wiring length.

これに対し、本発明は、ＳＭＴ（Surface Mount Technology）による一括リフローではんだ接続するシンプルな製造工程となっており、製造コストの面で優位である。また、接続支持部と電子部品を接続することで、配線長の短縮も可能である。   On the other hand, the present invention is a simple manufacturing process in which solder connection is performed by batch reflow using SMT (Surface Mount Technology), which is advantageous in terms of manufacturing cost. Also, the wiring length can be shortened by connecting the connection support portion and the electronic component.

（実施の形態１）
以下、本発明の実施の形態１について図面を参照して説明する。図２は、本実施の形態に係る実装構造１００の構成を示す概略断面図であり、図３は、図２の実装構造１００の拡大断面図である。この実装構造１００は、例えば、スマートフォンやタブレット端末、携帯電話など、小型化や薄型化が求められる携帯電子機器に内蔵される実装構造１００である。(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings. 2 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment, and FIG. 3 is an enlarged cross-sectional view of the mounting structure 100 of FIG. The mounting structure 100 is a mounting structure 100 built in a portable electronic device that is required to be reduced in size or thickness, such as a smartphone, a tablet terminal, or a mobile phone.

本実施の形態は、子基板に両面プリント配線板を用いて、親基板に半導体装置を実装する例である。図２に示すように、実装構造１００は、主に、子基板１、半導体装置２、親基板５、周辺部品７を備えている。本実施の形態の実装構造１００では、親基板５の上面（実装面）に周辺部品７を実装するとともに、両面配線板から構成される子基板１を介して半導体装置２を実装する。   This embodiment is an example in which a semiconductor device is mounted on a parent substrate using a double-sided printed wiring board on the child substrate. As shown in FIG. 2, the mounting structure 100 mainly includes a child substrate 1, a semiconductor device 2, a parent substrate 5, and peripheral components 7. In the mounting structure 100 of the present embodiment, the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5, and the semiconductor device 2 is mounted via the child substrate 1 constituted by a double-sided wiring board.

なお、実装構造１００で親基板５に半導体装置２が実装されている状態において、親基板５の位置よりも半導体装置２の位置の方が上であり、反対に、半導体装置２の位置よりも親基板５の位置の方が下である。   In the state where the semiconductor device 2 is mounted on the parent substrate 5 in the mounting structure 100, the position of the semiconductor device 2 is higher than the position of the parent substrate 5, and conversely, the position of the semiconductor device 2. The position of the parent substrate 5 is lower.

半導体装置２は、ｅＭＭＣなどの半導体装置である。半導体装置２は、ＢＧＡ（Ball grid array）やＬＧＡ（Land grid array）などのパッケージ構造であり（図２はＢＧＡの例である）、下面に複数の下部電極３を有するフェイスダウン実装型の半導体装置である。例えば、複数の下部電極３は、ＪＥＤＥＣ等の規格に規定された形状、サイズ、配列数、ピッチにしたがって配列されている。また、半導体装置２は、大容量のメモリを内蔵した大型パッケージの装置であり、下部電極３が半導体装置２の下面の略中央部の配置領域５ａに配置されている。このため、下部電極３の配置領域５ａとパッケージ外形端とが離間している。例えば、下部電極３の配置領域５ａから半導体装置２の外形端までは、周辺部品７の大きさと同じ程度もしくはそれ以上離れている。   The semiconductor device 2 is a semiconductor device such as eMMC. The semiconductor device 2 has a package structure such as a BGA (Ball grid array) or an LGA (Land grid array) (FIG. 2 is an example of a BGA), and a face-down mounting type semiconductor having a plurality of lower electrodes 3 on the lower surface. Device. For example, the plurality of lower electrodes 3 are arranged in accordance with the shape, size, number of arrangements, and pitch specified in standards such as JEDEC. The semiconductor device 2 is a large package device incorporating a large-capacity memory, and the lower electrode 3 is arranged in the arrangement region 5 a at the substantially central portion of the lower surface of the semiconductor device 2. For this reason, the arrangement | positioning area | region 5a of the lower electrode 3 and the package external end are spaced apart. For example, the arrangement region 5 a of the lower electrode 3 and the outer edge of the semiconductor device 2 are separated by the same size or more than the size of the peripheral component 7.

周辺部品７は、バイパスコンデンサ等であり半導体装置２のノイズ低減等のために電気的特性上必要な部品である。周辺部品７は、両端部に、親基板５と接続し実装するための接続電極７ａを備えている。そして、周辺部品７は、親基板５及び子基板１を介して半導体装置２と電気的に接続される。   The peripheral component 7 is a bypass capacitor or the like, and is a component necessary for electrical characteristics for reducing noise of the semiconductor device 2. The peripheral component 7 is provided with connection electrodes 7a at both ends so as to be connected to and mounted on the parent substrate 5. The peripheral component 7 is electrically connected to the semiconductor device 2 via the parent substrate 5 and the child substrate 1.

親基板５は、半導体装置２及び周辺部品７を上面（実装面）に実装するための実装基板である。例えば、親基板５の外形は、半導体装置２を実装するために、少なくとも半導体装置２の外形よりも大きい形状である。親基板５は、片面、または２層以上の多層プリント配線板であり、上面に複数の接続パッド（接続配線）９を有している。接続パッド９は、実装される半導体装置２及び周辺部品７と電気的に接続するためのパッドであり、必要な配線パターンとなるように形成されている。例えば、接続パッド９ａは周辺部品７と半導体装置２を接続するように配線されている。   The parent substrate 5 is a mounting substrate for mounting the semiconductor device 2 and the peripheral components 7 on the upper surface (mounting surface). For example, the outer shape of the parent substrate 5 is larger than at least the outer shape of the semiconductor device 2 in order to mount the semiconductor device 2. The parent substrate 5 is a single-sided or multilayer printed wiring board having two or more layers, and has a plurality of connection pads (connection wirings) 9 on the upper surface. The connection pad 9 is a pad for electrical connection with the semiconductor device 2 and the peripheral component 7 to be mounted, and is formed to have a necessary wiring pattern. For example, the connection pad 9 a is wired so as to connect the peripheral component 7 and the semiconductor device 2.

複数の接続パッド９は、半導体装置２と重なる領域のうち、半導体装置２の下部電極３（配置領域５ａ）に対応する位置に形成されている。もしくは、複数の接続パッド９は、子基板１の下面電極４ｂに対応する位置に配列形成されているともいえる。また、接続パッド９は、半導体装置２と重なる領域のうち、周辺部品７の接続電極７ａ（配置領域５ｂ）に対応する位置にも形成されている。   The plurality of connection pads 9 are formed at positions corresponding to the lower electrode 3 (arrangement region 5 a) of the semiconductor device 2 in the region overlapping the semiconductor device 2. Alternatively, it can be said that the plurality of connection pads 9 are arranged and formed at positions corresponding to the lower surface electrodes 4 b of the daughter board 1. Further, the connection pad 9 is also formed at a position corresponding to the connection electrode 7 a (arrangement region 5 b) of the peripheral component 7 in the region overlapping with the semiconductor device 2.

接続パッド９と周辺部品７の接続電極７ａとは半田接続されている。周辺部品７に接続される接続パッド９ａは、周辺部品７の接続電極７ａに対応する位置から、半導体装置２の下部電極３（子基板１の下面電極４ｂ）に対応する位置まで延在形成されており、周辺部品７と半導体装置２（子基板１）とを電気的に接続する。   The connection pad 9 and the connection electrode 7a of the peripheral component 7 are connected by soldering. The connection pad 9a connected to the peripheral component 7 is formed to extend from a position corresponding to the connection electrode 7a of the peripheral component 7 to a position corresponding to the lower electrode 3 of the semiconductor device 2 (the lower surface electrode 4b of the child substrate 1). The peripheral component 7 and the semiconductor device 2 (child board 1) are electrically connected.

子基板１は、半導体装置２を親基板５に接続し実装するとともに、半導体装置２を所定の位置（高さ）に支持するための接続支持基板である。また、子基板１は、半導体装置２を支持することで、周辺部品７を配置するための配置領域（空間）５ｂを形成する基板ともいえる。   The sub board 1 is a connection support board for connecting and mounting the semiconductor device 2 to the main board 5 and supporting the semiconductor device 2 at a predetermined position (height). The sub board 1 can also be said to be a board that forms the arrangement region (space) 5b for arranging the peripheral component 7 by supporting the semiconductor device 2.

例えば、子基板１の基材は、ポリイミドフィルムやセラミックス、ガラスなど、配線パターンの形成が可能で、且つリフロー耐熱性を持つ材料であれば、特に限定されない。また、配線材料は、高い導電性を持つ材料であれば特に限定されない。   For example, the base material of the sub-board 1 is not particularly limited as long as it is a material that can form a wiring pattern and has reflow heat resistance, such as polyimide film, ceramics, and glass. The wiring material is not particularly limited as long as it is a material having high conductivity.

子基板１は、両面プリント配線板であり、上面（表面）に複数の上面電極４ａを有し、下面（裏面）に複数の下面電極４ｂを有している。複数の上面電極４ａ及び下面電極４ｂは、半導体装置２の下部電極３（配置領域５ａ）と対応する位置に配列形成されている。なお、下部電極３のうち、特性上電気接続が不要な電極については、対応する上面電極４ａ及び下面電極４ｂを配置しなくても良い。下面電極４ｂは、上面電極４ａの直下の下面（裏面）に形成されている。上面電極４ａ及び下面電極４ｂは、基板の表裏がほぼ対称となるよう同形状、またはそれに近い形状とし、リフロー時の反り対策が施されている。   The sub board 1 is a double-sided printed wiring board, and has a plurality of upper surface electrodes 4a on the upper surface (front surface) and a plurality of lower surface electrodes 4b on the lower surface (back surface). The plurality of upper surface electrodes 4 a and lower surface electrodes 4 b are arranged in positions corresponding to the lower electrodes 3 (arrangement regions 5 a) of the semiconductor device 2. Note that the upper electrode 4a and the lower electrode 4b that correspond to the electrodes that do not require electrical connection due to characteristics among the lower electrodes 3 do not have to be disposed. The lower surface electrode 4b is formed on the lower surface (back surface) immediately below the upper surface electrode 4a. The upper surface electrode 4a and the lower surface electrode 4b have the same shape or a shape close to that so that the front and back of the substrate are substantially symmetrical, and are provided with a countermeasure against warping during reflow.

図３に示すように、上面電極４ａと下面電極４ｂの間にインタスティシャルバイアホール（Interstitial Via Hole、もしくはバイアホールとも称する）８が形成されている。バイアホール８は、子基板１の上面から下面まで貫通するように、すなわち、上面電極４ａの下面（裏面）から下面電極４ｂの上面（裏面）に達するように形成されている。そして、バイアホール８の内部に銅めっき１５が埋め込まれており、銅めっき１５により上面電極４ａと下面電極４ｂとが電気的に接続されている。   As shown in FIG. 3, an interstitial via hole (also referred to as an interstitial via hole or via hole) 8 is formed between the upper surface electrode 4a and the lower surface electrode 4b. The via hole 8 is formed so as to penetrate from the upper surface to the lower surface of the daughter board 1, that is, from the lower surface (back surface) of the upper electrode 4a to the upper surface (back surface) of the lower electrode 4b. A copper plating 15 is buried inside the via hole 8, and the upper surface electrode 4 a and the lower surface electrode 4 b are electrically connected by the copper plating 15.

上面電極４ａは、半導体装置２の下部電極３と半田接続され、下面電極４ｂは、親基板５の接続パッド（半田付けパッド）９と半田等の導電性接続材料６を介して接続されている。これにより、半導体装置２の下部電極３と親基板５の接続パッド９とを電気的に接続している。   The upper surface electrode 4a is connected to the lower electrode 3 of the semiconductor device 2 by soldering, and the lower surface electrode 4b is connected to a connection pad (soldering pad) 9 of the parent substrate 5 via a conductive connection material 6 such as solder. . Thus, the lower electrode 3 of the semiconductor device 2 and the connection pad 9 of the parent substrate 5 are electrically connected.

子基板１の外形端は、上面電極４ａ及び下面電極４ｂの近傍となるよう切断されている。子基板１は、半導体装置２の下部電極３に対応して上面電極４ａ及び下面電極４ｂが形成できる程度の外形であり、例えば、半導体装置２の下部電極３の配置領域５ａと同程度の大きさである。   The outer end of the daughter board 1 is cut so as to be in the vicinity of the upper surface electrode 4a and the lower surface electrode 4b. The sub-substrate 1 has an outer shape that can form an upper surface electrode 4 a and a lower surface electrode 4 b corresponding to the lower electrode 3 of the semiconductor device 2, and is, for example, as large as the arrangement region 5 a of the lower electrode 3 of the semiconductor device 2. That's it.

なお、各接続パッド９の間、各下部電極３の間、各上面電極４ａの間、各下面電極４ｂの間には、半田付けする際に半田が不要な箇所へ流れないようにするためソルダーレジストを形成してもよい。   In order to prevent solder from flowing to unnecessary portions between the connection pads 9, the lower electrodes 3, the upper surface electrodes 4a, and the lower surface electrodes 4b. A resist may be formed.

実装構造１００の配置関係を説明すると、図２に示すように、親基板５の上に子基板１が配置され、さらに子基板１の上に半導体装置２が配置される。半導体装置２の下面中央部の配置領域５ａに下部電極３が形成されており、配置領域５ａの下に子基板１が配置される。子基板１は、半導体装置２の下部電極３の配置領域５ａに対応した形状であり、半導体装置２の外形よりも小さい。
そして、半導体装置２の下面周辺部の配置領域５ｂの下に周辺部品７が配置される。すなわち、子基板１の外形端から半導体装置２の外形端までの配置領域５ｂに周辺部品７が配置される。配置領域５ｂは、子基板１が半導体装置を所定の高さに支持することにより、半導体装置２の下面と子基板１の側面と親基板５の上面とに囲まれて形成される空間である。すなわち、周辺部品７は、配置領域５ｂに収納配置されており、配置領域５ｂは、少なくとも、周辺部品７の全部もしくは一部が収納可能な領域である。The arrangement relationship of the mounting structure 100 will be described. As shown in FIG. 2, the sub board 1 is arranged on the main board 5, and the semiconductor device 2 is arranged on the sub board 1. The lower electrode 3 is formed in the arrangement region 5a at the center of the lower surface of the semiconductor device 2, and the child substrate 1 is arranged under the arrangement region 5a. The sub substrate 1 has a shape corresponding to the arrangement region 5 a of the lower electrode 3 of the semiconductor device 2 and is smaller than the outer shape of the semiconductor device 2.
Then, the peripheral component 7 is arranged below the arrangement region 5 b in the lower peripheral portion of the semiconductor device 2. That is, the peripheral component 7 is arranged in the arrangement region 5 b from the outer edge of the sub board 1 to the outer edge of the semiconductor device 2. The arrangement region 5b is a space formed by the child substrate 1 supporting the semiconductor device at a predetermined height so as to be surrounded by the lower surface of the semiconductor device 2, the side surface of the child substrate 1, and the upper surface of the parent substrate 5. . That is, the peripheral component 7 is accommodated and arranged in the arrangement area 5b, and the arrangement area 5b is an area in which at least all or a part of the peripheral component 7 can be accommodated.

本実施の形態では、このような配置とするため、各部材は図３に示すような高さ（上下方向の長さ）の関係となる。すなわち、本実施の形態における子基板１の厚み（上下電極間距離）は、半導体装置２と周辺部品７とが高さ方向で接触しないよう、次の式１を満たす厚みで予め設計される。なお、子基板１のスタンドオフＬ１は子基板１の導電性接続材料６（半田ペースト）の実装時の高さであり、半導体装置２のスタンドオフＬ３は半導体装置２の下部電極３の実装時の高さである。
［子基板１のスタンドオフＬ１］＋［子基板１の上下電極間距離Ｌ２］＋［半導体装置２のスタンドオフＬ３］≧［周辺部品７の半田高さＬ４］＋［周辺部品７の高さＬ５］・・・（式１）In this embodiment, in order to achieve such an arrangement, each member has a relationship of height (length in the vertical direction) as shown in FIG. That is, the thickness (distance between the upper and lower electrodes) of the sub board 1 in the present embodiment is designed in advance so as to satisfy the following formula 1 so that the semiconductor device 2 and the peripheral component 7 do not contact in the height direction. The stand-off L1 of the sub-board 1 is the height when the conductive connection material 6 (solder paste) of the sub-board 1 is mounted, and the stand-off L3 of the semiconductor device 2 is when the lower electrode 3 of the semiconductor device 2 is mounted. Of height.
[Standoff L1 of Substrate 1] + [Distance L2 between Upper and Lower Electrodes of Substrate 1] + [Standoff L3 of Semiconductor Device 2] ≧ [Solder Height L4 of Peripheral Component 7] + [Height of Peripheral Component 7] L5] (Formula 1)

式１を満たすように子基板１の厚さを設計することで、図３のように、周辺部品７を半導体装置２の直下に配置することが可能となり、周辺部品７と半導体装置２の下部電極３との配線長の短縮による電気特性の向上、及び実装面積の削減という効果がもたらされる。   By designing the thickness of the sub board 1 so as to satisfy Equation 1, the peripheral component 7 can be arranged directly below the semiconductor device 2 as shown in FIG. The effect of improving the electrical characteristics and reducing the mounting area by shortening the wiring length with the electrode 3 is brought about.

なお、プリント配線板の設計ツール（ＣＡＤ）では、部品搭載時に隣接する部品同士が干渉しないよう、部品の外形公差や搭載機の搭載位置精度等を考慮し、部品外形よりも一回り大きい重複禁止領域を設けており、プリント配線板を設計する際は各部品の重複禁止領域が重ならないよう制限している。このため、本実施の形態の実装構造を設計する際には、予め本制限を解除し、親基板を設計する。すなわち、設計者は、プリント板配線設計ツールの設計ルールを変更し、親基板５と半導体装置２の間に、子基板１を配置するとともに、周辺部品７を配置する。   In addition, the printed wiring board design tool (CAD) prohibits duplication that is one size larger than the part outline, taking into consideration the outline tolerance of the parts and the mounting position accuracy of the mounting machine so that adjacent parts do not interfere with each other when mounting the parts. An area is provided, and when the printed wiring board is designed, the overlap prohibition area of each part is restricted so as not to overlap. For this reason, when designing the mounting structure of the present embodiment, the restriction is released in advance and the parent board is designed. That is, the designer changes the design rule of the printed board wiring design tool, and places the child board 1 and the peripheral component 7 between the parent board 5 and the semiconductor device 2.

次に、図４Ａ〜図４Ｅ及び図５Ａ〜図５Ｄを参照して、本実施の形態に係る実装構造１００の製造方法を説明する。まず、図４Ａ〜図４Ｅを用いて前工程の製造方法を説明する。図４Ａ〜図４Ｅの前工程では、両面にそれぞれ上面電極４ａと下面電極４ｂを有する子基板１を形成する。   Next, a method for manufacturing the mounting structure 100 according to the present embodiment will be described with reference to FIGS. 4A to 4E and FIGS. 5A to 5D. First, the manufacturing method of a pre-process is demonstrated using FIG. 4A-FIG. 4E. 4A to 4E, the child substrate 1 having the upper surface electrode 4a and the lower surface electrode 4b on both surfaces is formed.

前工程では、まず、図４Ａに示すように、上面に上面導体１２が形成され、下面に下面導体１３が形成された両面銅張積層板１１を用意する。続いて、図４Ｂに示すように、両面銅張積層板１１の両面の上面導体１２及び下面導体１３をフォトリソ（フォトリソグラフィ）法により化学エッチングすることで、上面電極４ａ及び下面電極４ｂを形成する。半導体装置２における下部電極３の配置パターンと対応するマスクパターンを用いて、上面電極４ａ及び下面電極４ｂを下部電極３の配置に対応するように形成する。上面電極４ａ及び下面電極４ｂの形状は、後の工程で上面電極４ａ上に実装される半導体装置２の下部電極３が接続されるサブストレートの電極に近い形状とする。   In the pre-process, first, as shown in FIG. 4A, a double-sided copper clad laminate 11 having an upper surface conductor 12 formed on the upper surface and a lower surface conductor 13 formed on the lower surface is prepared. Subsequently, as shown in FIG. 4B, the upper surface electrode 4a and the lower surface electrode 4b are formed by chemically etching the upper surface conductor 12 and the lower surface conductor 13 on both surfaces of the double-sided copper-clad laminate 11 by a photolithography method. . Using the mask pattern corresponding to the arrangement pattern of the lower electrode 3 in the semiconductor device 2, the upper surface electrode 4 a and the lower surface electrode 4 b are formed so as to correspond to the arrangement of the lower electrode 3. The shape of the upper surface electrode 4a and the lower surface electrode 4b is a shape close to the electrode of the substrate to which the lower electrode 3 of the semiconductor device 2 mounted on the upper surface electrode 4a in a later step is connected.

続いて、図４Ｃに示すように、両面銅張積層板１１の上面側からレーザー穴開け機を用いて、上面電極４ａの中央部に、上面電極４ａの上面（表面）から下面電極４ｂの上面（裏面）が露出するようにバイアホール８を開ける。続いて、図４Ｄに示すように、デスミア処理後に銅めっき１５でバイアホール８を埋め、上面電極４ａと下面電極４ｂを接続させる。この時、銅めっき１５により上面電極側の導体が厚くなることで、反りが生じる場合は、上面電極側の導体を下面電極側の導体と同等の厚みまでエッチングにより薄くしても良い。   Subsequently, as shown in FIG. 4C, from the upper surface side of the double-sided copper-clad laminate 11, using a laser drilling machine, in the center of the upper electrode 4a, from the upper surface (front surface) of the upper electrode 4a to the upper surface of the lower electrode 4b. Open the via hole 8 so that the (back side) is exposed. Subsequently, as shown in FIG. 4D, the via hole 8 is filled with the copper plating 15 after the desmear process, and the upper surface electrode 4a and the lower surface electrode 4b are connected. At this time, if the conductor on the upper surface electrode side is thickened by the copper plating 15 and warpage occurs, the conductor on the upper surface electrode side may be thinned by etching to the same thickness as the conductor on the lower surface electrode side.

そして最後に、図４Ｅに示すように、上面電極４ａ及び下面電極４ｂの形状精度や位置精度、分割装置の分割精度等を考慮し、上面電極４ａ及び下面電極４ｂと極力近い位置で両面銅張積層板１１を切断することで、子基板１が完成する。その後、後工程のために、完成した子基板１をトレー、またはエンボステープなど、自動搭載機で搭載可能な荷姿に収納する。なお、子基板１の厚みは、前述の式１を満たすよう基材厚、銅箔厚、めっき厚を選択し、調整しておく。   Finally, as shown in FIG. 4E, in consideration of the shape accuracy and position accuracy of the upper surface electrode 4a and the lower surface electrode 4b, the division accuracy of the dividing device, etc., the double-sided copper-clad wires are positioned as close as possible to the upper surface electrode 4a and the lower surface electrode 4b. By cutting the laminated plate 11, the daughter board 1 is completed. Thereafter, the completed sub-substrate 1 is stored in a package that can be mounted by an automatic mounting machine, such as a tray or embossed tape, for a subsequent process. The thickness of the sub board 1 is adjusted by selecting the base material thickness, the copper foil thickness, and the plating thickness so as to satisfy the above-described formula 1.

なお、図４Ａ〜図４Ｅでは、子基板１を両面銅張積層板を用いて形成しているが、両面銅張積層板以外のその他の基板を用いてもよい。例えば、両面銅張積層板ではなく、Ｂ２ｉｔ工法にて上面銅箔と下面銅箔との張り合わせと導電接続を行った後、パターンを形成した両面板を用いて子基板１を形成しても良い。また、３層以上の多層板を用いて子基板１を形成してもよい。In addition, in FIG. 4A-FIG. 4E, although the child substrate 1 is formed using the double-sided copper clad laminated board, you may use other board | substrates other than a double-sided copper clad laminated board. For example, instead of a double-sided copper-clad laminate, after the upper and lower copper foils are bonded and conductively connected by the B 2 it method, the child board 1 is formed using the double-sided board on which the pattern is formed. Also good. Further, the child substrate 1 may be formed using a multilayer board having three or more layers.

また、図４Ａ〜図４Ｅでは、子基板１の上面電極４ａから下面電極４ｂに達するバイアホール８に銅めっきを埋め込んだ、その他の方法により上面電極４ａと下面電極４ｂを電気的に接続するようにしてもよい。例えば、バイアホール８の全体を銅めっきにより埋めるのではなく、図６に示すように、バイアホール８の内壁（穴壁）に銅めっき膜１５を形成することで、上面電極４ａ及び下面電極４ｂを接続しても良い。また、銅めっきの代わりに、導電性ペーストで埋めても良い。更に、レーザーではなくメカドリルで貫通穴を開け、絶縁性ペーストで穴を埋めた後に銅めっきで蓋を形成しても良い。   4A to 4E, the upper surface electrode 4a and the lower surface electrode 4b are electrically connected by another method in which copper plating is embedded in the via hole 8 reaching the lower surface electrode 4b from the upper surface electrode 4a of the daughter board 1. It may be. For example, instead of filling the entire via hole 8 with copper plating, as shown in FIG. 6, by forming a copper plating film 15 on the inner wall (hole wall) of the via hole 8, the upper surface electrode 4a and the lower surface electrode 4b are formed. May be connected. Moreover, you may fill with a conductive paste instead of copper plating. Further, a through hole may be formed with a mechanical drill instead of a laser, and the hole may be filled with an insulating paste, and then the lid may be formed by copper plating.

次に、図５Ａ〜図５Ｄを用いて後工程の製造方法を説明する。図５Ａ〜図５Ｄの後工程では、親基板５に周辺部品７の実装と、図４Ａ〜図４Ｅで形成した子基板１を介して半導体装置２を実装し、本実施の形態に係る実装構造を形成する。   Next, the manufacturing method of a post process is demonstrated using FIG. 5A-FIG. 5D. 5A to 5D, the peripheral device 7 is mounted on the parent substrate 5 and the semiconductor device 2 is mounted via the child substrate 1 formed in FIGS. 4A to 4E, and the mounting structure according to the present embodiment Form.

後工程では、まず、図５Ａに示すように、親基板５の上面に接続パッド９を形成し、接続パッド９上に半田ペーストなどの導電性接続材料６を印刷、あるいはディスペンス等で供給する。続いて、図５Ｂに示すように、所定の接続パッド９上の導電性接続材料６の位置に、図４Ａ〜図４Ｅで形成した子基板１の下面電極４ｂを位置合わせして子基板１を搭載する。また、所定の接続パッド９上の導電性接続材料６の位置に、周辺部品７の接続電極７ａを位置合わせして周辺部品７を搭載する。   In the post-process, first, as shown in FIG. 5A, a connection pad 9 is formed on the upper surface of the parent substrate 5, and a conductive connection material 6 such as solder paste is supplied on the connection pad 9 by printing or dispensing. Subsequently, as shown in FIG. 5B, the lower substrate electrode 4 b of the child substrate 1 formed in FIGS. 4A to 4E is aligned with the position of the conductive connection material 6 on the predetermined connection pad 9 so that the child substrate 1 is positioned. Mount. Further, the peripheral component 7 is mounted by aligning the connection electrode 7 a of the peripheral component 7 at the position of the conductive connection material 6 on the predetermined connection pad 9.

続いて、図５Ｃに示すように、半導体装置２の下部電極３にフラックス、あるいは半田ペースト等の導電性接続材料１６を転写した後、子基板１の上面電極４ａの位置に、導電性接続材料１６を位置合わせして、子基板１上に半導体装置２を搭載する。   Subsequently, as shown in FIG. 5C, after the conductive connection material 16 such as flux or solder paste is transferred to the lower electrode 3 of the semiconductor device 2, the conductive connection material is placed at the position of the upper surface electrode 4a of the daughter board 1. 16 is aligned and the semiconductor device 2 is mounted on the daughter board 1.

最後に、図５Ｄに示すように、リフロー加熱を行い、半田ペーストなどの導電性接続材料６及び導電性接続材料１６を一括リフローすることで、親基板５の接続パッド９と子基板１の下面電極４ｂ、親基板５の接続パッド９と周辺部品７の接続電極７ａ、子基板１の上面電極４ａと半導体装置２の下部電極３をそれぞれ接合し、実装構造１００が完成する。これにより、半導体装置２の下部電極３の近傍（半導体装置２の直下）に周辺部品７を配置することが可能となる。   Finally, as shown in FIG. 5D, reflow heating is performed, and the conductive connection material 6 such as solder paste and the conductive connection material 16 are collectively reflowed, whereby the connection pads 9 of the parent substrate 5 and the lower surface of the child substrate 1 are obtained. The mounting structure 100 is completed by bonding the electrode 4b, the connection pad 9 of the parent substrate 5 and the connection electrode 7a of the peripheral component 7, and the upper electrode 4a of the child substrate 1 and the lower electrode 3 of the semiconductor device 2, respectively. As a result, the peripheral component 7 can be disposed in the vicinity of the lower electrode 3 of the semiconductor device 2 (immediately below the semiconductor device 2).

以上のように、本実施の形態では、下部電極を有する半導体装置と同じ位置に上面電極を有し、且つ上面電極の直下に親基板との接続用電極を有する表裏が対称の子基板において、子基板の外形端が、子基板の電極から近い位置となるよう予め切断しておき、周辺部品と共に親基板上に搭載する。その後、下部電極にフラックス、あるいは半田ペーストが転写された半導体装置を、子基板の電極に位置を合わせて子基板上に搭載し、リフロー加熱等により半田接続する。   As described above, in the present embodiment, the front and back electrodes having the upper surface electrode at the same position as the semiconductor device having the lower electrode and the connection electrode with the parent substrate immediately below the upper surface electrode are symmetrical child substrates. It cut | disconnects beforehand so that the external shape end of a sub-board may become a position near the electrode of a sub-board, and it mounts on a main board with a peripheral part. Thereafter, the semiconductor device with the flux or solder paste transferred to the lower electrode is mounted on the daughter board in alignment with the electrodes of the daughter board, and soldered by reflow heating or the like.

このような実装構造の構成とし、また、製造方法とすることで、周辺部品を半導体装置と近い距離に配置することが可能となり、電気特性の向上、及び周辺部品を含めた実装面積の削減効果を得ることができる。   By adopting such a mounting structure configuration and manufacturing method, it becomes possible to dispose peripheral components at a short distance from the semiconductor device, improving electrical characteristics, and reducing the mounting area including peripheral components. Can be obtained.

すなわち、本実施の形態の第１の効果として、子基板を介して半導体装置を親基板に実装することにより、半導体装置下方のデッドスペースに他の部品を配置することができ、高密度実装を実現した実装構造を提供することができる。   That is, as a first effect of the present embodiment, by mounting the semiconductor device on the parent substrate via the child substrate, other components can be arranged in the dead space below the semiconductor device, and high-density mounting is achieved. Realized mounting structure can be provided.

第２の効果として、半導体装置下方にバイパスコンデンサ等の周辺部品を実装するため、周辺部品と半導体装置の電極との距離を短くすることができ、電気特性の向上を実現した実装構造を提供することができる。   As a second effect, since a peripheral component such as a bypass capacitor is mounted below the semiconductor device, the distance between the peripheral component and the electrode of the semiconductor device can be shortened, and a mounting structure realizing improved electrical characteristics is provided. be able to.

第３の効果として、両面銅張積層板から構成される子基板を用いて実装構造を実現できるため、前述第１、第２の効果を、安価に提供することができる。本実施の形態では、一般的なプリント配線板の製造工程にて製造された子基板を利用し、親基板上でのパッケージオンパッケージの実装（オンボードスタック）工程を採用しているため、安価に電気特性と実装密度の向上が実現できる。   As a third effect, the mounting structure can be realized by using a child board composed of a double-sided copper-clad laminate, so that the first and second effects can be provided at low cost. In this embodiment, since a sub-board manufactured in a general printed wiring board manufacturing process is used and a package-on-package mounting (on-board stack) process is used on the parent board, the cost is low. In addition, improvements in electrical characteristics and mounting density can be realized.

（実施の形態２）
以下、本発明の実施の形態２について図面を参照して説明する。実施の形態１では、子基板を両面プリント配線板（両面銅張積層板）により構成したのに対し、本実施の形態では、子基板１を片面プリント配線板により構成する。その他の構成については、実施の形態１と同様である。(Embodiment 2)
Embodiment 2 of the present invention will be described below with reference to the drawings. In the first embodiment, the slave board is configured by a double-sided printed wiring board (double-sided copper-clad laminate), whereas in this embodiment, the secondary board 1 is configured by a single-sided printed wiring board. Other configurations are the same as those in the first embodiment.

図７は、本実施の形態に係る実装構造１００の構成を示す概略断面図であり、図８は、図７の実装構造１００の拡大断面図である。図７に示すように、実装構造１００は、図２と同様に、半導体装置２、親基板５、周辺部品７を備えており、また、片面配線板の子基板１を備えている。すなわち、本実施の形態の実装構造１００では、親基板５の上面（実装面）に周辺部品７を実装するとともに、片面配線板から構成される子基板１を介して半導体装置２を実装する。   FIG. 7 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment, and FIG. 8 is an enlarged cross-sectional view of the mounting structure 100 of FIG. As shown in FIG. 7, the mounting structure 100 includes the semiconductor device 2, the parent substrate 5, and peripheral components 7 as in FIG. 2, and also includes the single-sided wiring board child substrate 1. That is, in the mounting structure 100 of the present embodiment, the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5 and the semiconductor device 2 is mounted via the child substrate 1 composed of a single-sided wiring board.

この例では、子基板１における下面導体の下面（表面）が複数の下面電極４ｂとなり、下面導体（下面電極４ｂ）の上面（裏面）が上面電極４ａとなる。なお、子基板１の下面導体ではなく、上面導体の上面（表面）を上面電極４ａとし、上面導体の下面（裏面）を下面電極４ｂとしてもよい。   In this example, the lower surface (front surface) of the lower surface conductor in the sub-substrate 1 is a plurality of lower surface electrodes 4b, and the upper surface (back surface) of the lower surface conductor (lower surface electrode 4b) is the upper surface electrode 4a. The upper surface (front surface) of the upper surface conductor may be the upper surface electrode 4a, and the lower surface (back surface) of the upper surface conductor may be the lower surface electrode 4b instead of the lower surface conductor of the child substrate 1.

図８に示すように、子基板１は、上面から下面まで貫通するようにバイアホール８が形成されている。すなわち、バイアホール８は、子基板１の上面から下面電極４ｂの上面（裏面）に達するように形成され、下面電極４ｂの上面が上面電極４ａとなる。バイアホール８には実装時に下部電極３が埋め込まれ、上面電極４ａは下部電極３とバイアホール８を介して半田接続される。   As shown in FIG. 8, the sub-substrate 1 is formed with via holes 8 so as to penetrate from the upper surface to the lower surface. That is, the via hole 8 is formed so as to reach the upper surface (back surface) of the lower surface electrode 4b from the upper surface of the daughter board 1, and the upper surface of the lower surface electrode 4b becomes the upper surface electrode 4a. The lower electrode 3 is embedded in the via hole 8 at the time of mounting, and the upper surface electrode 4 a is solder-connected to the lower electrode 3 via the via hole 8.

本実施の形態では、実施の形態１と同様に、半導体装置２と親基板５の間の配置領域５ａに子基板１が実装され、半導体装置２と親基板５の間の配置領域５ｂに周辺部品７が実装される。このような配置とするため、各部材は図８に示すような高さ（上下方向の長さ）の関係となる。すなわち、本実施の形態における子基板１の厚み（電極の導体厚＋基板厚）は、半導体装置２と周辺部品７とが高さ方向で接触しないよう、次の式２を満たす厚みで予め設計される。
［子基板１のスタンドオフＬ１］＋［子基板１の導体厚及び基板厚Ｌ２］＋［半導体装置２のスタンドオフＬ３］≧［周辺部品７の半田高さＬ４］＋［周辺部品７の高さＬ５］・・・（式２）In the present embodiment, similar to the first embodiment, the sub board 1 is mounted in the arrangement area 5 a between the semiconductor device 2 and the parent board 5, and the arrangement area 5 b between the semiconductor device 2 and the parent board 5 is peripheral. The component 7 is mounted. In order to achieve such an arrangement, each member has a height (vertical length) relationship as shown in FIG. That is, the thickness of the daughter board 1 in this embodiment (electrode conductor thickness + substrate thickness) is designed in advance so as to satisfy the following expression 2 so that the semiconductor device 2 and the peripheral component 7 do not contact in the height direction. Is done.
[Stand-off L1 of Sub-Substrate 1] + [Conductor Thickness of Sub-Substrate 1 and Substrate Thickness L2] + [Stand-off L3 of Semiconductor Device 2] ≧ [Solder Height L4 of Peripheral Component 7] + [High of Peripheral Component 7] L5] (Expression 2)

式２を満たすように子基板１の厚さを設計することで、図８のように、実施の形態１と同様、周辺部品７を半導体装置２の直下に配置することが可能となる。実施の形態１の式１では、Ｌ２は子基板１の上下電極間距離（２枚の導体厚＋基材厚）であったため、Ｌ２を小さくすることは困難な恐れがある。本実施の形態では式２のように、Ｌ２が子基板１の下面導体の厚さと基板の厚さの合計（導体厚＋基板厚）のみとなる。このため、容易にＬ２を小さくすることが可能となる。したがって、Ｌ２の厚さを大きくする必要がある場合には、実施の形態１を採用することが好ましく、Ｌ２の厚さを小さくする必要がある場合には、実施の形態２を採用することが好ましい。   By designing the thickness of the sub board 1 so as to satisfy Expression 2, the peripheral component 7 can be arranged immediately below the semiconductor device 2 as in the first embodiment as shown in FIG. In Formula 1 of Embodiment 1, L2 is the distance between the upper and lower electrodes of the child substrate 1 (the thickness of two conductors + the thickness of the base material), so it may be difficult to reduce L2. In the present embodiment, as expressed by Equation 2, L2 is only the sum of the thickness of the lower surface conductor of the child substrate 1 and the thickness of the substrate (conductor thickness + substrate thickness). For this reason, L2 can be easily reduced. Therefore, when it is necessary to increase the thickness of L2, it is preferable to adopt the first embodiment, and when it is necessary to reduce the thickness of L2, it is possible to adopt the second embodiment. preferable.

次に、図９Ａ〜図９Ｄ及び図１０Ａ〜図１０Ｄを参照して、本実施の形態に係る実装構造１００の製造方法を説明する。まず、図９Ａ〜図９Ｄを用いて前工程の製造方法を説明する。図９Ａ〜図９Ｄの前工程では、片面に下面電極４ｂを有する子基板１を形成する。   Next, a method for manufacturing the mounting structure 100 according to the present embodiment will be described with reference to FIGS. 9A to 9D and FIGS. 10A to 10D. First, the manufacturing method of the previous process will be described with reference to FIGS. 9A to 9D. 9A to 9D, the child substrate 1 having the lower surface electrode 4b on one side is formed.

前工程では、まず、図９Ａに示すように、下面にのみ下面導体１３が形成された片面銅張積層板（導体層）１１を用意する。続いて、図９Ｂに示すように、片面銅張積層板１１の下面導体１３をフォトリソ（フォトリソグラフィ）法により化学エッチングすることで、下面電極４ｂを形成する。半導体装置２における下部電極３の配置パターンと対応するマスクパターンを用いて、下面電極４ｂを下部電極３の配置に対応するように形成する。   In the pre-process, first, as shown in FIG. 9A, a single-sided copper-clad laminate (conductor layer) 11 having a lower surface conductor 13 formed only on the lower surface is prepared. Next, as shown in FIG. 9B, the lower surface electrode 4b is formed by chemically etching the lower surface conductor 13 of the single-sided copper clad laminate 11 by a photolithography method. Using the mask pattern corresponding to the arrangement pattern of the lower electrode 3 in the semiconductor device 2, the lower surface electrode 4 b is formed so as to correspond to the arrangement of the lower electrode 3.

続いて、図９Ｃに示すように、片面銅張積層板１１の上面側からレーザー穴開け機を用いて、絶縁層を除去して下面電極４ｂの裏面（上面）を一部露出するようにバイアホール８を開ける。この露出した部分が上面電極４ａとなる。   Subsequently, as shown in FIG. 9C, vias are used so that the insulating layer is removed from the upper surface side of the single-sided copper clad laminate 11 to partially expose the back surface (upper surface) of the lower electrode 4b. Open hole 8. This exposed portion becomes the upper surface electrode 4a.

そして最後に、図９Ｄに示すように、下面電極４ｂ（上面電極４ａ）の形状精度や位置精度、分割装置の分割精度等を考慮し、下面電極４ｂ（上面電極４ａ）と極力近い位置で片面銅張積層板１１を切断することで、子基板１が完成する。   Finally, as shown in FIG. 9D, in consideration of the shape accuracy and position accuracy of the lower surface electrode 4b (upper surface electrode 4a), the division accuracy of the dividing device, etc., one side is positioned as close as possible to the lower surface electrode 4b (upper surface electrode 4a). By cutting the copper-clad laminate 11, the daughter board 1 is completed.

なお、図９Ａ〜図９Ｄでは、子基板１の上面から下面電極４ｂに達するバイアホール８を形成し、上面電極４ａと半導体装置２の下部電極３と接続しているが、その他の方法により上面電極４ａと下部電極３を電気的に接続するようにしてもよい。例えば、図１１に示すようにバイアホール８の底部において、下面電極４ｂの導体上に銅めっきやニッケルめっき等の導電層１５ａを形成し、導電層１５ａの上面を上面電極４ａとしてもよい。導電層１５ａにより上面電極４ａの高さが嵩上げされるため、式２のＬ２の微調整が容易に可能となる。   9A to 9D, via holes 8 reaching the lower surface electrode 4b from the upper surface of the daughter board 1 are formed and connected to the upper surface electrode 4a and the lower electrode 3 of the semiconductor device 2, but the upper surface is formed by other methods. The electrode 4a and the lower electrode 3 may be electrically connected. For example, as shown in FIG. 11, a conductive layer 15a such as copper plating or nickel plating may be formed on the conductor of the lower surface electrode 4b at the bottom of the via hole 8, and the upper surface of the conductive layer 15a may be used as the upper surface electrode 4a. Since the height of the upper surface electrode 4a is raised by the conductive layer 15a, fine adjustment of L2 in Expression 2 can be easily performed.

また、片面銅張積層板の剛性が低く、リフロー中の反りが大きくなる場合は、上面電極４ａの周囲を開口した補強板を、予め子基板１の上面に貼り付けておいても良い。   If the single-sided copper-clad laminate has low rigidity and warpage during reflow increases, a reinforcing plate having an opening around the upper surface electrode 4a may be attached to the upper surface of the child substrate 1 in advance.

次に、図１０Ａ〜図１０Ｄを用いて後工程の製造方法を説明する。図１０Ａ〜図１０Ｄの後工程では、親基板５に周辺部品７の実装と、図９Ａ〜図９Ｄで形成した子基板１を介して半導体装置２を実装し、本実施の形態に係る実装構造を形成する。   Next, a post-process manufacturing method will be described with reference to FIGS. 10A to 10D. 10A to 10D, the peripheral component 7 is mounted on the parent substrate 5 and the semiconductor device 2 is mounted via the child substrate 1 formed in FIGS. 9A to 9D, and the mounting structure according to the present embodiment. Form.

後工程では、まず、図１０Ａに示すように、親基板５の上面に接続パッド９を形成し、接続パッド９上に半田ペーストなどの導電性接続材料６を印刷、あるいはディスペンス等で供給する。続いて、図１０Ｂに示すように、所定の接続パッド９上の導電性接続材料６の位置に、図９Ａ〜図９Ｄで形成した子基板１の下面電極４ｂを位置合わせして子基板１を搭載する。また、所定の接続パッド９上の導電性接続材料６の位置に、周辺部品７の接続電極７ａを位置合わせして周辺部品７を搭載する。   In the post-process, first, as shown in FIG. 10A, the connection pad 9 is formed on the upper surface of the parent substrate 5, and the conductive connection material 6 such as solder paste is supplied on the connection pad 9 by printing or dispensing. Subsequently, as shown in FIG. 10B, the lower substrate 4 b of the child substrate 1 formed in FIGS. 9A to 9D is aligned with the position of the conductive connection material 6 on the predetermined connection pad 9 so that the child substrate 1 is positioned. Mount. Further, the peripheral component 7 is mounted by aligning the connection electrode 7 a of the peripheral component 7 at the position of the conductive connection material 6 on the predetermined connection pad 9.

続いて、図１０Ｃに示すように、半導体装置２の下部電極３にフラックス、あるいは半田ペースト等の導電性接続材料１６を転写した後、子基板１のバイアホール８（上面電極４ａ）の位置に、導電性接続材料１６を位置合わせして、子基板１上に半導体装置２を搭載する。   Subsequently, as shown in FIG. 10C, after the conductive connection material 16 such as flux or solder paste is transferred to the lower electrode 3 of the semiconductor device 2, it is placed at the position of the via hole 8 (upper surface electrode 4a) of the child substrate 1. Then, the conductive connecting material 16 is aligned, and the semiconductor device 2 is mounted on the daughter board 1.

最後に、図１０Ｄに示すように、リフロー加熱を行い、半田ペーストなどの導電性接続材料６及び導電性接続材料１６を一括リフローすることで、親基板５の接続パッド９と子基板１の下面電極４ｂ、親基板５の接続パッド９と周辺部品７の接続電極７ａ、バイアホール８を介した子基板１の上面電極４ａと半導体装置２の下部電極３をそれぞれ接合し、実装構造１００が完成する。これにより、実施の形態１と同様に、半導体装置２の下部電極３の近傍（半導体装置２の直下）に周辺部品７を配置することが可能となる。   Finally, as shown in FIG. 10D, reflow heating is performed, and the conductive connection material 6 such as solder paste and the conductive connection material 16 are collectively reflowed, whereby the connection pads 9 of the parent substrate 5 and the lower surface of the child substrate 1 are obtained. The mounting structure 100 is completed by bonding the electrode 4b, the connection pad 9 of the parent substrate 5, the connection electrode 7a of the peripheral component 7, and the upper electrode 4a of the child substrate 1 via the via hole 8 and the lower electrode 3 of the semiconductor device 2, respectively. To do. As a result, similarly to the first embodiment, it is possible to arrange the peripheral component 7 in the vicinity of the lower electrode 3 of the semiconductor device 2 (directly below the semiconductor device 2).

以上のように、本実施の形態では、親基板に片面配線板の子基板を介して半導体装置を実装し、子基板により形成される領域に周辺部品を実装することとした。これにより、実施の形態１と同様に、周辺部品を半導体装置と近い距離に配置することができるため、電気特性を向上することができるとともに、周辺部品を含めた実装面積を削減することができる。   As described above, in this embodiment, the semiconductor device is mounted on the parent substrate via the child substrate of the single-sided wiring board, and the peripheral components are mounted on the region formed by the child substrate. Thus, as in the first embodiment, peripheral components can be arranged at a distance close to the semiconductor device, so that electrical characteristics can be improved and a mounting area including peripheral components can be reduced. .

また、本実施の形態では、子基板を片面配線板により構成するため、両面配線板を用いた実施の形態１に対して、材料価格を安価にすることができる。さらに、前述の式２のように、子基板１の厚さＬ２を小さくしたい場合、Ｌ２は１枚の導体厚のみとなるため、容易にＬ２を小さくすることが可能となる。   Further, in this embodiment, since the sub board is constituted by a single-sided wiring board, the material price can be reduced compared to the first embodiment using the double-sided wiring board. Further, when it is desired to reduce the thickness L2 of the daughter board 1 as in the above-described formula 2, L2 is only one conductor thickness, so that L2 can be easily reduced.

（実施の形態３）
以下、本発明の実施の形態３について図面を参照して説明する。実施の形態１では、子基板を介して半導体装置を実装したのに対し、本実施の形態では、子基板の代わりに半田付けタイプのスペーサを介して半導体装置を実装する。その他の構成については、実施の形態１と同様である。(Embodiment 3)
Embodiment 3 of the present invention will be described below with reference to the drawings. In the first embodiment, the semiconductor device is mounted via a child substrate, whereas in this embodiment, the semiconductor device is mounted via a soldering type spacer instead of the child substrate. Other configurations are the same as those in the first embodiment.

図１２は、本実施の形態に係る実装構造１００の構成を示す概略断面図であり、図１３は、図１２の実装構造１００の拡大断面図である。図１２に示すように、実装構造１００は、図２と同様に、半導体装置２、親基板５、周辺部品７を備えており、また、半田付けスペーサ１７を備えている。すなわち、本実施の形態の実装構造１００では、親基板５の上面（実装面）に周辺部品７を実装するとともに、半田付けスペーサ１７を介して半導体装置２を実装する。   12 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment, and FIG. 13 is an enlarged cross-sectional view of the mounting structure 100 of FIG. As illustrated in FIG. 12, the mounting structure 100 includes the semiconductor device 2, the parent substrate 5, peripheral components 7, and also includes a soldering spacer 17, as in FIG. 2. That is, in the mounting structure 100 of the present embodiment, the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5 and the semiconductor device 2 is mounted via the soldering spacer 17.

半田付けスペーサ１７は、子基板１と同様に、半導体装置２を親基板５に接続し実装するとともに、半導体装置２を所定の位置（高さ）に支持するための接続支持部材である。また、半田付けスペーサ１７は、半導体装置２を支持することで、周辺部品７を配置するための配置領域（空間）５ｂを形成する基板ともいえる。半田付けスペーサ１７は、導電性スペーサであり、半導体装置２の下部電極３ごとに別々に配置される。   The soldering spacer 17 is a connection support member for connecting and mounting the semiconductor device 2 to the parent substrate 5 and supporting the semiconductor device 2 at a predetermined position (height), similarly to the child substrate 1. In addition, the soldering spacer 17 can be said to be a substrate that supports the semiconductor device 2 and forms an arrangement region (space) 5 b for arranging the peripheral component 7. The soldering spacers 17 are conductive spacers and are arranged separately for each lower electrode 3 of the semiconductor device 2.

図１３に示すように、半田付けスペーサ１７は、上面が半導体装置２の下部電極３と半田接続されると共に、下面が親基板５の接続パッド（半田付けパッド）９と半田等の導電性接続材料６を介して接続されている。これにより、半導体装置２の下部電極３と親基板５の接続パッド９とを電気的に接続している。   As shown in FIG. 13, the soldering spacer 17 has an upper surface connected to the lower electrode 3 of the semiconductor device 2 by soldering, and a lower surface connected to a connection pad (soldering pad) 9 of the parent substrate 5 and a conductive connection such as solder. It is connected via material 6. Thus, the lower electrode 3 of the semiconductor device 2 and the connection pad 9 of the parent substrate 5 are electrically connected.

本実施の形態では、実施の形態１と同様に、半導体装置２と親基板５の間の配置領域５ａに半田付けスペーサ１７が配置され、半導体装置２と親基板５の間の配置領域５ｂに周辺部品７が実装される。このような配置とするため、各部材は図１３に示すような高さ（上下方向の長さ）の関係となる。すなわち、本実施の形態における半田付けスペーサ１７の厚み（上下端間距離）は、半導体装置２と周辺部品７とが高さ方向で接触しないよう、次の式３を満たす厚みで予め設計される。
［子基板１のスタンドオフＬ１］＋［半田付けスペーサ１７の厚さＬ２］＋［半導体装置のスタンドオフＬ３］≧［周辺部品７の半田高さＬ４］＋［周辺部品７の高さＬ５］・・・（式３）In the present embodiment, as in the first embodiment, the soldering spacers 17 are arranged in the arrangement region 5 a between the semiconductor device 2 and the parent substrate 5, and the arrangement region 5 b between the semiconductor device 2 and the parent substrate 5 is arranged. A peripheral component 7 is mounted. In order to achieve such an arrangement, the members have a height (vertical length) relationship as shown in FIG. That is, the thickness (distance between the upper and lower ends) of the soldering spacer 17 in the present embodiment is designed in advance so as to satisfy the following expression 3 so that the semiconductor device 2 and the peripheral component 7 do not contact in the height direction. .
[Standoff L1 of Substrate 1] + [Thickness L2 of Soldering Spacer 17] + [Standoff L3 of Semiconductor Device] ≧ [Solder Height L4 of Peripheral Component 7] + [Height L5 of Peripheral Component 7] ... (Formula 3)

式３を満たすように半田付けスペーサ１７の厚さを設計することで、図１３のように、実施の形態１と同様、周辺部品７を半導体装置２の直下に配置することが可能となる。   By designing the thickness of the soldering spacer 17 so as to satisfy Expression 3, the peripheral component 7 can be arranged directly below the semiconductor device 2 as in the first embodiment, as shown in FIG.

次に、図１４Ａ〜図１４Ｄを参照して、本実施の形態に係る実装構造１００の製造方法を説明する。まず、図１４Ａに示すように、親基板５の上面に接続パッド９を形成し、接続パッド９上に半田ペーストなどの導電性接続材料６を印刷、あるいはディスペンス等で供給する。   Next, a method for manufacturing the mounting structure 100 according to the present embodiment will be described with reference to FIGS. 14A to 14D. First, as shown in FIG. 14A, a connection pad 9 is formed on the upper surface of the parent substrate 5, and a conductive connection material 6 such as a solder paste is supplied onto the connection pad 9 by printing or dispensing.

続いて、図１４Ｂに示すように、銅やＳＵＳ等の金属材料の両面に半田接続が可能な表面処理を施し、それを半田付けスペーサ１７として、親基板５の所定の接続パッド９上の導電性接続材料６に搭載する。また、所定の接続パッド９上の導電性接続材料６の位置に、周辺部品７の接続電極７ａを位置合わせして周辺部品７を搭載する。   Subsequently, as shown in FIG. 14B, a surface treatment capable of soldering is performed on both surfaces of a metal material such as copper or SUS, and this is used as a soldering spacer 17 to conduct on a predetermined connection pad 9 of the parent substrate 5. It is mounted on the conductive connecting material 6. Further, the peripheral component 7 is mounted by aligning the connection electrode 7 a of the peripheral component 7 at the position of the conductive connection material 6 on the predetermined connection pad 9.

続いて、図１４Ｃに示すように、半導体装置２の下部電極３にフラックス、あるいは半田ペースト等の導電性接続材料１６を転写した後、半田付けスペーサ１７の位置に、導電性接続材料１６を位置合わせして、半田付けスペーサ１７上に半導体装置２を搭載する。   Subsequently, as shown in FIG. 14C, after the conductive connection material 16 such as flux or solder paste is transferred to the lower electrode 3 of the semiconductor device 2, the conductive connection material 16 is positioned at the position of the soldering spacer 17. In addition, the semiconductor device 2 is mounted on the soldering spacer 17.

最後に、図１４Ｄに示すように、リフロー加熱を行い、半田ペーストなどの導電性接続材料６及び導電性接続材料１６を一括リフローすることで、親基板５の接続パッド９と半田付けスペーサ１７の下面、親基板５の接続パッド９と周辺部品７の接続電極７ａ、半田付けスペーサ１７の上面と半導体装置２の下部電極３をそれぞれ接合し、実装構造１００が完成する。これにより、実施の形態１と同様に、半導体装置２の下部電極３の近傍（半導体装置２の直下）に周辺部品７を配置することが可能となる。   Finally, as shown in FIG. 14D, reflow heating is performed, and the conductive connection material 6 and the conductive connection material 16 such as solder paste are collectively reflowed, so that the connection pads 9 of the parent substrate 5 and the soldering spacers 17 The mounting structure 100 is completed by bonding the lower surface, the connection pad 9 of the parent substrate 5 and the connection electrode 7a of the peripheral component 7, the upper surface of the soldering spacer 17 and the lower electrode 3 of the semiconductor device 2, respectively. As a result, similarly to the first embodiment, it is possible to arrange the peripheral component 7 in the vicinity of the lower electrode 3 of the semiconductor device 2 (directly below the semiconductor device 2).

以上のように、本実施の形態では、親基板に半田付けスペーサを介して半導体装置を実装し、半田付けスペーサにより形成される領域に周辺部品を実装することとした。これにより、実施の形態１と同様に、周辺部品を半導体装置と近い距離に配置することができるため、電気特性を向上することができるとともに、周辺部品を含めた実装面積を削減することができる。   As described above, in this embodiment, the semiconductor device is mounted on the parent substrate through the soldering spacer, and the peripheral components are mounted in the region formed by the soldering spacer. Thus, as in the first embodiment, peripheral components can be arranged at a distance close to the semiconductor device, so that electrical characteristics can be improved and a mounting area including peripheral components can be reduced. .

また、本実施の形態では、半田付けスペーサの材料の厚みを変更することで、前述の式３のＬ２の値を容易に変更することが可能となる。また、半導体装置２の下部電極３の数が少ない場合、実施の形態１及び２よりも材料コストが安価となる。   Further, in the present embodiment, it is possible to easily change the value of L2 in Expression 3 described above by changing the thickness of the material of the soldering spacer. Further, when the number of the lower electrodes 3 of the semiconductor device 2 is small, the material cost is lower than in the first and second embodiments.

（実施の形態４）
以下、本発明の実施の形態４について図面を参照して説明する。本実施の形態では、実施の形態１における子基板をチップ部品内蔵基板により構成する。その他の構成については、実施の形態１と同様である。(Embodiment 4)
Embodiment 4 of the present invention will be described below with reference to the drawings. In the present embodiment, the sub board in the first embodiment is configured by a chip component built-in board. Other configurations are the same as those in the first embodiment.

図１５は、本実施の形態に係る実装構造１００の構成を示す概略断面図である。図１５に示すように、実装構造１００は、図２と同様に、半導体装置２、親基板５、周辺部品７を備えており、また、チップ部品内蔵基板１８を備えている。すなわち、本実施の形態の実装構造１００では、親基板５の上面（実装面）に周辺部品７を実装するとともに、チップ部品内蔵基板１８を介して半導体装置２を実装する。   FIG. 15 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment. As shown in FIG. 15, the mounting structure 100 includes the semiconductor device 2, the parent substrate 5, and peripheral components 7, and also includes a chip component built-in substrate 18, as in FIG. 2. That is, in the mounting structure 100 of the present embodiment, the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5 and the semiconductor device 2 is mounted via the chip component built-in substrate 18.

チップ部品内蔵基板１８は、子基板１と同様に、半導体装置２を親基板５に接続し実装するとともに、半導体装置２を所定の位置（高さ）に支持するための接続支持基板である。また、チップ部品内蔵基板１８は、半導体装置２を支持することで、周辺部品７を配置するための配置領域（空間）５ｂを形成する基板ともいえる。さらに、チップ部品内蔵基板１８は、予め内部にチップ部品１８ａが形成されている。チップ部品１８ａは、回路素子であり、例えば、周辺部品７と同様にバイパスコンデンサ等である。   The chip component built-in substrate 18 is a connection support substrate for connecting and mounting the semiconductor device 2 to the parent substrate 5 and supporting the semiconductor device 2 at a predetermined position (height), similarly to the child substrate 1. The chip component built-in substrate 18 can also be said to be a substrate that forms the arrangement region (space) 5b for arranging the peripheral component 7 by supporting the semiconductor device 2. Further, the chip component built-in substrate 18 has a chip component 18a formed therein in advance. The chip component 18a is a circuit element, and is, for example, a bypass capacitor or the like, similar to the peripheral component 7.

チップ部品内蔵基板１８は、両面プリント配線板であり、上面（表面）に複数の上面電極４ａを有し、下面（裏面）に複数の下面電極４ｂを有している。複数の上面電極４ａは、半導体装置２の下部電極３と対応する位置に配列形成され、複数の下面電極４ｂは、上面電極４ａの下面（裏面）直下に形成されている。   The chip component built-in substrate 18 is a double-sided printed wiring board, and has a plurality of upper surface electrodes 4a on the upper surface (front surface) and a plurality of lower surface electrodes 4b on the lower surface (back surface). The plurality of upper surface electrodes 4a are arranged and formed at positions corresponding to the lower electrode 3 of the semiconductor device 2, and the plurality of lower surface electrodes 4b are formed immediately below the lower surface (back surface) of the upper surface electrode 4a.

上面電極４ａ及び下面電極４ｂからチップ部品１８ａまでインタスティシャルバイアホール（Interstitial Via Hole）８が形成されている。バイアホール８は銅めっきなどが埋め込まれており、上面電極４ａ及び下面電極４ｂとチップ部品１８ａとが接続されている。なお、チップ部品１８ａは、バイアホール８を介して上面電極４ａ及び下面電極４ｂの両方と接続することもできるし、上面電極４ａと下面電極４ｂのいずれか一方とのみ接続することもできる。   An interstitial via hole 8 is formed from the upper surface electrode 4a and the lower surface electrode 4b to the chip component 18a. The via hole 8 is embedded with copper plating or the like, and the upper surface electrode 4a and the lower surface electrode 4b are connected to the chip component 18a. The chip component 18a can be connected to both the upper surface electrode 4a and the lower surface electrode 4b through the via hole 8, or can be connected to only one of the upper surface electrode 4a and the lower surface electrode 4b.

上面電極４ａは、半導体装置２の下部電極３と半田接続され、下面電極４ｂは、親基板５の接続パッド（半田付けパッド）９と半田等の導電性接続材料６を介して接続されている。これにより、半導体装置２の下部電極３とチップ部品１８ａとが電気的に接続され、親基板５の接続パッド９とチップ部品１８ａとが電気的に接続される。そして、上面電極４ａ及び下面電極４ｂの両方に接続されるチップ部品１８ａを介して、半導体装置２の下部電極３と親基板５の接続パッド９とが電気的に接続される。   The upper surface electrode 4a is connected to the lower electrode 3 of the semiconductor device 2 by soldering, and the lower surface electrode 4b is connected to a connection pad (soldering pad) 9 of the parent substrate 5 via a conductive connection material 6 such as solder. . As a result, the lower electrode 3 of the semiconductor device 2 and the chip component 18a are electrically connected, and the connection pad 9 of the parent substrate 5 and the chip component 18a are electrically connected. Then, the lower electrode 3 of the semiconductor device 2 and the connection pad 9 of the parent substrate 5 are electrically connected via the chip component 18a connected to both the upper surface electrode 4a and the lower surface electrode 4b.

また、図１５では、チップ部品内蔵基板１８に周辺部品７と同様のチップ部品を内蔵している。このため、周辺部品７の下の接続パッド９と半導体装置２の下の接続パッド９とは接続されておらず、周辺部品７と半導体装置２とは電気的に接続されていない。すなわち、図１５のように、半導体装置２と接続されない周辺部品７を、半導体装置２の下方に実装してもよい。   In FIG. 15, chip components similar to the peripheral components 7 are built in the chip component built-in substrate 18. For this reason, the connection pad 9 under the peripheral component 7 and the connection pad 9 under the semiconductor device 2 are not connected, and the peripheral component 7 and the semiconductor device 2 are not electrically connected. That is, as shown in FIG. 15, peripheral components 7 that are not connected to the semiconductor device 2 may be mounted below the semiconductor device 2.

以上のように、本実施の形態では、親基板にチップ部品内蔵基板を介して半導体装置を実装し、チップ部品内蔵基板により形成される領域に周辺部品を実装することとした。これにより、実施の形態１と同様に、周辺部品を半導体装置と近い距離に配置することができるため、電気特性を向上することができるとともに、周辺部品を含めた実装面積を削減することができる。   As described above, in this embodiment, the semiconductor device is mounted on the parent substrate via the chip component built-in substrate, and the peripheral components are mounted on the region formed by the chip component built-in substrate. Thus, as in the first embodiment, peripheral components can be arranged at a distance close to the semiconductor device, so that electrical characteristics can be improved and a mounting area including peripheral components can be reduced. .

特に、半導体装置と親基板とを接続する基板に周辺部品を内蔵しているため、周辺部品と半導体装置２の下部電極３との距離が更に短くなり、電気特性を向上することができる。また、子基板１に部品を内蔵した分、子基板１の周囲にはスペースが創出されるため、より多くの部品を半導体装置２の直下に配置し、高密度実装が可能となる。   In particular, since the peripheral component is built in the substrate connecting the semiconductor device and the parent substrate, the distance between the peripheral component and the lower electrode 3 of the semiconductor device 2 is further shortened, and the electrical characteristics can be improved. Further, since a space is created around the child substrate 1 because the components are built in the child substrate 1, more components can be arranged directly below the semiconductor device 2 and high-density mounting becomes possible.

なお、本発明は上記実施の形態に限られたものではなく、趣旨を逸脱しない範囲で適宜変更することが可能である。   Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

例えば、子基板１を使用する構成において（実施の形態１、２や４）、子基板１を形成する際にソルダーレジストを形成してもよい。図４Ａ〜図４Ｅや図９Ａ〜図９Ｄなどで、上面電極４ａ及び下面電極４ｂを形成した後、上面電極４ａの間の領域及び下面電極４ｂの間の領域にソルダーレジストを形成してもよい。例えば、ソルダーレジストは、上面電極４ａ及び下面電極４ｂに合わせて基板の表裏対称となるように形成する。また、半田漏れが防止できれば、ソルダーレジストは、基板の表裏対称となるように形成しなくても良い。   For example, in a configuration using the sub-substrate 1 (Embodiments 1, 2, and 4), a solder resist may be formed when the sub-substrate 1 is formed. 4A to 4E, 9A to 9D, and the like, after forming the upper surface electrode 4a and the lower surface electrode 4b, a solder resist may be formed in a region between the upper surface electrode 4a and a region between the lower surface electrode 4b. . For example, the solder resist is formed so as to be symmetric with respect to the front and back of the substrate in accordance with the upper surface electrode 4a and the lower surface electrode 4b. Further, if solder leakage can be prevented, the solder resist may not be formed so as to be symmetrical with respect to the front and back of the substrate.

また、子基板１を使用する構成において（実施の形態１、２や４）、子基板１を親基板５に実装する前に、子基板１に半田バンプを形成してもよい。図５Ａ〜図５Ｄや図１０Ａ〜図１０Ｄなどで、予め子基板１の下面電極４ｂに半田バンプを形成しておき、半田バンプが形成された子基板１を親基板５の接続パッド９上に搭載し、下面電極４ｂと接続パッド９を接続してもよい。なお、同様に、周辺部品７に予め半田バンプを形成しておき、親基板５に搭載してもよい。   In the configuration using the sub board 1 (Embodiments 1, 2 and 4), solder bumps may be formed on the sub board 1 before mounting the sub board 1 on the main board 5. In FIG. 5A to FIG. 5D, FIG. 10A to FIG. 10D, etc., solder bumps are formed in advance on the lower electrode 4b of the sub board 1, and the sub board 1 on which the solder bumps are formed is placed on the connection pads 9 of the main board 5. It may be mounted and the lower surface electrode 4b and the connection pad 9 may be connected. Similarly, solder bumps may be formed in advance on the peripheral component 7 and mounted on the parent substrate 5.

また、子基板１を使用する構成において（実施の形態１、２や４）、子基板１を親基板５に実装する前に、子基板１に半導体装置２を搭載してもよい。図５Ａ〜図５Ｄや図１０Ａ〜図１０Ｄなどで、予め子基板１上に半導体装置２を接続（プリスタック）しておき、子基板１及び半導体装置２を１つの部品（モジュール）として親基板５に搭載しても良い。この場合、図４Ｅや図９Ｄのような切断後（分割）の子基板１に半導体装置２を実装しても良いし、切断前の子基板１に半導体装置２を複数個実装した後、下面電極４ｂの面より切断装置（分割装置）の刃を入れて切断（分割）しても良い。   In the configuration using the sub board 1 (Embodiments 1, 2 and 4), the semiconductor device 2 may be mounted on the sub board 1 before mounting the sub board 1 on the main board 5. In FIGS. 5A to 5D and FIGS. 10A to 10D, the semiconductor device 2 is connected (prestacked) on the child substrate 1 in advance, and the child substrate 1 and the semiconductor device 2 are used as a single component (module). 5 may be mounted. In this case, the semiconductor device 2 may be mounted on the sub-board 1 after being cut (divided) as shown in FIG. 4E or FIG. 9D, or a plurality of semiconductor devices 2 may be mounted on the sub-board 1 before cutting. A blade of a cutting device (dividing device) may be inserted and cut (divided) from the surface of the electrode 4b.

また、上記の実施の形態（実施の形態１、２や３）では、主に、周辺部品７を半導体装置２に接続する構成としていたが、周辺部品７は、必ずしも半導体装置２と電気的に接続されなくても良い。この場合、半導体装置２の特性に影響はないが、少なくとも、高密度実装を実現するという効果を得ることができる。   In the above embodiments (Embodiments 1, 2 and 3), the peripheral component 7 is mainly connected to the semiconductor device 2. However, the peripheral component 7 is not necessarily electrically connected to the semiconductor device 2. It does not have to be connected. In this case, the characteristics of the semiconductor device 2 are not affected, but at least the effect of realizing high-density mounting can be obtained.

以上、実施の形態を参照して本願発明を説明したが、本願発明は上記によって限定されるものではない。本願発明の構成や詳細には、発明のスコープ内で当業者が理解し得る様々な変更をすることができる。   Although the present invention has been described with reference to the exemplary embodiments, the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.

この出願は、２０１２年４月１２日に出願された日本出願特願２０１２−０９０８１２を基礎とする優先権を主張し、その開示の全てをここに取り込む。   This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2012-090812 for which it applied on April 12, 2012, and takes in those the indications of all here.

１ 子基板
２ 半導体装置
３ 下部電極
３ａ 半田ボールバンプ
４ａ 上面電極
４ｂ 下面電極
５ 親基板
５ａ 配置領域
５ｂ 配置領域
６ 導電性接続材料
７ 周辺部品
７ａ 接続電極
８ バイアホール
９、９ａ 接続パッド
１１ 積層板（両面銅張積層板、片面銅張積層板）
１２ 上面導体
１３ 下面導体
１５ 銅めっき膜
１５ａ 導電層
１６ 導電性接続材料
１７ 半田付けスペーサ
１８ チップ部品内蔵基板
１８ａ チップ部品
１９ 導電性ペースト
１００ 実装構造（電子機器）
１０１ 接続支持部
１０２ 第１の電子部品
１０３ 基板
１０３ａ 実装面
１０４ 第２の電子部品
１０５ａ 配置領域
１０５ｂ 配置領域DESCRIPTION OF SYMBOLS 1 Sub-substrate 2 Semiconductor device 3 Lower electrode 3a Solder ball bump 4a Upper surface electrode 4b Lower surface electrode 5 Parent substrate 5a Arrangement area 5b Arrangement area 6 Conductive connection material 7 Peripheral component 7a Connection electrode 8 Via hole 9, 9a Connection pad 11 Laminate board (Double-sided copper-clad laminate, single-sided copper-clad laminate)
12 Upper surface conductor 13 Lower surface conductor 15 Copper plating film 15a Conductive layer 16 Conductive connection material 17 Soldering spacer 18 Chip component built-in substrate 18a Chip component 19 Conductive paste 100 Mounting structure (electronic device)
101 Connection Support Unit 102 First Electronic Component 103 Substrate 103a Mounting Surface 104 Second Electronic Component 105a Arrangement Area 105b Arrangement Area

Claims (20)

基板と、
前記基板上に実装される第１の電子部品と、
前記基板と前記第１の電子部品との間で、前記基板と前記第１の電子部品とを電気的に接続するとともに、前記基板上に前記第１の電子部品を支持する接続支持部と、
前記基板と前記第１の電子部品との間で、前記基板上に実装される第２の電子部品と、
を備える電子機器。A substrate,
A first electronic component mounted on the substrate;
A connection support unit that electrically connects the substrate and the first electronic component between the substrate and the first electronic component, and supports the first electronic component on the substrate;
A second electronic component mounted on the substrate between the substrate and the first electronic component;
Electronic equipment comprising. 前記第２の電子部品は、前記接続支持部を介して前記第１の電子部品と電気的に接続される、
請求項１に記載の電子機器。The second electronic component is electrically connected to the first electronic component via the connection support portion.
The electronic device according to claim 1. 前記基板と前記第１の電子部品の間隔は、前記基板から前記第２の電子部品の上端までの長さよりも長い、
請求項１または２に記載の電子機器。The distance between the substrate and the first electronic component is longer than the length from the substrate to the upper end of the second electronic component.
The electronic device according to claim 1. 前記接続支持部は、前記第１の電子部品の中央部と前記基板との間に配置され、
前記第２の電子部品は、前記第１の電子部品の周辺部と前記基板との間に配置される、
請求項１乃至３のいずれか一項に記載の電子機器。The connection support portion is disposed between a center portion of the first electronic component and the substrate,
The second electronic component is disposed between a peripheral portion of the first electronic component and the substrate;
The electronic device as described in any one of Claims 1 thru | or 3. 前記接続支持部は、両面配線基板から構成され、
前記両面配線基板は、
上面に形成され前記第１の電子部品と電気的に接続される上面電極と、
下面に形成され前記基板と電気的に接続される下面電極と、を備える、
請求項１乃至４のいずれか一項に記載の電子機器。The connection support part is composed of a double-sided wiring board,
The double-sided wiring board is
An upper surface electrode formed on an upper surface and electrically connected to the first electronic component;
A lower surface electrode formed on the lower surface and electrically connected to the substrate,
The electronic device as described in any one of Claims 1 thru | or 4. 前記第１の電子部品から前記上面電極までの接続部の長さと、前記上面電極の厚さと、前記両面配線基板の厚さと、前記下面電極の厚さと、前記基板から前記下面電極までの接続部の長さとの合計が、前記基板から前記第２の電子部品までの接続部の長さと、前記第２の電子部品の厚さとの合計よりも長い、
請求項５に記載の電子機器。The length of the connecting portion from the first electronic component to the upper surface electrode, the thickness of the upper surface electrode, the thickness of the double-sided wiring board, the thickness of the lower surface electrode, and the connecting portion from the substrate to the lower surface electrode Is longer than the sum of the length of the connecting portion from the substrate to the second electronic component and the thickness of the second electronic component,
The electronic device according to claim 5. 前記両面配線基板は、前記上面電極の上面から前記下面電極の上面まで達するバイアホールが形成され、
前記バイアホールを埋めるように形成された導電体により、前記上面電極と前記下面電極が接続されている、
請求項５または６に記載の電子機器。In the double-sided wiring board, a via hole reaching from the upper surface of the upper surface electrode to the upper surface of the lower surface electrode is formed,
The upper surface electrode and the lower surface electrode are connected by a conductor formed so as to fill the via hole.
The electronic device according to claim 5 or 6. 前記両面配線基板は、前記上面電極の上面から前記下面電極の上面まで達するバイアホールが形成され、
前記バイアホールの内壁に形成された導電膜により、前記上面電極と前記下面電極が接続されている、
請求項５または６に記載の電子機器。In the double-sided wiring board, a via hole reaching from the upper surface of the upper surface electrode to the upper surface of the lower surface electrode is formed,
The upper electrode and the lower electrode are connected by a conductive film formed on the inner wall of the via hole,
The electronic device according to claim 5 or 6. 前記両面配線基板は、内部に回路素子を有し、
前記回路素子は、前記上面電極または前記下面電極に電気的に接続されている、
請求項５乃至８のいずれか一項に記載の電子機器。The double-sided wiring board has a circuit element inside,
The circuit element is electrically connected to the upper surface electrode or the lower surface electrode,
The electronic device as described in any one of Claims 5 thru | or 8. 前記接続支持部は、下面に下面配線が形成された片面配線基板から構成され、
前記下面配線の上面が前記第１の電子部品と電気的に接続され、前記下面配線の下面が前記基板と電気的に接続される、
請求項１乃至４のいずれか一項に記載の電子機器。The connection support portion is composed of a single-sided wiring board having a lower surface wiring formed on the lower surface,
An upper surface of the lower surface wiring is electrically connected to the first electronic component, and a lower surface of the lower surface wiring is electrically connected to the substrate;
The electronic device as described in any one of Claims 1 thru | or 4. 前記第１の電子部品から前記片面配線基板までの接続部の長さと、前記片面配線基板の厚さと、前記下面配線の厚さと、前記基板から前記下面配線までの接続部の長さとの合計が、前記基板から前記第２の電子部品までの接続部の長さと、前記第２の電子部品の厚さとの合計よりも長い、
請求項１０に記載の電子機器。The sum of the length of the connection part from the first electronic component to the single-sided wiring board, the thickness of the single-sided wiring board, the thickness of the lower surface wiring, and the length of the connection part from the substrate to the lower surface wiring is , Longer than the sum of the length of the connecting portion from the substrate to the second electronic component and the thickness of the second electronic component,
The electronic device according to claim 10. 前記片面配線基板は、前記片面配線基板の上面から前記下面配線の上面まで達するバイアホールが形成され、
前記バイアホールを介して、前記第１の電子部品と前記下面配線の上面が接続されている、
請求項１０または１１に記載の電子機器。The single-sided wiring board is formed with via holes reaching from the upper surface of the single-sided wiring board to the upper surface of the lower surface wiring,
The first electronic component and the upper surface of the lower surface wiring are connected via the via hole,
The electronic device according to claim 10 or 11. 前記バイアホール底部の前記下面配線上に導電体が形成されている、
請求項１２に記載の電子機器。A conductor is formed on the lower surface wiring at the bottom of the via hole.
The electronic device according to claim 12. 前記接続支持部は、前記第１の電子部品と前記基板との間に接続される導電性スペーサから構成されている、
請求項１乃至４のいずれか一項に記載の電子機器。The connection support portion is composed of a conductive spacer connected between the first electronic component and the substrate.
The electronic device as described in any one of Claims 1 thru | or 4. 前記第１の電子部品から前記導電性スペーサの上面までの接続部の長さと、前記導電性スペーサの厚さと、前記基板から前記導電性スペーサの下面までの接続部の長さとの合計が、前記基板から前記第２の電子部品までの接続部の長さと、前記第２の電子部品の厚さとの合計よりも長い、
請求項１４に記載の電子機器。The sum of the length of the connection portion from the first electronic component to the upper surface of the conductive spacer, the thickness of the conductive spacer, and the length of the connection portion from the substrate to the lower surface of the conductive spacer is Longer than the sum of the length of the connecting portion from the substrate to the second electronic component and the thickness of the second electronic component;
The electronic device according to claim 14. 基板に第１の電子部品を実装する電子機器の製造方法であって、
前記基板上の第１の領域に、前記基板と前記第１の電子部品とを電気的に接続するとともに、前記基板上に前記第１の電子部品を支持するための接続支持部を、導電性接続材料を介して配置し、
前記基板上の第２の領域に、導電性接続材料を介して第２の電子部品を配置し、
前記接続支持部及び前記第２の電子部品の上方を含む領域で、前記接続支持部上に導電性接続材料を介して前記第１の電子部品を配置する、
電子機器の製造方法。A method of manufacturing an electronic device in which a first electronic component is mounted on a substrate,
An electrical connection between the substrate and the first electronic component is electrically connected to the first region on the substrate, and a connection support portion for supporting the first electronic component on the substrate is electrically conductive. Placed through the connecting material,
Placing a second electronic component in a second region on the substrate via a conductive connection material;
The first electronic component is disposed on the connection support portion via a conductive connection material in a region including the connection support portion and the second electronic component.
Manufacturing method of electronic equipment. 前記第２の電子部品は、前記接続支持部と電気的に接続される配線上に配置される、
請求項１６に記載の電子機器の製造方法。The second electronic component is disposed on a wiring electrically connected to the connection support portion.
The manufacturing method of the electronic device of Claim 16. 前記第１の電子部品を配置した後、一括リフローを行い、前記基板と前記接続支持部、前記基板と前記第２の電子部品、及び、前記接続支持部と前記第１の電子部品をそれぞれ接合する、
請求項１６または１７に記載の電子機器の製造方法。After arranging the first electronic component, batch reflow is performed to join the substrate and the connection support part, the substrate and the second electronic component, and the connection support part and the first electronic component, respectively. To
The manufacturing method of the electronic device of Claim 16 or 17. 前記接続支持部の配置前に前記接続支持部を形成し、
前記接続支持部の形成は、
両面配線基板の上面に上面電極を形成し、
前記両面配線基板の下面に下面電極を形成し、
前記上面電極の上面から前記下面電極の上面まで達するバイアホールを形成し、
前記バイアホールの内部に前記上面電極と前記下面電極を接続する導電部を形成し、
前記両面配線基板を、前記上面電極及び前記下面電極近傍で切断する、
請求項１６乃至１８のいずれか一項に記載の電子機器の製造方法。Forming the connection support part before the arrangement of the connection support part,
The connection support portion is formed by:
An upper surface electrode is formed on the upper surface of the double-sided wiring board,
Forming a bottom electrode on the bottom surface of the double-sided wiring board;
Forming a via hole extending from the upper surface of the upper electrode to the upper surface of the lower electrode;
Forming a conductive portion connecting the upper surface electrode and the lower surface electrode inside the via hole;
Cutting the double-sided wiring board in the vicinity of the upper surface electrode and the lower surface electrode;
The manufacturing method of the electronic device as described in any one of Claims 16 thru | or 18. 前記接続支持部の配置前に前記接続支持部を形成し、
前記接続支持部の形成は、
片面配線基板の下面に下面配線を形成し、
前記片面配線基板の上面から前記下面配線の上面まで達するバイアホールを形成し、
前記片面配線基板を、前記下面配線近傍で切断する、
請求項１６乃至１８のいずれか一項に記載の電子機器の製造方法。Forming the connection support part before the arrangement of the connection support part,
The connection support portion is formed by:
Form the lower surface wiring on the lower surface of the single-sided wiring board,
Forming a via hole extending from the upper surface of the single-sided wiring board to the upper surface of the lower surface wiring;
Cutting the single-sided wiring board in the vicinity of the lower surface wiring;
The manufacturing method of the electronic device as described in any one of Claims 16 thru | or 18.
JP2014510026A 2012-04-12 2013-01-24 Electronic device and manufacturing method thereof Pending JPWO2013153717A1 (en)

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