TWI503982B - N-type metal oxide semiconductor (mos) device and manufacturing method thereof - Google Patents

Description

N-type metal oxide semiconductor device and method of manufacturing same

The present invention relates to an N-type metal oxide semiconductor (MOS) device and a method of fabricating the same; and more particularly to an increase in the width of a portion of a P-type well region to increase a breakdown voltage of an N-type MOS device.

1A and 1B are schematic cross-sectional and top views, respectively, of a conventional N-type metal oxide semiconductor (MOS) device 100. As shown in FIGS. 1A and 1B, the N-type MOS device 100 includes a substrate 11, a P-type well region 12, an isolation region 13, a body electrode 14, a gate 15, an N-type source 16, and an N-type drain 17. Among them, the isolation region 13 defines the operation region 13a as a main action region when the N-type MOS device 100 operates. The conductivity type of the P-type well region 12 and the body pole 14 is P-type, and the conductivity type of the N-type source electrode 16 and the N-type drain electrode 17 is N-type. Referring to FIG. 1A, when the N-type MOS device 100 is operated, it is necessary to avoid the collapse caused by the parasitic transistor conduction. In detail, a parasitic bipolar junction transistor (BJT), as illustrated by the dashed line in the figure, has a base B, an emitter E, and a collector C. The base B, the emitter E, and the collector C of the parasitic BJT correspond to the P-type well region 12, the N-type source electrode 16, and the N-type drain electrode 17 of the N-type MOS device 100, respectively. When the base-emitter voltage Vbe is higher than the barrier of the parasitic BJT, the parasitic BJT will conduct. The base-emitter voltage Vbe is related to the base resistance Rb (not shown, which refers to the resistance value between the base B and the emitter E, which is well known to those skilled in the art and will not be described here), that is, It is said that the larger the base resistance Rb is, the larger the base-emitter voltage Vbe is when the N-type MOS device 100 is operated, and the more likely the collapse occurs.

When the operating region width of the N-type MOS device is reduced in size to less than 5 μm, the parasitic BJT is easier to conduct, especially in the case of an increase in temperature. Therefore, the component designer will encounter a problem that the base resistance Rb of the parasitic BJT is increased and the conduction resistance is easily turned on when the width of the operation area of the component is reduced due to the miniaturization of the component, thereby causing the breakdown protection voltage to be The parasitic BJT is turned on and lowered because the gate voltage when the parasitic BJT is turned on is lower than the threshold voltage at which the avalanche breakdown occurs. Therefore, it is impossible to increase the collapse protection voltage by reducing the impurity concentration of the P-type well region.

Similarly, Figures 3A-3B show a schematic cross-sectional view and a top view, respectively, of a conventional N-type lateral double diffused metal oxide semiconductor (LDMOS) device 300. As shown in FIGS. 3A and 3B, the N-type LDMOS device 300 includes a substrate 31, a P-type well region 32, an isolation region 33, a body electrode 34, a gate 35, an N-type source 36, an N-type drain 37, and N. Type well area 38. The isolation region 33 defines an operation region 33a as a main active region when the N-type LDMOS device 300 operates. The conductivity type of the P-type well region 32 and the body pole 34 is P-type, and the conductivity type of the N-type source electrode 36, the N-type drain electrode 37, and the N-type well region 38 is N-type. Referring to FIG. 3A, when the N-type LDMOS device 300 is operated, it is necessary to avoid the collapse caused by the parasitic BJT conduction. In detail, a parasitic bipolar junction transistor, as illustrated by the dashed line in the figure, has a base B, an emitter E, and a collector C. The base B, the emitter E, and the collector C of the parasitic BJT correspond to the P-type well region 32, the N-type source 36, and the N-type well region 38 of the N-type LDMOS device 300, respectively. Similar to the N-type MOS device 100, when the operating region width of the N-type LDMOS device is reduced in size to less than 5 μm, the drain voltage of the parasitic BJT is lower than that of the cumulative collapse, and the breakdown protection voltage is lowered. . Therefore, it is impossible to increase the collapse protection voltage by reducing the impurity concentration of the P-type well region.

In view of the above, the present invention is directed to an improvement of the prior art described above, and provides an N-type MOS device and a method of fabricating the same, which can prevent parasitic BJT conduction and improve the breakdown protection voltage of the component.

In one aspect, the present invention provides an N-type metal oxide semiconductor (MOS) device formed in a substrate having an upper surface, the N-type MOS device comprising: an isolation region, Formed on the upper surface to define an operating region; a P-type well region formed under the upper surface; an N-type source formed under the upper surface; an N-type drain formed on the upper surface a gate formed on the upper surface, the gate being interposed between the N-type source and the N-type drain; and a body pole formed on the same side of the gate as the N-type source And the N-type source is between the body pole and the gate, and the body pole is used as An electrical contact of the P-type well region; wherein the P-type well region has a first portion and a second portion connected to each other, the first portion and the source are located on the same side of the gate, and the first portion Between the second portion and the second portion, the first junction is between the gate and the body, as viewed from a top view, the first portion is at the first junction In one of the width directions, both ends are at least 2 microns beyond the second portion.

In another aspect, the present invention provides a method of fabricating an N-type metal oxide semiconductor (MOS) device, comprising: providing a substrate having an upper surface; forming an isolation region on the upper surface Upper to define an operating region; forming a P-type well region below the upper surface; forming a gate on the upper surface; forming an N-type source under the upper surface; forming an N-type drain a lower surface, wherein the gate is interposed between the N-type source and the N-type drain; and a body pole is formed, the body pole and the N-type source are located on the same side of the gate, and the N a source is interposed between the body pole and the gate, the body pole is used as an electrical contact of the P-type well region; wherein the P-type well region has one of the first portion and the second portion connected to each other The first portion and the source are located on the same side of the gate, and the first portion and the second portion have a first junction, the first junction being between the gate and the body Between the two views, the first portion is in the width direction of the first junction, and both ends are super The second portion is at least 2 microns.

In a preferred embodiment, the operating area has a third portion and a fourth portion connected to each other, the third portion and the source are located on the same side of the gate, and the third portion is There is a second junction between the fourth portion, the second junction is between the gate and the body pole, as viewed from a top view, the third portion is at the second junction In the width direction, both ends are at least 2 microns beyond the fourth portion.

In one preferred embodiment, the operating zone has a first active width and the first active width does not exceed 5 microns.

In the foregoing embodiments, the fourth portion has a second active width and the second applied width does not exceed 5 microns.

In a preferred embodiment, the body extends beyond the operating region in the width direction.

100,200,500‧‧‧N type MOS components

11,21,31,41,51‧‧‧substrate

12,22,32,42‧‧‧P type well area

13,23,33,43,53‧‧ ‧Isolation area

13a, 23a, 33a, 43a, 53a‧‧‧ operation area

14,24,34,44,54‧‧‧ body

15,25,35,45,55‧‧‧ gate

16,26,36,46,56‧‧‧Source

17,27,37,47,57‧‧‧汲

21a, 41a‧‧‧ upper surface

22a, 42a‧‧‧ part one

22b, 42b‧‧‧ part two

22c, 42c‧‧‧ joint

48‧‧‧N type well area

53b‧‧‧Part III

53c‧‧‧Part IV

B‧‧‧ base

C‧‧‧集极

E‧‧‧射极

d ‧‧‧distance

w ‧‧‧width direction

W1 ‧‧‧effect width

300,400‧‧‧N type LDMOS components

1A-1B shows a conventional N-type MOS device 100.

Fig. 2A-2B shows a first embodiment of the present invention.

3A-3B shows a conventional N-type LDMOS device 300.

4A-4B shows a second embodiment of the present invention.

Fig. 5 shows a third embodiment of the present invention.

6A-6B are diagrams respectively showing an ON breakdown voltage and an OFF breakdown voltage using the N-type MOS device of the present invention.

Figures 7A-7J show a fourth embodiment of the invention.

Fig. 2A-2B shows a first embodiment of the present invention. 2A and 2B are respectively a cross-sectional schematic view and a top view showing an N-type metal oxide semiconductor (MOS) device 200 according to the present invention. As shown in FIGS. 2A and 2B, the N-type MOS device 200 includes a substrate 21, a P-type well region 22, an isolation region 23, a body electrode 24, a gate electrode 25, an N-type source electrode 26, and an N-type drain electrode 27. The substrate 21 has an upper surface 21a. The substrate 21 is, for example but not limited to, a P-type germanium germanium or other semiconductor substrate, and the upper surface 21a is indicated by a broken line in FIG. 2A. The P-type well region 22 is formed below the upper surface 21a. The isolation region 23 is formed on the upper surface 21a to define the operation area 23a. The operation area 23a is located in the P-type well region 22 as a main active area when the N-type MOS element 200 operates. The conductivity type of the P-type well region 22 and the body pole 24 is P-type, and the N-type source electrode 26 and the N-type drain electrode 27 are formed under the upper surface 21a, and the conductivity type is N-type. The gate 25 is formed on the upper surface 21a, and the gate 25 is interposed between the N-type source 26 and the N-type drain 27. The body pole 24 and the N-type source 26 are formed on the same side of the gate 25, and the N-type source 26 is interposed between the body pole 24 and the gate 25, and the body pole 24 is used as the electrical connection of the P-type well region 22. point. The P-type well region 22 has a first portion 22a and a second portion 22b connected to each other. The first portion 22a and the source 26 are located on the same side of the gate 25, and the first portion 22a and the second portion 22b have a junction. 22c, the junction 22c is interposed between the gate 25 and the body pole 24, as viewed from the second view of FIG. 2B, the first portion 22a is in the width direction w of the junction 22c, and both ends exceed the second portion 22b. At least 2 micrometers, as indicated by the distance d in FIG. 2B, the first portion 22a is at least one distance d from the second portion 22b in the width direction w at the junction 22c, that is, the distance d is greater than 2 Micron. Of course, the distance between the two ends beyond the second portion 22b does not have to be the same as long as it exceeds 2 micrometers.

The main concept of the present invention is to design a P-type well region at a width close to both ends of the P-type body pole side, exceeding a width of at least 2 microns near the N-type drain side (or the other side of the N-type source), such that when N When the MOS device is operated, whether the conduction operation or the non-conduction operation, the base resistance value Rb of the parasitic BJT can be controlled below a preset value to avoid the parasitic BJT of the N-type MOS device before the cumulative collapse occurs. Turning on, so that the breakdown protection voltage of the N-type MOS device is lowered.

4A-4B shows a second embodiment of the present invention. This embodiment is intended to illustrate a so-called N-type MOS device according to the present invention, and also includes an N-type lateral double diffused metal oxide semiconductor (LDMOS) device. 4A and 4B are schematic cross-sectional and top views, respectively, showing an N-type LDMOS device 400 in accordance with the present invention. As shown in FIGS. 4A and 4B, the N-type LDMOS device 400 includes a substrate 41, a P-type well region 42, an isolation region 43, a body electrode 44, a gate 45, an N-type source 46, an N-type drain 47, and N. Shape well area 48. The substrate 41 has an upper surface 41a. The substrate 41 is, for example but not limited to, a P-type germanium, or other such as a semiconductor substrate; and the upper surface 41a is indicated by a broken line in FIG. 4A. The P-type well region 42 is formed under the upper surface 41a. The isolation region 43 is formed on the upper surface 41a to define the operation region 43a. The operating zone 43a is located in the N-well zone 48 as the primary active zone for operation of the N-type LDMOS component 400. The conductivity type of the P-type well region 42 and the body pole 44 is P-type, and the N-type source 46, the N-type drain 47, and the N-type well region 48 are formed under the upper surface 41a, and the conductivity type is N-type. The gate 45 is formed on the upper surface 41a, and the gate 45 is interposed between the N-type source 46 and the N-type drain 47. The body pole 44 and the N-type source 46 are formed on the same side of the gate 45, and the N-type source 46 is interposed between the body pole 44 and the gate 45. The body pole 44 is used as the electrical connection of the P-type well region 42. point. Wherein, the P-type well region 42 has a first portion 42a and a second portion 42b connected to each other, the first portion 42a and the source 46 are on the same side of the gate 45, and the junction between the first portion 42a and the second portion 42b 42c, the junction 42c is interposed between the gate 45 and the body pole 44. As viewed from the top view of FIG. 4B, the first portion 42a is in the width direction w of the junction 42c, and both ends exceed the second portion 42b. At least 2 micrometers, as indicated by the distance d in FIG. 4B, the first portion 42a is in the width direction w at the junction 42c, and both ends exceed the second portion 42b by at least one distance d , that is, the distance d is greater than 2 Micron. Of course, the distance between the two ends beyond the second portion 42b does not have to be the same as long as it exceeds 2 micrometers.

Fig. 5 shows a third embodiment of the present invention. Fig. 5 is a top plan view showing an N-type MOS device 500 according to the present invention. As shown in FIG. 5, the N-type MOS device 500 includes a substrate 51, a P-type well region 52, an isolation region 53, a body electrode 54, a gate 55, an N-type source 56, and an N-type drain 57. Different from the first embodiment, in the embodiment, except that the P-type well region 52 is in the width direction w , both ends of the first portion exceed the second portion by at least one distance d (not shown, please refer to the first An embodiment, and the distance d is greater than 2 microns, as shown in FIG. 5, the operation region 53a has a third portion 53b and a fourth portion 53c connected to each other, and the third portion 53b and the source 56 are located at the gate 55 On the same side, and between the third portion 53b and the fourth portion 53c, there is a junction 53d, and the junction 53d is interposed between the gate 55 and the body pole 54. The fifth portion 53b is viewed from the top view. In the width direction w at the junction 53d, both ends exceed the fourth portion 53c by at least 2 microns. The present embodiment is intended to explain that, according to the present invention, in addition to adjusting the width of the P-type well region on the source side of the gate, the width of the operation region on the source side of the gate can be adjusted to increase the N-type MOS device. The crash protection voltage.

It should be noted that the present invention is designed to avoid N-type MOS element, the parasitic BJT is turned on, the voltage drop crash protection, the preferred range of applications, in that the N-type MOS element, as illustrated in FIG. 5, the effect width w1 When not more than 5 microns. Please refer to the action width w1 of FIGS. 2B and 4B at the same time. Further, in a preferred embodiment, the body pole 54 extends beyond the operating region 53a in the width direction w (please refer to both the body poles 24 and 44 of FIGS. 2B and 4B, and the operating regions 23a and 43a).

6A-6B show an example of an ON breakdown voltage and an OFF breakdown voltage using the N-type MOS device of the present invention, respectively. Fig. 6A is a view showing the conduction breakdown voltage of the N-type MOS device according to the present invention, which is measured in a voltage-limiting manner and is about 40V. Fig. 6B is a view showing the non-conduction collapse protection voltage of the N-type MOS device according to the present invention, which is measured by a current limiting method, and is about 35V. It is shown that with the present invention, the N-type MOS device can maintain the required collapse protection voltage even when the effective width w1 is reduced to not more than 5 μm without being reduced by the component size being reduced in the channel direction.

Figures 7A-7J show a fourth embodiment of the invention. This example is an example A method of manufacturing the N-type MOS device 200 of the first embodiment of the present invention will be described. For convenience of description, in the drawings of FIGS. 7A-7J, a top view and a cross-sectional view of the N-type MOS device 200 are shown from left to right. As shown in Figures 7A and 7B, first, for example, but not limited to, a substrate 21 having an upper surface 21a is provided. Then, for example, but not limited to, the isolation region 23 is formed by an oxidation process, which is, for example, a shallow trench isolation (STI) structure as shown in FIG. 7B, or may be local oxidation of silicon (LOCOS). structure. An isolation region 23 is formed on the upper surface 21a to define the operation region 23a as shown in Fig. 7A.

Next, as shown in FIGS. 7C and 7D, for example, but not limited to, forming a photoresist layer as a mask (not shown) by a lithography process to define a P-type well region 22, and using an ion implantation process, the P-type Impurities, in the form of accelerated ions, as indicated by the dashed arrows in Figure 7D, are implanted within defined regions to form a P-type well region 22 below the upper surface 21a. Wherein, the P-type well region 22 has a first portion 22a and a second portion 22b connected to each other, and the first portion 22a and the source 26 to be formed subsequently are located on the same side of the gate 25 (refer to FIG. 2B), and the first portion There is a junction 22c between the 22a and the second portion 22b, and the junction 22c is interposed between the gate 25 and the body pole 24, as viewed from the top view 7C, the width of the first portion 22a at the junction 22c. On w , both ends are at least 2 microns beyond the second portion 22b, as indicated by the distance d in Figure 7C.

Next, as shown in Figs. 7E and 7F, the gate 25 is formed on the upper surface 21a. Next, as shown in FIGS. 7G and 7H, for example, but not limited to, forming a photoresist layer (not shown) and a gate 25 as a mask by a lithography process, defining an N-type source 26 and an N-type drain 27, and In the ion implantation process, the N-type impurity is implanted in the defined region in the form of an accelerated ion, as indicated by the dashed arrow in Fig. 7H, and the N-type source 26 and the N-type drain electrode 27 are formed thereon. Under the surface 21a, the gate 25 is interposed between the N-type source 26 and the N-type drain 27. The N-type source 26 and the N-type drain 27 do not overlap each other.

Next, as shown in FIGS. 7I and 7J, for example, but not limited to, forming a photoresist layer as a mask (not shown) by a lithography process to define a P-type body pole 24, and using an ion implantation process, the P-type Impurities, in the form of accelerated ions, are implanted into defined regions to form a P-type body pole 24 below the upper surface 21a. The body pole 24 and the N-type source 26 are located on the same side of the gate 25, and the N-type source 26 is interposed between the body pole 24 and the gate 25, and the body pole 24 is used as the electrical property of the P-type well region 22. contact.

The present invention has been described with reference to the preferred embodiments thereof, and the present invention is not intended to limit the scope of the present invention. In the same spirit of the invention, various equivalent changes can be conceived by those skilled in the art. For example, other process steps or structures, such as a threshold voltage adjustment region, may be added without affecting the main characteristics of the component; for example, the lithography technology is not limited to the reticle technology, and may also include electron beam lithography; In addition to the LDMOS device, the N-type MOS device according to the present invention also includes an N-type double diffused drain metal oxide semiconductor (DDDMOS) device, and a N-type double diffused metal oxide semiconductor (double diffused). Metal oxide semiconductor, DMOS) components. The above and other equivalent variations are intended to be covered by the scope of the invention.

21‧‧‧Substrate

22‧‧‧P type well area

22a‧‧‧First District

22b‧‧‧Second District

22c‧‧‧Connected

23‧‧ ‧ isolation zone

23a‧‧‧Operating area

24‧‧‧ body pole

25‧‧‧ gate

26‧‧‧N source

27‧‧‧N type bungee

200‧‧‧N type MOS components

d ‧‧‧distance

w ‧‧‧width direction

W1 ‧‧‧effect width

Claims (8)

An N-type metal oxide semiconductor (MOS) device is formed in a substrate having an upper surface, the N-type MOS device comprising: an isolation region formed on the upper surface to define a An operation zone; a P-type well region formed under the upper surface; an N-type source formed under the upper surface; an N-type drain formed under the upper surface; and a gate formed on the upper surface a gate is interposed between the N-type source and the N-type drain; and a body electrode is formed on the same side of the gate as the N-type source, and the N-type source is interposed Between the body pole and the gate, the body pole is used as an electrical contact of the P-type well region; wherein the P-type well region has a first portion and a second portion connected to each other, the first portion is The source is located on the same side of the gate, and a first junction is formed between the first portion and the second portion, and the first junction is between the gate and the body pole, the first Part of the width direction of one of the first junctions, both ends exceeding at least 2 micrometers of the second portion; wherein the operation regions have each other Connecting a third portion and a fourth portion, the third portion and the source are on the same side of the gate, and the second portion and the fourth portion have a second junction, the second portion The junction is between the gate and the body pole, and the third portion is at least 2 micrometers beyond the fourth portion in the width direction of the second junction. The N-type metal oxide semiconductor device of claim 1, wherein the fourth portion has a second active width and the second applied width does not exceed 5 microns. An N-type metal oxide semiconductor (MOS) device is formed in a substrate having an upper surface, the N-type MOS device comprising: an isolation region formed on the upper surface to define a An operation zone; a P-type well region formed under the upper surface; an N-type source formed under the upper surface; an N-type drain formed under the upper surface; and a gate formed on the upper surface a gate is interposed between the N-type source and the N-type drain; and a body electrode is formed on the same side of the gate as the N-type source, and the N-type source is interposed Ontology Between the pole and the gate, the body pole is used as an electrical contact of the P-type well region; wherein the P-type well region has a first portion and a second portion connected to each other, the first portion and the first portion The source is located on the same side of the gate, and a first junction is formed between the first portion and the second portion, the first junction is between the gate and the body pole, the first portion And a width of the first junction is at least 2 micrometers beyond the second portion; wherein the operation region has a first active width, and the first active width does not exceed 5 micrometers. An N-type metal oxide semiconductor (MOS) device is formed in a substrate having an upper surface, the N-type MOS device comprising: an isolation region formed on the upper surface to define a An operation zone; a P-type well region formed under the upper surface; an N-type source formed under the upper surface; an N-type drain formed under the upper surface; and a gate formed on the upper surface a gate is interposed between the N-type source and the N-type drain; and a body electrode is formed on the same side of the gate as the N-type source, and the N-type source is interposed Between the body pole and the gate, the body pole is used as an electrical contact of the P-type well region; wherein the P-type well region has a first portion and a second portion connected to each other, the first portion is The source is located on the same side of the gate, and a first junction is formed between the first portion and the second portion, and the first junction is between the gate and the body pole, the first a portion of the first junction in a width direction, both ends exceeding the second portion by at least 2 microns; wherein the body is at the width In the direction, exceed the operating area. An N-type metal oxide semiconductor (MOS) device manufacturing method, comprising: providing a substrate, wherein the substrate has an upper surface; forming an isolation region on the upper surface to define an operation region; forming a a P-type well region under the upper surface; forming a gate on the upper surface; forming an N-type source under the upper surface; forming an N-type drain under the upper surface, wherein the gate is interposed Between the N-type source and the N-type drain; Forming a body pole, the body pole and the N-type source are located on the same side of the gate, and the N-type source is interposed between the body pole and the gate, and the body pole is used as the P-type well region An electrical contact; wherein the P-type well region has a first portion and a second portion connected to each other, the first portion and the source are located on the same side of the gate, and the first portion and the second portion Between the portions having a first junction, the first junction is between the gate and the body pole, and the first portion is in a width direction of the first junction, and both ends exceed the The second portion is at least 2 micrometers; wherein the operating region has a third portion and a fourth portion connected to each other, the third portion and the source are located on the same side of the gate, and the third portion and the fourth portion Between the portions having a second junction between the gate and the body pole, the third portion of the second junction at the width direction of the second junction The fourth part is at least 2 microns. The method of fabricating an N-type metal oxide semiconductor device according to claim 5, wherein the fourth portion has a second active width, and the second applied width does not exceed 5 micrometers. An N-type metal oxide semiconductor (MOS) device manufacturing method, comprising: providing a substrate, wherein the substrate has an upper surface; forming an isolation region on the upper surface to define an operation region; forming a a P-type well region under the upper surface; forming a gate on the upper surface; forming an N-type source under the upper surface; forming an N-type drain under the upper surface, wherein the gate is interposed Between the N-type source and the N-type drain; and forming a body pole, the body pole and the N-type source are located on the same side of the gate, and the N-type source is interposed between the body pole and the body Between the gates, the body pole is used as an electrical contact of the P-type well region; wherein the P-type well region has a first portion and a second portion connected to each other, the first portion being located with the source The gate is on the same side, and a first junction is formed between the first portion and the second portion, the first junction is between the gate and the body pole, and the first portion is One of the first junctions in the width direction, both ends of which exceed the second portion by at least 2 microns; wherein the operation zone has a A width of action, and the action of the first width not exceeding 5 microns. A method for manufacturing an N-type metal oxide semiconductor (MOS) device, comprising: Providing a substrate, the substrate having an upper surface; forming an isolation region on the upper surface to define an operation region; forming a P-type well region under the upper surface; forming a gate on the upper surface; Forming an N-type source under the upper surface; forming an N-type drain under the upper surface, wherein the gate is interposed between the N-type source and the N-type drain; and forming a body pole The body pole and the N-type source are located on the same side of the gate, and the N-type source is interposed between the body pole and the gate, and the body pole is used as an electrical connection of the P-type well region. a P-well region having a first portion and a second portion connected to each other, the first portion and the source being located on the same side of the gate, and having a relationship between the first portion and the second portion a first junction, the first junction is between the gate and the body pole, and the first portion is in a width direction of the first junction, and both ends exceed the second portion 2 microns; wherein the body is in the width direction beyond the operating area.