TW201316512A - MOS device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.

Description

Metal oxide semiconductor device and method of manufacturing same

The present invention relates to a semiconductor technology, and more particularly to a metal oxide semiconductor (MOS) device and a method of fabricating a metal oxide semiconductor device.

Metal oxide semiconductor devices, such as transistors and memory cells of similar structure, are generally known to have the configuration as shown in FIG. The metal oxide semiconductor device illustrated in FIG. 1 is an N-type metal oxide semiconductor device and is referred to as an NMOS device 100. The NMOS device 100 is formed on a semiconductor substrate 102, which is, for example, a germanium wafer. A P-well 104 is formed on the substrate 102 and is considered to be the body and active region of the NMOS device. The P well region 104 can be formed by a well-known implantation process, such as implantation of boron (B) ions, as a P-type impurity. NMOS device 100 includes diffusion regions 106 and 108, which may serve as source and drain, respectively. The NMOS device 100 includes a gate structure including a gate oxide layer 110 and a polysilicon gate 112. The gate oxide layer 110 is generally formed on the upper surface of the substrate 102 by a thermal oxidation process, and then the polysilicon is deposited as a gate 112 through a deposition process. The gate oxide layer 110 and the gate 112 can then be formed by patterning the oxide layer and the polysilicon layer, for example using a photolithography process. In some embodiments, the gate structure can be formed prior to the diffusion regions 106 and 108 such that the gate can be used to assist in the alignment of the diffusion regions 106 and 108.

Next, an interlevel dielectric (ILD) structure 116 is formed to electrically insulate various structures of the NMOS device 100. Performing a well-known back-end-of-line (BEOL) will include the fabrication of vias and conductive traces including source interconnects 118, drain interconnects 120 and gate interconnects 122. .

For components such as NMOS device 100, design goals often require both high voltage and low voltage limits. These simultaneous goals are often contradictory. For example, high voltage transistors with high junction breakdown characteristics and high punch-through characteristics can be expected to deliver relatively high voltages. However, in order to effectively pass a high voltage from the drain to the source without significant voltage drop, the transistor should preferably have a low channel resistance. These contradictory high voltage requirements are sometimes encountered in the use of transistors with long channel lengths. However, with the trend of technology, shorter channels are desirable, thus increasing the difficulty of stacking high voltage transistors, such as having appropriate on-resistance and break-down. Voltage, BVD) NMOS element 100.

The present invention relates to a semiconductor device including a well of a first conductivity type, a gate electrode, a first implant region, a second implant region, a source diffusion region, and a drain diffusion region. A well of the first conductivity type is formed in the substrate, and a gate electrode is formed on the well. A first implant region is formed in the well and extends below the gate electrode and has a first conductivity type. A second implant region is formed in the well and extends below the gate electrode and has a second conductivity type. The second implant region is separated from the first implant region by a channel region under the gate electrode. A source diffusion region is formed in the first implant region and has a second conductivity type. The drain diffusion region is formed in the second implant region, has a second conductivity type, and has a higher doping concentration than the second implant region.

In one embodiment, a third implant region is further included, the third implant region being interposed between the source diffusion region and the first implant region.

In one embodiment, the third implant region has a second conductivity type that is the same as the source diffusion region.

In one embodiment, the third implant region has a lower doping concentration than the source diffusion region.

In one embodiment, a fourth implant region is further included, and the fourth implant region is interposed between the drain diffusion region and the second implant region.

In one embodiment, the fourth implant region has a second conductivity type that is the same as the drain diffusion region.

In one embodiment, the fourth implant region has a lower doping concentration than the source diffusion region.

In one embodiment, the fourth implanted region has a higher doping concentration than the second implanted region.

In one embodiment, the second implant region has a lower doping concentration than the drain diffusion region.

In one embodiment, the first conductivity type is a P type, and the second conductivity type is an N type.

In one embodiment, the first conductivity type is an N type and the second conductivity type is a P type.

The present invention relates to a method of fabricating a semiconductor device, comprising forming a well of a first conductivity type in a substrate, forming a gate electrode over the well, forming a first implant region in the well, the first value entry region being below the gate electrode Extending, the first implanted region has a first conductivity type, the second implanted region is formed in the well, the second implanted region extends from below the gate electrode, the second implanted region has a second conductivity type, and the second implant The region is separated from the first implant region by a channel region under the gate electrode to form a source diffusion region in the first implant region, the source diffusion region has a second conductivity type, and a drain diffusion region is formed in the second implant region In the in-region, the drain diffusion region has a second conductivity type and has a higher doping concentration than the second implant region.

In an embodiment, the method further includes forming a third implant region in the first implant region, wherein forming the source diffusion region includes forming a source diffusion region, so that the third implant region is interposed between the source diffusion region and the first implant region An implanted area.

In one embodiment, the third implant region has a second conductivity type that is the same as the source diffusion region.

In one embodiment, the third implant region has a lower doping concentration than the source diffusion region.

In an embodiment, the method further includes forming a fourth implant region in the second implant region, wherein the forming of the drain diffusion region includes forming a drain diffusion region, and the fourth implant region is interposed between the drain diffusion region and the first implant region Between the two implanted areas.

In one embodiment, the fourth implant region has a second conductivity type that is the same as the drain diffusion region.

In one embodiment, the fourth implant region has a lower doping concentration than the source diffusion region.

In one embodiment, the fourth implanted region has a higher doping concentration than the second implanted region.

In one embodiment, the second implant region has a lower doping concentration than the drain diffusion region.

In one embodiment, the first conductivity type is a P type, and the second conductivity type is an N type.

In one embodiment, the first conductivity type is an N type and the second conductivity type is a P type.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

2 is a cross-sectional view of NMOS device 200 that allows for improved breakdown voltage (BVD) and specific on-resistance (Ron-sp) in short channel components. NMOS device 200 includes an anti-punch implant region, referred to as HVPW 202, near the source of the device. NMOS device 200 also includes a very lightly doped region near the drain of the device, referred to as N-region 204. The HVPW 202 and the N--region 204 are separated from each other by the channel region of the NMOS device 200, and the channel region extends below the gate electrode 216. The addition of these two regions helps to improve component characteristics. More specifically, HVPW 202 improves the breakdown voltage and also improves the off-state drain-to-source leakage current (Ioff). The HVPW 202 can also allow adjustment of the threshold voltage (Vt). N--zone 204 improves component on-resistance and component breakdown voltage. Even though the NMOS device is an exemplary embodiment, other alternative embodiments can be implemented. For example, one skilled in the art will be aware of the exchange of conductive types (eg, N-type or P-type materials) for achieving P-type metal oxide semiconductor (PMOS) devices.

The NMOS device 200 will now be described in more detail. Figure 3 illustrates the intermediate structure of the NMOS device 200 during fabrication. The intermediate structure illustrated in FIG. 3 includes a semiconductor substrate 206. The semiconductor substrate 206 can be either a germanium wafer or any of a variety of known semiconductor substrates.

Regarding the insulation of the components, the NMOS device 200 includes a deep N-well 208 formed in the semiconductor substrate 206, followed by a P-well 210 formed in the deep N well region 208. The deep N well region 208 and the P well region 210 can be formed using conventional masking and ion implantation techniques. Other insulating structures may include a field oxide (FOX) layer 212, which may be formed using masking and thermal oxidation techniques. For example, an oxide definition (OD) nitride mask can be used to define a region of the field oxide layer 212, which can then be used to form the field oxide layer 212. Although there may be variations, the field oxide layer 212 may have a thickness in the range of 4000 to 7000 angstroms, exemplarily about 5000 angstroms.

NMOS device 200 includes a gate oxide layer 214 with a gate oxide layer 214 disposed between gate electrode 216 and P well region 210. NMOS device 200 can also include a threshold voltage implant region 218 that is located below gate oxide layer 214 and that extends between HVPW 202 and N--region 204. Gate oxide layer 214, gate electrode 216, and threshold voltage implant region 218 can be formed using conventional processes. For example, threshold voltage implantation can be formed using conventional processes including the use of sacrificial oxide (SAC-OX) followed by a thermal oxidation process to form an oxide layer on substrate 206. Polycrystalline germanium deposition may be used to form a polysilicon layer on the oxide layer, and then the polysilicon layer and the oxide layer may be selectively etched according to a conventional lithography process to form a gate oxide layer 214 from the oxide layer and a gate from the polysilicon layer. Electrode 216.

Next, an N--region 204 is formed at the position shown in FIG. An N-type photoresist mask 220 is formed prior to implantation of the N-region 204. Next, using a well implant, implant conductive impurities into the P well region 210, such as using phosphorus (P) or arsenic (As) ions, and in one embodiment using an oblique angle of 20 degrees. To a range of 60 degrees, for example, an oblique angle of about 45 degrees is implanted. Likewise, the gate electrode 216 can also be used to partially mask the implant process, allowing self-alignment of the N--regions 204. After the N-region 204 is formed, the N-type photoresist mask 220 is removed using an ashing process.

Referring next to Fig. 4, another intermediate structure of the NMOS device 200 in the manufacturing process is illustrated. The HVPW 202 is formed at the position depicted in FIG. Prior to implantation of the HVPW 202, an HVPW photoresist mask 222 is formed. Next, conductive implants are implanted into the P well region 210 using a well implant process, such as using boron (B) ions, and implanting at an oblique angle of about 7 degrees. Likewise, the gate electrode 216 can also be used to partially mask the implant process, allowing self-alignment of the HVPW 202. After forming the HVPW 202, the HVPW photoresist mask 222 is removed using an ashing process.

Referring next to Fig. 5, another intermediate structure of the NMOS device 200 in the manufacturing process is illustrated. Additional impact zones are formed at the locations depicted in Figure 5. The additional impact zone includes an N-zone 226 on the source side and an N-region 228 on the drain side. An N-block mask 224 is formed prior to implantation of N-regions 226 and 228. Next, using well implanting, conductive impurities are implanted into the P-well region 210, for example using phosphorus (P) or arsenic (As) ions, and implanted at an oblique angle of about 0 degrees. Likewise, the gate electrode 216 can also be used to partially mask the implant process, allowing self-alignment of the N-regions 226 and 228. After the N-regions 226 and 228 are formed, the N-resistive mask 224 is removed using an ashing process.

Referring back to Figure 2, the remaining structure can be formed using standard NMOS fabrication procedures. For example, spacer 230, such as tetraethyl ortho silicate (TEOS), can be formed by deposition and etching. The spacers 230 can be used to align the source diffusion regions 232 and the drain diffusion regions 234 formed after alignment. Therefore, after the spacer 230 is formed, the N+ source diffusion region 232 and the N+ drain diffusion region 234 can be formed by a lithography etching and well implantation process. Similarly, a P+ body diffusion region 236 can be formed using a lithography and well implant process. After the diffusion regions 232, 234, and 236 are formed, an insulating material such as borophosphosilicate glass (BPSG) or the like may be formed to form an inter-layer dielectric (ILD) structure 240 for electricity. Various structures of the insulating NMOS device 200. A conventional back end process (BEOL) is then performed to complete the NMOS device 200. The back end process includes the fabrication of the body via 242, the source via 244, the gate via 246, and the drain via 248.

Those skilled in the art will recognize exchanged conductivity types (e.g., N-type or P-type materials) for achieving PMOS components. For example, the conductivity type of the HVPW 202, the P well region 210, and the P+ region 236 can be changed to N-type, and the N--region 204, the N-region 226, the N-region 228, the N+ region 232, and the N+ region can be changed. The conductivity type of 234 is P type to fabricate a PMOS device.

Figures 6 through 9 show graphs of comparative data showing the improved effects of the elements disclosed by the present invention. The graphs depicted in Figures 6 and 7 compare the NMOS and prior art components depicted in Figure 2, both having a gate length of approximately 0.4 μm. In the graph depicted in Figure 6, it can be seen that the breakdown voltage is in the elements of the present invention, which is approximately 11 volts compared to prior art components, and the prior art components are approximately 3 volts. In the graph depicted in Figure 7, it can be seen that a particular on-resistance is in the elements of the present invention, as compared to prior art elements. When the drain voltage (Vd) is within a certain range, particularly greater than 1 volt, the inventive device has a larger drain current at the same drain voltage than prior art components. Figures 8 and 9 show graphs showing the completion of the disclosed NMOS device data. In Figure 8, it can be seen that the completed NMOS device can achieve an improved bulk current (I-bulk) of about 70% compared to prior art components. (Depending on the dosage range from -316 microamperes to -92 microamperes). In Figure 9, it can be seen that the completed NMOS device is completed to achieve an improved initial breakdown voltage. As depicted in Figure 9, the initial collapse voltage can be improved by about 13.3% (depending on the dose range from 6 volts to 6.8 volts) compared to prior art components.

While the various embodiments of the present invention have been described hereinabove, it is understood that the embodiments are merely illustrative of the invention and are not intended to limit the invention. Therefore, the scope and breadth of the invention should not be construed as being limited by the scope of the invention. In addition, the above advantages and features are described in the embodiments, and it is not intended to limit the advantages of any or all of the above, but to limit the scope of the published patent application to specific processes and structures.

In addition, the category headings here are used to provide hints on the content group. These headings are not intended to limit or characterize the invention contained in the claims that may be issued in connection with the disclosure. By way of specific example, although the title is related to the "technical field", the request item should not be limited to the language used under the heading to describe the so-called technical field. In addition, a technique described in the "Background" section should not be taken as an admission that the technology is prior art to the present invention. The “Content” section should not be considered as a characterization of the invention contained in the request being issued. In addition, any "invention" referred to in the singular of this disclosure should not be used to contend for the only point of view that is merely novel in the disclosure. The features of a plurality of claims that are issued by the present disclosure are to be construed as a plurality of inventions, and such claims may be defined as the invention(s) and the equivalents thereof. In all cases, the scope of such claims is to be considered in its own right, and may be referred to in this disclosure, but the title thereof should not be used as a limitation.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200. . . NMOS device

102, 206. . . Substrate

104, 210. . . P well area

106, 108. . . Diffusion zone

110, 214. . . Gate oxide layer

112, 216. . . Gate electrode

116, 240. . . Interlayer dielectric structure

118. . . Source interconnect

120. . . Bungee interconnect

122. . . Gate interconnect

202. . . Anti-implantation area (HVPW)

204. . . N--zone

208. . . Deep N well area

212. . . Field oxide layer

218. . . Threshold voltage implant

220. . . N--resistive mask

222. . . HVPW photoresist mask

224. . . N-resistive mask

226, 228. . . N-zone

230. . . Spacer

232. . . Source diffusion region (N+ region)

234. . . Bungee diffusion zone (N+ zone)

236. . . Bulk diffusion zone (P+ zone)

242, 244, 246, 248. . . Through hole

Features, shapes and embodiments of the present invention are described in conjunction with additional drawings in which:

1 is a cross-sectional perspective view of a conventional NMOS device;

2 is a cross-sectional view showing an NMOS device in accordance with an embodiment of the present invention;

Figures 3 through 5 illustrate respective intermediate structures formed in an exemplary process for fabricating the NMOS device of Figure 2;

Figures 6-9 show graphs of comparative data showing the improved effects of the elements disclosed by the present invention.

200. . . NMOS device

202. . . Anti-implantation area (HVPW)

206. . . Substrate

204. . . N--zone

208. . . Deep N well area

210. . . P well area

212. . . Field oxide layer

214. . . Gate oxide layer

216. . . Gate electrode

218. . . Threshold voltage implant

230. . . Spacer

232. . . Source diffusion region (N+ region)

234. . . Bungee diffusion zone (N+ zone)

236. . . Bulk diffusion zone (P+ zone)

240. . . Interlayer dielectric structure

242, 244, 246, 248. . . Through hole

Claims (10)

A semiconductor device comprising: a well of a first conductivity type formed in a substrate; a gate electrode formed on the well; a first implant region formed in the well and from the well Extending below the gate electrode, the first implant region has the first conductivity type; a second implant region is formed in the well and extends from below the gate electrode, the second implant region has a second conductivity a second implant region is separated from the first implant region by a channel region under the gate electrode; a source diffusion region is formed in the first implant region, the source diffusion region having the a second conductivity type; and a drain diffusion region formed in the second implant region, the drain diffusion region having the second conductivity type and having a higher dopant than the second implant region Miscellaneous concentration. The semiconductor component of claim 1, further comprising a third implant region between the source diffusion region and the first implant region. The semiconductor device of claim 2, wherein the third implant region has the same second conductivity type as the source diffusion region. The semiconductor device of claim 3, wherein the third implant region has a lower doping concentration than the source diffusion region. The semiconductor device of claim 1, further comprising a fourth implant region between the drain diffusion region and the second implant region. The semiconductor device of claim 5, wherein the fourth implant region has the same second conductivity type as the drain diffusion region. The semiconductor device of claim 6, wherein the fourth implant region has a lower doping concentration than the source diffusion region. The semiconductor device of claim 7, wherein the fourth implant region has a higher doping concentration than the second implant region. The semiconductor device of claim 1, wherein the second implant region has a lower doping concentration than the drain diffusion region. A method of fabricating a semiconductor device, comprising: forming a well of a first conductivity type in a substrate; forming a gate electrode over the well; forming a first implant region in the well, the first value entry region Extending below the gate electrode, the first implant region has the first conductivity type; forming a second implant region in the well, the second implant region extending from below the gate electrode, the second implant The region has a second conductivity type, and the second implant region is separated from the first implant region through a channel region below the gate electrode; forming a source diffusion region in the first implant region, a source diffusion region having the second conductivity type; and forming a drain diffusion region in the second implant region, the drain diffusion region having the second conductivity type and having a second implant region compared to the second implant region A higher doping concentration.