TWI501531B - Interleaved zero voltage switching converter - Google Patents

Description

Interleaved zero voltage switching converter

The invention relates to an interleaved zero voltage switching converter, in particular to a zero voltage switching performance, which can reduce switching loss, improve power conversion efficiency, and the switching voltage stress is only an input voltage, which can reduce the switching voltage stress, and It has the output current chopping cancellation effect, reduces the output chopping current, can reduce the volume of the output filter component, and can effectively reduce the overall production cost, and it has more practical and practical characteristics interleaved in its overall implementation. An innovative designer of zero voltage switching converters.

Press, due to the decreasing oil source, the awareness of energy conservation is high, the US Environmental Protection Agency has developed ENERGY STAR 4.0, and the 80 PLUS specification is included in the standard, for the AC-DC switching power supply provided to the PC. , SPS], regardless of the power load 20%, 50%, 100% state, AC / DC power conversion efficiency must reach 80%, even Version 5.0 must exceed 80% efficiency begging. As 80 PLUS meets the trend of energy saving and environmental protection, the newly introduced switching power supply (SPS) is almost always supporting the 80 PLUS specification as the main selling point, and adopts the characteristics of energy saving and power saving to obtain the recognition of the European and American consumer market. In 2008, the 80 PLUS specification added more stringent copper, silver, and gold medal certifications; in 2009 and 2011, respectively, the Platinum and Titanium grade certifications were added. Therefore, designing high-efficiency power converters to meet increasingly stringent power supply specifications is a constant trend.

For details, please refer to M372997, “Interlaced Series Input Parallel Output Zero-Voltage Switching Forward Converter”, published on January 21, 1999. The switching stress of this converter is V _in /2(1-D). The switching stress changes with the conduction ratio. If the conduction ratio D>0.5, the switching voltage stress is greater than V _in .

Please refer to the schematic diagram of one of the existing circuit diagrams in Figure 17, which is KBPark, CEKim, GWMoon and MJYoun, "Three-switch active-clamp forward converter with low switch voltage stress and wide ZVS range for high-input -voltage applications," IEEE Trans. Power Electronics , Vol. 25, No. 4, pp. 889-898, 2010. The converter has three power switches with a large number of power switches.

Please refer to the schematic diagram of the existing circuit structure of the eighteenth figure, which is T.Qian and B.Lehman, "Dual Interleaved Active-Clamp Forward With Automatic Charge Balance Regulation for High Input Voltage Application," IEEE Trans. Power Electronics, Vol. 23, No. 1, pp. 38-44, 2008., published an "interleaved dual active clamp forward converter" with automatic charging balance adjustment function, suitable for high Input voltage application, it must use two additional sets of windings, so transformer The production is more complicated. In the four switches of the converter, two high voltage stress switches are required, and two lower voltage stress switches. Because this converter lacks the design of the resonant inductor, the switch ZVS operation cannot be guaranteed, and the leakage inductance of the transformer will cause voltage surge on the switch, and an additional snubber circuit must be added.

In addition, please refer to the schematic diagram of the three circuit architectures in the nineteenth figure, which is T.Jin, K.Zhang, K.Zhang; K.Smedley, "A New Interleaved Series Input Parallel Output (ISIPO) Forward Converter With Inherent Demagnetizing Features, "IEEE Trans. Power Electronics, Vol. 23, No. 2, pp. 888-895, 2008. "Interlaced Series Input Parallel Output (ISIPO) Forward Converter", which is interleaved The characteristics and advantages of the two-switch forward converter and half-bridge converter have the advantages of natural flux reset, suitable for high input voltage, high output current and high power applications. Although only two switches are used, the maximum voltage stress of the switch is V _in , but the switch of this converter is hard switching and does not have flexible switching performance, so the large switching loss is a disadvantage.

The reason is that the inventor has been rich in design and development and practical production experience of the relevant industry for many years, and has researched and improved the existing structure to provide an interleaved zero-voltage switching converter for the purpose of achieving better practical value.

The main object of the present invention is to provide an interleaved zero-voltage switching converter, which mainly has zero voltage switching performance, can reduce switching loss, improve power conversion efficiency, and the switching voltage stress is only an input voltage, which can reduce switching voltage stress. And has the output current chopping cancellation effect, reducing the output chopping current, reducing the size of the output filter component, the same It can be effectively reduced in overall production cost, and it is more practical and effective in its overall implementation.

The main purpose and effect of the interleaved zero-voltage switching converter of the present invention are achieved by the following specific technical means: the main reason is that the converter is connected _in parallel with the power supply input terminal V _{in in} parallel with the bridge switch Q ₂ and the lower bridge switch. Q ₁ , the upper bridge switch Q ₂ includes a related body diode and a switch output capacitor C _r2 , and the lower bridge switch Q ₁ includes an off body diode and a switch output capacitor C _r1 , and the switch output capacitor C _r2 C _{r1 is} used as a resonant capacitor, so that the ends of the upper bridge switch Q ₂ are respectively connected to the first end points of the DC blocking capacitor C ₁ and the resonant inductor L _{r , and} the ends of the lower bridge switch Q ₁ are respectively blocked from the DC The first end of the capacitor C ₂ and the resonant inductor L _{r are} connected such that the second end of the DC blocking capacitor C ₁ and the resonant inductor L _r is connected in parallel with the magnetizing inductance L _m1 of the primary side of the transformer T ₁ , and the DC is The second end of the blocking capacitor C ₂ and the resonant inductor L _r is connected in parallel with the magnetizing inductance L _m2 of the primary side of the transformer T ₂ , so that the second end of the secondary side of the transformer T _{1 and the} secondary side of the transformer T ₂ It is connected to one end point, and a first end of _a secondary side of the transformer T L ₁ associated with a first end and a negative output inductor stage rectifying diode D _1, a second parallel terminal ₂ of the secondary side of the transformer T L ₂ has a first end of the rectifier diode D ₂ and the negative electrode of the output inductor Pointing, the second end of the output inductors L ₁ and L ₂ are connected to the first end of the output capacitor C _O and the output load R, and the positive poles of the rectifying diodes D ₁ and D ₂ are And connected to the output capacitor C _O and the second end of the output load R.

(1)‧‧‧ converter

First picture: schematic diagram of the circuit of the present invention

Second picture: timing waveform diagram of the main components of the present invention

Third figure: schematic diagram of the first linear circuit stage circuit of the present invention

Fourth figure: schematic diagram of the second linear circuit stage circuit of the present invention

Figure 5: Schematic diagram of the third linear circuit stage circuit of the present invention

Figure 6 is a schematic diagram of the fourth linear circuit stage circuit of the present invention

Figure 7: Schematic diagram of the fifth linear circuit stage circuit of the present invention

Figure 8 is a schematic diagram of the sixth linear circuit stage circuit of the present invention

Ninth diagram: schematic diagram of the seventh linear circuit stage circuit of the present invention

Figure 10: Schematic diagram of the eighth linear circuit stage circuit of the present invention

Figure 11: Waveform diagram of driving signal, input voltage and output voltage of bridge switch and upper bridge switch under the present invention

Twelfth figure: waveform signal of the driving signal and DC blocking capacitor voltage V _C1 and V _C2 of the bridge switch and the upper bridge switch under the present invention

Thirteenth diagram: driving signal and 汲-source voltage waveform diagram of bridge switch and upper bridge switch under the present invention [full load 480W]

Figure 14: Driving signal and 汲-source voltage waveform diagram of bridge switch and upper bridge switch under the present invention [half load 240W]

Figure 15: Waveform diagram of the output inductor current and total output inductor current of the present invention

Figure 16: Driving signal of the bridge switch and the upper bridge switch and the current waveform of the rectifying diode under the present invention

Figure 17: Schematic diagram of a circuit structure existing

Figure 18: Schematic diagram of the existing two circuit architecture

Figure 19: Schematic diagram of the existing three circuit architecture

For a more complete and clear disclosure of the technical content, the purpose of the invention and the effects thereof achieved by the present invention, the following is a detailed description, and please refer to the drawings and drawings: First, please refer to The first diagram shows the circuit diagram of the present invention. The converter (1) of the present invention is mainly connected to a power supply input terminal V _{in in} parallel with a series connection upper bridge switch Q ₂ and a lower bridge switch Q ₁ , the upper bridge switch Q ₂ The utility model comprises a related body diode and a switch output capacitor C _r2 , wherein the lower bridge switch Q ₁ comprises an off body diode and a switch output capacitor C _r1 , and the switch output capacitors C _r2 and C _{r1 are} used as resonance capacitors, so that the The _two ends of the upper bridge switch Q ₂ are respectively connected to the first end points of the DC blocking capacitor C ₁ and the resonant inductor L _{r , and} the ends of the lower bridge switch Q ₁ are respectively connected with the DC blocking capacitor C ₂ and the resonant inductor L An end point is connected such that the second end of the DC blocking capacitor C ₁ and the resonant inductor L _r is in parallel with the magnetizing inductance L _m1 of the primary side of the transformer T ₁ , and the DC blocking capacitor C ₂ and the resonant inductor L _{r are m2} magnetizing inductance connected in parallel to a second end of the primary side ₂ of the transformer T L Enabling the secondary of the transformer T ₁ and the second end side of the transformer T ₂ a first end of the secondary side is connected in parallel to the first end of _a secondary side of the transformer T has a rectifying diode D ₁ Negative stage and a first terminal of the output inductor L _1, the second terminal of the transformer T ₂ of the secondary side parallel rectifier diode D ₂ and the negative electrode of the output terminal of the first inductor L _2, enabling the output inductor L _1, The second terminal of L ₂ is connected to the first terminal of the output capacitor C _O and the output load R, and the anodes of the rectifier diodes D ₁ and D ₂ are combined with the output capacitor C _O and the output load. The second endpoint of R is connected.

The invention is used in operation, which makes the upper bridge switch Q ₂ and the lower bridge switch Q ₁ mutually auxiliary switches, and is driven by complementary interleaving, and there is a slight dead time between the driving signals as The circuit resonance time zone enables the upper bridge switch Q ₂ and the lower bridge switch Q _{1 to} achieve zero voltage switching [ZVS] operation, reducing switching losses and improving efficiency. Moreover, since the upper bridge switch Q ₂ and the lower bridge switch Q _{1 have} a bridge structure, the switching voltage stress is only V _in , which is suitable for high input voltage applications. On the other hand, since the output of the converter (1) is a double current rectification architecture, the output terminals of the output inductors L ₁ and L ₂ are connected in parallel, so that the total output current can be shared and the current ripple at the output capacitor C _O can be reduced. In turn, the smaller output inductors L ₁ , L ₂ and the output capacitor C _O can be used to reduce the size and therefore suitable for high output current applications.

In this way, when the present invention is in a steady state, in one switching period T _S , according to the upper bridge switch Q ₂ and the lower bridge switch Q ₁ switching and rectifying the diodes D ₁ , D _{2 are} turned on or off, the circuit action can be It is divided into 8 linear circuit stages, and its waveform is as shown in the second figure of the present invention.

The eight linear circuit phase circuits in a switching cycle T _S are analyzed as follows:

The first stage [t ₀ ~ t ₁ ] [lower bridge switch Q ₁ :on, upper bridge switch Q ₂ :off, rectifying diode D ₁ :off, rectifying diode D ₂ :on]: please refer to the third As shown in the schematic diagram of the first linear circuit stage circuit of the present invention, the first phase starts at t=t ₀ , the lower bridge switch Q ₁ is on, the upper bridge switch Q ₂ is off, and the lower bridge switch Q _{1 is} across voltage V. _Cr1 =0, transformer T ₁ primary side voltage V _{p1 is} similar to V _in -V _c1 >0, magnetization inductance L _m1 current i _Lm1 rises linearly, transformer T ₁ secondary side V _S1 =n ₁ (V _in -V _C1 )>0, the upper bridge switch Q ₂ crosses voltage V _cr2 =V _in , the transformer T ₂ primary side voltage V _{p2 is} similar to -V _c2 <0, and the transformer T ₂ secondary side V _S2 =n ₂ V _P2 = -n ₂ V _C2 <0, so the rectifying diode D ₂ is on, and the rectifying diode D ₁ is off, the voltage of the output inductor L ₁ is V _L1 =V _S1 -V _S2 -V _o >0, current i _L1 rises linearly. On the other hand, the voltage of the output inductor L ₂ is V _L2 = -V _o <0, and the current i _L2 decreases linearly. Therefore, the total output current i _Lo =i _L1 +i _L2 has the effect of chopping cancellation. When t = t ₁ , the lower bridge switch Q _{1 is} switched off, and this phase ends.

Second stage [t ₁ ~ t ₂ ] [lower bridge switch Q ₁ : off, upper bridge switch Q ₂ : off, rectifying diode D ₁ : off, rectifying diode D ₂ : on]: see fourth As shown in the schematic diagram of the second linear circuit stage circuit of the present invention, the second phase starts at t=t ₁ , the lower bridge switch Q _{1 is} switched off, and the resonant inductor current i _Lr charges the switch output capacitor C _r1 to the switch output. The capacitor C _{r2 is} discharged, so the voltage V _{Cr1 of the} switching output capacitor C _r1 rises and the voltage V _{Cr2 of the} switching output capacitor C _r2 decreases. Since the switching output capacitors C _r1 and C _r2 are very small, the voltage V _{Cr1 of the} switching output capacitor C _r1 rises and the voltage V _{Cr2 of the} switching output capacitor C _r2 drops very fast, so this phase is very short. When t=t ₂ , the lower bridge switch Q ₁ rises to V _in -V _C1 across the voltage V _cr1 , and the upper bridge switch Q ₂ crosses the voltage V _cr2 also drops to V _c1 , the transformer T ₁ primary side crossover voltage V _p1 = 0, the transformer T ₂ primary side voltage V _p2 =0, so the transformer T ₁ secondary side V _S1 =0 and the transformer T ₂ secondary side V _S2 =0, the rectifying diodes D ₁ , D _{2 are} all turned on, the output The rectifier enters the current commutation, and the primary side of the transformers T ₁ and T ₂ is clamped at zero voltage, and this phase ends.

The third stage [t ₂ ~ t ₃ ] [lower bridge switch Q ₁ : off, upper bridge switch Q ₂ : off, rectifying diode D ₁ : on, rectifying diode D ₂ : on]: see the fifth As shown in the schematic diagram of the third linear circuit stage circuit of the present invention, the third stage starts at t=t ₂ , the lower bridge switch Q ₁ crosses the voltage V _cr1 =V _in -V _C1 , and the upper bridge switch Q ₂ crosses the voltage V _Cr2 = V _c1 , the primary side voltage of the transformers T ₁ and T ₂ is clamped at zero voltage; the currents i _Lm1 and i _{Lm2 of the} magnetizing inductances L _m1 and L _{m2 are} kept constant, and the secondary side of the transformers T ₁ and T ₂ is V _S1 =V _S2 =0, the output rectifier starts current exchange, current i _D2 decreases, and i _D1 increases. Resonant inductor Lr, the switching output capacitance C _r1 and C _r2 form a resonance circuit, low-side switch Q ₁ cross voltage V _cr1 in resonance forms continue to rise, the upper-side switch Q ₂ cross voltage V _cr2 continued to decline, the resonant inductor Lr across the negative voltage, The current i _Lr drops, the output rectifier continues to commutate, the rectifying diode D ₂ current i _{D2 is} decremented, and the rectifying diode D ₁ current i _{D1 is} incremented. In the third stage, the initial energy storage of the resonant inductor Lr must be greater than the initial energy storage of the switching output capacitors C _r2 and C _r1 , so that the upper bridge switch Q ₂ can be reduced to zero across the voltage V _cr2 to reach the zero voltage switch [ZVS]. condition. When t=t ₃ , the upper bridge switch Q ₂ drops to zero across the voltage V _cr2 , and the body diode of the upper bridge switch Q ₂ starts to conduct, and this phase ends.

The fourth stage [t ₃ ~ t ₄ ] [lower bridge switch Q ₁ : off, upper bridge switch Q ₂ : on, rectifying diode D ₁ : on, rectifying diode D ₂ : on]: see sixth fourth linear phase circuit diagram of the circuit of the present invention shown in the fourth stage starts at t = t _3, the side switch Q ₂ of the body diode conduction, the side switch Q ₂ cross voltage V _cr2 clamped zero And the lower bridge switch Q ₁ crosses the voltage V _cr1 =V _in . Before the upper bridge switch Q ₂ current i _Q2 changes the flow direction, the upper bridge switch Q ₂ must be switched to on to achieve zero voltage switching [ZVS] operation. At this stage, the output rectifier continues to commutate, the primary side voltage of the transformers T ₁ and T ₂ is zero, and the voltage V _{Lr of the} resonant inductor Lr is similar to -V _Cr1 and the current i _Lr decreases linearly. When t=t ₄ , the rectifying diode D ₁ current i _D1 rises to the current i _{L1 of the} output inductor L ₁ , and the rectifying diode D ₂ current i _D2 falls to 0, the commutation is completed, and the rectifying diode D ₂ Become off, this phase ends.

The fifth stage [t ₄ ~ t ₅ ] [lower bridge switch Q ₁ : off, upper bridge switch Q ₂ : on, rectifying diode D ₁ : on, rectifying diode D ₂ : off]: see the seventh The fifth linear circuit stage circuit diagram of the present invention shows that the fifth stage starts at t=t ₄ and the output rectifier commutation is completed, that is, the rectifying diode D ₁ current i _D1 =i _L1 +i _L2 , and the rectification Diode D ₂ current i _D2 =0. The voltages of the magnetizing inductances L _m1 and L _{m2 are} clamped off, V _{p2 is} similar to V _in -V _c2 >0, and the current i _{Lm2 of the} magnetizing inductance L _m2 rises linearly with a slope of (V _in -V _c2 )/L _m2 , transformer T ₂ of the secondary-side voltage _{V S2 = n 2 V p2>} 0, V p1 similar to -V _c1, so the magnetizing inductance L _m1 i _Lm1 current decreases linearly. Since the secondary side voltages V _S1 - V _S2 <0 of the transformers T ₁ and T _{2 are} , the rectifying diode D ₁ is on and the rectifying diode D ₂ is off. The current i _{L1 of the} output inductor L ₁ causes the current i _{L1 to} decrease linearly because V _L1 =−V _O , and the current i _{L2 of the} output inductor L ₂ causes the current i because V _L2 =V _s2 -V _s1 -V _O >0 _L2 rises linearly; therefore, the total output current i _Lo =i _L1 +i _L2 has the effect of chopping cancellation. When t=t ₅ , the upper bridge switch Q _{2 is} switched off, and this phase ends.

The sixth stage [t ₅ ~ t ₆ ] [lower bridge switch Q ₁ : off, upper bridge switch Q ₂ : off, rectifying diode D ₁ : on, rectifying diode D ₂ : off]: please refer to the eighth As shown in the schematic diagram of the sixth linear circuit stage circuit of the present invention, the sixth stage starts at t=t ₅ and the upper bridge switch Q _{2 is} switched off. The current i _Lr of the resonant inductor Lr is a negative value, charges the switching output capacitor C _r2 , and discharges the switching output capacitor C _r1 , the voltage V _{Cr2 of the} switching output capacitor C _r2 rises and the voltage V _{Cr1 of the} switching output capacitor C _r1 decreases. Since the switching output capacitors C _r1 and C _r2 are very small, the voltage V _{Cr2 of the} switching output capacitor C _r2 rises and the voltage V _{Cr1 of the} switching output capacitor C _r1 drops very fast, so the duration of this phase is very short. When t = t _6, the upper-side switch Q ₂ cross voltage V rises to V _{a C1 CR2,} low-side switch Q _{1 CRl} cross voltage V drops to V is _in -V _c1, the primary side of the transformer T ₂ cross voltage V _p2 = 0 And the primary side voltage of the transformer T _{1 is} V _p1 =0. The rectifying diode D ₂ starts to conduct, the rectifying diodes D ₁ and D ₂ begin to exchange, the current i _{D2 of the} rectifying diode D ₂ increases, and the current i _{D1 of the} rectifying diode D ₁ decreases, and this phase ends.

The seventh stage [t ₆ ~ t ₇ ] [lower bridge switch Q ₁ : off, upper bridge switch Q ₂ : off, rectifying diode D ₁ : on, rectifying diode D ₂ : on]: see ninth As shown in the schematic diagram of the seventh linear circuit stage circuit of the present invention, the seventh stage starts at t=t ₆ , the primary side voltages V _p1 and V _{p2 of the} transformers T ₁ and T _{2 are} clamped at 0, and the rectifying diode D ₁ , D ₂ commutation, this stage is similar to the third stage, the magnetizing inductance L _m1, L _m2 of the zero voltage clamp; magnetizing inductance L _m1, L _m2 of current i _Lm1, i _Lm2 remains constant. Resonant inductor Lr, the switching output capacitance C _r1 and C _r2 form a resonance circuit, the high-side switch Q ₂ cross voltage V _cr2 rising, low-side switch Q ₁ cross voltage V _cr1 continued to decline, the resonant inductor Lr across the positive voltage, the current I _Lr Ascending, the output rectifier continues to commutate. In the seventh stage, the initial energy storage of the resonant inductor Lr must be greater than the initial energy storage of the switching output capacitors C _r2 and C _r1 , so that the lower bridge switch Q ₁ can be reduced to zero across the voltage V _cr1 to reach the condition of the zero voltage switch [ZVS]. . When t = t _7, the low-side switch Q ₁ V _cr1 cross voltage drops to zero, the body-side switch Q ₁ of the diode begins to conduct, the end of this stage.

The eighth stage [t ₇ ~ t ₈ ] [lower bridge switch Q ₁ :on, upper bridge switch Q ₂ :off, rectifying diode D ₁ :on, rectifying diode D ₂ :on]: please refer to the tenth an eighth stage of the circuit schematic diagram of linear circuits of the present invention shown in FIG., the eighth stage begins at t = t _7, the body-side switch Q ₁ is turned diode, the voltage across the bridge switch Q ₁ zero cross voltage V _{Cr1 is} clamped at zero and the upper bridge switch Q _{2 is} across voltage V _cr2 =V _in . Since V _cr1 =0, before the lower bridge switch Q ₁ current i _Q1 becomes positive, the lower bridge switch Q ₁ must be switched to on to achieve zero voltage switching [ZVS] operation. At this stage, the voltage V _{Lr of the} resonant inductor Lr is similar to V _Cr2 , and the current i _Lr rises linearly, and the output rectifier continues the commutation process. When t=t ₈ , the rectifying diode D ₂ current i _D2 =i _L1 +i _L2 and i _D2 falls to 0, the rectifying diode D _{1 is} turned off, the commutating diode commutation is completed, and the end of this phase , enter the next switching cycle.

In the verification of the present invention, the steady-state characteristic is first verified. In the steady state, the magnetization inductance voltage V _{p1 is} approximately V _in -V _c1 , and the first stage is due to the magnetization inductance L _m >>L _r . _{P2 is} approximately -V _c2 ; the fifth stage is when the lower bridge switch Q ₁ is off, the upper bridge switch Q ₂ is on, V _p1 = -V _c1 , and V _{p2 is} approximately V _in -V _c2 . According to the volt-second equilibrium theorem, V _c1 =DV _in , V _c2 =(1-D)V _in , and the voltage conversion ratio is V _o /V _in =(n ₁ +n ₂ )D(1-D). Let V _in = 400V, V _o = 24V, n ₁ = n ₂ = 0.145, and the output power is 480W, and the switch-on ratio D can be obtained to be approximately 0.3. Please refer to FIG. 11 for the driving signal, the input voltage and the output voltage waveform diagram of the bridge switch and the upper bridge switch, and the driving signals of the bridge switch and the upper bridge switch according to the twelfth embodiment of the present invention, As shown in the waveform diagrams of the DC blocking capacitor voltages V _C1 and V _C2 , the present invention is quite close to the theoretical value in the simulation results.

According to the thirteenth figure, the driving signal and the 汲-source voltage waveform diagram (full load 480W) of the bridge switch and the upper bridge switch of the present invention show that the lower bridge switch Q ₁ and the upper bridge switch Q _{2 are} switched to Before the on, its cross-over voltages V _ds1 and V _ds2 have been reduced to zero, so the zero voltage switch [ZVS] operation is achieved; and please refer to the fourteenth diagram of the driving signal of the bridge switch and the upper bridge switch of the present invention. As shown in the 汲-source voltage waveform diagram (half load 240W), the zero voltage switch [ZVS] operation can still be achieved at half load of 240W. It can be known that when the input voltage V _in =400V, the maximum voltage across the lower bridge switch Q ₁ and the upper bridge switch Q ₂ is V _in , so the voltage stress of the lower bridge switch Q ₁ and the upper bridge switch Q ₂ is V _in , The converter (1) has a lower voltage stress.

In addition, please refer to the fifteenth diagram of the present invention, the output inductor current and the total output inductor current waveform diagram, it can be seen that the chopping current magnitude Δi _L1 = 1.44A and Δi _L2 = 1.37A, and Δi _Lo = 0.3A, therefore, the output inductors L ₁ and L ₂ can not only share the output current i _Lo =i _L1 +i _L2 , but also have a chopping cancellation action, which reduces the chopping current of the output capacitor C _O . Please refer to the sixteenth figure of the present invention, the driving signal of the bridge switch and the upper bridge switch and the output rectifier diode current waveform diagram, the steady state current and current commutation waveform are in accordance with the analysis result.

From the above, the composition and use of the structure of the present invention show that the present invention has the following advantages in comparison with the existing structure:

1. The invention utilizes an output capacitor and a resonant inductor to form a resonant circuit, so that it has zero voltage switching performance, reduces switching loss, and improves power conversion efficiency.

2. The invention uses two bridge switches in series and an upper bridge to form a bridge structure, and the switching voltage stress is only an input voltage, which can reduce the switching voltage stress.

3. The invention utilizes two output inductors at the output end to share the total output current, and has an output current chopping cancellation effect, which reduces the chopping current of the output capacitor, and can reduce the volume of the output filter component.

4. The present invention uses only two bridge switches and an upper bridge switch in series, so that it can be effectively reduced in overall manufacturing cost.

However, the above-described embodiments or drawings are not intended to limit the structure or the use of the present invention, and any suitable variations or modifications of the invention will be apparent to those skilled in the art.

In summary, the embodiments of the present invention can achieve the expected use efficiency, and the specific structure disclosed therein has not been seen in similar products, nor has it been disclosed before the application, and has completely complied with the provisions of the Patent Law. And the request, the application for the invention of a patent in accordance with the law, please forgive the review, and grant the patent, it is really sensible.

Claims (1)

An interleaved zero-voltage switching converter mainly comprises a converter connected in series with a bridge switch Q ₂ and a lower bridge Q _{1 in} parallel with a power input terminal V _in , the upper bridge switch Q ₂ comprising a related body body pole Body and switch output capacitor C _r2 , the lower bridge switch Q ₁ includes the off body diode and the switch output capacitor C _r1 , and the switch output capacitors C _r2 , C _r1 as resonant capacitors, so that the upper bridge switch Q ₂ The end points are respectively connected to the first ends of the DC blocking capacitor C ₁ and the resonant inductor L _{r , and} the ends of the lower bridge switch Q ₁ are respectively connected to the _first ends of the DC blocking capacitor C ₂ and the resonant inductor L _r , The second end of the DC blocking capacitor C ₁ and the resonant inductor L _r is connected in parallel with the magnetizing inductance L _m1 of the primary side of the transformer T ₁ , and the second end point of the DC blocking capacitor C ₂ and the resonant inductor L _r is ₂ magnetizing inductance of the primary side of the transformer T L _m2 in parallel, enabling the transformer T ₁ and the second end of the secondary side of the first end ₂ of the secondary side of the transformer T is connected, and _a secondary side of the transformer T, L ₁ is connected in parallel a first end of the first stage and the negative terminal of the output inductor rectifying diode D _1, the T ₂ pressure on the secondary side of the second end in parallel with a rectifying diode D ₂ L ₂ of the first stage and the negative terminal of the output inductor, enabling the output inductor L _1, L ₂ together with the second output terminal The first end of the capacitor C _O and the output load R are connected, and the anodes of the rectifying diodes D ₁ and D ₂ are connected to the output capacitor C _O and the second end of the output load R.