TWI499009B - 封裝有具有內嵌線及金屬界定襯墊之基板的裝置 - Google Patents

封裝有具有內嵌線及金屬界定襯墊之基板的裝置 Download PDF

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Publication number
TWI499009B
TWI499009B TW100145584A TW100145584A TWI499009B TW I499009 B TWI499009 B TW I499009B TW 100145584 A TW100145584 A TW 100145584A TW 100145584 A TW100145584 A TW 100145584A TW I499009 B TWI499009 B TW I499009B
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Taiwan
Prior art keywords
metal
package substrate
surface level
layer
level dielectric
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TW100145584A
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English (en)
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TW201246466A (en
Inventor
Mark S Hlad
Islam A Salama
Mihir K Roy
Tao Wu
Yueli Liu
Kyu Oh Lee
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Intel Corp
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Publication of TW201246466A publication Critical patent/TW201246466A/zh
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Publication of TWI499009B publication Critical patent/TWI499009B/zh

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Description

封裝有具有內嵌線及金屬界定襯墊之基板的裝置 領域
本發明的實施例係有關於半導體裝置且更特別有關於半導體裝置封裝技術。
 相關技藝的討論
諸如微處理器等積體電路(IC)裝置係時常封裝有一使用微球凸塊技術被安裝至一封裝體基板之晶片。該技藝的進展係不斷需要能夠以降低的凸塊間距具有增加的晶片輸入/輸出(I/O)之裝置封裝技術。習見用於微球技術的封裝體基板係典型地以半加成製程(SAP)製造，如第1圖所示。
如第1圖所示，SAP 100首先在基板101的一層中所形成之一金屬化襯墊102上方形成一介電增層104。一通孔孔109隨後被雷射鑽製於介電增層104中，且一金屬種晶層115形成於基板上方。一暫時阻劑圖案120在金屬種晶層115上方被微影圖案化，且傳導軌跡及通孔125被電鍍於金屬種晶層115上。隨後移除暫時阻劑圖案120且蝕除金屬種晶層115。SAP 100繼續以此方式增建任何數量的金屬化層於一封裝體基板上，直到形成供一銲球附接的一第一(亦即頂)層級金屬為止。假設傳導軌跡及通孔125是表面層級金屬，一銲阻膜140隨後形成於傳導軌跡及通孔125上方。一銲阻膜140隨後被微影圖案化以在金屬化襯墊136上方形成一開口，且一表面修製145被施加至金屬化襯墊136的經曝露部分。然後 使用一微球技術將一銲球150放入銲阻罩幕開口內，隨後使銲球150被迴流。
在組裝時，一諸如形成為一晶片側C4製程的部份之銅柱等晶片連接點係隨後對準至經迴流的銲球150，且進行另一銲料迴流以將晶片接合至基板。一下填及/或包封製程隨後使用微球技術完成習見的製程。
基於需要較高I/O繞佈使凸塊間距縮小，封裝體基板線及間隔係依此降低，而對於現今SAP達成高良率構成顯著挑戰。降低的凸塊間距亦需使現今微球技術達成高的後端良率(由於凸塊橋接及損失銲球所致的極小損失)。為了以降低的凸塊間距達成這些高良率，銲球直徑應較低而導致較低的凸塊高度，其係為總成去銲劑製程的挑戰。
依據本發明之一實施例，係特地提出一種用於將IC晶片組裝至封裝體基板之方法，該方法包含下列步驟：使一經銲接IC晶片連接點對準一封裝體基板連接點，該封裝體基板連接點具有突伸超出配置於相鄰基板連接點間之一表面層級介電質之一頂表面的一曝露表面修製金屬，其中該表面修製金屬係配置於包含有內嵌在該表面層級介電質中之一充填金屬的一表面層級金屬特徵體上；以及使配置於該IC晶片連接點上的該銲料熔接，以將該晶片連接點固附至該封裝體基板連接點。
圖式簡單說明
第1圖是一習見半加成基板製造製程的橫剖視圖；第2A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程的流程圖；第2B圖是根據本發明的一實施例顯示第2A圖所述的封裝體基板製造製程中的階段之選定操作的橫剖視圖；第3A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程的流程圖；第3B圖是根據本發明的一實施例顯示第3A圖所述的封裝體基板製造製程中的階段之選定操作的橫剖視圖；第4A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程的流程圖；第4B圖是根據本發明的一實施例顯示第4A圖所述的封裝體基板製造製程中的階段之選定操作的橫剖視圖；第5圖是根據本發明的一實施例之一利用一具有降低的凸塊間距之基板的一組裝製程之流程圖；第6至7圖是根據本發明的一實施例顯示用於一具有降低的凸塊間距之基板之第5圖所述的封裝體組裝製程中的階段之選定操作的橫剖視圖。
 詳細描述
下列描述中，提出許多特定細節以供徹底瞭解本發明。熟習該技術者將瞭解：本發明可以無這些特定細節下被實行。在其他情形中，未詳細描述諸如特定製造技術等熟知的特徵構造以免不必要地模糊本發明。此說明書全文提到“一實施例”係指連同該實施例所描述的一特定特徵構造、結構、材料或特徵被包括在本發明的至少一實施例中。因此，在此說明書全文不同地方出現“一實施例中”用語則未必指涉本發明的同一實施例。尚且，特定的特徵構造、結構、材料、或特徵可在一或多個實施例中以任何適當方式被組合。並且，請瞭解圖式顯示的不同示範性實施例僅為示範性代表物且未必依比例繪製。
“耦合”及“連接”用語及其衍生物可在本文用來描述組件之間的結構性關係。應瞭解這些用語無意作為彼此的同義詞。而是，在特定實施例中，“連接”可用來表示兩或更多個元件彼此直接物理性或電性接觸。“耦合”可用來表示兩或更多個元件彼此直接或間接(之間具有其他中介元件)物理性或電性接觸，及/或兩或更多個元件彼此合作或交互作用(譬如，如同具有一因果關係)。
如本文所用的“上方”、“底下”、“之間”及“上”用語係指一材料層相對於其他材料層的相對位置。因此，譬如，配置於另一層上方或底下的一層係可直接接觸於另一層或者可具有一或多個中介層。並且，配置於兩層之間的一層係可直接接觸於兩層或者可具有一或多個中介層。反之，一第二層“上”的一第一層係接觸於該第二層。此外，一層相對於其他層的相對位置係假設相對於一基板進行操作而不考慮該基板的絕對定向。
本文係描述能夠以降低的凸塊間距在一封裝體中形成IC晶片-基板總成之製造積體電路(IC)晶片封裝體基板之方法。在特定實施例中，一封裝體基板係製成利於將一銲球放置在晶片側上涉及銲料直接接觸至基板上的一金屬界定襯墊而非由一銲阻所界定的襯墊之組裝。因此，在特定的此等實施例中，封裝體基板的表面上未存在銲阻，且在將一晶片耦合至封裝體基板之前，封裝體基板上未放置有銲料。用於一內嵌表面金屬特徵體之本文所描述的製造製程係可重覆多次以提供多重層上的繞佈。在表面層級金屬特徵體曝露於下填(譬如用以取代銲阻)之處可能存在的BHAST可靠度議題，係藉由將金屬特徵體內嵌在一表面層級介電膜中而被減輕。
第2A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程200的流程圖。第2B圖提供根據一示範性實施例顯示封裝體基板製造製程200中的階段之選定操作的橫剖視圖。
製程200開始係為操作201，其中將一介電層(譬如第2B圖的表面介電層110)層疊於一基板增層101中的一圖案化金屬層(譬如次表面層級金屬特徵體105)上方。一般而言，圖案化金屬層及該圖案化金屬層下方之任何數量的層係可以該技藝已知的任何方式形成。譬如，圖案化金屬層可能是以類似於第1圖所示的一SAP所形成之一頂增層。介電層可能是該技藝已知且以任何習見方式施加在圖案化次表面層級金屬層上方的任何組成物。在一特定實施例中，介電層110係包含一具有矽土填料以提供符合封裝體可靠度要求的適當機械性質之聚合物(以環氧樹脂為基礎的樹脂)。該材料必須亦具有適當燒蝕率以能夠作雷射圖案化，如本文他處所描述。
回到第2A圖，在操作209，通孔孔(譬如第2B圖的通孔孔210)被雷射鑽製於介電層(譬如表面介電層110)內以曝露下屬金屬層的一部分。可使用任何習見技術，諸如採用CO2 雷射的技術。在操作211，介電質隨後進一步被雷射圖案化以形成一軌跡凹部(譬如第2B圖的軌跡凹部212)及/或一襯墊凹部(未描繪)，其中在介電質中的深度係小於通孔的深度(亦即次表面層級金屬特徵體105未在操作211被圖案化所曝露)。如第2B圖所示，軌跡凹部212係與下屬次表面層級金屬特徵體105側向地分開。在第2B圖中雖未描繪，應瞭解一配置於通孔231上方的襯墊凹部(譬如類似於第4B圖描繪者)亦可由形成軌跡凹部212的製程被形成。為了形成軌跡凹部212及/或一襯墊凹部，可譬如以一受激準分子雷射進行雷射圖案化。
接著，在操作214，係沉積一種晶層(譬如第24圖的種晶層215)。在一實施例中，使用無電極鍍覆形成種晶層215。譬如，可沉積一諸如鈀(Pd)等催化劑，接著係為一無電極銅鍍覆製程。在一替代性實施例中，使用一物理氣相沉積(亦即濺鍍)技術以沉積種晶層215。
通孔孔、軌跡凹部、及/或襯墊凹部隨後在操作224譬如以一電解鍍覆製程被充填。如第2B圖所示，進行一電解銅鍍覆製程以沉積該充填金屬225。在操作226，隨後藉由蝕刻、擦光研磨、化學機械拋光等中的一或多者移除過度鍍覆的充填金屬，以使充填金屬225平面化。譬如，可使用化學機械拋光(CMP)或擦光研磨以首先平面化充填金屬225，然後可採用一蝕刻以從表面層級介電層的110頂表面移除任何留存的充填金屬225，藉此劃定一內嵌金屬化通孔231及一內嵌金屬化軌跡232。內嵌金屬化軌跡232可為一頸縮軌跡，其從晶粒及基板他處之間已產生的一連接攜載一信號且因此可能未直接結合至晶粒側上的銲料。如進一步顯示，次表面層級金屬特徵體105具有與表面層級介電層110相鄰的側壁，其中內嵌有金屬化通孔231及金屬化軌跡232。
對於其中種晶層被無電極鍍覆之實施例，操作227後留存的任何催化劑係可在步驟235被移除，以避免表面修製金屬後續鍍覆在表面層級介電層110上之危險。可依據充填金屬及所採用催化劑而定商業性購得不同化學溶液以移除催化劑。譬如，如第2B圖所示，Pd催化劑229可以商業購得的濕化學處理被移除，而不蝕刻銅充填金屬225。對於種晶層被濺鍍之實施例，可略過操作235。
在操作243，一表面修製金屬係形成於內嵌金屬特徵體的全部經曝露表面(譬如內嵌金屬化通孔231及內嵌金屬化軌跡232的頂表面)上，而形成超過表面層級介電層110的一頂表面之一突件。雖然表面修製具有與充填金屬225不同的一組成物，可採用多種不同的表面修製金屬組成物或鍍覆堆積體。在第2B圖描繪的示範性實施例中，使用一無電極鍍覆製程形成包含至少一層的鎳(Ni)之表面修製金屬245，且可進一步包括諸如鈀(Pd)、及/或金(Au)等額外的層。在一示範性實施例中，表面修製金屬245包括一6至8μm厚的鎳層。
在一實施例中，一諸如Pd等催化劑只形成於經曝露的銅充填金屬225上(譬如，由於表面修製製程中相較於種晶層沉積製程中之預處理及Pd活化步驟的差異，Pd催化劑將只留存在經曝露的Cu金屬上)。由於表面層級介電層110上不存在催化劑，表面修製金屬可以自我對準方式被鍍覆因此不需要充填金屬225的遮罩且因此不需額外的鋪覆物/尺寸誤差邊際值。由於表面修製金屬245只形成於通孔上，“頂墊”在本文稱為“金屬界定”而非光界定或銲阻界定。位於一連接點之一表面修製金屬的臨界尺寸(CD)、或最小側向寬度WSF 隨後將至少與下屬內嵌金屬化通孔231或內嵌金屬化軌跡232的最大直徑WV 一樣大，但只比WV 更大達到表面修製金屬245在鍍覆製程期間經歷側向擴張的程度。因為金屬軌跡232內嵌於表面層級介電層110的頂表面下方，表面修製金屬245未鍍覆於充填金屬的側壁上，而容許相鄰內嵌金屬化軌跡232之間的空間降低。在一其中WV 是近似60至65μm的實施例中，WSF 將位於從等於WV (對於異向性鍍覆)到小於WV 加上表面修製金屬245兩倍厚度(對於等向性鍍覆)的任何數值。在其中連接點具有近似90μm的間距(亦即凸塊間距)及63μm的襯墊大小之特定實施例中，內嵌金屬軌跡232具有近似9μm的最小間距(9μm的最小側向尺寸軌跡對於一最近相鄰金屬特徵體具有9μm的最小側向空間)，以提供比SAP所可能者更高的I/O繞佈密度。
進一步如第2A圖所示，製程200可重覆操作201、209、211、214、224、227及235以在複數個層級中內嵌金屬特徵體並能夠譬如以微帶及帶線繞佈具有多重I/O繞佈層。藉由多重層的內嵌金屬化軌跡232，在只可能對於一表面層級金屬層作I/O繞佈之處，係可能具有遠為更高的I/O密度。進行所欲的反覆數之後，以自我對準表面修製鍍覆操作243完成製程200。
第3A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程300的流程圖。第3B圖提供根據一示範性實施例顯示封裝基板製造製程300的階段之選定操作的橫剖視圖。
如第3A圖所示，在操作201，一介電層(譬如，第3B圖的表面層級介電層110)係以第2A圖所述的實質相同方式層疊在一圖案化金屬層(譬如次表面層級金屬特徵體105)上方。在操作209，通孔孔(譬如第3B圖的通孔孔210)被雷射鑽製至介電層(譬如表面層級介電層110)中，以曝露下屬金屬層的一部分(譬如次表面層級金屬特徵體105)。
在操作303，一永久性可光界定層(譬如第3B圖的305)係被層疊或塗覆。可利用適合諸如控制式崩潰晶片連接(C4)等應用的任何材料作為永久性可光界定層305。譬如，永久性可光界定層305可為一可光界定聚醯亞胺。在操作307，永久性可光界定層係利用任何習見微影技術被曝露及圖案化以形成圖案化凹部，諸如軌跡凹部212及襯墊凹部223，如第3B圖所示。在示範性實施例中，軌跡凹部212具有約5μm寬的CD，且襯墊凹部223具有約75μm寬的CD，其中內嵌金屬化通孔231具有約50至55μm的最大直徑WV 。
操作214、224、227及235隨後以本文他處對於製程200所描述的相同方式進行，但在操作227具有充填金屬225的平面化及/或回蝕，而曝露永久性可光界定層305的一頂表面且劃定一內嵌金屬化通孔231、一內嵌金屬化頂襯墊233、及一內嵌金屬化軌跡232。如圖所示，不像SAP技術，次表面層級金屬特徵體105具有與表面層級介電層110相鄰的側壁，其中內嵌有金屬化通孔231。並且，因為至少部分永久性可光界定層305被永久性扣留於封裝體基板中(若採用一不具有選擇性回蝕的CMP平面化方法，則部分的可光界定層可被移除)，用以在頂襯墊233側壁上形成種晶層215之任何催化劑(譬如Pd)將留置於頂襯墊233與表面層級介電層110之間的介面。依據曝露永久性可光界定層305的頂表面所採用製程而定，永久性可光界定層305頂表面上的催化劑229係可能需要或可能不需要在所鍍覆的表面修製前由一濕化學處理被移除。譬如，利用CMP以曝露永久性可光界定層305的頂表面亦可能適當地從頂表面移除任何催化劑。
進一步如第3A圖所示，製程300可重覆操作201、209、303、307、214、224、227及235以內嵌金屬特徵體於複數個層級中且能夠具有多重繞佈層，譬如藉由微帶及帶線繞佈。藉由多重層的內嵌金屬化軌跡232，可能具有遠為更高的I/O密度，其中I/O繞佈只在一表面層級金屬層中為可能。進行所欲的反覆數之後，以自我對齊表面修製金屬鍍覆操作243完成製程300。
從永久性可光界定層305頂表面移除用以形成種晶層215的任何催化劑之後，在操作243鍍覆表面修製金屬245。在一實施例中，鍍覆由於受到曝露的銅區域(在內嵌金屬化頂襯墊233、內嵌金屬化通孔231、或內嵌金屬化軌跡232處)所限制而係為自我對齊式。因為內嵌金屬化軌跡232的側壁未被曝露，表面修製金屬245的鍍覆係較具異向性而容許相鄰內嵌金屬化軌跡232與金屬化軌跡232所相鄰的內嵌金屬化頂襯墊233之間的最小空間對於1：1的線：空間間距譬如係為近似5μm(在具有75μm襯墊之90μm凸塊間距的實例中)，即使當表面修製金屬厚度大於相鄰內嵌金屬充填特徵體之間最小空間的至少一半(譬如大於相鄰內嵌金屬化軌跡232之間最小空間的一半)時亦然。永久性可光界定介電質305係能夠形成一配置於金屬化通孔231上方的頂襯墊233。在一示範性實施例中，頂襯墊233具有比通孔的最大直徑WV 更大之最大側向尺寸。
第4A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程400的流程圖。第4B圖提供顯示根據一示範性實施例之封裝體基板製造製程400中的階段之選定操作的橫剖視圖。
製程400開始係為操作201，將一介電層(譬如第4B圖的表面層級介電層110)層疊於一基板增層101中的一圖案化金屬層(譬如次表面層級金屬特徵體105)上方。如本文他處所描述，圖案化金屬層及圖案化金屬層下方之任何數量的層係可以該技藝已知的任何方式形成(譬如藉由一SAP技術)。介電層可能是該技藝已知且以任何習見方式施加在圖案化次表面層級金屬層上方的任何組成物。在一特定實施例中，介電層110係包含一具有矽土填料以提供符合封裝體可靠度要求的適當機械性質之聚合物(以環氧樹脂為基礎的樹脂)。該材料亦必須具有適當燒蝕率以能夠作雷射圖案化，如本文他處所描述。
回到第4A圖，在操作209，通孔孔(譬如第4B圖的通孔孔210)被雷射鑽製於介電層(譬如表面層級介電層110)內以曝露下屬金屬層的一部分。可使用任何習見技術，諸如採用CO2 雷射的技術。在操作211，介電質隨後進一步被圖案化以形成凹部。第4B圖顯示一軌跡凹部212及襯墊凹部233，各具有比通孔者更小之進入表面層級介電質內的深度(亦即次表面層級金屬特徵體105未在操作211被圖案化所曝露)。為了圖示簡明起見，第4B圖顯示一寬通孔實施例及一金屬化頂襯墊實施例，但請瞭解寬通孔及金屬化襯墊實施例不需在單一封裝體基板內混合，而是典型地在一給定基板中採用一者或另一者。如同在製程200，圖案化凹部可藉由雷射圖案化被形成。
接著，在操作214，係沉積一種晶層(譬如第2B圖的種晶層215)。如同在製程200中，可使用無電極鍍覆形成種晶層215。譬如，可沉積一諸如Pd等催化劑，接著係為一無電極銅鍍覆製程。在一替代性實施例中，使用一物理氣相沉積(亦即濺鍍)技術以沉積種晶層215。
通孔凹部、頂襯墊凹部、及軌跡凹部隨後在操作224譬如以一電解鍍覆製程被充填。如第4B圖所示，進行一電解銅鍍覆製程以沉積該充填金屬225。在操作226，隨後藉由蝕刻、擦光研磨、化學機械拋光等中的一或多者移除過度鍍覆的充填金屬，以使充填金屬225平面化。譬如，可使用CMP以首先平面化充填金屬225，然後可採用一蝕刻以在表面層級介電層110的頂表面上只留下一薄的金屬種晶層215以供一表面修製金屬的後續電解鍍覆。如顯示，次表面層級金屬特徵體105具有與表面層級介電層110相鄰的側壁，其中內嵌有金屬化通孔231、金屬化軌跡232及頂襯墊233。
如第4A圖進一步所示，製程400可重覆操作201、209、211、214、224、227以將金屬特徵體內嵌在複數個層級中並能夠譬如以微帶及帶線繞佈具有多重繞佈層。藉由多重層的內嵌金屬化軌跡232，比起只可能對於一表面層級金屬層作繞佈之處，係可能具有遠為更高的I/O密度。進行所欲的反覆數之後，以修製金屬鍍覆操作420完成製程400。
在操作420，一乾膜阻劑(DFR)係使用該技藝已知的任何技術被層疊及圖案化。在第4B圖所示的示範性實施例中，DFR 421被圖案化以曝露內嵌金屬化通孔231(及/或內嵌金屬化頂襯墊233)中的充填金屬225而不曝露內嵌金屬化軌跡232。考慮到對準變異，DFR 421中的開口可具有小側向尺寸以形成一比內嵌金屬充填特徵體(譬如WTP )具有更小側向尺寸WSF 之表面修製。
在操作445，一表面修製金屬係在曝露的通孔充填金屬上方鍍覆至比DFR者更小的厚度。表面修製金屬可能是本文他處所描述的任何者，且譬如可包括Ni、Pd、及Au的一堆積體或Ni與Au金屬層。如第4B圖所示，修製金屬425係鍍覆在未被DFR 421保護之留存的種晶層215區上。因為內嵌金屬化軌跡232被DFR 421所保護，並未形成表面修製金屬。相鄰金屬化軌跡232之間的最小空間因此係與金屬修製厚度獨立無關。
選用性地，在操作445中鍍覆表面修製金屬之前亦可鍍覆額外的充填金屬(譬如銅)。對於一具有近似50至55μm直徑的內嵌金屬化通孔231，可開啟一較大的頂襯墊開口(譬如75μm)，且一額外的充填金屬及/或表面修製隨後係在超過內嵌金屬化通孔231所出現的種晶層215上方鍍覆至比DFR 421者更小的厚度。對於此實施例，充填金屬係形成一具有不含表面修製金屬245的側壁之從表面層級介電層110頂表面突伸的拓樸特徵體(亦即一頂襯墊)。因此，一頂襯墊可內嵌於表面層級介電層110中(譬如如第4B圖所示藉由內嵌頂襯墊233)或配置於表面層級介電層110的一頂表面上方。
在操作422，使用任何習見的剝除製程移除DFR，且選擇性蝕刻薄種晶層215以曝露內嵌金屬化通孔231、內嵌金屬化軌跡232、及頂襯墊233之間的表面層級介電層110。
第5圖是根據本發明的一實施例之利用一具有降低的凸塊間距之封裝體基板的組裝製程500之流程圖。
組裝製程500首先係為操作501，其係接收一在預定的基板連接點具有曝露的表面修製之封裝體基板。因此，在示範性實施例中，封裝體基板的表面上未出現銲阻，且在一晶片耦合至封裝基板之前，表面修製上未放置有銲料。製程200、300或400中製作的任何封裝體基板皆可使用在組裝製程500中。第6至7圖是根據本發明的另一示範性實施例顯示封裝體組裝製程500中的階段之選定操作的橫剖視圖。如第6至7圖所示，基板連接點可為一表面修製襯墊233抑或內嵌金屬化通孔231。
在操作502，接收一IC晶片，其中銲料凸塊配置於晶片連接點上。雖然IC晶片可概括屬於任何習見的類型，在一特定實施例中，IC晶片係為一具有大I/O數目的微處理器。在一實施例中，晶片I/O及電力銲料凸塊可具有小於100μm(譬如90μm)的間距。如第6圖所示，IC晶片502係包括一表面層級晶片側金屬特徵體503上的銲料凸塊504。IC晶片502隨後對準於表面修製基板以使經銲接的IC晶片連接點對準於經表面修製的基板連接點。晶片側銲料隨後係在操作520被熔接以將晶片固附至基板連接點。如第7圖所示，封裝體基板在基板連接點具有曝露的表面修製金屬245而形成一突伸超過配置於相鄰連接點之間的表面層級介電層110的一頂表面之拓樸特徵體。在特定實施例中，如本文他處所描述，表面修製金屬245具有等於相鄰金屬軌跡232之間的一最小側向空間的至少一半之厚度。
如第7圖所示，晶片銲料凸塊504當熔接時可包繞在從表面層級介電層110突伸的表面修製物周圍以接觸表面修製金屬245的一側壁。如第7圖所示，晶片銲料凸塊504可直 接地耦合至內嵌金屬化通孔231的表面修製(亦即，不具有比內嵌金屬化通孔231更大尺寸的頂襯墊)，或替代性地，晶片銲料凸塊504可直接地耦合至內嵌金屬化233的表面修製。
藉由晶片固附至封裝體基板，可施加任何習見的下填650以充填IC晶片502與封裝體基板101之間的間隙。由於並無銲阻被施加至封裝體基板，下填650係接觸表面層級介電層110的頂表面。對於第7B圖所示的實施例，下填650亦接觸其中未施加表面修製之內嵌金屬軌跡232。隨後利用習見技術完成封裝製程。
本發明的示範性實施例的上文描述、包括發明摘要的描述並無意窮舉本發明或將本發明限制成所揭露的確切形式。雖然本文為示範而描述特定的實行方式及範例，如熟習該技術者所瞭解，可在本發明的範圍內作出不同的均等性修改。本發明的範圍係完全由根據申請專利範圍詮釋的既立原則作解釋之下列申請專利範圍所界定。
100．．．半加成製程(SAP)
101．．．基板
102,136．．．金屬化襯墊
104．．．介電增層
105．．．次表面層級金屬特徵體
109,210．．．通孔孔
110．．．表面介電層
115．．．金屬種晶層
120．．．暫時阻劑圖案
125．．．傳導軌跡及通孔
140．．．銲阻膜
145．．．表面修製
150．．．銲球
200,300,400．．．封裝體基板製造製程
201,209,211,214,224,226,227,235,243,303,307,420,422,430,445,501,502,510,520,530．．．操作
212．．．軌跡凹部
215．．．種晶層
225．．．充填金屬
229．．．Pd催化劑
231．．．內嵌金屬化通孔
232．．．內嵌金屬化軌跡
233．．．頂襯墊
245．．．表面修製金屬
305．．．永久性可光界定層
421．．．DFR
425．．．修製金屬
500．．．封裝體基板的組裝製程
502．．．IC晶片
503．．．表面層級晶片側金屬特徵體
504．．．晶片銲料凸塊
650．．．下填
CD．．．表面修製金屬的臨界尺寸
WSF ．．．表面修製側向尺寸
WTP ．．．內嵌金屬充填特徵體側向尺寸
WV ．．．內嵌金屬化通孔231或內嵌金屬化軌跡232的最大直徑
第1圖是一習見半加成基板製造製程的橫剖視圖；第2A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程的流程圖；第2B圖是根據本發明的一實施例顯示第2A圖所述的封裝體基板製造製程中的階段之選定操作的橫剖視圖；第3A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程的流程圖；第3B圖是根據本發明的一實施例顯示第3A圖所述的封裝體基板製造製程中的階段之選定操作的橫剖視圖；第4A圖是根據本發明的一實施例之一用於降低的凸塊間距之封裝體基板製造製程的流程圖；第4B圖是根據本發明的一實施例顯示第4A圖所述的封裝體基板製造製程中的階段之選定操作的橫剖視圖；第5圖是根據本發明的一實施例之一利用一具有降低的凸塊間距之基板的一組裝製程之流程圖；第6至7圖是根據本發明的一實施例顯示用於一具有降低的凸塊間距之基板之第5圖所述的封裝體組裝製程中的階段之選定操作的橫剖視圖。
101．．．基板
105．．．次表面層級金屬特徵體
110．．．表面介電層
210．．．通孔孔
212．．．軌跡凹部
215．．．種晶層
225．．．充填金屬
229．．．Pd催化劑
231．．．內嵌金屬化通孔
232．．．內嵌金屬化軌跡
245．．．表面修製金屬
WSF ．．．表面修製側向尺寸
WV ．．．內嵌金屬化通孔231或內嵌金屬化軌跡232的最大直徑

Claims (18)

  1. 一種用於將IC晶片組裝至封裝體基板的方法，該方法包含下列步驟：使帶有焊料的一IC晶片連接點對準一封裝體基板連接點，該封裝體基板連接點具有突伸超出一表面層級介電質之一頂表面的一曝露表面修製金屬，該表面層級介電質係配置在相鄰基板連接點之間，其中，該表面修製金屬係配置於包含有內嵌在該表面層級介電質中之一充填金屬的一表面層級金屬特徵體上；以及熔接配置於該IC晶片連接點上的該銲料，以使該晶片連接點固附至該封裝體基板連接點，其中，該充填金屬具有與該表面修製金屬不同的成分，並且該表面修製金屬具有等於內嵌在該表面層級介電質中之相鄰金屬特徵體間之一最小側向空間之至少一半的厚度。
  2. 如申請專利範圍第1項之方法，其進一步包含下列步驟：下填在該IC晶片與該封裝體基板之間的一間隙，以藉由下填物接觸該表面層級介電質之該頂表面。
  3. 一種用於形成一積體電路(IC)封裝體基板的方法，該方法包含下列步驟：於一第一金屬特徵體上方層疊一第一介電層；在該介電層中雷射鑽製一通孔以曝露出該第一金屬特徵體；於該第一介電層上方層疊一永久性可光界定層； 在該永久性可光界定層中形成一襯墊凹部之圖案，該襯墊凹部係配置於該通孔上方；將一充填金屬電解鍍覆至該通孔及該襯墊凹部中，此步驟包含：在該永久性可光界定層上沉積一催化劑；及在該催化劑上無電極鍍覆一種晶層；將該充填金屬平面化成與該永久性可光界定層之一頂表面齊平；以一濕化學處理，自於該充填金屬受到平面化時曝露出的該永久性可光界定層移除該催化劑；以及在該充填金屬之一頂表面上方進行對於一表面修製金屬的自我對齊鍍覆。
  4. 如申請專利範圍第3項之方法，其中，將一表面修製金屬鍍覆於該充填金屬上方之步驟進一步包含：在該充填金屬之一曝露表面上形成催化劑，以及鍍覆一或多個金屬層。
  5. 一種積體電路(IC)封裝體基板，其包含：內嵌於一表面層級介電層中的一第一表面層級金屬特徵體，其中一充填金屬之一頂表面係與該表面層級介電層之一頂表面齊平；配置於該第一表面層級金屬特徵體之一頂表面上方的一表面修製金屬，該表面修製金屬突伸超出該表面層級介電層之該頂表面且具有與該充填金屬不同的成分；以及 一次表面層級金屬特徵體，其具有與表面層級介電材料相鄰的側壁。
  6. 如申請專利範圍第5項之IC封裝體基板，其中，該表面修製金屬具有等於在內嵌於該表面層級介電層中的一第一表面層級金屬軌跡與一第二表面層級金屬軌跡之間的一最小側向空間之至少一半的厚度。
  7. 如申請專利範圍第6項之IC封裝體基板，其中，該等第一和第二表面層級金屬軌跡有一部分不具有任何表面修製金屬。
  8. 如申請專利範圍第5項之IC封裝體基板，其中，該第一表面層級金屬特徵體具有為9μm以下的最小側向尺寸，且在該等第一和第二表面層級金屬軌跡之間的一最小側向空間不大於9μm。
  9. 如申請專利範圍第5項之IC封裝體基板，其中，該第一表面層級金屬特徵體形成從該表面層級介電層之該頂表面突伸的一拓樸特徵體，並且其中，該表面修製金屬並非配置於突伸之該第一表面層級金屬特徵體之一側壁上。
  10. 如申請專利範圍第5項之IC封裝體基板，其中，該第一表面層級金屬特徵體包括配置於該通孔上方的一襯墊，該襯墊所具有的最大側向尺寸大於該通孔之最大直徑。
  11. 如申請專利範圍第5項之IC封裝體基板，其中，該第一表面層級金屬特徵體包含銅(Cu)，該表面修製金屬包含 鎳，且該第一介電質包含具有矽土填料的以環氧樹脂為基礎之樹脂。
  12. 一種封裝體總成，其包含：一積體電路(IC)晶片，其具有輸入/輸出(I/O)及電力連接點；以及一封裝體基板，其包含：一第一表面層級金屬特徵體，其包含內嵌於一表面層級介電層中的一充填金屬；及配置於該充填金屬之一頂表面上方的一表面修製金屬，該表面修製金屬突伸超出該表面層級介電層之一頂表面，其中，該表面修製金屬具有與該充填金屬不同的成分，並且其中，該表面修製金屬係藉由銲料而被固附至該等連接點中之一第一者，其中，該IC晶片為一微處理器，其中，該充填金屬包含銅，且該表面修製金屬包含鎳，並且其中，鈀(Pd)存在於該第一表面層級金屬特徵體之一側壁與該表面層級介電層之間的一介面。
  13. 如申請專利範圍第12項之封裝體總成，其中，該銲料包繞該表面修製金屬周圍，以接觸該表面修製金屬之一側壁。
  14. 一種用於將積體電路(IC)晶片組裝至封裝體基板的方法，該方法包含下列步驟： 提供一IC晶片，該IC晶片具有多個IC晶片連接點，在該等IC晶片連接點上各配置有焊料；提供一封裝體基板，該封裝體基板具有多個封裝體基板連接點，該等封裝體基板連接點各具有包含內嵌在一表面層級介電質內的一充填金屬的一表面層級金屬特徵體，該表面層級介電質係配置在相鄰封裝體基板連接點之間，該等封裝體基板連接點各具有形成於該充填金屬上且突伸超出該表面層級介電質之一頂表面的一表面修製金屬，該封裝體基板進一步包含一金屬軌跡，該金屬軌跡係於該等封裝體基板連接點中之二者之間處內嵌於該表面層級介電質內；使該等IC晶片連接點對準該等封裝體基板連接點；以及使配置於該等IC晶片連接點上的該銲料與該等封裝體基板連接點上的該表面修製金屬熔接，以使該等晶片連接點固附至該等封裝體基板連接點。
  15. 如申請專利範圍第14項之方法，其進一步包含下列步驟：下填在該IC晶片與該封裝體基板之間的一間隙，以藉由下填物接觸該表面層級介電質之該頂表面。
  16. 如申請專利範圍第14項之方法，其中，該充填金屬具有與該表面修製金屬不同的成分，且該表面修製金屬具有等於在內嵌於該表面層級介電質中之相鄰金屬特徵體之間的一最小側向空間之至少一半的厚度。
  17. 如申請專利範圍第14項之方法，其中，內嵌的該金屬軌跡具有實質上與該表面層級介電質之該頂表面共平面的一曝露頂表面。
  18. 如申請專利範圍第14項之方法，其進一步包含形成於該金屬軌跡上的一表面金屬修製物，該表面金屬修製物突伸超出該表面層級介電質之該頂表面。
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