TWI494730B - Circuit for generating boosted voltage and method for operating the same - Google Patents

Description

Circuit for generating boost voltage and operation method thereof

The following description relates to a circuit for generating a boost voltage higher than an input voltage, and a method for operating the boost voltage generating circuit.

The present application claims the rights of the Korean Patent Application No. 10-2009-0126071, filed on Dec. 17, 2009, and the Korean Patent Application No. 10-2010-003563, filed on Apr. 19, 2010. The entire disclosure of each of the examples is hereby incorporated by reference in its entirety for all purposes.

Different semiconductor devices operate internal circuits by voltages supplied from the outside. Since voltages of different levels are used in the internal constituent elements of the semiconductor device, it is difficult to supply all voltages to be used inside the semiconductor device from outside the device. Therefore, the semiconductor device is equipped with an internal voltage generating circuit to generate voltages of different levels inside the device.

In particular, when the level of the power supply voltage supplied from the battery is low and the level of the driving voltage to be used inside the device is higher than the level of the input power supply voltage, the device using the battery power supply should be able to generate a higher level. The voltage at the level of the input supply voltage from the external input. A voltage DC-DC converter that generates a level higher than the input voltage is classified into a switched mode power supply (SMPS) type using an inductor and a charge pump type using a capacitor. In the case of mobile devices, mobile devices typically have a charge pump type because current consumption is not large.

Unlike linear power supplies, the SMPS's pass transistor switches very fast (typically between 50 kHz and 1 MHz) between the all-on state and the fully-off state, which minimizes wasted energy. Chemical. Voltage regulation is provided by varying the ratio of on time to off time. In contrast, a linear power supply must dissipate excess voltage to regulate the output. This higher efficiency is the main advantage of SMPS. When a higher efficiency, smaller size, and/or lighter weight is required, a switching regulator is used to replace the linear regulator.

1 is a block diagram showing the voltage, signal, and output voltage of a boost voltage generating circuit.

The input voltage VCIN and the supercharging rate BT[a:0] are input to the boost voltage generating circuit 100. The boost voltage generating circuit 100 boosts the input voltage VCIN based on the boost rate indicated by the boost rate BT[a:0], and generates the boost voltage VOUT. For example, when the boost rate BT[a:0] is 2 (which means double or double), the boost voltage generating circuit 100 boosts the input voltage VCIN by two times (ie, doubles the voltage) And generate a boost voltage VOUT.

Although the target value of the boost voltage VOUT is the same, there may be different input voltages VCIN and boost rates BT[a:0] in the boost voltage generating circuit 100. For example, when the target value of the boost voltage VOUT is 3 V, the boost voltage VOUT of (a) 3 V can be generated by boosting (ie, doubling) the input voltage VCIN of 1.5 V. Or (b) 3 V boost voltage VOUT can be generated by boosting the input voltage VCIN of 1 V by three times (ie, by three times). However, although the same boost voltage VOUT is generated, the amount of current consumed by the boost voltage generating circuit 100 may be greatly different based on how the input voltage VCIN and the boost rate BT[a:0] are set.

However, the conventional power supply does not optimize the input voltage VCIN and the boost rate BT[a:0] input to the boost voltage generating circuit 100 in accordance with the target level of the boost voltage VOUT.

In a general aspect, a boost voltage generating circuit is provided, comprising: a boosting circuit configured to: boost an input voltage based on a boost rate, and output a boost voltage; a pressure rate setting unit configured to: receive one of a feedback level of one of the input voltages, and set the boost rate; and an input voltage level setting unit configured to respond to the following The level of the input voltage is set: a target level of the boost voltage and the boost rate.

In the boost voltage generating circuit, the input voltage level setting unit may be further configured to set a target level of the input voltage according to one of the following values: (the target level of the boost voltage / the Supercharge rate).

In the boost voltage generating circuit, the boost rate setting unit may be further configured to increase the boost rate in response to the target level of the input voltage exceeding a level of the input voltage.

In the boost voltage generating circuit, the boost rate setting unit may be further configured to respond to the target level of the input voltage falling within the level range of the input voltage when the boost rate is decreased The boost rate is small.

In the boost voltage generating circuit, the input voltage level setting unit may include: an output voltage divider configured to: divide the boost voltage by a ratio based on the boost rate determination, and Outputting a divided voltage; an input reference voltage selector configured to select an input reference voltage based on the boost rate and a plurality of voltages generated based on the target level of the boost voltage; a comparator configured to: compare an output voltage of the output voltage divider with an output voltage of the input reference voltage selector, and generate a preliminary input voltage; and an amplifier configured to: amplify The preliminary input voltage and the generation of the input voltage.

In the boost voltage generating circuit, the amplifier includes: a comparator configured as a linear regulator; and a plurality of resistors.

In the boost voltage generating circuit, the output voltage divider can be further configured to divide the boost voltage by a ratio of: 1/(the boost rate * one of the amplifiers) .

In the boost voltage generating circuit, the input reference voltage selector may be further configured to input a reference voltage for one of the target levels according to the following formula: the boost voltage / (the boost rate * the amplifier a magnification).

In the boost voltage generating circuit, the input voltage level setting unit further includes a voltage clamp configured to prevent the preliminary input voltage from excessively increasing or decreasing.

In the boost voltage generating circuit, the voltage clamp can include an analog multiplexer configured to select a clamp voltage among the input voltages in response to the boost rate.

In the boost voltage generating circuit, the input voltage level setting unit may further include a compensation circuit configured to stabilize the level of the preliminary input voltage.

In the boost voltage generating circuit, the compensation circuit includes: a resistor; and a capacitor.

In the boost voltage generating circuit, the boost rate setting unit may include: a voltage divider configured to generate: a boost rate increment reference voltage, and a boost rate decrement reference voltage; a flag a signal generator configured to: responsive to the initial input voltage being higher than the boost rate increment reference voltage to enable a boost rate increment flag signal, and responsive to the preliminary input voltage being lower than the boost rate decrement a boost rate decrement flag signal is enabled with reference to the voltage; and a boost rate controller configured to set the boost rate increase flag signal and/or the boost rate down flag signal in response to the boost rate flag signal Supercharging rate.

In the boost voltage generating circuit, the boost rate setting unit may further include an initial value determiner configured to provide the boost rate controller with information regarding an initial value of the boost rate.

In the boost voltage generating circuit, the initial value determiner can include a plurality of comparators configured to compare the respective input reference voltage values with an initial reference voltage.

In the boost voltage generating circuit, the boost rate controller may be further configured to: increase the boost rate in response to the boost rate increment flag signal being enabled for longer than a reference time, and in response to The boost rate decrement flag signal is reduced by the enablement duration for longer than a reference time.

In the boost voltage generating circuit, the boost rate controller may include: a plurality of counters, a plurality of comparators, a plurality of flip-flops, an initial value decoder, and a preset up/down counter.

In the boost voltage generating circuit, the preset up/down counter may be configured to set an initial boost rate signal input to the preset up/down counter to the boost rate An initial value; in response to the boost rate increment flag signal being a logic high, one of the plurality of counters can be configured to count a clock to increase an up count value; and in response to the The increased up count value converges to the boost rate increment reference voltage, and the preset up/down counter can be further configured to enable one of the boost rates to increase.

In the boost voltage generating circuit, the preset up/down counter may be configured to set an initial boost rate signal input to the preset up/down counter to the boost rate An initial value; in response to the boost rate decrement flag signal being a logic high, one of the plurality of counters is configurable to count a clock to increase a countdown value; and responsive to the The increased incremental count value converges to the boost rate decrementing reference voltage, and the pre-settable up/down counter can be further configured to enable one of the boost rate reductions.

In the boost voltage generating circuit, the preset up/down counter may be configured to set an initial boost rate signal input to the preset up/down counter to the boost rate An initial value; and in response to the boost rate decrement flag signal being logic high, one of the plurality of counters can be configured to count a clock to increase a decrement count value, the boost The rate decrement flag signal transitions to a logic low when the down count value is increased such that the down count value does not increase further such that the preset up/down counter does not enable one of the boost rate changes.

In the boost voltage generating circuit, one of the boost rate increment reference voltage levels can be determined according to the following equation: a power supply voltage / (one of the amplifier amplification factors), and the boost rate is decremented by one of the reference voltages The level can be determined according to the following equation: the power supply voltage * (the boost rate - a unit of pressure change rate) / (the amplification factor of the amplifier * the boost rate).

In another general aspect, a method for operating a boost voltage generating circuit for generating a boosted voltage by boosting an input voltage based on a boost rate is provided. The method includes: generating the input voltage whose target is one of the following: (one target voltage of the boost voltage / a boost rate); and the target level in response to the input voltage exceeds a level of the input voltage And increasing the boost rate; and decreasing the boost rate in response to the target level of the input voltage falling within the level range of the input voltage when the boost rate is decreased.

In the method, the input voltage may not have a level higher than a power supply voltage.

In the method, the decrease in the boost rate may be performed in response to the target level of the input voltage being lower than one of: (the boost rate - a unit of pressure change rate) / Supercharging rate.

In another general aspect, a method of generating a boost voltage is provided, the method comprising: boosting an input voltage based on a boost rate; outputting a boost voltage; receiving a level with respect to the input voltage a feedback; setting the boost rate; and setting the level of the input voltage in response to: a target level of the boost voltage and the boost rate.

The method can further include setting a target level of the input voltage based on one of: (the target level of the boost voltage / the boost rate).

The method can further include increasing the boost rate in response to the target level of the input voltage exceeding a level of the input voltage.

The method can further include reducing the boost rate in response to the target level of the input voltage being within the level of the input voltage as the boost rate decreases.

The method may further include: dividing the boosted voltage by a ratio based on the boost rate determination; outputting the divided voltage; generating the target level based on the boosted voltage based on the boosting rate Selecting an input reference voltage among the plurality of voltages; comparing an output voltage with an input reference voltage; generating a preliminary input voltage; amplifying the preliminary input voltage; and generating the input voltage.

The method may further comprise dividing the boost voltage by one of: 1/(the boost rate * a magnification).

The method can further include selecting an input reference voltage for the target level according to the following equation: the boost voltage / (the boost rate * a magnification).

The method can further include preventing the preliminary input voltage from excessively increasing or decreasing.

The method can further include selecting a clamp voltage in the input voltage in response to the boost rate.

The method can further include stabilizing the level of the preliminary input voltage.

The method may further include: generating: a boost rate increment reference voltage, and a boost rate decrementing reference voltage; and in response to the preliminary input voltage being higher than the boost rate increment reference voltage, enabling a boost rate increment flag signal Transmitting a boost rate decrement flag signal in response to the preliminary input voltage being lower than the boost rate decrementing reference voltage; and responding to the boost rate increment flag signal and/or the boost rate down flag signal Set the boost rate.

The method can further include providing information regarding an initial value of the boost rate.

The method can further include comparing the respective input reference voltage values to an initial reference voltage.

The method may further include: increasing the boost rate in response to the boost rate increment flag signal being enabled for longer than a reference time, and in response to the boost rate down flag signal being enabled for longer than a reference time Reduce the boost rate.

In the method, the boost level increment reference voltage level can be determined according to the following formula: a power supply voltage / (one of the amplifier amplification); and the boost rate decrementing one of the reference voltage levels according to the following formula To determine: the power supply voltage * (the boost rate - a unit of pressure change rate) / (the amplification rate of the amplifier * the boost rate).

Other features and aspects can be apparent from the following [embodiments], drawings, and claims.

The following [embodiments] are provided to assist the reader in obtaining a comprehensive understanding of the methods, devices, and/or systems described herein. Accordingly, various changes, modifications, and equivalents of the systems, devices and/or methods described herein will be suggested to those skilled in the art. The described processing steps and/or the progress of the operations are an example; however, the order of steps and/or operations is not limited to the order set forth herein, and unless the steps and/or operations that occur in a particular order are necessary, The order of steps and/or operations can be varied as known in the art. Also, descriptions of well-known functions and constructions may be omitted for the purpose of enhancing clarity and conciseness.

2 is a block diagram illustrating a boost voltage generating circuit in accordance with an embodiment.

Referring to FIG. 2, the boost voltage generating circuit includes a boosting circuit 200, a boost rate setting unit 210, and an input voltage level setting unit 220.

The boost circuit 200 can boost an input voltage VCIN based on a boost rate BT[a:0] and can output a boost voltage VOUT of a series of output voltages. Therefore, the boost voltage VOUT can be the product of the input voltage VCIN multiplied by the boost rate BT[a:0]. For example, when the boost rate BT[a:0] is "2" and the input voltage VCIN is 1 V, the boost voltage VOUT can be changed to 2 V. When the boost rate BT[a:0] is "3" and the input voltage VCIN is 0.8 V, the boost voltage VOUT can be changed to 2.4 V.

The input voltage level setting unit 220 can set the level of the input voltage VCIN in response to the target level of the boost voltage VOUT and the boost rate BT[a:0]. For example, the input voltage level setting unit 220 can be configured to divide the target level of the boost voltage VOUT by the boost rate BT[a:0] (eg, the target level/boost rate of the boost voltage VOUT). The value obtained by BT[a:0]) is used as the target level of the input voltage VCIN. Although the target level of the input voltage VCIN may be the target level of the boost voltage VOUT divided by the boost rate BT[a:0], the level of the input voltage VCIN may be lower than the target of the boost voltage VOUT. The value obtained by dividing the supercharge rate BT[a:0] (for example, the target level/boost rate BT[a:0] of the boost voltage VOUT). Since the target level of the input voltage VCIN may exceed the level of the power supply voltage VDD, the input voltage VCIN may not be higher than the power supply voltage VDD.

[Equation 1]

VCIN = target level/boost rate of boost voltage VOUT BT[a:0]

The boost rate setting unit 210 can receive feedback on the level of the input voltage VCIN, and can set the boost rate BT[a:0]. The boost rate setting unit 210 may increase the boost rate BT[a:0] in response to the target level of the input voltage VCIN being at a level that the input voltage VCIN cannot have. The target level of the input voltage VCIN can be determined by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (the target level of the boost voltage VOUT/boost rate BT[a:0] ]) The value obtained. In response to a value obtained by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (eg, the target level/boost rate BT[a:0] of the boost voltage VOUT) Above the supply voltage VDD, the input voltage VCIN cannot converge to its target level. In this case, the boost rate setting unit 210 can increase the boost rate BT[a:0]. The boost rate BT[a:0] can be increased only when it is necessary to increase the supercharging rate BT[a:0]. Since the target level of the input voltage VCIN is obtained by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (for example, the target level of the boost voltage VOUT/boost rate BT[a: 0]) The value obtained, so in response to the increased boost rate BT[a:0], the target level of the input voltage VCIN can also be reduced.

Although the boost rate BT[a:0] can be reduced by one step, the boost rate setting unit 210 can decrease the boost rate BT in response to the target level of the input voltage VCIN being at a level that the input voltage VCIN can have. [a:0]. Since the target level of the input voltage VCIN is obtained by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (for example, the target level of the boost voltage VOUT/boost rate BT[a: 0]) The obtained value, therefore in response to the reduced boost rate BT[a:0], the target level of the input voltage VCIN can be increased. If the boost rate BT[a:0] is decreased and the target level of the input voltage VCIN is increased, and the increased target level of the input voltage VCIN becomes higher than the power supply voltage VDD, the boost can be increased again. Rate BT[a:0].

The supercharging rate setting unit 210 can perform all of the above operations. In other words, the boost rate setting unit 210 may increase the boost rate BT[a:0] only when it is required to increase the boost rate BT[a:0], and the boost rate setting unit 210 may attempt to perform the increase The pressure rate BT[a:0] reduces an operation as much as the allowable amount.

The boost operation is an operation for generating a voltage having a level higher than the level of the input voltage. The higher the boost rate becomes, the more current may be consumed. Therefore, in response to generating a voltage having the same level, the amount of current consumed by the boosting operation can be reduced by reducing the boost rate. For example, generating a 3 V voltage by boosting 2 V by 1.5 times consumes less current than generating a 3 V voltage by three times the 1 V boost. According to an embodiment, since the boost rate BT[a:0] is set to a minimum value by the operation of the boost rate setting unit 210 and the input voltage level setting unit 220, the current consumption of the boost voltage generating circuit can be minimized. Chemical.

FIG. 3 is a detailed block diagram illustrating the boost voltage generating circuit of FIG. 2. FIG.

Referring to FIG. 3, the boost rate setting unit 210 may include a voltage divider 311, a flag signal generator 312, a boost rate controller 313, and an initial value determiner 314. The input voltage level setting unit 220 can include an output voltage divider 321 , an input reference voltage selector 322 , a comparator 323 , an amplifier 324 , a lower clamp voltage selector 325 , a voltage clamp 326 , and a compensation Circuit 327.

The voltage divider 311 can generate a boost rate increment reference voltage BTUP_REF and a boost rate decrease reference voltage BTDN_REF. In response to the initial input voltage VCIN_F being higher than the boost rate increment reference voltage BTUP_REF, the flag signal generator 312 can enable the boost rate increment flag signal BTUP_FG. In response to the preliminary input voltage VCIN_F being lower than the boost rate decrement reference voltage BTDN_REF, the flag signal generator 312 can enable the boost rate decrement flag signal BTDN_FG. The boost rate controller 313 can set the boost rate BT[a:0] in response to the boost rate increase flag signal BTUP_FG and the boost rate down flag signal BTDN_FG. The initial value determiner 314 can provide the boost rate controller 313 with a signal BT_INI[m:0] regarding the initial value of the boost rate BT[a:0].

The output voltage divider 321 divides the boost voltage VOUT by a ratio determined based on the boost rate BT[a:0], and may output at least one divided voltage. The input reference voltage selector 322 may select an input reference voltage VC_REF0 among the plurality of voltages VR_REF[m:0] based on the boost rate BT[a:0], and the plurality of voltages VR_REF[m:0] may be based on the boost voltage The target level of VOUT is generated. The comparator 323 can compare the output voltage VOUT_F of the output voltage divider 321 with the output voltage VC_REF0 of the input reference voltage selector 322, and can generate a preliminary input voltage VCIN_F. Amplifier 324 can amplify preliminary input voltage VCIN_F and can generate input voltage VCIN. The lower clamp voltage selector 325 can select the lower clamp voltage VCMP_DN0 and can output a selected clamp voltage. The voltage clamp 326 can control the preliminary input voltage VCIN_F to be not higher than the upper clamp voltage VCMP_UP0 and not lower than the lower clamp voltage VCMP_DN0 such that the preliminary input voltage VCIN_F does not become too high or too low. The compensation circuit 327 can help stabilize the level of the preliminary input voltage VCIN_F. The structure and operation of the constituent elements will be described in detail with reference to the accompanying drawings.

FIG. 4 is a schematic diagram illustrating a voltage divider 311 in accordance with an embodiment.

Referring to FIG. 4, the voltage divider 311 can include a plurality of resistors coupled to the supply voltage VDD and ground, and an analog multiplexer (MUX) 401. In the following examples (A) to (D), the boost rate increment reference voltage BTUP_REF generated by the voltage divider 311, the boost rate decrement reference voltage BTDN_REF, the upper clamp voltage VCMP_UP0, and an initial reference voltage BTINI_REF are described in detail.

(A) The boost rate increment reference voltage BTUP_REF is a reference voltage for increasing the boost rate BT[a:0]. The boost rate increment reference voltage BTUP_REF and the preliminary input voltage VCIN_F can be compared. The comparison result can be used to determine whether to increase the supercharging rate BT[a:0]. The preliminary input voltage VCIN_F is a voltage that can have, for example, one-half of the level of the input voltage VCIN. In response to the same input voltage VCIN as the power supply voltage VDD, the input voltage VCIN cannot become higher regardless of how high the initial input voltage VCIN_F becomes. In short, when the preliminary input voltage VCIN_F has a level of the power supply voltage VDD/2, even if the level of the preliminary input voltage VCIN_F is raised to be higher, the boosted voltage VOUT cannot be further increased. Therefore, the voltage at this point can be the level of the boost rate increment reference voltage BTUP_REF. The level of the boost rate increment reference voltage BTUP_REF can be set to the power supply voltage VDD/2 because the boost rate of the amplifier 324 can be 2. Therefore, in order to express the boost rate increment reference voltage BTUP_REF in a general equation, the level of the boost rate increment reference voltage BTUP_REF may be changed to the power supply voltage VDD/the boost rate of the amplifier 324.

[Equation 2]

BTUP_REF=VDD/amplifier boost rate

(B) The boost rate decrement reference voltage BTDN_REF is a reference voltage for reducing the boost rate BT[a:0]. The boost rate decrementing reference voltage BTDN_REF and the preliminary input voltage VCIN_F can be compared. The result of the comparison decision can be used to determine whether to reduce the boost rate BT[a:0]. In this context, m' denotes the boost step size and m starts from step 0. Also, n' represents a supercharging rate between 0.5 and 1.5. In other words, the initial value of m is "0" and 0.5 n' 1.5.

Table 1 below shows the supercharging step m' and the supercharging rate n'. The input voltage VCIN is multiplied by a factor equal to the boost rate n'.

As can be seen from Table 1, the boost step m' and the boost rate n' have a relationship according to Equation 3.

[Equation 3]

n'=(m'+3)/2

Although the boost rate n' is lowered by one step, the boost rate decrementing reference voltage BTDN_REF is set based on a point at which the level of the preliminary input voltage VCIN_F is lower than the value of the power supply voltage VDD/2. Therefore, when the boost rate decrement reference voltage BTDN_REF is represented by the boost step m', the boost rate decrement reference voltage BTDN_REF can be set according to Equation 4.

[Equation 4]

BTDN_REF(m')=VDD(m'+2)/((2*m')+6)

When the boost rate decrement reference voltage BTDN_REF is represented by the boost rate (n'), the boost rate decrement reference voltage BTDN_REF can be set according to Equation 5.

[Equation 5]

BTDN_REF(n')=VDD(n'-0.5)/(2*n')

The value used in Equation 5 is obtained on the assumption that the amplification factor of the amplifier 324 is 2 and the difference of one boost step is 0.5. This value can be expressed as Equation 6 below:

[Equation 6]

BTDN_REF(n')=VDD(n'-unit of change in boost rate)/(magnification of amplifier*n')

The analog voltage multiplexer 401, which may select the boost rate decrement reference voltage BTDN_REF, is operable to select the above-described boost rate decrement reference voltage BTDN_REF (BTDN_REF[m:0]) based on the amplification factor BT[a:0], the amplification factor BT[a:0] is a code having information on the magnification n'.

(C) The upper clamp voltage VCMP_UP0 may be input to the voltage clamp 326 to prevent an increase in the initial input voltage when the level of the preliminary input voltage VCIN_F is unnecessarily increased and the load condition or the boost rate BT[a:0] is changed. The problem that VCIN_F can converge to the target value may take time. It is important that the initial input voltage VCIN_F meets the following:

[Equation 7]

VCIN_F=VDD/2.

However, the preliminary input voltage VCIN_F may be higher than this point, and the upper clamp voltage VCMP_UP0 may be used to prevent the preliminary input voltage VCIN_F from increasing above this point. Therefore, the upper clamp voltage VCMP_UP0 can be set according to Equation 8.

[Equation 8]

VCMP_UP0=VDD/2+a

As used herein, "a" means a tolerance of, for example, no more than about 50 mV.

(D) The initial reference voltage BTINI_REF is a reference voltage used to determine the appropriate boost rate BT[a:0] during the initial boost operation. In the initial operation, since the input voltage VCIN may be required to start in the same state as the state of the power supply voltage VDD, the initial reference voltage BTINI_REF may be set to a value of the power supply voltage VDD/2. If a certain tolerance is given in consideration of the operating current of the boost voltage generating circuit, the initial reference voltage BTINI_REF can be set to a value of the system (power supply voltage VDD / 2 + β), where β is a value of about 50 mV.

FIG. 5 is a diagram illustrating a flag signal generator 312 in accordance with an embodiment.

Referring to FIG. 5, the flag signal generator 312 can include two comparators 501 and 502. The first comparator 501 can compare the preliminary input voltage VCIN_F with the boost rate decrement reference voltage BTDN_REF, and can generate the boost rate decrement flag signal BTDN_FG. The second comparator 502 can compare the preliminary input voltage VCIN_F with the boost rate increment reference voltage BTUP_REF, and can generate the boost rate increase flag signal BTUP_FG.

In response to the initial input voltage VCIN_F being lower than the boost rate decrement reference voltage BTDN_REF, the boost rate down flag signal BTDN_FG may be enabled to reduce the boost rate BT[a:0]. In response to the initial input voltage VCIN_F being higher than the boost rate increment reference voltage BTUP_REF, the boost rate increment flag signal BTUP_FG may be enabled to increase the boost rate BT[a:0].

In response to the initial input voltage VCIN_F being higher than the boost rate decrement reference voltage BTDN_REF and lower than the boost rate increment reference voltage BTUP_REF, the boost rate increment flag signal BTUP_FG and the boost rate down flag signal BTDN_FG may be disabled. In an example, it means that the current boost rate BT[a:0] is appropriate.

FIG. 6 is a diagram illustrating an input reference voltage selector 322 in accordance with an embodiment.

Referring to FIG. 6, the input reference voltage selector 322 can include an analog voltage multiplexer (MUX) 601.

The input reference voltage VC_REF0 is the target value of the preliminary input voltage VCIN_F. Therefore, the input reference voltage VC_REF0 can be set to the value VOUT _tar /(2n'), where VOUT _tar represents the target value of the boost voltage VOUT. This is based on the assumption that the magnification is twice. The input reference voltage VC_REF0 can be calculated according to Equation 9.

[Equation 9]

VC_REF0=VOUT _tar / (amplifier value n')

When Equation 9 is converted to a value based on n' and m' to obtain a value VC_REF[m'] input to the analog voltage multiplexer (MUX) 601, VC_REF[m'] is set according to Equation 10.

[Equation 10]

VC_REF[m']=VOUT _tar /(m'+3).

Therefore, VC_REF[m:0] can be set as above, and the analog voltage multiplexer (MUX) 601 can select a voltage suitable for the corresponding boost rate BT[a:0] as the input reference voltage VC_REF0.

FIG. 7 is a schematic diagram illustrating an initial value determiner 314 in accordance with an embodiment.

Referring to FIG. 7, the initial value determiner 314 can include m+1 comparators 701 that can compare respective VC_REF[m:0] values with an initial reference voltage BTINI_REF. The m+1 comparators 701 can output a signal BT_INI[m:0] regarding the initial value of the supercharging rate BT[a:0]. Although the comparator 701 is illustrated as a constituent element in the drawings, the number of comparators 701 may be m+1 or may be another number as appropriate. The first comparator can compare VC_REF[0] with the initial reference voltage BTINI_REF and can output BT_INI[0]. Finally, the comparator compares VC_REF[m] with the initial reference voltage BTINI_REF and can output BT_INI[m].

Since the initial reference voltage BTINI_REF generated in the voltage divider 311 is (VDD/2+β) (see the above example (D)), the information about the initial value can be changed as to whether the VC_REF[m:0] is higher than the value. (VDD/2+β) information. As shown in Table 2 below, the initial boost rate can be determined based on the number of voltages higher than (VDD/2+β) in VC_REF[m:0].

Table 2 shows that when BT_INI[m:0] is (2 ^m+1 -1) (for example, at the last column of Table 2), when all values of BT_INI[m:0] are logic high, The lowest supercharging rate (1.5) is taken as the initial supercharging rate. When BT_INI[m:0] is (2*m) (for example, at the first column of Table 2), when only the value of BT_INI[m] is logic high, the highest boost rate (n) can be used as Initial boost rate.

FIG. 8 is a schematic diagram illustrating a boost rate controller 313 in accordance with an embodiment.

The boost rate controller 313 may increase the boost rate BT[a:0] in response to the boost rate increment flag signal BTUP_FG being enabled for longer than a reference time. The boost rate controller 313 may decrease the boost rate BT[a:0] in response to the boost rate decrement flag signal BTDN_FG being enabled for longer than a reference time.

The boost rate controller 313 can include counters 801 and 802, comparators 803 and 804, D-type flip-flops 805 and 806, an initial value decoder 807, and a preset up/down counter 808. The components of the boost rate controller 313 will be described in detail later.

Figure 9 illustrates the operation of counters 801 and 802.

The counters 801 and 802 can perform the increase of the output value to the output terminal OUT[b:0] code value BTUP_CNT[b: at the rising edge of the clock CK in the period in which the signal BTUP_FG or BTDN_FG input to the enable EN terminal is logic high. 0] or BTDN_CNT[b:0] operation. BTUP_CNT[b:0] is an up counting signal; BTDN_CNT[b:0] is a down counting signal. Further, in response to the initialization signal P_ST input to the logic high in the reset RST terminal, all the bits output to the code of the terminal OUT[b:0] can be initialized to 0. Referring to Figure 9, the operation of counters 801 and 802 can be understood. The signal input to the RST terminal is the periodic signal P_ST, and the periodic signal P_ST can be enabled once during one of the periods in which the boost rate controller 313 changes the boost rate BT[a:0].

Referring back to FIG. 8, the comparator 803 can compare the BTUP_CNT[b:0] output from the counter 801 with the boost rate increment reference value BTUP_R[b:0]. In response to the BTUP_CNT[b:0] value being greater than the boost rate increment reference value BTUP_R[b:0], the comparator 803 can output a boost boost enable signal BTUP_PEN at a logic high. In response to the BTUP_CNT[b:0] value being less than the boost rate increment reference value BTUP_R[b:0], the comparator 803 can output the signal BTUP_PEN at a logic low.

The comparator 804 can compare the BTDN_CNT[b:0] with the boost rate decrement reference value BTDN_R[b:0]. In response to the BTDN_CNT[b:0] value being greater than the boost rate decrement reference value BTDN_R[b:0], the comparator 804 can output the signal BTDN_PEN at logic high. In response to the BTDN_CNT[b:0] value being less than the boost rate decrement reference value BTDN_R[b:0], the comparator 804 can output the signal BTDN_PEN at a logic low.

As the boost rate increment reference value BTUP_R[b:0] and the boost rate decrease reference value BTDN_R[b:0] increase, the boost rate increment flag signal BTUP_FG and the boost rate down flag signal BTDN_FG enable time lengthen.

The initial value decoder 807 can change the format of BT_INI[m:0] generated in the initial value determiner 314. Table 3 below shows the relationship between BT_INI[m:0] and D_BT_INI[a:0] and the initial supercharging rate expressed by the foregoing two.

FIG. 10 illustrates the operation of a preset up/down counter 808. In response to the logic high signal BTUP_EN input to the UP terminal, the preset up/down counter 808 can make the code BT[a:0] of the terminal OUT[a:0] at the rising edge of the CK terminal signal. Increasing one, the CK terminal signal is the inverse of the P_ST signal. In response to the signal BTDN_DN input to the logic high in the DN terminal, the preset up/down counter 808 can make the code BT[a:0] of the terminal OUT[a:0] at the rising edge of the CK terminal signal. Decrease one.

Further, in response to the DC conversion start signal DCC_ST of the enable terminal PEN being logic high, the code D_BT_INI[a:0] of the P[a:0] terminal can be the code of the OUT[a:0] terminal BT[a:0] . In short, in response to the logic high signal of the PEN terminal, the boost rate can be initialized to the value of D_BT_INI[a:0].

The DCC_ST signal input to the PEN terminal can be enabled to a logic high signal in response to the operation of the boosted voltage generating circuit that is starting.

Table 4 below shows the relationship between the supercharging rate code BT[a:0] (which indicates the supercharging rate) and the initial supercharging rate.

11 through 14 illustrate the operation of the boost rate controller 313. FIG. 11 illustrates the initial operation of the boost rate controller 313. FIG. 12 illustrates an operation of the boost rate controller 313 to increase the boost rate after the initial operation. FIG. 13 illustrates an operation of the boost rate controller 313 to reduce the boost rate after the initial operation. FIG. 14 illustrates the operation of the boost rate controller 313 to maintain the boost rate set during the initial operation.

Referring to Figure 11, the initial operation of the boost rate controller 313 is described.

The DCC_ST signal can be enabled to a logic high after operation of the initial boost voltage generating circuit. Then, the preset up/down counter 808 can set D_BT_INI[2:0] input to its P[a:0] terminal to the initial value of the boost rate BT[2:0]. Figure 11 shows that the value of D_BT_INI[2:0] is 2, and therefore the value of the code BT[2:0] representing the boost rate is 2 in this example and will correspond to the BT[2:0] value (2 The boost rate (2.5) is set to the boost rate. In other words, the boost rate is 2.5 in the illustrated example. It should be understood that the values given are for example purposes only, and that other input values may provide different output values.

FIG. 12 illustrates an operation of the boost rate controller 313 to increase the boost rate after the initial operation. As an example, the boost rate increment reference value BTUP_R[9:0] and the boost rate decrease reference value BTDN_R[9:0] may be set to 600.

After the P_ST signal is enabled and the P_ST signal experiences a porch period, the clock CK can begin to toggle. In response to the logic high boost rate increment flag signal BTUP_FG, the counter 801 can count the clock CK and can gradually increase the BTUP_CNT[9:0] value. The BTUP_PEN signal can be enabled to a logic high in response to an increased BTUP_CNT[9:0] value that converges to a boost rate increment reference value (eg, BTUP_R[9:0]=600). The BTUP_EN signal can be enabled by a BTUP_PEN signal that can be enabled to logic high. In response to the re-enabled P_ST signal, a preset up/down counter 808 can increase the value of the code BT[2:0] representing the boost rate from 2 to 3. Therefore, the boost rate can be increased from 2.5 to 3.

FIG. 13 illustrates an operation of the boost rate controller 313 to reduce the boost rate after the initial operation. As an example, the boost rate increment reference value BTUP_R[9:0] and the boost rate decrease reference value BTDN_R[9:0] may be set to 600.

After the P_ST signal is enabled and the P_ST signal experiences an occlusion period, the clock CK can begin to toggle. In response to the logic high decrement flag signal BTDN_FG, the counter 802 can count the clock CK and can gradually increase the BTDN_CNT[9:0] value. The BTDN_PEN signal can be enabled to a logic high in response to an increase in the BTDN_CNT[9:0] value that converges to a boost rate decrement reference value (eg, BTDN_R[9:0]=600). The BTUP_EN signal can be enabled by a BTDN_PEN signal that can be enabled to logic high. In response to the re-enabled P_ST signal, the preset up/down counter 808 may decrease the boost rate code BT[2:0] value representing the boost rate from 2 to 1. Therefore, the boost rate can be reduced from 2.5 to 2.

FIG. 14 illustrates the operation of the boost rate controller 313 to maintain the boost rate set during the initial operation. As an example, the boost rate increment reference value BTUP_R[9:0] and the boost rate decrease reference value BTDN_R[9:0] may be set to 600.

After the P_ST signal is enabled and the P_ST signal experiences an occlusion period, the clock CK can begin to toggle. In response to the logic high decrement flag signal BTDN_FG, the counter 802 can count the clock CK and can gradually increase the BTDN_CNT[9:0] value. When the BTDN_CNT[9:0] value is increased, the boost rate decrement flag signal BTDN_FG can transition to a logic low. Thus, for example, the BTDN_CNT[9:0] value may no longer increase from value 413. Since BTDN_CNT[9:0] may not converge to the boost rate decrement reference value (eg, BTDN_R[9:0]=600), the BTUP_PEN signal and the BTUP_EN signal may not be enabled. As a result, the preset up/down counter 808 may not change the value of the code BT[2:0] indicating the boost rate. Therefore, the supercharging rate can be maintained at 2.5.

In the example shown in FIG. 14, since the time at which the boost rate decrement flag signal BTDN_FG is enabled does not converge to the reference time (eg, 600 clock cycles), the boost rate may not be changed. In other words, in the example of Figure 14, even at 600 clock cycles, the BTDN_CNT[9:0] value stays at 413 and will never reach 600, so there will be no signal to change the boost rate.

FIG. 15 is a block diagram illustrating the lower clamp voltage selector 325.

The lower clamp voltage selector 325 may include an analog multiplexer (MUX) 1501 and may select the clamp voltage VCMP_DN0 in the input voltage VCMP_DN[m:0] in response to the boost rate BT[a:0].

In response to the low initial input voltage VCIN_F and the changed load condition or boost rate BT[a:0], the lower clamp voltage VCMP_DN0 can be input to the voltage clamp 326 to prevent the preliminary input voltage VCIN_F from converge to the target value. The time increases.

The input voltage VCMP_DN[m:0] input to the lower clamp voltage selector 325 can be generated according to Equation 11.

[Equation 11]

VCMP_DN[m']=VC_REF[m']-a,

Where a 50 mV

The lower clamp voltage selector 325 can select the input voltage VCMP_DN[m:0] suitable for the boost rate BT[a:0] as the lower clamp voltage VCMP_DNO.

FIG. 16 is a block diagram showing the voltage clamp 326.

The voltage clamp 326 can include an upper clamp 1601 and a lower clamp 1602.

The upper clamp 1601 can generate a sinking current between the ground terminals from the preliminary input voltage VCIN_F in response to the preliminary input voltage VCIN_F becoming higher than the upper clamp voltage VCMP_UPO, thereby preventing the preliminary input voltage VCIN_F from becoming higher than the upper clamp Bit voltage VCMP_UPO.

The lower clamp 1602 can generate a drive current between the power supply voltage VDD from the preliminary input voltage VCIN_F in response to the preliminary input voltage VCIN_F becoming lower than the lower clamp voltage VCMP_DNO, thereby preventing the preliminary input voltage VCIN_F from becoming higher than the upper clamp voltage VCMP_DNO .

FIG. 17 is a block diagram showing the output voltage divider 321 .

The output voltage divider 321 can include a plurality of resistors coupled in series to divide the boost voltage VOUT, and an analog voltage multiplexer (MUX) 1701.

In response to the current boost rate BT[a:0] for n', the level of the boost voltage VOUT_F output from the output voltage divider 321 can be calculated according to Equation 12.

[Equation 12]

VOUT/(2*n').

This is because the amplification factor of the amplifier 324 is 2 in this example. This relationship can be expressed more generally according to Equation 13 below.

[Equation 13]

VOUT_F=(VOUT/(n'* amplifier magnification)

When VOUT/(2*n') is expressed as a value based on m', VOUT/(2*n') can be expressed according to Equation 14.

[Equation 14]

VOUT_F=VOUT/(m'+3).

The analog voltage multiplexer (MUX) 1701 is operable to select an appropriate output voltage VOUT_F based on the boost rate BT[a:0].

FIG. 18 is a block diagram illustrating the compensation circuit 327.

The compensation circuit 327 can include a resistor Rc and a capacitor Cc. The compensation circuit 327 can ensure the stability of a feedback loop that can generate a preliminary input voltage VCIN_F by adding a pole and/or a zero to the loop.

Referring back to FIG. 3, the comparator 323 can compare the output voltage VOUT_F of the output voltage divider 321 with the output voltage VC_REF0 of the input reference voltage selector 322, and can generate a preliminary input voltage VCIN_F.

In response to the output voltage VOUT_F of the output voltage divider 321 being higher than the input reference voltage VC_REF0, the comparator 323 can reduce the level of the preliminary input voltage VCIN_F. In response to the output voltage VOUT_F of the output voltage divider 321 being lower than the input reference voltage VC_REF0, the comparator 323 can increase the level of the preliminary input voltage VCIN_F.

In response to the output voltage VOUT_F of the output voltage divider 321 being higher than the input reference voltage VC_REF0, the level of the preliminary input voltage VCIN_F can be reduced. Therefore, the level of the input voltage VCIN can be reduced. This decrease can be reflected in the output voltage VOUT, and the output voltage VOUT_F of the output voltage divider 321 can also be reduced. The level of the initial input voltage VCIN_F converges to the input reference voltage VC_REF0.

In response to the output voltage VOUT_F of the output voltage divider 321 being lower than the input reference voltage VC_REF0, the level of the preliminary input voltage VCIN_F can be increased. Therefore, the level of the input voltage VCIN can be increased. This increase can be reflected in the output voltage VOUT, and the output voltage VOUT_F of the output voltage divider 321 can also be increased. The level of the initial input voltage VCIN_F converges to the input reference voltage VC_REF0.

Amplifier 324 can include a comparator 328 as a linear regulator and two resistors R. Amplifier 324 can amplify preliminary input voltage VCIN_F by two times (eg, with 2) and can generate input voltage VCIN. It will be appreciated that the amplification of amplifier 324 can be changed to a magnification other than twice.

The overall operation of the boost voltage generating circuit will now be described.

The input voltage level setting unit 220 can generate an input voltage VCIN whose target is at a level of (target output voltage/boost rate). In other words, it can control the level of the input voltage VCIN according to Equation 15.

[Equation 15]

VCIN=VOUT _tar /n'

The boost rate setting unit 210 can respond to the target level of the input voltage VCIN (VOUT _tar /n') at a level that the input voltage VCIN cannot have (for example, in response to the target level VOUT _tar /n' exceeding the power supply voltage) Increase the boost rate BT[a:0]. Even if the boost rate BT[a:0] can be reduced by one step, if the target level of the input voltage VCIN is a level that the input voltage VCIN cannot have (for example, the target level of the input voltage VCIN is lower than the power supply voltage) The boost rate setting unit 210 can still reduce the boost rate BT[a:0].

Through the operation of the input voltage level setting unit 220 and the boost rate setting unit 210, the boost rate BT[a:0] may become as low as possible, and the input voltage VCIN is such that the input voltage VCIN cannot exceed the power supply voltage. The range of levels is increased to as high as possible.

The higher the boost rate BT[a:0] becomes, the more current the boost voltage generating circuit can consume. According to an embodiment, the operation of the boost rate setting unit 210 and the input voltage level setting unit 220 can reduce the boost rate BT[a:0] as permitted as possible, and the current consumption of the boost voltage generating circuit Can be reduced.

The boost voltage generating circuit fabricated in accordance with an embodiment maximizes the input voltage and minimizes the boost rate to produce a boost voltage having a target level. Therefore, the boost voltage generating circuit can generate a boost voltage having a target level by boosting the input voltage with a minimum boost rate.

As a result, the boost voltage generating circuit can maintain a minimum current consumption.

Several examples have been described above. However, it will be understood that various modifications can be made. For example, where the described techniques are performed in a different order and/or components in the described systems, architecture, devices, or circuits are combined in various ways and/or replaced by other components or equivalents thereof In the case of supplementation, a suitable result can be achieved. For example, as described, the described hardware devices and/or components thereof can be configured to function as one or more software modules to perform the operations and processes described above, or vice versa. The processes, functions, methods and/or software may be recorded, stored or fixed on one or more computer readable storage media, the one or more computer readable storage media comprising program instructions to be executed by a computer Causes the processor to execute or execute the program instructions. Such media may also include (individually or in combination with program instructions) data files, data structures and the like. Accordingly, other implementations are within the scope of the following claims.

100. . . Boost voltage generating circuit

200. . . Booster circuit

210. . . Supercharging rate setting unit

220. . . Input voltage level setting unit

311. . . Voltage divider

312. . . Flag signal generator

313. . . Boost rate controller

314. . . Initial value determiner

321. . . Output voltage divider

322. . . Input reference voltage selector

323. . . Comparators

324. . . Amplifier

325. . . Lower clamp voltage selector

326. . . Voltage clamp

327. . . Compensation circuit

328. . . Comparators

401. . . Analog voltage multiplexer (MUX)

501. . . Comparators

502. . . Comparators

601. . . Analog voltage multiplexer (MUX)

701. . . Comparators

801. . . counter

802. . . counter

803. . . Comparators

804. . . Comparators

805. . . D-type flip-flop

806. . . D-type flip-flop

807. . . Initial value decoder

808. . . Presettable increment/decrement counter

1501. . . Analog multiplexer (MUX)

1601. . . Upper clamp

1602. . . Lower jaw

BT[2:0]. . . Supercharging rate

BT[a:0]. . . Supercharging rate

BTDN_CNT[9:0]. . . value

BTDN_CNT[b:0]. . . Code value

BTDN_EN. . . signal

BTDN_FG. . . Supercharge rate decrement flag signal

BT_INI[m:0]. . . Signal about the initial value of the boost rate

BTDN_PEN. . . Pressurization rate decrement enable signal

BTDN_R[b:0]. . . Pressurization rate decrement reference value

BTDN_REF. . . Pressurization rate decrementing reference voltage

BTDN_REF[m:0]. . . Pressurization rate decrementing reference voltage

BTINI_REF. . . Initial reference voltage

BTUP_CNT[9:0]. . . value

BTUP_CNT[b:0]. . . Code value

BTUP_EN. . . signal

BTUP_FG. . . Supercharge rate increasing flag signal

BTUP_PEN. . . Boost increment enable signal

BTUP_R[b:0]. . . Pressurization rate increment reference value

BTUP_REF. . . Pressurization rate increment reference voltage

Cc. . . Capacitor

CK. . . Clock / terminal

D_BT_INI[2:0]. . . code

D_BT_INI[a:0]. . . code

DCC_ST DC. . . Conversion start signal

DN. . . Terminal

EN. . . Enable terminal

OUT[a:0]. . . Terminal

OUT[b:0]. . . Output terminal

P[a:0]. . . Terminal

P_ST. . . Initialization signal

PEN. . . Enable terminal

R. . . Resistor

Rc. . . Resistor

RST. . . Reset terminal

UP. . . Terminal

VC_REF0. . . Input reference voltage / output voltage

VCIN. . . Input voltage

VCIN_F. . . Preliminary input voltage

VCMP_DN[m:0]. . . Input voltage

VCMP_DN0. . . Lower clamp voltage

VCMP_UP0. . . Upper clamp voltage

VDD. . . voltage

VOUT. . . Boost voltage

VOUT_F. . . The output voltage

VR_REF[m:0]. . . Voltage

1 is a block diagram showing the voltage, signal, and output voltage of a boost voltage generating circuit.

2 is a block diagram illustrating a boost voltage generating circuit in accordance with an embodiment.

FIG. 3 is a detailed block diagram illustrating the boost voltage generating circuit of FIG. 2. FIG.

4 is a schematic diagram illustrating a voltage divider in accordance with an embodiment.

FIG. 5 is a schematic diagram illustrating a flag signal generator in accordance with an embodiment.

6 is a schematic diagram illustrating an input reference voltage selector in accordance with an embodiment.

FIG. 7 is a schematic diagram illustrating an initial value determiner according to an embodiment.

FIG. 8 is a schematic diagram illustrating a boost rate controller in accordance with an embodiment.

Figure 9 illustrates the operation of the counter.

Figure 10 illustrates the operation of a preset up/down counter.

11 to 14 illustrate the operation of the boost rate controller.

Figure 15 is a block diagram illustrating the lower clamp voltage selector.

Figure 16 is a block diagram showing a voltage clamp.

Figure 17 is a block diagram illustrating an output voltage divider.

Figure 18 is a block diagram showing the compensation circuit.

Throughout the drawings, the same reference numerals will be understood to refer to the same elements, features and structures. The relative size and depiction of such elements may be exaggerated for clarity, illustration, and convenience.

200. . . Booster circuit

210. . . Supercharging rate setting unit

220. . . Input voltage level setting unit

BT[a:0]. . . Supercharging rate

VCIN. . . Input voltage

VOUT. . . Boost voltage

Claims (39)

A boosted voltage generating circuit includes: a boosting circuit configured to: boost an input voltage based on a boost rate; and output a boosted voltage; a boost rate setting unit State: receiving a feedback about one of the input voltage levels; and setting the boost rate; and an input voltage level setting unit configured to set the bit of the input voltage in response to the following Quasi: one of the target levels of the boost voltage; and the boost rate. The boost voltage generating circuit of claim 1, wherein the input voltage level setting unit is further configured to set a target level of the input voltage according to one of: (the target level of the boost voltage) / The boost rate). The boost voltage generating circuit of claim 2, wherein the boost rate setting unit is further configured to increase the boost rate in response to the target level of the input voltage exceeding a level of the input voltage. The boost voltage generating circuit of claim 3, wherein the boost rate setting unit is further configured to respond to the target level of the input voltage when the boost rate is decreased. The boost rate is reduced. The boost voltage generating circuit of claim 1, wherein the input voltage level The setting unit includes: an output voltage divider configured to: divide the boosted voltage by a ratio based on the boost rate determination; and output a divided voltage; an input reference voltage selector Configuring to select an input reference voltage based on the boost rate and a plurality of voltages generated based on the target level of the boost voltage; a comparator configured to: compare the output voltage divider One of the output voltages and one of the input reference voltage selectors outputs a voltage; and generates a preliminary input voltage; and an amplifier configured to: amplify the preliminary input voltage; and generate the input voltage. The boost voltage generating circuit of claim 5, wherein the amplifier comprises: a comparator configured as a linear regulator; and a plurality of resistors. The boost voltage generating circuit of claim 5, wherein the output voltage divider is further configured to divide the boost voltage by one of: 1 (the boost rate * one of the amplifiers is amplified) rate). The boost voltage generating circuit of claim 7, wherein the input reference voltage selector is further configured to select a reference voltage for the target level according to: The boost voltage / (the boost rate * one of the amplifier's amplification). The boost voltage generating circuit of claim 5, wherein the input voltage level setting unit further comprises a voltage clamp configured to prevent the preliminary input voltage from excessively increasing or decreasing. The boost voltage generating circuit of claim 9, wherein the voltage clamp comprises an analog multiplexer configured to select a clamp voltage among the input voltages in response to the boost rate. The boost voltage generating circuit of claim 9, wherein the input voltage level setting unit further comprises a compensation circuit configured to stabilize the level of the preliminary input voltage. The boost voltage generating circuit of claim 11, wherein the compensation circuit comprises: a resistor; and a capacitor. The boost voltage generating circuit of claim 5, wherein the boost rate setting unit comprises: a voltage divider configured to generate: a boost rate increment reference voltage; and a boost rate decrement reference voltage; a flag signal generator configured to: responsive to the preliminary input voltage being higher than the boost rate increment reference voltage to enable a boost rate increment flag signal; and responsive to the preliminary input voltage being lower than the boost Rate decrementing the reference voltage to enable a boost rate decrement flag signal; and A boost rate controller configured to set the boost rate in response to the boost rate increment flag signal and/or the boost rate down flag signal. The boost voltage generating circuit of claim 13, wherein the boost rate setting unit further comprises an initial value determiner configured to provide the boost rate controller with information about an initial value of the boost rate . The boost voltage generating circuit of claim 14, wherein the initial value determiner comprises a plurality of comparators configured to compare the respective input reference voltage values with an initial reference voltage. The boost voltage generating circuit of claim 13, wherein the boost rate controller is further configured to: increase the boost rate in response to the boost rate increment flag signal being enabled for longer than a reference time; The boost rate is reduced in response to the boost rate decrement flag signal being enabled for longer than a reference time. The boost voltage generating circuit of claim 16, wherein the boost rate controller comprises: a plurality of counters; a plurality of comparators; a plurality of flip-flops; an initial value decoder; and a preset increment/decrement counter. The boost voltage generating circuit of claim 17, wherein: the preset up/down counter is configured to set an initial boost rate signal input to the preset up/down counter to the increment An initial value of the pressure rate; in response to the boost rate increasing flag signal being a logic high, one of the plurality of counters is configured to count a clock to increase an incrementing count; and The incremented up count value converges to the boost rate increment reference voltage, and the preset up/down counter is further configured to enable one of the boost rates to increase. The boost voltage generating circuit of claim 17, wherein: the preset up/down counter is configured to set an initial boost rate signal input to the preset up/down counter to the increment An initial value of the pressure rate; in response to the boost rate decrement flag signal being a logic high, one of the plurality of counters is configured to count a clock to increase a countdown value; and The increased down-counting value converges to the boost rate decrementing reference voltage, the pre-set up/down counter being further configured to enable one of the boost rates to decrease. The boost voltage generating circuit of claim 17, wherein: the preset up/down counter is configured to set an initial boost rate signal input to the preset up/down counter to the increment An initial value of the pressure rate; and in response to the boost rate decrement flag signal being a logic high, one of the plurality of counters is configured to count a clock to increase a countdown value, The boost rate decrement flag signal increases the decrement The count value transitions to a logic low such that the countdown value does not increase further such that the preset up/down counter does not enable one of the boost rate changes. The boost voltage generating circuit of claim 13, wherein: the one of the boost rate increment reference voltages is determined according to the following equation: a power supply voltage / (one of the amplifiers); and the boost rate is decreased One of the reference voltage levels is determined according to the following equation: the power supply voltage * (the boost rate - a unit of pressure change rate) / (the amplification factor of the amplifier * the boost rate). A method for operating a boost voltage generating circuit that generates a boosted voltage by boosting an input voltage based on a boost rate, the method comprising: generating a target of one of the following bits The input voltage: (one target voltage of the boost voltage / the boost rate); increasing the boost rate in response to the target level of the input voltage exceeding a level of the input voltage; and The boost rate is decreased in response to the target level of the input voltage falling within the level of the input voltage as the boost rate decreases. The method of claim 22, wherein the input voltage does not have a level above a supply voltage. The method of claim 22, wherein the decreasing of the boost rate is performed in response to the target level of the input voltage being lower than one of: (the boost rate - one of the boost rate changes) ) / The boost rate. A method of generating a boosted voltage comprising: Pressurizing an input voltage based on a boost rate; outputting a boost voltage; receiving a feedback on one of the input voltage levels; setting the boost rate; and setting the input voltage in response to the following Level: one of the target levels of the boost voltage; and the boost rate. The method of claim 25, further comprising setting a target level of the input voltage according to one of: (the target level of the boost voltage / the boost rate). The method of claim 26, further comprising increasing the boost rate in response to the target level of the input voltage exceeding a level of the input voltage. The method of claim 27, further comprising reducing the boost rate in response to the target level of the input voltage being within the level range of the input voltage when the boost rate is decreased. The method of claim 25, further comprising: dividing the boosted voltage by a ratio based on the boost rate determination; outputting the divided voltage; and based on the boosted voltage, the target based on the boosted voltage Selecting an input reference voltage from a plurality of voltages generated by the level; comparing an output voltage with an input reference voltage; generating a preliminary input voltage; amplifying the preliminary input voltage; This input voltage is generated. The method of claim 29, further comprising dividing the boost voltage by a ratio of 1/(the boost rate * a magnification). The method of claim 30, further comprising selecting a reference voltage for the target level according to the following formula: the boost voltage / (the boost rate * a magnification). The method of claim 29, further comprising preventing the preliminary input voltage from excessively increasing or decreasing. The method of claim 32, further comprising selecting a clamp voltage among the input voltages in response to the boost rate. The method of claim 32, further comprising stabilizing the level of the preliminary input voltage. The method of claim 29, further comprising: generating: a boost rate increment reference voltage; and a boost rate decrementing reference voltage; enabling a boost in response to the preliminary input voltage being higher than the boost rate increment reference voltage Rate increasing the flag signal; enabling a boost rate decrement flag signal in response to the preliminary input voltage being lower than the boost rate decrementing reference voltage; and responding to the boost rate increasing flag signal and/or the boost rate The boost rate is set by decrementing the flag signal. The method of claim 35, further comprising providing the boost rate An initial value information. The method of claim 36, further comprising comparing the respective input reference voltage values to an initial reference voltage. The method of claim 35, further comprising: increasing the boost rate in response to the boost rate increment flag signal being enabled for longer than a reference time; and in response to the boost rate down flag signal being enabled for a duration The boost rate is reduced by a reference time. The method of claim 35, wherein: the one of the boost rate increment reference voltages is determined according to the following equation: a power supply voltage / (one of the amplifiers); and the boost rate decrements one of the reference voltages The criterion is determined according to the following equation: the power supply voltage * (the boost rate - a unit of pressure change rate) / (the amplification factor of the amplifier * the boost rate).