JP5937442B2 - DC-DC converter - Google Patents

Description

  The present invention relates to a DC-DC converter used for a power source of an electronic device, and more particularly to a SEPIC synchronous rectification type DC-DC converter.

  Electronic devices such as mobile phones and personal computers are supplied with voltage from secondary batteries such as lithium ion batteries. The output voltage of the secondary battery varies depending on the remaining amount and load conditions. For example, the power consumption of a processor such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processor) varies depending on the instruction processing number MIPS (Million Instruction Per Second) per unit time. That is, when the processor power is directly supplied from a secondary battery or the like, the power supply voltage fluctuates due to load fluctuations. Thus, stable power supply is an important issue in the field of electronic devices such as processors.

  A DC-DC converter is known as a circuit that converts the voltage of the secondary battery into a stable voltage.

  The DC-DC converter is a circuit for converting a power supply voltage of a battery or the like into a required voltage for driving a load such as an electronic device, and is roughly classified into a step-down type, a step-up type, and a step-up / step-down type.

  A step-down DC-DC converter, for example, uses a relatively high voltage battery output voltage in a personal computer as a power supply voltage for an integrated circuit such as a CPU that is driven at a relatively low voltage and consumes a large current. Used to convert.

  A step-up DC-DC converter, for example, in a power generation system using solar cells, converts a relatively low voltage output voltage of a solar cell into a relatively high voltage power supply voltage such as a household power supply. To be used.

  The step-up / step-down DC-DC converter is used, for example, in a low fuel consumption environment vehicle equipped with an idling stop system. In an idling stop vehicle, the engine is started with the internal electrical components operating, and the battery voltage drops due to the initial rush current (initial inrush current) of the cell motor used to start the engine. To do. A step-up / step-down DC-DC converter is used to supply voltage / current necessary for the operation of the electrical components even when the battery voltage is lowered. The step-up / step-down DC-DC converter steps down the voltage of the battery when idling is stopped or stable after the engine starts and supplies a stable power supply voltage to the internal electrical components. When the battery drops when the engine starts, Boosts and supplies a stable power supply voltage to internal electrical components.

  FIG. 10 is a circuit diagram of a conventional DC-DC converter described in Patent Document 1. In FIG.

  The conventional DC-DC converter is a DC-DC converter called SEPIC. SEPIC is an acronym for Single-Ended Primary Inductive Converter, and is a step-up / step-down DC-DC converter.

The conventional DC-DC converter includes a coil L _S , a capacitor C _C , a coil L _L , and a common connection between the capacitor C _C and the coil L _L and an output terminal connected in series from the input power source _VIN to the ground. connected diodes D1, constitutes a connected N-channel MOS transistor Nch, in SEPIC between the common connection portion and the ground between the coil _{L S} and capacitor _{C C.} Further, a P-channel MOS transistor Pch for performing synchronous rectification is connected in parallel to the diode D1.

The synchronous rectification MOS transistor Pch is arranged to reduce the loss due to the forward resistance of the diode D1 when performing the step-up / step-down operation. Synchronous rectification MOS transistor Pch is complementarily turned on and off the MOS transistor Nch, is turned on when a current flows to the output capacitor _{C L.}

In the conventional DC-DC converter, a feedback voltage FB obtained by dividing the output voltage V _O by resistors R1 and R2 is input to a control circuit CC, and a PWM signal having a pulse width corresponding to the magnitude of the output voltage V _O is input to the control circuit. Output from the CC to the MOS transistors Pch and Nch. First, Nch is turned on and MOS transistor Pch is turned off. At this time, the coil _L input voltage _{V IN} is applied to the _S current _{i LS} flows to ground via the MOS transistor Nch from the coil _{L S,} the voltage _{V C} is applied to the _{L L} coil _{L L} and a capacitor _{C C} , Current i _LL flows through MOS transistor Nch, and energy is stored in coils L _S and L _L.

When the MOS transistor Nch is MOS transistor Pch turned off and turned on, current _{i LS} flows through the MOS transistor Pch coil _{L S} and the capacitor C _C, the current _{i LL} via the MOS transistor Pch from the coil _{L L} Flowing. With the voltage V _O with pressure elevating the input voltage V _IN to the output capacitor C _L by repeating these operations is output, the load R _L is driven.

US Patent Application Publication No. 2006/0250826

However, the conventional SEPIC synchronous rectification type DC-DC converter shown in FIG. 1 has a problem that current flows backward from the output capacitor C _L to the output side coil L _L when the load R _L is light, that is, when the load is light. .

Load when R _L is a heavy heavy load, the charging current stored in the output coil L _L and the input-side coil L _S is supplied to the output capacitor C _L from MOS transistor Pch as the output current supplied to the load R _L, A large load current flows through the load _RL .

However, when the load R _L is lighter light load, the load since the R _L flows only small load current, many of the charging current is supplied to the output capacitor C _L as the output current, most supplied to the load R _L Disappear. Then, the accumulated number of charges, the output voltage V _O rises in the output capacitor C _L. Output voltage V _O increases, the output voltage V _O is greater than the voltage of the output coil L _L, while the MOS transistor Pch is turned on, current flows back to the output side coil L _L from the output terminal. The reverse flow of current causes a power loss and a prolonged adaptation time when the load changes from a light load to a heavy load.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a DC-DC converter in which current does not flow backward from an output capacitor to an output side coil at light load.

  In order to solve the above-mentioned problem, the invention described in claim 1 is a DC-DC converter that is a synchronous rectification type SEPIC, wherein the current value of the first current that flows through the input side coil and the first current that flows through the output side coil. And a control circuit for adjusting a period during which the synchronous rectification MOS transistor is turned off during the rectification operation based on the current value of the second current.

  According to a second aspect of the present invention, in the DC-DC converter according to the first aspect, the control circuit has a predetermined sum total of the current value of the first current and the current value of the second current. The synchronous rectification MOS transistor is turned off when the value becomes smaller than.

  According to a third aspect of the present invention, in the DC-DC converter according to the second aspect, the control circuit converts the first current into a first voltage, a first current-voltage converter, and the first A second current-voltage conversion unit that converts a current of 2 into a second voltage, an addition unit that adds the first voltage and the second voltage, an output of the addition unit, and the predetermined value And a determination unit that compares the corresponding reference voltage and outputs a determination signal, and the synchronous rectification MOS transistor is turned off according to the determination signal.

  According to a fourth aspect of the present invention, in the DC-DC converter according to any one of the first to third aspects, the control circuit stores whether or not the synchronous rectification is performed in the first switching cycle. And further comprising a storage unit, wherein the storage unit stores that the synchronous rectification has been performed, and the predetermined value is smaller in a second switching cycle after the first switching cycle. The predetermined value is set to a larger value in the second switching cycle when it is set to a value and it is stored that the synchronous rectification has not been performed.

  According to a fifth aspect of the present invention, in the DC-DC converter according to the fourth aspect, in the first switching cycle, the storage unit is configured to input a first logic value input to an input-side MOS transistor, and It is possible to store whether or not the synchronous rectification is performed by latching the second logical value input to the synchronous rectification type MOS transistor.

  A sixth aspect of the present invention is the DC-DC converter according to any one of the first to fifth aspects, wherein the synchronous rectification type SEPIC is connected in series from the input terminal to the ground in order. A capacitor and a second coil; a first MOS transistor connected between a connection between the first coil and the capacitor and the ground; a connection between the capacitor and the second coil; and an output terminal A second MOS transistor connected between and a diode connected in parallel to the second MOS transistor, the first coil is the input side coil, and the second coil is The output side coil, the first MOS transistor is the input side MOS transistor, and the second MOS transistor is the synchronous rectification M Characterized in that it is a S transistor.

  According to a seventh aspect of the present invention, in the DC-DC converter according to any one of the first to sixth aspects, the control circuit is responsive to an output voltage output from an output terminal of the DC-DC converter. The control circuit outputs a control signal for controlling on / off of the input side MOS transistor and the synchronous rectification MOS transistor.

  According to the present invention, the synchronous rectification transistor is turned off based on the current flowing through the input side coil and the output side coil, thereby preventing the current from flowing backward from the output capacitor to the output side coil at a light load. Play.

1 is a circuit diagram of a DC-DC converter according to Embodiment 1 of the present invention. It is the circuit diagram which actualized the current-voltage conversion part of the DC-DC converter which concerns on Embodiment 1 of this invention. It is the circuit diagram which actualized the control circuit of the DC-DC converter which concerns on Embodiment 1 of this invention. It is a timing chart at the time of normal operation of the DC-DC converter concerning Embodiment 1 of the present invention. It is a timing chart at the time of backflow prevention of the DC-DC converter concerning Embodiment 1 of the present invention. It is a circuit diagram of the DC-DC converter of Embodiment 2 of this invention. It is the circuit diagram which actualized the control circuit of the DC-DC converter which concerns on Embodiment 2 of this invention. It is a timing chart when the threshold value compared with the value of the sum total of each coil current of the DC-DC converter which concerns on Embodiment 2 of this invention changes highly. It is a timing chart when the threshold value compared with the value of the sum total of each coil current of the DC-DC converter which concerns on Embodiment 2 of this invention changes low. It is a circuit diagram of the conventional DC-DC converter.

  Embodiments 1 and 2 of the DC-DC converter of the present invention will be described below with reference to the drawings.

(Embodiment 1)
(Constitution)
FIG. 1 is a circuit diagram of a DC-DC converter according to Embodiment 1 of the present invention.

The DC-DC converter of this embodiment includes a coil L _S (input side coil), a capacitor _CC and a coil L _L (output side coil), a coil L _S and a capacitor C _C that are connected in series from the input terminal to the ground. the connections and the parallel-connected MOS transistor Nch connected to a diode D1 and a diode D1 between the ground (input side MOS transistor), between a connection portion of the capacitor C _C and the coil L _L and the output terminal The connected MOS transistor Pch (synchronous rectification MOS transistor), the MOS transistor Nch, and the Pch have a control circuit CC that outputs a control signal for controlling on / off. That is, the coils L _S and L _L , the capacitor C _C , the diode D1, the MOS transistors Nch and Pch, and the control circuit CC constitute a DC-DC converter that is a synchronous rectification type SEPIC.

Then, the control circuit CC, the current value of the current _{i LS} flowing through the coil _{L S,} when the voltage value representing the sum of the current value _{i LL} of the current flowing through the coil _{L L} is, becomes smaller than a predetermined reference voltage Vref1 In addition, a determination unit that outputs a determination signal indicating that it has become smaller is provided, and the MOS transistor Pch is turned off during the rectifying operation in accordance with the determination signal.

  Here, MOS transistor Nch is formed of an N channel MOS transistor, and MOS transistor Pch is formed of a P channel MOS transistor. The MOS transistor Pch is a so-called synchronous rectification MOS transistor.

The predetermined reference voltage Vref1 is realized by the reference voltage source RVS1, and is a voltage corresponding to a limit load that does not flow backward. When the load _RL is a heavy heavy load, a large load current flows through the load _RL , so that the sum of the current i _LS and the current i _LL increases. On the other hand, when the load _RL is a light load, a small load current flows through the load _RL , so that the sum of the current i _LS and the current i _LL becomes small. In other words, when the reference voltage Vref1 is set to a voltage corresponding to the value of the load that flows backward when the load becomes lighter than this, the voltage value representing the sum of the current i _LS and the current i _LL falls below the reference voltage Vref1. , It can be determined that the load is a limit value for backflow.

The MOS transistor Pch, coil _{L L} Output excess current of the capacitor _{C L} and the load _{R L} diode D1 so that it can supply to are connected in parallel when the MOS transistor Pch is off. In addition, the MOS transistor Pch is formed with a body diode in which the bulk and the source are connected and the direction from the drain to the source is the forward direction so that no current flows from the source to the drain when the transistor is off. That is, the diode D1 may be replaced with a body diode of the MOS transistor Pch.

Moreover, the current _{i LS} current voltage converter _{S S,} is converted into a voltage value corresponding to the current _{i LS,} the current _{i LL} current voltage converter _{S L,} is converted into a voltage value corresponding to the current _{i LL} . Then, the outputs of the current-voltage converters S _S and S _L are added by the adder Adder 1 and compared with the reference voltage Vref 1 by the comparator CMP 1. The current-voltage converters S _S and S _L are realized by a sense resistor, a current mirror circuit, or the like. The current / voltage converters S _S and S _L , the adder Adder1, the reference voltage source RVS1 that realizes the reference voltage Vref1, and the comparator CMP1 constitute a determination unit.

The control circuit CC controls on / off of the MOS transistors Nch and Pch from the PWM signal generation circuit PWMSG during normal operation without backflow prevention (when the sum of the currents i _LS and i _LL is greater than a predetermined reference voltage Vref1). The PWM signal to be output is output. The control circuit CC that outputs a control signal for controlling on / off of the MOS transistors Nch and Pch is not limited to the PWM signal generation circuit PWMSG that outputs a PWM signal, but may be a PFM signal generation circuit that outputs a PFM signal, or ΔΣ A ΔΣ modulator that outputs a modulation signal may be used. The PWM signal generation circuit PWMSG monitors the output voltage V _O by a resistance dividing circuit composed of resistors R1 and R2 connected in series, and outputs a PWM signal with a duty corresponding to the output voltage V _O to the MOS transistors Nch and Pch, respectively. To do.

Here, the control circuit CC forcibly turns off the MOS transistor Pch according to the determination signal output from the comparator CMP1 during the backflow prevention operation for preventing backflow. That is, when the load _RL is light and light, the output of the adder Adder1 falls below the reference voltage Vref1, and the comparator CMP1 outputs low to the PWM signal generation circuit PWMSG. Then, the PWM signal generation circuit PWMSG outputs high to the MOS transistor Pch and turns off the MOS transistor Pch.

Thus, DC-DC converter of this embodiment monitors the current flowing through the coil L _L of the input coil L _S and the output side, when the sum of these currents is smaller than a predetermined value, synchronization Since the rectifying MOS transistor Pch is turned off, it is possible to prevent a current from flowing backward from the output capacitor C _L to the output side coil L _L at a light load. That is, the present embodiment, on the basis of the current flowing through the input-side coil L _S to the output side coil L _L, synchronized due to so as to turn off the rectifying MOS transistor Pch, the output-side coil L from the output capacitor C _L at light loads _It is possible to prevent a current from flowing backward through _L.

Further, since the current flowing through the output terminal is not monitored, but only the currents of the input side coil L _S and the output side coil L _L are monitored, the power loss is small and the configuration is simple.

(Specific example of current-voltage converter)
FIG. 2 is a circuit diagram embodying the current-voltage conversion units S _S and S _L.

Current-to-voltage converter _{S S} is constituted by a sense resistor SR and a differential amplifier SAMP. The sense resistor SR, current flows _{i LS} flowing through the coil _{L S} is, a voltage is generated in accordance with the current _{i LS} at both ends of the sense resistor SR. The differential amplifier SAMP amplifies and outputs the voltage across the sense resistor SR.

Current-to-voltage converter _{S L} is constituted by a sense resistor LR and a differential amplifier LAMP. The sense resistor LR, current flows _{i LL} flowing through the coil _{L L} is, voltage is generated in accordance with the current _{i LL} at both ends of the sense resistor LR. The differential amplifier LAMP amplifies and outputs the voltage across the sense resistor LR.

  Thus, signal processing can be performed with a simple configuration by converting current into voltage.

(Specific example of control circuit)
Next, a specific example of the control circuit of this embodiment will be described.

  FIG. 3 is a circuit diagram showing a specific control circuit.

  The PWM signal generation circuit PWMSG includes an error amplifier Error AMP, a reference voltage source RVS2, an impedance element Z, an adder Adder2, a sawtooth generation circuit RAMP, a comparator CMP2, flip-flops FF1, FF2, FF3, an inverter INV, a NOR circuit NOR, OR The circuit OR includes buffers BUF1 and BUF2.

  The output terminal of the comparator CMP1, which is the output of the determination unit, is connected to the reset terminals of the flip-flops FF2 and FF3, and is reset when a low level is input. Then, a low signal is output from the flip-flops FF2 and FF3 to the NOR circuit NOR, converted to high by the NOR circuit NOR, and input to the MOS transistor Pch through the OR circuit OR. The MOS transistor Pch is turned off to prevent backflow.

(Operation)
Hereinafter, a specific operation will be described.

<During normal operation>
The output voltage _{V O} by dividing, divided voltage FB is input to the negative input terminal of the error amplifier Error AMP, a current corresponding to the error of the reference voltage Vref2 of the reference voltage source RVS2 is output to the impedance element Z, Converted to error voltage. The reference voltage Vref2 is a voltage corresponding to a desired output voltage.

The error voltage is added by the adder Adder2 with the sawtooth wave output from the sawtooth wave generation circuit RAMP, and compared with a voltage according to the current i _LS by the comparator CMP2, and a signal with a duty according to the error voltage is given to the flip-flop FF1. The PWM signal is output from the flip-flop FF1 in synchronization with the clock signal CLK. This PWM signal is input to the MOS transistor Nch via the buffer BUF1, and is input to the MOS transistor Pch via the OR circuit OR and the buffer BUF2. During normal operation, the output of the adder Adder1 is higher than the reference voltage Vref1, and the comparator CMP1 outputs high. That is, since the flip-flops FF2 and FF3 each output high, and the NOR circuit NOR outputs low to the OR circuit OR, the output of the comparator CMP1 is disabled.

  FIG. 4 shows waveforms from nodes a to f during this normal operation.

  As shown in FIG. 4, a goes down at the rising timing of the clock signal CLK, and b becomes a triangular wave that repeats falling and rising in synchronization with the rising of the clock signal CLK. Then, a goes down, b goes up, and when a touches b, a goes back to the level before the descent. Further, f obtained by adding b and e is larger than the reference voltage Vref1, and a PWM signal having a duty corresponding to the error voltage output from the comparator CMP2 is output to c and d, and the MOS transistors Nch and Pch are normally connected. The switching operation is performed.

<When preventing backflow>
When the load _RL becomes a light load, the sum of the current i _LS and the current i _LL is reduced and the sum signal of the adder Adder1 outputs the sum of b and e falls below the reference voltage Vref1, the comparator CMP1 becomes low. The flip-flops FF2 and FF3 are reset. Low is output from the flip-flops FF2 and FF3 and input to the NOR circuit NOR. The NOR circuit NOR outputs high and is input to the OR circuit OR. The OR circuit OR outputs high and is input to the MOS transistor Pch, and the MOS transistor Pch is turned off. That is, regardless of the PWM signal output from the PWM signal generation circuit PWMSG, the MOS transistor Pch is inputted with a high back-flow prevention signal, and the MOS transistor Pch is turned off.

  FIG. 5 shows waveforms up to nodes a to f when the backflow is prevented.

  As shown in FIG. 5, a has a rough waveform equivalent to that of normal operation. However, since the load is light, the feedback voltage FB is lowered and a is also lowered. b falls in contact with a earlier than in normal operation, and maintains a constant value when reaching the level at the rising edge of the clock signal CLK. That is, since it is a light load, the duty of c becomes small and b becomes a discontinuous mode. When f from which the addition signal of b and e is output falls below the reference voltage Vref1, high is added to c to generate d that is high, and d is supplied to the MOS transistor Pch. That is, regardless of the PWM signal of c, a backflow prevention signal that is a signal for turning off the MOS transistor Pch is input to d, and the MOS transistor Pch can be turned off.

  In this way, backflow can be prevented at light load by setting d high during the period of backflow when nothing is controlled.

The configuration and operation described above, DC-DC converter of this embodiment monitors the current flowing through the input-side coil L _S to the output side coil L _L, when the sum of these currents is smaller than a predetermined value Since the synchronous rectification MOS transistor Pch is turned off, it is possible to prevent a current from flowing backward from the output capacitor C _L to the output side coil L _L at a light load. That is, the present embodiment, on the basis of the current flowing through the input-side coil L _S to the output side coil L _L, synchronized due to so as to turn off the rectifying MOS transistor Pch, the output-side coil L from the output capacitor C _L at light loads _It is possible to prevent a current from flowing backward through _L.

Further, since the current flowing through the output terminal is not monitored, but only the currents of the input side coil L _S and the output side coil L _L are monitored, the power loss is small and the configuration is simple.

(Embodiment 2)
(Constitution)
FIG. 6 is a circuit diagram of a DC-DC converter according to Embodiment 2 of the present invention.

  The DC-DC converter of the present embodiment further includes a storage unit MC that stores whether the control circuit CC of the first embodiment has performed synchronous rectification in the past switching cycle.

  When the memory unit MC stores that the synchronous rectification has been performed, the reference voltage Vref1 is set to a small value in the current switching cycle after the past switching cycle, and the synchronous rectification is not performed. In the current switching cycle, the reference voltage Vref1 is set to a large value.

  Specifically, in the past switching cycle, the memory unit MC indicates that the MOS transistor Pch is turned on and performs a synchronous rectification operation to indicate an on state (synchronous rectification state), and the MOS transistor Pch is turned on. When the asynchronous rectification operation is performed without storing the state signal, the state signal indicating the off state (asynchronous rectification state) is stored.

  The reference voltage source RVS1 that generates the reference voltage Vref1 can be composed of a plurality of reference voltage generation circuits that generate reference voltages having different voltage values and a selector. The selector selects one of the plurality of reference voltage generation circuits according to the value of the state signal so that the reference voltage Vref1 according to the state signal can be output. The reference voltage source RVS1 that generates the reference voltage Vref1 can also be configured by a resistor divider circuit that divides the reference voltage and the ground voltage and a selector.

  Here, the switching cycle is a cycle in which the MOS transistors Nch and Pch are turned on and off once, and means a cycle of the PWM signal and the clock signal CLK.

  The memory unit MC is composed of a latch LC and a flip-flop FF4. In the current switching cycle, a signal given to each of the MOS transistors Nch and Pch is stored as a status signal in the latch LC, and in the next switching cycle, the flip-flop The FF 4 outputs a status signal to the reference voltage source RVS1. The reference voltage Vref1 changes according to the state signal.

  When the MOS transistor Pch is turned on, that is, when it is low, the output of the latch becomes low, and the flip-flop FF4 outputs low to the reference voltage source RVS1 in the next switching cycle. When the output of the flip-flop FF4 is low, the value of the reference voltage Vref1 is set small, and when it is high, it is set large. The reference voltage source RVS1 is realized by switching two or more reference voltages Vref1 each having a different voltage value according to the output of the flip-flop FF4.

  That is, when the MOS transistor Nch is turned off and the MOS transistor Pch is turned on, that is, when low is input to the MOS transistor Nch and low is input to the MOS transistor Pch, this signal indicates that a synchronous rectification operation has been performed. The latch LC outputs low as a status signal indicating that the synchronous rectification operation has been performed, and the flip-flop FF4 outputs low in the next switching cycle. The reference voltage Vref1 is set to a small value.

  When the MOS transistor Nch is turned off and the MOS transistor Pch is not turned on, that is, when low is input to the MOS transistor Nch and high is input to the MOS transistor Pch, these signals have undergone asynchronous rectification (no synchronous rectification is performed). Shows). As a status signal indicating that the asynchronous rectification operation has been performed, the latch LC outputs high, and the flip-flop FF4 outputs high in the next switching cycle. The reference voltage Vref1 is set to a large value.

  By the way, when the MOS transistor Pch is turned on while a forward current flows at light load (when synchronous rectification is performed by the MOS transistor Pch at light load) and when it is not turned on (diode D1 at light load). When the rectification is performed only), the loss is reduced when the MOS transistor Pch is turned on because the ON voltage of the MOS transistor Pch is smaller than the forward voltage of the diode D1.

When the loss is reduced, the power can be supplied to the output. If the input power is the same between when the loss is small and when the loss is large, the output power increases when the loss is small. If the loss is small, the duty of the PWM signal input to the MOS transistor Nch becomes small so that the input power becomes small when the load _RL uses the power supplied to the output constantly. On the other hand, if the loss is large, the duty of the PWM signal is increased so that the input power is increased.

That is, when synchronous rectification is performed by the MOS transistor Pch at light load, the output voltage V _O is maintained by shortening the time for which the MOS transistor Nch is turned on, and when rectification is performed only by the diode D1 at light load, The output voltage _VO is maintained by lengthening the time during which the transistor Nch is turned on. Since the duty of the PWM signal is different between the state where synchronous rectification is performed by the MOS transistor Pch (synchronous rectification state) and the state where rectification is performed only by the diode D1 (asynchronous rectification state), the MOS transistor Nch is turned on and the coil L The amount of charging current charged in _S and L _L is different between the synchronous rectification state and the asynchronous rectification state. Therefore, when a load change occurs near the boundary between the synchronous rectification state and the asynchronous rectification state, the synchronous rectification state and the asynchronous rectification state are alternately changed, and the amount of current supplied to the load _RL changes. That is, when the synchronous rectification state and the backflow prevention state coexist, the output voltage V _O changes by an amount corresponding to the difference between the duty of the PWM signal in the synchronous rectification state and the duty of the PWM signal in the asynchronous rectification state.

In the current switching cycle, when the MOS transistor Pch is turned on, that is, when the load is not light, the output voltage _VO is stable and the load current is properly supplied to the load _RL . That is, there is a possibility that _VO is stable in the next switching cycle instead of a light load.

  In the DC-DC converter according to the second embodiment, when the signal input to the MOS transistor Pch is low, the normal operation can be maintained more by lowering the reference voltage Vref1 in the next switching cycle.

Further, the output voltage V _O of the output capacitor C _L when a light load is high, there may not be fully down the output voltage V _O at light load in the next switching cycle in reverse flow easily state.

  Therefore, when the signals input to the MOS transistors Nch and Pch are both high, the asynchronous rectification operation can be further maintained by raising the reference voltage Vref1 in the next switching cycle.

  That is, in the DC-DC converter according to the second embodiment, when synchronous rectification is performed by turning on the synchronous rectification MOS transistor Pch in the past switching cycle, in the current switching cycle after the past switching cycle. When the reference voltage Vref1 is set small and the asynchronous rectification operation is performed without turning on the synchronous rectification MOS transistor Pch in the past switching cycle, the reference voltage Vref1 is set large in the current switching cycle.

Thus, even in the event the load fluctuation in the vicinity of the boundary of the synchronous rectification state and non-synchronous state, a stable V _O duty of the PWM signal to MOS transistor Nch corresponding to, it is possible to output respective Pch, synchronous rectification The fluctuation of the output voltage corresponding to the difference between the duty of the PWM signal in the state and the duty of the PWM signal in the asynchronous rectification state can be suppressed.

  In other words, when a load change occurs alternately between the synchronous rectification state and the asynchronous rectification state, the amount corresponding to the difference between the duty of the PWM signal in the synchronous rectification state and the duty of the PWM signal in the asynchronous rectification state Since the adaptation time of the output voltage due to the fluctuation of the output voltage can be omitted, the time from when the output voltage changes until it becomes stable can be shortened.

  In addition to the effects of the first embodiment, the DC-DC converter of the present embodiment suppresses fluctuations in the output voltage corresponding to the difference between the duty of the PWM signal in the synchronous rectification state and the duty of the PWM signal in the asynchronous rectification state. There is an effect that can be.

(Specific example of control circuit)
Hereinafter, a specific example of the control circuit will be described.

  FIG. 7 is a circuit diagram illustrating a specific control circuit.

  In the control circuit CC of the first embodiment, the outputs of the buffers BUF1 and BUF2 are input to the latch LC, the output of the latch LC is input to the flip-flop FF4, and the output of the flip-flop FF4 is input to the reference voltage source RVS1 It is. The clock signal CLK is shared with the flip-flops FF1 and FF2. In this case, the latch LC is composed of a NOR circuit and an inverter that are a set of predecessors.

(Operation)
Hereinafter, the operation of the second embodiment will be described.

<During normal operation>
The same as in the first embodiment.

<When preventing backflow>
FIG. 8 is a timing chart at the time of the asynchronous rectification operation when the reference voltage Vref1 to be compared with the total value of the coil currents changes to a high level.

  As shown in the second period in FIG. 8, when f does not exceed the reference voltage Vref1 during one switching cycle of the clock signal CLK, the reference voltage Vref1 is set high in the next period.

In the first switching cycle, f, which is the sum of b and e, exceeds the reference voltage Vref1 and falls again, so that the duty of the PWM signal changes and the amount of charging current charged in the coils L _S and L _L decreases. In the second switching cycle, f is always lower than the reference voltage Vref1. At the rising edge of the clock signal CLK in the second period, both c and d become high, and d remains high during the second switching cycle. After the second switching cycle, the input terminal D of the flip-flop FF4 becomes high, and the Q terminal of the flip-flop FF4 becomes high in the third switching cycle. Thereby, the reference voltage Vref1 is also increased, and it is possible to easily generate a period in which the MOS transistor Pch is not turned on continuously.

  FIG. 9 is a timing chart at the time of asynchronous rectification when the reference voltage Vref1 to be compared with the total value of each coil current changes to a low level.

  As shown in the second period of FIG. 9, when f exceeds the reference voltage Vref1 for one period of the clock signal CLK, the voltage of the reference voltage Vref1 is set low in the next period.

In the first switching cycle, f, which is the sum of b and e, is always lower than the reference voltage Vref1, so that the duty of the PWM signal changes and the amount of charging current charged in the coils L _S and L _L increases. In the switching cycle of the period, f exceeds the reference voltage Vref1 in a part of the section. When the error voltage of the comparator CMP2 is switched, since both c and d become low, the input D of the flip-flop FF4 becomes low. The Q terminal of the flip-flop FF4 becomes low at the rising edge of the clock signal CLK in the third switching cycle. As a result, the reference voltage Vref1 also decreases, and it is possible to easily generate a period in which the MOS transistor Pch is turned on continuously.

  In the present embodiment, the reference voltage Vref1 is binary, and when the reference voltage Vref1 is set to a low value, if f does not exceed the reference voltage Vref1 during one switching cycle, the next cycle During the switching cycle, the reference voltage Vref1 is set to a high value. If f exceeds the reference voltage Vref1 during one switching cycle, the reference voltage Vref1 is maintained at a low value during the next switching cycle.

  Also, when the reference voltage Vref1 is set to a high value, if f does not exceed the reference voltage Vref1 during one switching cycle, the reference voltage Vref1 is set to a high value during the next switching cycle. To maintain. If f exceeds the reference voltage Vref1 during one switching cycle, the reference voltage Vref1 is set to a low value during the next switching cycle.

  That is, the memory unit MC constitutes a state machine and performs hysteresis control so as not to cross the reference voltage Vref1 in successive switching cycles.

As described above, when the period in which the MOS transistor Pch is not turned on is entered, the MOS transistor Pch can be kept off by increasing the reference voltage Vref1. In addition, when the MOS transistor Pch is turned on, the reference voltage Vref1 is lowered to make it difficult for the MOS transistor Pch to be turned off, and the MOS transistor Pch is turned on easily. On the other hand, the fluctuation of the output voltage corresponding to the difference between the duty of the PWM signal in the synchronous rectification state and the duty of the PWM signal in the backflow prevention state can be suppressed. That is, the time until the output voltage _VO becomes stable can be shortened.

  With the configuration and operation described above, the DC-DC converter according to the present embodiment has an effect corresponding to the difference between the duty of the PWM signal in the synchronous rectification state and the duty of the PWM signal in the asynchronous rectification state in addition to the effect of the first embodiment. There is an effect that fluctuation of the output voltage can be suppressed.

  In the present embodiment, the logical value input to the MOS transistor Nch and the logical value input to the MOS transistor Pch are latched to store whether synchronous rectification has been performed in the past switching cycle. However, the determination signal output from the comparator CMP1 may be latched. However, in the configuration in which the logical value input to the MOS transistor Nch and the logical value input to the MOS transistor Pch are latched, even if the determination signal fluctuates instantaneously (from high to low for a moment, the high level again However, since the logical value is maintained for one switching cycle in synchronization with the clock CLK, it can be latched stably.

  The present invention can be suitably used in the field of power supply systems.

CC control circuit PWMSG PWM signal generation circuit CMP comparator RVS reference voltage source Nch, Pch MOS transistor R _L load RAMP sawtooth wave generation circuit Z impedance element MC storage unit LC latch S current voltage conversion unit

Claims (7)

In a DC-DC converter which is a synchronous rectification type SEPIC,
A control circuit for adjusting a period during which the synchronous rectification MOS transistor is turned off during rectification based on the current value of the first current flowing through the input side coil and the current value of the second current flowing through the output side coil A DC-DC converter comprising:   The control circuit turns off the synchronous rectification MOS transistor when the sum of the current value of the first current and the current value of the second current becomes smaller than a predetermined value. The DC-DC converter according to claim 1, wherein The control circuit includes:
A first current-voltage converter that converts the first current into a first voltage;
A second current-voltage converter for converting the second current into a second voltage;
An adder for adding the first voltage and the second voltage;
A determination unit that compares the output of the addition unit with a reference voltage corresponding to the predetermined value and outputs a determination signal;
The DC-DC converter according to claim 2, wherein the synchronous rectification MOS transistor is turned off according to the determination signal. The control circuit further includes a storage unit that stores whether synchronous rectification has been performed in the first switching cycle,
In the second switching cycle after the first switching cycle, when the storage unit stores that the synchronous rectification has been performed, the predetermined value is set to a smaller value, The predetermined value is set to a larger value in the second switching cycle when it is stored that synchronous rectification has not been performed. 4. The DC-DC converter described in 1.   The storage unit latches the first logical value input to the input-side MOS transistor and the second logical value input to the synchronous rectification MOS transistor in the first switching cycle, thereby latching the first logical value. The DC-DC converter according to claim 4, wherein whether or not synchronous rectification has been performed is stored. The synchronous rectification type SEPIC is
A first coil, a capacitor and a second coil connected in series from the input terminal to the ground in order, a first MOS transistor connected between the connection between the first coil and the capacitor and the ground; A second MOS transistor connected between a connection portion between the capacitor and the second coil and an output terminal; a diode connected in parallel to the second MOS transistor;
The first coil is the input side coil;
The second coil is the output coil;
The first MOS transistor is the input-side MOS transistor;
6. The DC-DC converter according to claim 1, wherein the second MOS transistor is the synchronous rectification MOS transistor. 7.   The control circuit outputs a control signal for controlling on / off of the input side MOS transistor and the synchronous rectification MOS transistor according to an output voltage output from an output terminal of the DC-DC converter. The DC-DC converter according to any one of claims 1 to 6.

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