JP4337060B2 - Switching power supply device and its control device - Google Patents

Description

  The present invention relates to a switching power supply device and a control device therefor, and more particularly to a DC-DC type switching power supply device that controls an output voltage by a PFM (pulse frequency modulation) method.

In general, a portable electronic device includes a DC-DC converter for converting a voltage generated in a battery into a desired power supply voltage of an electronic circuit.
The voltage of the battery changes according to the remaining amount, and for example, changes in the range of 4.2V to 3V in a lithium ion battery. When an external power source such as an AC adapter is used without using the built-in battery, a voltage of about 5 V may be input instead of the battery voltage. The DC-DC converter is configured to generate a constant output voltage even when such a change in input voltage occurs.

  DC-DC converters are generally classified into three types: a step-down type, a step-up type, and a step-up / down type. When the lower limit value of the input voltage is higher than the target value of the output voltage, it is a step-down type, when the upper limit value of the input voltage is lower than the target value of the output voltage, the boost type, and when the input voltage is higher or lower than the output voltage When both are present, the buck-boost type is selected.

  On the other hand, in order to reduce battery consumption as much as possible in portable electronic devices, a standby mode is generally provided in which a part of the circuit operation is stopped when not in use. In the standby mode, the load of the DC-DC converter becomes very light. Therefore, the PFM (pulse frequency modulation) method is more advantageous in terms of power saving than the PWM (pulse width modulation) method in which switching is always performed at a constant period.

Regarding the PFM type switching power supply, there is the following Patent Document 1.
Patent Document 1 describes a technique for reducing the ripple voltage when the power supply voltage is high by providing power supply voltage dependency to the duty ratio of the PFM.
Japanese Patent Laid-Open No. 11-235023

  By the way, generally, a voltage corresponding to the difference between the input voltage and the output voltage is applied to an inductor responsible for an energy conversion operation in a DC-DC converter. In the PFM method, the period during which the voltage is applied to the inductor in one cycle of the switching operation is fixed, and the output voltage is controlled by changing the repetition period of this fixed period.

However, if the input voltage fluctuates while the output voltage is controlled to be constant, the potential difference between the input and output changes, and the voltage applied to the inductor changes. In the case of the PFM method, since the time for applying a voltage to the inductor is fixed, when the voltage value changes, the temporal change rate of the current flowing through the inductor changes, and the amplitude of the ripple of the output voltage changes. For example, when the voltage difference between the input and output increases, the voltage applied to the inductor increases, and the temporal change rate of the current flowing through the inductor increases. Therefore, when the time for applying the voltage to the inductor is fixed, the ripple of the output voltage increases as the input / output voltage difference increases. That is, the PFM type DC-DC converter has a problem that the ripple of the output voltage varies greatly according to the input voltage.
In recent years, the power supply voltage of electronic circuits has been steadily decreasing, and the ripple of the power supply voltage has come to have a great influence on the reliability of the device. Therefore, stricter control of the ripple voltage has been demanded.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a switching power supply apparatus and a control apparatus for the switching power supply apparatus that can suppress fluctuations in output voltage ripples in response to fluctuations in input voltage.

The switching power supply according to the first aspect of the present invention includes a switching converter circuit, a control circuit, and a threshold adjustment circuit.
The switching converter circuit includes at least one inductor, and has a first state in which electric power input from an input terminal is accumulated in the inductor and a second state in which electric power accumulated in the inductor is discharged from an output terminal. It repeats alternately, and the DC voltage applied to the input terminal is boosted or lowered by the repetitive operation and output from the output terminal.
The control circuit sets the switching converter circuit to the second state when the voltage at the output terminal is higher than a target value, and sets the switching converter circuit to a predetermined value when the voltage at the output terminal falls below the target value. Is set to the first state for the period of time, and then returned to the second state. When the current of the inductor is larger than the threshold value, the switching converter circuit is set to the second state.
The threshold adjustment circuit is configured to reduce a change in the ripple voltage of the output terminal accompanying a change in the ratio or difference according to a ratio or difference between the voltage of the input terminal and the voltage of the output terminal. Adjust the threshold.

  A second aspect of the present invention relates to a control device for the switching converter circuit, and includes the control circuit and the threshold adjustment circuit.

The switching power supply device according to the first aspect and the control device according to the second aspect determine whether or not the current of the inductor is larger than a threshold value corresponding to an input threshold signal. One determination circuit may be included.
The threshold adjustment circuit includes: a first voltage dividing circuit that divides the voltage at the input terminal by a plurality of voltage dividing ratios; a plurality of voltages divided by the first voltage dividing circuit; A comparison circuit that compares a voltage or a predetermined voltage and a signal generation circuit that generates the threshold signal based on a comparison result of the comparison circuit may be included.

In addition, the switching power supply device according to the first aspect and the control device according to the second aspect may include a second determination circuit that determines whether or not the voltage at the output terminal is lower than the target value. .
The control circuit holds a signal having a first value when the first determination circuit determines that the voltage at the output terminal is lower than the target value, and cycles the signal in synchronization with an input clock signal. When the signal holding circuit resets to the second value and the signal holding circuit holds the signal of the first value, the switching converter circuit is set to the first state, and the signal holding circuit When a signal having a value of 2 is held, a control signal generation circuit that generates a control signal for setting the switching converter circuit to the second state may be included.
Furthermore, when the first determination circuit determines that the current of the inductor is larger than the threshold value, the signal holding circuit outputs the signal having the second value until the reset operation is performed at least once. May be held.

  According to the present invention, when the current flowing through the inductor of the switching converter circuit increases, control is performed to release the power stored in the inductor, and the threshold value of the inductor current set for the control is set as the input voltage. By adjusting according to the ratio or difference between the output voltage and the output voltage, fluctuations in the ripple of the output voltage according to fluctuations in the input voltage can be suppressed.

  First, the configuration of a switching power supply device according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a diagram illustrating an example of a configuration of a switching power supply apparatus according to an embodiment of the present invention.
1 includes a switching converter circuit 10, an operation mode determination circuit 20, a voltage determination circuit (second determination circuit) 30, a current determination circuit (first determination circuit) 40, and a threshold adjustment. A circuit 50 and a control circuit 60 are included.
FIG. 2 shows an example of the configuration of the voltage determination circuit 30, the current determination circuit 40, and the control circuit 60 among these components. FIG. 3 shows an example of the configuration of the threshold adjustment circuit 50.

[Switching converter circuit 10]
The switching converter circuit 10 boosts or steps down the voltage Vin input to the terminal Ti by a switching operation and outputs the voltage Vin from the terminal To as the voltage Vout. The switching converter circuit 10 includes at least one inductor, a state in which power input from the terminal Ti is stored in the inductor (first state), and a state in which the power stored in the inductor is discharged from the terminal To (first state). 2), the voltage Vin is stepped up or stepped down alternately.

  For example, as shown in FIG. 1, the switching converter circuit 10 includes an inductor L1, a p-type MOS MOS transistor Q1, n-type MOS MOS transistors Q2 and Q4, a diode D1, and an output smoothing capacitor C1.

The source of the MOS transistor Q1 is connected to the terminal Ti, and the drain thereof is connected to one terminal of the inductor L1.
The source of the MOS transistor Q2 is connected to the reference potential VSS, and the drain thereof is connected to one terminal of the inductor L1 and the drain of the MOS transistor Q1.
The cathode of the diode D1 is connected to the terminal To, and its anode is connected to the other terminal of the inductor L1.
The source of the MOS transistor Q4 is connected to the reference potential VSS, and the drain thereof is connected to the other terminal of the inductor L1 and the drain of the MOS transistor Q3.

  The capacitor C1 is connected between the output terminal To and the reference potential VSS.

  The switching converter circuit 10 shown in FIG. 1 can perform a step-up / step-down operation. When stepping down, the MOS transistor Q4 is always turned off, and the MOS transistors Q1 and Q2 are complementarily controlled on and off (FIG. 4). When boosting, the MOS transistor Q1 is always on, the MOS transistor Q2 is always off, and the MOS transistor Q4 is on / off controlled (FIG. 5).

[Operation Mode Determination Circuit 20]
The operation mode determination circuit 20 determines a mode (step-up / step-down) in which the switching converter circuit 10 should operate based on the input voltage Vin and the output voltage Vout. That is, when the input voltage Vin is higher than the output voltage Vout, it is determined that the mode is a step-down operation, and when the input voltage Vin is lower than the output voltage Vout, it is determined that the mode is a step-up operation.

[Voltage determination circuit 30]
The voltage determination circuit 30 determines whether or not the voltage at the output terminal To is lower than a predetermined target value. For example, the voltage Vout at the output terminal To is detected and compared with a target value, and a signal SA that is at a high level when the voltage Vout is lower than the target value and at a low level when the voltage Vout is higher than the target value is output.

For example, as shown in FIG. 2, the voltage determination circuit 30 includes a comparator 31 and resistors R1 and R2.
The resistors R1 and R2 are connected in series between the terminal To and the reference potential VSS, and divide the output voltage Vout.
The comparator 31 compares the voltage generated at the connection point of the resistors R1 and R2 with the reference voltage Vref, and outputs the comparison result as a signal SA. That is, when the voltage at the connection point is lower than the reference voltage Vref, a high level signal SA is output, and when it is higher than the reference voltage Vref, a low level signal SA is output.

[Current determination circuit 40]
Current determination circuit 40 determines whether or not the current flowing through inductor L1 of switching converter circuit 10 is greater than a predetermined threshold value corresponding to threshold signal Sth. For example, the voltage at the connection point between the MOS transistor Q1 and one terminal of the inductor L1 is detected, and the detected voltage is compared with the threshold signal Sth. The voltage at the connection point decreases when a current flows through the MOS transistor Q1. As a result, according to this comparison result, a signal SC that is high when the current flowing through the inductor L1 is higher than a predetermined threshold and low when it is lower than the predetermined threshold is output.

The current determination circuit 40 includes a comparator 41 as shown in FIG.
Comparator 41 compares the voltage at the connection point between MOS transistor Q1 and one terminal of inductor L1 with threshold signal Sth, and outputs the comparison result as signal SC. That is, when the output signal of the comparator 41 is lower than the threshold signal Sth, a high level signal SC is output, and when it is higher than the threshold signal Sth, a low level signal SC is output.

[Control circuit 60]
The control circuit 60 controls the switching operation of the switching converter circuit 10.
For example, the control unit 60 determines an operation mode (step-up or step-down) based on the determination result of the operation mode determination circuit 20, and controls the switching converter circuit 10 according to a predetermined control sequence in the determined mode. That is, the gates of the MOS transistors Q1 to Q4 are driven according to a control sequence determined for each operation mode so that the output voltage Vout approaches a predetermined target value.

When the voltage determination circuit 30 determines that the voltage Vout at the terminal To is higher than the target value, the control unit 60 enters a state where the power accumulated in the inductor L1 is discharged from the terminal To (second state). The switching converter circuit 10 is controlled. On the other hand, when the voltage determination circuit 30 determines that the voltage Vout at the terminal To has decreased below the target value, the power input from the terminal Ti is stored in the inductor L1 (first state). After switching converter circuit 10 is controlled and this state is maintained for a predetermined time, switching converter circuit 10 is returned to the second state.
According to the above control, when the voltage Vout of the terminal To becomes lower than the target value, a voltage is applied to the inductor L1 for a predetermined time, and after the predetermined time has elapsed, the power accumulated in the inductor L1 is changed to the terminal To. Released from. In other words, a PFM switching operation in which the repetition period of power storage and discharge in the inductor L1 changes according to the error from the target value of the voltage Vout is realized.

  Further, when the current determination circuit 40 determines that the current of the inductor L1 is larger than the threshold value set by the threshold signal Sth, the control unit 60 sets the switching converter circuit 10 to the second state described above. Thus, the electric power stored in the inductor L1 is discharged to the terminal To.

  As shown in FIG. 2, for example, the control unit 60 includes latch circuits 61 and 62, an inverter circuit 63, an AND circuit 64, and a control signal generation circuit 65.

The latch circuit 61 holds the output signal SB at a high level when the signal SA of the voltage determination circuit 30 rises from a low level to a high level while the clock signal CK is at a low level. When the clock signal CK becomes high level, the output signal SB is reset to low level.
The latch circuit 62 holds the output signal SD at a high level when the signal SC of the current determination circuit 40 rises from a low level to a high level while the clock signal CK is at a low level. When the clock signal CK becomes high level, the output signal SD is reset to low level.
The inverter circuit 63 logically inverts the output signal SD of the latch circuit 62.
The AND circuit 64 outputs a logical product of the output signal SB of the latch circuit 61 and the output signal of the inverter circuit 63 as a signal SE.

The latch circuits 61 and 62, the inverter circuit 63, and the AND circuit 64 constitute a circuit (signal holding circuit) that holds the signal SE corresponding to the determination results of the voltage determination circuit 30 and the current determination circuit 40.
That is, this signal holding circuit holds the signal SE at a high level when the voltage determination circuit 30 determines that the voltage Vout at the terminal To is lower than the target value. Further, the signal SE is periodically reset to a low level in synchronization with the clock signal CK. Further, when the current determination circuit 40 determines that the current of the inductor L1 is larger than the threshold value, the signal SE is held at the low level until the above-described periodic reset operation is performed at least once.

  The control signal generation circuit 65 sets the switching converter circuit 10 to the first state (a state in which power is input from the terminal Ti to the inductor L1) when the signal SE is at a high level, and when the signal SE is at a low level. Then, a control signal for setting the switching converter circuit 10 to the second state (a state in which the electric power stored in the inductor L1 is discharged to the terminal To) is generated.

For example, when the determination result of the operation mode determination circuit 20 is the step-down operation mode, the control signal generation circuit 65 sets the signal SD2 supplied to the gate of the MOS transistor Q4 to a low level and turns off the MOS transistor Q4. In this case, if the signal SE is at a high level, the signal SD1 supplied to the gates of the MOS transistors Q1 and Q2 is set at a low level, the MOS transistor Q1 is turned on, the MOS transistor Q2 is turned off, and the signal SE is at a low level. If so, the signal SD1 is set to a high level to turn off the MOS transistor Q1 and turn on the MOS transistor Q2.
On the other hand, when the determination result of the operation mode determination circuit 20 is the step-up operation mode, the control signal generation circuit 65 sets the signal SD1 to a low level to turn on the MOS transistor Q1 and turn off the MOS transistor Q2. In this case, if the signal SE is at a high level, the signal SD2 is set to a high level to turn on the MOS transistor Q4. If the signal SE is at a low level, the signal SD2 is set to a low level and the MOS transistor Q4 is turned on. Turn off.

[Threshold adjustment circuit 50]
The threshold adjustment circuit 50 adjusts the threshold signal Sth according to the ratio between the input voltage Vin and the output voltage Vout so that the change in the ripple voltage at the terminal To accompanying the change in the voltage ratio becomes small.
When the difference between the input voltage Vin and the output voltage Vout increases (the voltage ratio deviates from “1”), the voltage applied to the inductor L1 of the switching converter circuit 10 increases, and the temporal change rate of the current flowing through the inductor L1 Becomes larger. In this case, for example, by increasing the threshold value of the current determination circuit 40, the time for which the switching converter circuit 10 is held in the first state is prevented from becoming extremely short. On the other hand, when the difference between the input voltage Vin and the output voltage Vout is small (the voltage ratio approaches “1”), the temporal change rate of the current flowing through the inductor L1 is small. By lowering the threshold value of the circuit 40, the time for holding the switching converter circuit 10 in the first state is prevented from becoming too long.
The threshold adjustment circuit 50 suppresses a change in the ripple voltage at the terminal To by adjusting the threshold signal Sth according to the voltage ratio between the input voltage Vin and the output voltage Vout, for example.

  As shown in FIG. 3, for example, the threshold adjustment circuit 50 includes voltage dividing circuits 51 and 53, a selection circuit 52, a comparator 54, and a signal generation circuit 55.

The voltage dividing circuit 51 divides the input voltage Vin by five voltage dividing ratios K1 to K5. For example, as shown in FIG. 3, it is constituted by six (R11,..., R16) connected in series between the terminal Ti and the reference potential VSS. The divided voltages (“K1 · Vin”,..., “K5 · Vin”) are generated at the connection points of the resistors R11 to R16.
The voltage dividing circuit 53 divides the output voltage Vout by the voltage dividing ratio α. For example, as shown in FIG. 3, it is configured by two resistors (R22, R23) connected in series between the terminal To and the reference potential VSS. The divided voltage (α · Vin) is generated at the connection point of the resistors R22 and R23.

  The selection circuit 52 selects and outputs one voltage in order from the voltages (K1 · Vin,..., K5 · Vin) divided by the voltage dividing circuit 51.

  The comparator 54 sequentially compares the output voltage of the voltage dividing circuit 51 selected by the selection circuit 52 and the output voltage (α · Vout) of the voltage dividing circuit 53.

The signal generation circuit 55 generates the threshold signal Sth based on the comparison result of the comparator 54 corresponding to each of the voltages (K1 · Vin,..., K5 · Vin) divided by the voltage dividing circuit 51.
That is, the signal generation circuit 55 compares each comparison result between the voltage “α · Vout” output from the voltage dividing circuit 53 and the voltages “K1 · Vin”,..., “K5 · Vin” output from the selection circuit 52. The threshold value signal Sth is generated from the comparator 54 and based on the five comparison results.

  For example, the comparison result that the output voltage “α · Vout” of the voltage dividing circuit 53 is larger than “K1 · Vin” and “K2 · Vin” and smaller than “K3 · Vin”, “K4 · Vin”, and “K5 · Vin”. Is obtained, the input / output voltage ratio “Vout / Vin” falls within the range of “K2 / α” to “K3 / α”. Therefore, the signal generation circuit 55 generates a predetermined threshold signal Sth corresponding to this voltage ratio range.

  The signal generation circuit 55 is, for example, a latch circuit that holds the above five comparison results output from the comparator 54 as a binary code, and data that converts the binary code held in the latch circuit into binary threshold data. A conversion circuit and an analog / digital converter that converts threshold data output from the data conversion circuit into an analog threshold signal Sth can be used.

  Next, the operation of the switching power supply device according to this embodiment having the above-described configuration will be described.

  First, the step-up / step-down operation of the switching converter circuit 10 will be described.

FIG. 4 shows the state of each transistor of the switching converter circuit 10 during the step-down operation.
As shown in FIG. 4, the MOS transistor Q4 is always turned off. MOS transistors Q1 and Q2 are turned on and off in a complementary manner.
When the MOS transistor Q1 is turned on and the MOS transistor Q2 is turned off (FIG. 4A), the terminal Ti is connected to the terminal To via the inductor L1. In the step-down operation, since the terminal Ti is at a higher potential than the terminal To, the diode D1 is biased forward and turned on. When the diode D1 is turned on, a voltage corresponding to the difference between the input voltage Vin and the output voltage Vout is applied to the inductor L1, and the power input from the terminal Ti is accumulated (first state).
On the other hand, when the MOS transistor Q2 is turned on and the MOS transistor Q1 is turned off (FIG. 4B), the inductor L1 is disconnected from the terminal Ti and connected to the reference potential VSS. Thereby, the electric power stored in the inductor L1 is discharged to the capacitor C1 via the diode D1 (second state).

FIG. 5 shows the state of each transistor of the switching converter circuit 10 during the boosting operation.
As shown in FIG. 5, in the step-up operation, the MOS transistor Q1 is always on and the MOS transistor Q2 is always off.
When the MOS transistor Q4 is turned on (FIG. 5B), the inductor L1 is connected between the terminal Ti and the reference potential VSS. As a result, the input voltage Vin is applied to the inductor L1, and the power input from the terminal Ti is accumulated (first state).
On the other hand, when the MOS transistor Q4 is turned off (FIG. 5C), the inductor L1 is disconnected from the reference potential VSS and connected to the terminal To via the diode D1. Thereby, the electric power stored in the inductor L1 is discharged to the capacitor C1 via the diode D1 (second state).

  Next, control of the switching converter circuit 10 by the control circuit 60 will be described.

FIG. 6 is a diagram illustrating an example of the timing relationship of each signal in the control circuit 60.
The clock signal CK (FIG. 6A) repeats a high level (time T1) and a low level (time T2) at a constant period Tc.
When the output voltage Vout becomes lower than the target value at time t1 and the output signal SA (FIG. 6B) of the voltage determination circuit 30 becomes high level, the latch circuit 61 receives a high level signal SB (FIG. 6C). ) Is held. At this time, the low level signal SD (FIG. 6E) is held in the latch circuit 62, and the output signal SE (FIG. 6F) of the AND circuit 64 becomes high level. When the signal SE becomes high level, the switching converter circuit 10 is set to the first state by the control signal generation circuit 65, and the power input from the terminal Ti is accumulated in the inductor L1.

Next, when the voltage at one terminal of the inductor L1 becomes lower than the threshold set by the threshold signal Sth at time t2, the output signal SC (FIG. 6D) of the current determination circuit 40 becomes high. The latch circuit 62 holds the high level signal SD. As a result, the output signal SE of the AND circuit 64 becomes low level, and the switching converter circuit 10 is set to the second state.
When the switching converter circuit 10 enters the second state, the power stored in the inductor L1 is released, so the current in the inductor L1 decreases, the voltage at one terminal of the inductor L1 increases, and the voltage becomes the threshold. It becomes higher than the value signal Sth. Therefore, immediately after time t2 (t3), the output signal SC of the current determination circuit 40 becomes low level. However, even if the signal SC becomes low level, the signal SD of the latch circuit 62 is held at high level, so that the switching converter circuit 10 is kept in the second state.

  When the clock signal CK becomes high level in this state, the signal SD of the latch circuit 62 is reset to low level. Thereafter, the above operation is repeated.

Thus, according to the present embodiment, when the voltage Vout at the terminal To is higher than the target value, the switching converter circuit 10 is set to the second state (a state in which the electric power accumulated in the inductor L1 is discharged to the terminal To). When the voltage Vout at the terminal To drops below the target value, the switching converter circuit 10 is set to the first state (a state in which the power input from the terminal Ti is accumulated in the inductor L1) for a predetermined time and then the first time. The state is returned to 2. When the current of inductor L1 exceeds a predetermined threshold value, switching converter circuit 10 is set to the second state.
Further, the threshold value for the current of the inductor L1 is adjusted according to the ratio of the input voltage Vin and the output voltage Vout so that the fluctuation of the ripple of the output voltage Vout accompanying the fluctuation of the ratio is suppressed. .

Therefore, even if an input voltage fluctuation (for example, a battery voltage drop) occurs in the switching converter circuit in which the output voltage is controlled by the PFM method, fluctuations in the output voltage ripple associated therewith can be suppressed to a minimum.
This also makes it possible to keep the output voltage accuracy constant in a switching power supply installed in equipment that cannot avoid fluctuations in the input voltage (such as portable electronic equipment that operates on batteries). It is possible to improve the performance.

  Next, a modification of the threshold adjustment circuit will be described.

FIG. 7 is a diagram illustrating a first modification of the threshold adjustment circuit.
In the threshold adjustment circuit 50 shown in FIG. 3, one voltage is selected in order from the voltages “K1 · Vin”,..., “K5 · Vin” output from the voltage dividing circuit 51 and input to the comparator 54. However, as shown in FIG. 7, for example, comparators 54-1,..., 54-5 corresponding to the voltages “K1 · Vin”,.

7 includes voltage dividing circuits 51 and 53, comparators 54-1,..., 54-5, and a signal generation circuit 55A.
The voltage dividing circuits 51 and 53 are the same components as the same reference numerals in FIG.
The comparators 54-1,..., 54-5 are respectively supplied with voltages “K1 · Vin”,..., “K5 · Vin” output from the voltage dividing circuit 51 and voltages “α · Vout” output from the voltage dividing circuit 52. ".
The signal generation circuit 55A generates a threshold signal Sth based on the comparison results of the comparators 54-1,..., 54-5.

  Since the threshold adjustment circuit 50A shown in FIG. 7 can simultaneously obtain the comparison result between the voltages “K1 · Vin”,..., “K5 · Vin” and the voltage “α · Vout”, the threshold shown in FIG. The threshold signal Sth can be generated faster than the adjustment circuit 50.

FIG. 8 is a diagram illustrating a second modification of the threshold adjustment circuit.
In the threshold adjustment circuits 50 and 50A shown in FIGS. 3 and 7, the threshold signal Sth is generated according to the ratio between the input voltage Vin and the output voltage Vout. For example, as shown in FIG. The threshold signal Sth may be generated according to the difference between the input voltage Vin and the output voltage Vout.

The threshold adjustment circuit 50B shown in FIG. 8 includes an amplifier circuit 56, an analog / digital converter 57, a data conversion circuit 58, and a digital / analog conversion circuit 59.
The amplifier circuit 56 amplifies the difference between the input voltage Vin and the output voltage Vout.
The analog / digital converter 57 converts the output signal of the amplifier circuit 56 into a digital signal.
The data conversion circuit 58 converts the digital signal output from the analog / digital converter 57 into threshold data. For example, it is constituted by a memory for storing threshold data corresponding to the value of the output signal of the analog / digital converter 57.
The digital / analog conversion circuit 59 converts the threshold data output from the data conversion circuit 58 into an analog threshold signal Sth.

  As mentioned above, although one Embodiment of this invention and its modification were demonstrated, this invention is not limited only to said form, Furthermore, various variations are included.

  In the above-described embodiment, a step-up / step-down circuit is cited as an example of the switching converter circuit 10, but the configuration of the switching converter circuit 10 is arbitrary in this embodiment. Therefore, when the lower limit value of the input voltage is higher than the target value of the output voltage, a boost converter circuit may be used. Conversely, when the upper limit value of the input voltage is lower than the target value, a boost converter circuit may be used.

  In the current determination circuit 40 shown in FIG. 2, the current of the inductor L1 is detected based on the ON voltage of the MOS transistor Q1, but the present invention is not limited to this. For example, the current flowing through the diode D1 may be detected. Further, an element having a minute resistance value may be provided in a path through which the current of the inductor L1 flows, and the current of the inductor L1 may be detected based on the voltage generated at the voltage at both ends thereof.

In the above-described embodiment, the output voltage Vout and the input voltage Vin are divided and compared, but the present invention is not limited to this. For example, in the case of only the step-down operation, the output voltage Vout may be used for comparison with the voltage divided by the voltage dividing circuit 51 without being divided.
Further, since the output voltage Vout is constant in the steady state, a constant reference voltage corresponding to the target value of the output voltage Vout may be used instead of the voltage obtained by dividing the output voltage Vout.
In the present invention, a MOS transistor whose on / off is controlled by the control signal generation circuit 65 may be used in place of the diode D1.

It is a figure which shows an example of a structure of the switching power supply device which concerns on embodiment of this invention. It is a figure which shows an example of a structure of a voltage determination circuit, a current determination circuit, and a control circuit. It is a figure which shows an example of a structure of a threshold value adjustment circuit. It is a figure for demonstrating the pressure | voltage fall operation | movement of a switching converter circuit. It is a figure for demonstrating the pressure | voltage rise operation of a switching converter circuit. It is a figure which shows an example of the timing relationship of each signal in a control circuit. It is a figure which shows the 1st modification of a threshold value adjustment circuit. It is a figure which shows the 2nd modification of a threshold value adjustment circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Switching converter circuit, 20 ... Operation mode determination circuit, 30 ... Voltage determination circuit, 40 ... Current determination circuit, 50, 50A, 50B ... Threshold adjustment circuit, Q1 ... p-type MOS transistor, Q2, Q4 ... n-type MOS transistor, D1 ... diode, C1, C2 ... capacitor, R1, R2, R11 to R15, R21, R22 ... resistor, 56 ... amplifier circuit, 31, 41, 42, 54, 54-1 to 54-5 ... comparator, 51, 53 ... Voltage divider circuit, 52 ... Selection circuit, 55, 55A ... Signal generation circuit, 57 ... Analog / digital converter, 58 ... Data conversion circuit, 59 ... Digital / analog converter, 61, 62 ... Latch circuit, 63 ... Inverter circuit, 64 ... AND circuit, 65 ... Control signal generation circuit, T1, T2 ... Terminal

Claims (8)

Including at least one inductor, alternately repeating a first state in which power input from an input terminal is stored in the inductor and a second state in which power stored in the inductor is discharged from an output terminal, A switching converter circuit that boosts or lowers the DC voltage applied to the input terminal by the repetitive operation and outputs the DC voltage from the output terminal;
When the voltage at the output terminal is higher than a target value, the switching converter circuit is set to the second state, and when the voltage at the output terminal is lower than the target value, the switching converter circuit is set for the predetermined time. A control circuit which sets the switching converter circuit to the second state when the current of the inductor is larger than a threshold value after returning to the second state after setting the state to 1.
The threshold is adjusted according to the ratio or difference between the voltage at the input terminal and the voltage at the output terminal so that the change in the ripple voltage at the output terminal due to the change in the ratio or difference is reduced. A switching power supply device having a value adjustment circuit. A first determination circuit for determining whether or not the current of the inductor is larger than a threshold corresponding to an input threshold signal;
The threshold adjustment circuit is
A first voltage dividing circuit for dividing the voltage of the input terminal by a plurality of voltage dividing ratios;
A comparison circuit that compares each of the plurality of voltages divided in the first voltage dividing circuit with the voltage of the output terminal or a predetermined voltage;
Including a signal generation circuit that generates the threshold signal based on a comparison result of the comparison circuit,
The switching power supply device according to claim 1. A selection circuit that sequentially selects one voltage from the plurality of voltages divided in the first voltage dividing circuit;
The comparison circuit sequentially compares the voltage selected in the selection circuit with the voltage of the output terminal or a predetermined voltage,
The signal generation circuit generates the threshold signal based on a plurality of comparison results of the comparison circuit corresponding to the plurality of voltages divided in the first voltage dividing circuit;
The switching power supply device according to claim 2. The threshold adjustment circuit further includes a second voltage dividing circuit that divides the voltage of the output terminal,
The comparison circuit compares each of the plurality of voltages divided in the first voltage dividing circuit with the voltage divided in the second voltage dividing circuit;
The switching power supply device according to claim 2 or 3. A second determination circuit for determining whether or not the voltage at the output terminal is lower than the target value;
The control circuit is
When the first determination circuit determines that the voltage at the output terminal is lower than the target value, the first value signal is held, and the signal is periodically output in synchronization with the input clock signal. A signal holding circuit that resets to a value;
When the signal holding circuit holds a signal having a first value, the switching converter circuit is set to the first state, and when the signal holding circuit holds a signal having a second value, the switching converter circuit A control signal generation circuit for generating a control signal for setting the second state to the second state,
The switching power supply device according to claim 1, 2, 3, or 4. A first determination circuit for determining whether or not the current of the inductor is greater than the threshold;
The signal holding circuit holds the signal having the second value until the reset operation is performed at least once when the first determination circuit determines that the current of the inductor is larger than the threshold value. ,
The switching power supply device according to claim 5. The switching converter circuit is
A first switching element connected between one terminal of the inductor and the input terminal;
A second switching element connected between the one terminal of the inductor and a reference potential;
A third switching element connected between the other terminal of the inductor and the output terminal;
A fourth switching element connected between the other terminal of the inductor and the reference potential;
The control circuit is
When the voltage at the input terminal is higher than the voltage at the output terminal, the first switching element and the third switching element are turned on, and the second switching element and the fourth switching element are turned off in the first state. In the second state, the second switching element and the third switching element are turned on, the first switching element and the fourth switching element are turned off,
When the voltage at the input terminal is lower than the voltage at the output terminal, the first switching element and the fourth switching element are turned on and the second switching element and the third switching element are turned off in the first state. In the second state, the first switching element and the third switching element are turned on, and the second switching element and the fourth switching element are turned off.
The switching power supply device according to claim 1, 2, 3, 4, 5 or 6. Including at least one inductor, alternately repeating a first state in which power input from an input terminal is stored in the inductor and a second state in which power stored in the inductor is discharged from an output terminal, A control device for a switching converter circuit that boosts or lowers a DC voltage applied to an input terminal by the repetitive operation and outputs the DC voltage from the output terminal,
When the voltage at the output terminal is higher than a target value, the switching converter circuit is set to the second state, and when the voltage at the output terminal is lower than the target value, the switching converter circuit is set for the predetermined time. A control circuit which sets the switching converter circuit to the second state when the current of the inductor is larger than a threshold value after returning to the second state after setting the state to 1.
The threshold is adjusted according to the ratio or difference between the voltage at the input terminal and the voltage at the output terminal so that the change in the ripple voltage at the output terminal due to the change in the ratio or difference is reduced. A control device having a value adjustment circuit.

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