JP2010183723A - Dc-dc converter and switching control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve power efficiency during a light-load operation in a switching regulator type DC-DC converter. <P>SOLUTION: A switching control circuit is provided with: an error amplification circuit 21 that outputs a voltage according to an output voltage, a circuit 27 that supplies a current proportional to an output current, a waveform generating circuit 23 that generates a waveform signal having an inclination according to the output current, a first voltage comparison circuit 22 that receives output of the error amplification circuit and output of the waveform generating circuit, a second voltage comparison circuit 24 that compares the output of the waveform generating circuit with a predetermined voltage, a timing deciding means 25 that decides on-timing and off-timing of a driving switching element on the basis of output of the first voltage comparison circuit and output of the second voltage comparison circuit, and a drive control circuit that generates on/off-drive signals of the driving switching element on the basis of output of the timing deciding means. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a switching regulator type DC-DC converter that converts a DC voltage and a switching control circuit thereof, and more particularly to a DC-DC converter that is driven by changing a switching frequency and a pulse width according to the magnitude of a load current. It is related to effective technology.

  There is a switching regulator type DC-DC converter as a circuit for converting a DC input voltage and outputting DC voltages of different potentials. In such a DC-DC converter, a driving switching element that applies a DC voltage supplied from a DC power source such as a battery to an inductor (coil) to flow current and accumulate energy in the coil, and the driving switching element is turned off. There is a DC-DC converter provided with a rectifying element that rectifies the current of the coil during the energy release period and a control circuit that controls on and off of the driving switching element.

  Conventionally, in the switching regulator type DC-DC converter, the magnitude of the output voltage is detected by an error amplifier and fed back to a PWM (pulse width modulation) comparator or PFM (pulse frequency modulation) comparator. When the output voltage decreases, the on-time of the switching element is lengthened, and when the output voltage increases, the on-time of the switching element is shortened.

  In the PWM control, the pulse width is changed according to the ratio between the Vin voltage and the Vout voltage with the drive pulse period (frequency) constant. The pulse width is also reduced when the load is reduced and the discontinuous mode is entered. In addition, when the load becomes very light, there may be a case where the output current is too large even if the load is driven with the pulse having the minimum pulse width. Therefore, as shown in FIG. 6, both the PWM comparator 22 and the PFM comparator 24 are provided, and the PWM control is normally performed. When the current flowing through the load is reduced, that is, when the load is light, it is driven with a fixed pulse having a constant pulse width. There is also a DC-DC converter that shifts to PFM control in which the cycle is changed according to the load. As inventions related to such a DC-DC converter, there are those described in Patent Document 1 and Patent Document 2, for example.

JP 2006-149067 A JP 2003-219637 A

  In the PFM control mode at the time of light load in the DC-DC converter that switches the PWM control and the PFM control as shown in FIG. 6 and drives the switching element, the output of the error amplifier 21 is as shown in FIG. When the reference voltage Vref2 is exceeded, the output of the PFM comparator 24 changes to a low level. Then, the output of the inverter changes to a high level to open the AND gate G1, and the pulse from the pulse generation circuit 31 that generates a pulse with a fixed pulse width is supplied to the switching elements SW1 and SW2 via the selector 29 for switching. It comes to drive.

  The PWM / PFM switching type DC-DC converter of FIG. 6 has an advantage that the power efficiency at light load can be improved as compared with the DC-DC converter of only PWM control. However, in the case of driving with PFM control pulses, while the input voltage is relatively high, the pulse period is longer and the number of switching times is lower than in the case of PWM control. When the voltage becomes lower and the potential with respect to the target output voltage becomes smaller, the pulse cycle becomes shorter and the number of times of switching increases as shown in FIG. And if the number of times of switching increases, since the through current flowing through the switching elements SW1 and SW2 increases, there is a problem that the power efficiency decreases.

  The pulse generated by the pulse generation circuit 31 is generally designed so that the pulse width is fixed and the duty is 50% at maximum, that is, the on time and the off time are the same, so the input voltage range is limited to the duty. In other words, since the duty of the pulse does not increase when the input voltage falls below a certain level, it has been found that there is a problem that a desired output voltage cannot be obtained due to insufficient current flowing through the coil.

  The present invention has been made paying attention to the above-described problems, and an object of the present invention is to provide a control technology capable of improving power efficiency at light load in a switching regulator type DC-DC converter. It is to provide.

  Another object of the present invention is to provide a control technique for obtaining a desired output voltage in a switching regulator type DC-DC converter in a lower input voltage range as compared with the prior art.

  In order to achieve the above object, the present invention is a switching control circuit that generates and outputs an off / on drive signal for a driving switching element that supplies current to an inductor for voltage conversion, and outputs a voltage corresponding to the output voltage. An error amplifying circuit, a current generating circuit for passing a current proportional to the output current, a capacitor charged by the current output from the current generating circuit, and a discharging means capable of discharging the charge of the capacitor A waveform generation circuit that generates a waveform signal having a slope corresponding to the magnitude of the output current; a first voltage comparison circuit that receives the output of the error amplification circuit and the output of the waveform generation circuit; and the waveform A second voltage comparison circuit for comparing the output of the generation circuit with a predetermined voltage; and the drive switch based on the output of the first voltage comparison circuit and the output of the second voltage comparison circuit. Timing determining means for determining the on-timing and off timing of quenching elements, and the like provided off of the driving switching element based on an output of said timing determining means, and a drive control circuit for generating an on-drive signal.

  According to the above means, since the period of the waveform signal generated by the waveform generation circuit is changed according to the output current, the frequency of the drive switching element OFF and ON drive signal depends on the output current. And the first voltage comparison circuit compares the output of the error amplification circuit with the output of the waveform generation circuit, and the timing determination circuit determines whether the drive switching element is in accordance with the output of the first voltage comparison circuit. Since the on or off timing is determined, the pulse width of the drive switching element is turned off and on according to the output voltage. Therefore, when the output current is small, the switching frequency can be reduced to avoid a reduction in efficiency due to the through current, and when the input voltage is reduced, the pulse width of the drive signal is narrowed, so the input voltage is considerably reduced. Also, a desired output voltage can be obtained.

  Preferably, the timing determining unit determines an off timing of the driving switching element based on an output of the first voltage comparison circuit, and the driving based on an output of the second voltage comparison circuit. The on-timing of the switching element is determined. Thereby, it is possible to easily construct a control loop that can variably control the switching frequency and the pulse width of the drive signal in accordance with the output voltage and the output current.

  Preferably, the timing determination unit is a flip-flop in which the output of the first voltage comparison circuit is input to a reset terminal or a set terminal, and the output of the first voltage comparison circuit is input to a set terminal or a reset terminal. It is configured by a circuit. As a result, a circuit capable of determining the on-timing and off-timing of the driving switching element can be realized with a simple circuit, and the design becomes easy.

  Further preferably, the discharge means of the waveform generating circuit is configured by a field effect transistor, and the transistor is controlled to be turned on and off by the output of the second voltage comparison circuit so that the charge of the capacitive element can be discharged. To do. As a result, a waveform generation circuit can be configured with one transistor and one capacitor, which facilitates circuit design and reduces the chip size when the occupied area is reduced to form an IC.

  Preferably, the current generation circuit for supplying a current proportional to the output current receives the voltage of both terminals of the detection resistor connected between the smoothing capacitor and the output terminal as an input, and a current corresponding to the voltage. Is constituted by a voltage-current conversion circuit which outputs Thereby, the current proportional to the output current can be accurately limited to improve the accuracy of the switching control.

  Further, preferably, a constant current source for supplying a predetermined current to the waveform generation circuit, and either a current from the constant current source or an output current from the voltage-current conversion circuit is selected for the waveform generation circuit. Supplyable current switching means is provided. As a result, PWM control is performed by generating a fixed frequency waveform signal using the current of the constant current source under heavy load, and waveform signal is generated using the output current from the voltage-current conversion circuit at light load. By doing so, it becomes possible to perform variable control of the frequency and pulse width, and it is possible to improve the efficiency in both the heavy load state and the light load state.

  Further, preferably, a constant current source that constantly feeds a predetermined current to the waveform generation circuit is provided. As a result, even when the output current is very small, a waveform signal can be generated by the waveform generation circuit, and a stable operation at a light load can be ensured.

  According to the present invention, in a switching regulator type DC-DC converter, it is possible to improve the power efficiency when the load is reduced, and to obtain a desired output voltage in a lower input voltage range than in the past. There is an effect.

It is a circuit block diagram which shows one Embodiment of the DC-DC converter to which this invention is applied. It is a timing chart which shows the mode of the change of the signal of each part and electric potential in the DC-DC converter of embodiment of FIG. It is a circuit block diagram which shows the 1st modification of the DC-DC converter of embodiment of FIG. It is a circuit block diagram which shows the 2nd modification of the DC-DC converter of embodiment of FIG. It is a circuit block diagram which shows the 3rd modification of the DC-DC converter of embodiment of FIG. It is a circuit block diagram which shows the structure of the DC / DC converter of the conventional PWM / PFM switching system. It is a timing chart which shows the mode of the change of the signal of each part and electric potential in the conventional DC / DC converter of a PWM / PFM switching system.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of a switching regulator type DC-DC converter to which the present invention is applied.

  The DC-DC converter of this embodiment includes a coil L1 serving as an inductor, a voltage input terminal IN to which a DC input voltage Vin is applied, and one terminal of the coil L1, and a P channel for passing a current through the coil L1. A driving transistor SW1 as a switching element composed of a MOSFET (insulated gate field effect transistor), a rectifying transistor SW2 composed of an N-channel MOSFET connected in series with SW1 between the voltage input terminal IN and the ground point, A switching control circuit 20 that controls on / off of the transistors SW1 and SW2 and a smoothing capacitor C1 connected between the other terminal of the coil L1 and a ground point are provided.

  Although not particularly limited, among the elements constituting the DC-DC converter, elements other than the coil L1 and the smoothing capacitor C1 are formed on a semiconductor chip, and the switching control circuit 20 and the transistors SW1 and SW2 are integrated in a semiconductor integrated circuit. It is configured as a circuit (power supply driving IC), and the coil L1 and the capacitor C1 are connected as external elements to external terminals provided in the IC.

  In the DC-DC converter of this embodiment, the switching control circuit 20 generates a drive signal that complementarily turns on and off the transistors SW1 and SW2. In the steady state, the drive transistor SW1 Is turned on, the DC input voltage Vin is applied to the coil L1 and a current directed to the output terminal flows to charge the smoothing capacitor C1. When the driving transistor SW1 is turned off, the rectifying transistor SW2 is turned on instead. Then, a current is supplied to the coil L1 through the turned-on transistor SW2. Then, the pulse width of the drive signal input to the control terminal (gate terminal) of SW1 is controlled according to the output voltage, so that the DC output voltage Vout obtained by stepping down the DC input voltage Vin is generated.

  The switching control circuit 20 of this embodiment is connected in series between the voltage feedback terminal FB and the ground point, and divides the output voltage Vout by a resistance ratio, and the bleeder resistors R1 and R2 divide the output voltage Vout. An error amplifier 21 that compares the generated voltage with the reference voltage Vref1 and outputs a voltage corresponding to the potential difference; a first comparator 22 that receives the output of the error amplifier 21 at its inverting input terminal; It has a waveform generation circuit 23 for generating a sawtooth waveform signal RAMP input to the inverting input terminal.

  The switching control circuit 20 includes a second comparator 24 in which the output of the waveform generation circuit 23 is input to the non-inverting input terminal and the reference voltage Vref2 is input to the inverting input terminal, and the output of the second comparator 24 is set to the set terminal. An RS flip-flop 25 that receives the output of the first comparator 22 and receives the output of the flip-flop 25, and generates gate drive signals GP1 and GP2 that turn on and off the switch transistors SW1 and SW2. The drive control circuit 26 is provided. The drive control circuit 26 is preferably configured to generate and output gate drive signals GP1 and GP2 having a so-called dead time so that the switch transistors SW1 and SW2 are simultaneously turned on and no through current flows. .

  Furthermore, the switching control circuit 20 of this embodiment receives the voltage of both terminals of the current detection resistor Rs connected between the coil L1 and the output terminal OUT, and is directed to the load connected to the output terminal OUT. And a current detection amplifier 27 for generating a current proportional to the load current IL. The current detection amplifier 27 is configured by a gm amplifier, for example, and functions as a voltage-current conversion circuit.

  The waveform generation circuit 23 includes a capacitor C2 connected between the non-inverting input terminals of the first comparator 22 and the second comparator 24 and a ground point, and a discharge N-channel MOS connected in parallel with the capacitor C2. This is constituted by a transistor SW3. The output terminal of the second comparator 24 is connected to the gate terminal of the transistor SW3, and the output terminal of the current detection amplifier 27 is connected to the connection node N2 between the capacitor C2 and the transistor SW3.

  As a result, when the transistor SW3 is turned off by the output of the second comparator 24, the waveform generation circuit 23 charges the capacitor C2 by the output current of the current detection amplifier 27, and the potential V2 of the node N2 rises. When the potential V2 of N2 reaches the reference voltage Vref2, the output of the second comparator 24 changes to high level and the transistor SW3 is turned on. As a result, the charge of the capacitor C2 is discharged, the potential V2 of the node N2 falls sharply, and V2 has a waveform that changes in a sawtooth shape as shown in FIG. This sawtooth wave is supplied to the non-inverting input terminals of the first comparator 22 and the second comparator 24. The slope of the waveform when the potential V2 of the node N2 rises is proportional to the output current of the current detection amplifier 27, that is, the load current IL. The slope is steeper as IL increases, and the slope becomes gentler as IL decreases. .

  Next, the operation of the switching control circuit 20 will be described with reference to the timing chart of FIG. In FIG. 2B, what is indicated by V error is the output voltage of the error amplifier 21, and this voltage V error and the potential V 2 of the node N 2 are input to the first comparator 22.

  When the load current IL is small as in the periods T1 and T3 shown in FIG. 2A, the potential V2 of the node N2 gradually increases as shown in FIG. 2B, and V2 is the output voltage Verror of the error amplifier 21. 2, the output of the first comparator 22 changes from the low level to the high level as shown in FIG. 2C, the RS flip-flop 25 is reset, and the gate drive signal GP1 becomes the low level as shown in FIG. To high level (timing t1).

  Thereafter, when the potential V2 of the node N2 further rises and reaches the reference voltage Vref2 which is the discrimination level of the second comparator 24, the output of the second comparator 24 changes to high level, and the RS flip-flop 25 is set. The gate drive signal GP1 changes from the high level to the low level (timing t2). At the same time, the transistor SW3 is turned on, and the potential C2 of the node N2 falls sharply by discharging the capacitor C2.

  Then, the output of the first comparator 22 changes from high level to low level. Further, since the output of the second comparator 24 also changes to a low level, a short pulse-like waveform is obtained as shown in FIG. By repeating the above operation, the switching operation of the driving transistor SW3 is repeatedly performed. The rectifying transistor SW2 is driven on and off in a complementary manner to SW1 by a drive signal GP2 having substantially the same phase as GP1 output from the drive control circuit 26.

  As in the period T2 shown in FIG. 2A, when the load current IL is large, the operation of the circuit itself is the same as when the IL is small. However, since the output current of the current detection amplifier 27 increases, the node The gradient of the potential V2 of N2 increases. As a result, the pulse width of the gate drive signal GP1 of the drive transistor SW1 is narrowed, but at the same time the cycle is narrowed, and the drive transistor SW1 is driven on and off.

  Although not apparent from FIG. 2, when the load fluctuates and the output voltage Vout changes, the output Verror of the error amplifier 21 changes accordingly, thereby changing the pulse width of the gate drive signal GP1. Specifically, for example, as indicated by a broken line F in FIG. 2B, if Verror of the error amplifier 21 becomes high, the pulse width of the output of the first comparator 22 becomes narrow, and the gate drive signal GP1 becomes high. The level period, that is, the off period of the driving transistor SW1 is shortened. On the contrary, if Verror of the error amplifier 21 becomes low, the pulse width of the output of the first comparator 22 becomes wide, and the high level period of the gate drive signal GP1, that is, the off period of the drive transistor SW1 becomes long.

  As described above, in the DC-DC converter according to this embodiment, both the pulse period and pulse width of the drive signal are controlled in accordance with the load variation. For this reason, for example, even when the input voltage decreases, the duty is not limited, and when the load current is small, the switching frequency decreases, thereby reducing the number of switching and reducing the efficiency due to the through current. It will be avoided. In addition, since the switching frequency increases as the load increases, there is an advantage that ripples (changes in output voltage) are reduced.

  Next, modified examples of the DC-DC converter of the above embodiment will be described with reference to FIGS.

  3 to 5 is based on the oscillation circuit OSC and the oscillation signal output from the oscillation circuit, in addition to the circuit blocks constituting the switching control circuit 20 in the embodiment of FIG. A second waveform generation circuit 28 for generating a waveform signal RAMP such as a sawtooth wave or a triangular wave having a fixed frequency and a waveform signal output from the waveform generation circuit 28 or the waveform generation circuit 23; A selector 29 a that supplies the first comparator 22, and a selector 29 b that selects either the fixed-frequency waveform signal output from the oscillation circuit or the output of the second comparator 24 and supplies the selected signal to the flip-flop 25. It is provided.

  The selectors 29a and 29b are controlled by a switching control signal CNT supplied from a control circuit such as an external CPU. When the selector 29a selects a waveform signal output from the waveform generation circuit 28, the selector 29b also oscillates. A waveform signal having a fixed frequency output from the circuit is selected (first mode). Further, when the selector 29a selects the waveform signal output from the waveform generation circuit 23, the selector 29b is switched so as to select the output of the second comparator 24 (second mode).

  In this second mode, the switching control circuit 20 operates exactly the same as the control circuit of the embodiment of FIG. 1, and is driven by a variable pulse whose frequency and pulse width change according to the output voltage. On the other hand, in the first mode, the PWM / PFM switching type DC-DC converter shown in FIG. 6 operates in the same manner as the PWM control mode, and the driving transistor SW1 has a fixed frequency and a pulse width of the output voltage. It is driven by PWM pulses that change accordingly.

  Therefore, for example, the CPU that controls the entire system detects that the load has been reduced, changes the switching control signal CNT, and switches from the PWM control mode (first mode) to the second mode that uses the output of the comparator 24. Thus, the switching frequency and the pulse width can be controlled to change according to the load, and the operation can be performed so as to improve the efficiency at a light load.

  In the above embodiment, the selectors 29a and 29b are switched by the switching control signal CNT input from the outside. However, an input voltage detection circuit for detecting whether or not the input voltage Vin has become a predetermined level or less is provided. The waveform signal output from the waveform generation circuit 28 is selected when the input voltage Vin is equal to or higher than a predetermined level, and the waveform output from the waveform generation circuit 23 when the input voltage Vin is lower than the predetermined level. You may comprise so that a signal may be selected.

  FIG. 4 shows a second modification of the DC-DC converter of FIG.

  In this modification, a constant current source 30 for supplying a predetermined current and selection of whether the current output from the current detection amplifier 27 or the current of the constant current source 30 is supplied to the charge / discharge node N2 of the waveform generation circuit 23 are selected. The selector 29 is provided. When the selector 29 is switched so as to select the current output from the current detection amplifier 27, the switching control circuit 20 performs exactly the same operation as the control circuit of the embodiment of FIG. 1, and the driving transistor SW1. Is driven with a variable pulse whose frequency and pulse width change according to the output voltage.

  On the other hand, when the selector 29 is switched so as to select the current supplied from the constant current source 30, the waveform generated in the waveform generation circuit 23 indicates the magnitude of the current of the constant current source and the capacitance value of the capacitor C2. Therefore, the switching control circuit 20 operates in the PWM control mode, and the driving transistor SW1 has a fixed frequency and a pulse width corresponding to the output voltage. It will be driven by the changing PWM pulse.

  Also in the DC-DC converter of this embodiment, the selector 29 may be switched by a switching control signal CNT inputted from the outside, or an input voltage detection circuit is provided inside the chip and automatically according to the input voltage Vin. You may comprise so that the selector 29 may be switched.

  FIG. 5 shows a third modification of the DC-DC converter of FIG.

  In this modification, a constant current source 30 is provided to constantly flow a relatively small predetermined offset current to the charge / discharge node N2 of the waveform generation circuit 23. Since the current from the constant current source 30 is always flowed into the waveform generation circuit 23 as an offset current, the waveform generation circuit 23 generates a waveform even when there is almost no current from the current detection amplifier 27, that is, when the load current is very small. There is an advantage that a signal can be generated and a stable operation at a light load is guaranteed.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the embodiment, as a circuit for passing a current proportional to the output current (load current IL), a current detection amplifier that detects the magnitude of the output current from the voltage across the terminals of the sense resistor Rs connected in series with the coil. 27 is used, a transistor connected to the switching element SW1 and a current mirror may be provided to obtain a current proportional to the output current.

  In the above embodiment, on-chip elements are used as the switching elements SW1 and SW2. However, external elements formed separately from the control circuit may be used. Furthermore, although the synchronous rectification type DC-DC converter in which the rectification transistor SW2 is connected in series with the drive transistor SW1 and is turned on and off complementarily with the SW1 is shown in the above embodiment, the rectification transistor SW2 is used instead. It is also possible to apply to a diode rectification type DC-DC converter using a diode.

  Further, in the embodiment, an RS flip-flop having a set terminal and a reset terminal is used as the flip-flop 23. However, other types of flip-flops may be used, and the logic of the drive control circuit 26 is devised. Thus, it is also possible to configure so that the output of the first comparator 22 is input to the set terminal and the output of the second comparator 24 is input to the reset terminal.

  In the above description, the present invention is applied to a step-down DC-DC converter. However, the present invention is not limited thereto, and a step-up DC-DC converter or a negative voltage is generated. The present invention can also be applied to an inverting DC-DC converter.

20 switching control circuit 21 error amplifier 22 first comparator 23 waveform generation circuit 24 second comparator 25 flip-flop 26 drive control circuit 27 current detection amplifier 28 second waveform generation circuit 29 selector 30 constant current source L1 coil (inductor)
C1 Smoothing capacitor SW1 Coil driving transistor (driving switching element)
SW2 Synchronous rectifier transistor (rectifier switching element)

Claims (8)

A switching control circuit that generates and outputs an off / on driving signal of a driving switching element that causes a current to flow through an inductor for voltage conversion,
An error amplification circuit that outputs a voltage corresponding to the output voltage;
A current generation circuit for supplying a current proportional to the output current;
Waveform generation for generating a waveform signal having a capacitance element charged by the current output from the current generation circuit and a discharge means capable of discharging the charge of the capacitance element and having a slope corresponding to the magnitude of the output current Circuit,
A first voltage comparison circuit that receives the output of the error amplification circuit and the output of the waveform generation circuit;
A second voltage comparison circuit for comparing the output of the waveform generation circuit with a predetermined voltage;
Timing determining means for determining an on timing and an off timing of the driving switching element based on an output of the first voltage comparison circuit and an output of the second voltage comparison circuit;
A drive control circuit for generating an off / on drive signal for the drive switching element based on an output of the timing determining means;
A switching control circuit comprising:   The timing determining means determines an off timing of the driving switching element based on an output of the first voltage comparison circuit, and an on timing of the driving switching element based on an output of the second voltage comparison circuit. The switching control circuit according to claim 1, wherein the switching control circuit is configured to determine   The timing determination unit is configured by a flip-flop circuit in which the output of the first voltage comparison circuit is input to a reset terminal or a set terminal, and the output of the second voltage comparison circuit is input to a set terminal or a reset terminal. The switching control circuit according to claim 2, wherein:   The discharge means of the waveform generation circuit is constituted by a field effect transistor, and the transistor is controlled to be turned on and off by an output of the second voltage comparison circuit, and is configured to be able to discharge the charge of the capacitive element. The switching control circuit in any one of 1-3.   The current generation circuit for supplying a current proportional to the output current has as input a voltage at both terminals of a detection resistor connected between the smoothing capacitor and the output terminal, and outputs a current corresponding to the voltage − The switching control circuit according to claim 1, comprising a current conversion circuit.   A constant current source for supplying a predetermined current to the waveform generation circuit, and a current switching capable of selecting and supplying either the current from the constant current source or the output current from the voltage-current conversion circuit to the waveform generation circuit The switching control circuit according to claim 5, further comprising: means.   6. The switching control circuit according to claim 5, further comprising a constant current source that constantly supplies a predetermined current to the waveform generation circuit.   Inductor for voltage conversion, driving switching element for passing current through the inductor, rectifying element for rectifying coil current while the driving switching element is off, and smoothing capacitor connected to the output terminal A detection resistor connected in series with the inductor; and the switching control circuit according to claim 5, wherein a voltage at both terminals of the detection resistor is the voltage-current conversion circuit. The DC-DC converter characterized by being input to.

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