201140273 六、發明說明： 【發明所屬之技術領域】 以下描述係關於一種用於產生一高於一輸入電壓之增壓 電壓的電路，及一種用於操作該增壓電壓產生電路之方 法。 本申請案主張2009年12月17曰申請之韓國專利申請案第 10-2009-0 126071號及2010年4月19日申請之韓國專利申請 案第10-2010-0035631號之權利，該等專利申請案中之每一 者的整體揭示内容出於所有目的以全文引用之方式併入本 文中。 【先前技術】 不同半導體器件藉由自外部供應之電壓來操作内部電 路。由於不同位準之電壓用於半導體器件之内部構成元件 中，因此難以自器件外部供應待在半導體器件内部使用之 所有電壓。因此，半導體器件配備有一内部電壓產生電路 以在器件内部產生不同位準之電壓。 特疋言之，當自電池供應之電源電壓之位準為低的且待 在器件内部使用之驅動電壓之位準高於輸入電源電壓之位 準時，使用電池電源之器件應能夠產生位準高於自外部輸 入之輸入電源電壓之位準的電壓。將產生位準高於輸入電 壓之位準的電壓DC_DC轉換器分為使用電感器之切換模式 电源供應(SMPS)類型及使用電容器之電荷泵類型。在行 動器件之狀況下，由於電流消耗並不大，因此行動器件通 常具有電荷泵類型。 151662.doc 201140273 不同於線性電源供應器，SMPSi傳遞型電晶體（pa% 11^1134〇〇在全通狀態與全斷狀態之間極快速地（通常在π kHz與1 MHz之間）切換’此使所浪費之能量最小化。藉由 改變接通時間與斷開時間之比率來提供電壓調節。相^之 下，線性電源供應器必須耗散過量電壓以調節輸出。此較 高效率為SMPS之主要優點。當需要較高效率、較小大小 及/或較輕重量時，使用切換調節器來替換線性調節器。 圖1為展示增壓電壓產生電路之電壓、信號及輸出電壓 的方塊圖。 將輸入電壓VCIN及增壓率BT[a:0]輸入至增壓電壓產生 電路1〇〇中。增壓電壓產生電路100基於由增壓率BT[a:〇]表 示之增壓率來使輸入電壓VCIN增壓，並產生增壓電塵 VOUT。舉例而言，當增壓率BT[a:0]為2時（其意謂兩倍或 雙倍），增壓電壓產生電路100使輸入電壓VCIN增壓兩倍 (亦即’使電壓加倍），並產生增壓電塵ν〇υτ。 儘ί增壓電壓VOUT之目標值為相同的，但在增壓電壓 產生電路100中可存在不同之輸入電壓增麗率 BT[a:0]。舉例而言，當增壓電壓ν〇υτ之目標值為3 ν 時’（a) 3 V之增壓電壓VOUT可藉由使15 ν之輸入電壓 VCIN增壓'兩倍（亦即，加倍）來產生，或（b) 3 ν之增壓電壓 VOUT可藉由使1 V之輸入電壓VCIN增壓三倍（亦即，增至 三倍）來產生。然而’儘管產生同一增壓電壓V0UT，但增 壓電壓產生電路100所消耗之電流的量基於如何設定輸入 電壓VCIN及增壓率BT[a:0]而可大大不同。 151662.doc 201140273 然而，習知電源供應益並不根據增壓電壓ν〇υτ之目標 位準而使輸入至增壓電壓產生電路1〇〇中之輸入電壓VCIN 及增壓率BT[a:0]最佳化。 【發明内容】 在 般態樣中，提供一種增壓電壓產生電路，其包 括：一增壓電路’其經組態以：基於一增壓率使一輸入電 壓增壓，及輸出一增壓電壓；一增壓率設定單元，其經組 態以·接收關於該輸入電壓之一位準之一回饋，及設定該 增壓率；及一輸入電壓位準設定單元，其經組態以回應於 以下各項而設定該輸入電壓之該位準：該增壓電壓之一目 標位準及該增壓率。 在該增壓電壓產生電路中，該輸入電壓位準設定單元可 經進一步組態以根據以下之一值來設定該輸入電壓之一目 標位準：（該增壓電壓之該目標位準/該增壓率）。 在該增壓電壓產生電路中，該增壓率設定單元可經進一 步組態以回應於該輸入電壓之該目標位準超出該輸入電壓 之一位準範圍而增大該增壓率。 在該增壓電壓產生電路中，該增壓率設定單元可經進一 步組態以回應於在減小該增壓率時該輸入電壓之該目標位 準屬於該輸入電壓之該位準範圍而減小該增壓率。 在該增壓電壓產生電路中，該輸入電壓位準設定單元可 包括.一輸出電壓分壓器，其經組態以：將該增壓電壓除 以基於該增壓率判定之一比率，及輸出經分壓之電壓；一 輸入參考電壓選擇器，其經組態以基於該增壓率而在基於 15I662.doc 201140273 該增壓電壓之該目標位準所產生之複數個電壓中選擇一輸 入參考電壓·，一比較器，其經組態以：比較該輸出電壓分 壓器之一輸出電壓與該輸入參考電壓選擇器之一輸出電 壓，及產生一初步輸入電壓；及一放大器，其經組態以： 放大該初步輸入電壓’及產生該輸入電壓。 在該增壓電壓產生電路中，該放大器包含：一比較器， 其經組態為一線性調節器；及複數個電阻器。 在該增壓電壓產生電路中，該輸出電壓分壓器可經進一 步組態以按以下之一比率對該增壓電壓進行分壓：丨/(該增 壓率*該放大器之一放大率）。 在該增壓電壓產生電路中，該輸入參考電壓選擇器可經 進一步組態以根據下式選擇為該目標位準之一輸入參考電 壓：該增壓電壓/(該增壓率*該放大器之一放大率）。 在该增壓電壓產生電路中，該輸入電壓位準設定單元進 步包括一電壓箝，該電壓箝經組態以防止該初步輸入電 壓過度增大或減小。 在該增壓電壓產生電路中，該電壓箝可包括一類比多工 器，其經組態以回應於該增壓率而在輸入之電壓中選擇一 下箝位電壓。 在該增壓電壓產生電路中，該輸入電壓位準設定單元可 進一步包括一補償電路，其經組態以使該初步輸入電壓之 位準穩定。 在該增壓電壓產生電路中’該補償電路包含··一電阻 器；及一電容器。 151662.doc 201140273 在該增壓電壓產生電路中，該增壓率設定單元可包括： 一分屋器，其經組態以產生：一增壓率遞增參考電壓，及 一增壓率遞減參考電壓；一旗標信號產生器，其經組態 以：回應於該初步輪入電壓高於該增壓率遞增參考電壓而 啟用一增壓率遞增旗標信號，及回應於該初步輸入電壓低 於該增壓率遞減參考電壓而啟用一增壓率遞減旗標信號； 及一增壓率控制器’其經組態以回應於該增壓率遞增旗標 信號及/或該增壓率遞減旗標信號而設定該增壓率。 在該增壓電壓產生電路中，該增壓率設定單元可進一步 包括一初始值判定器，其經組態以向該增壓率控制器提供 關於5亥增壓率之^一初始值的資訊。 在該增壓電壓產生電路中，該初始值判定器可包括複數 個比較器，該複數個比較器經組態以比較各別輸入參考電 壓值與一初始參考電壓。 在該增壓電壓產生電路中，該增壓率控制器可經進—步 組態以：回應於該增壓率遞增旗標信號經啟用歷時長於— 參考時間而增大該增壓率，及回應於該增壓率遞減旗標信 號經啟用歷時長於一參考時間而減小該增壓率。 在該增壓電壓產生電路中，該增壓率控制器可包括：複 數個計數器、複數個比較器、複數個正反器、一初始值解 碼器，及一可預設之遞増/遞減計數器。 在該增壓電壓產生電路中，該可預設之遞增/遞減計數 器可經組態以將輸入至該可預設之遞增/遞減計數器中之 一初始增壓率信號設定為該增壓率之一初始值；回應於為 151662.doc 201140273 邏輯高之該增壓率遞增旗標信號，該複數個計數器中之一 第一計數器可經組態以對一時脈計數從而增大一遞增計數 值’及回應於該增大之遞增計數值收斂至該增壓率遞增參 考電壓，S亥可預設遞增/遞減計數器可經進一步組態以啟 用該增壓率之一增大。 在該增壓電壓產生電路中，該可預設之遞增/遞減計數 器可經組態以將輸入至該可預設之遞增/遞減計數器中之 初始增壓率k號设定為該增壓率之一初始值丨回應於為 邏輯南之S亥增壓率遞減旗標信號，該複數個計數器中之— 第二計數器可經組態以對—時脈計數從而增大一遞減計數 值，及回應於該增大之遞増計數值收斂至該增壓率遞減參 考電壓，該可預設遞增/遞減計數器可經進一步組態以啟 用該增壓率之一減小。 在該增壓電壓產生電路中，該可預設之遞增/遞減計數 态可經組態以將輸入至該可預設之遞增/遞減計數器中之 初始增壓率信號設定為該增壓率之一初始值丨及回應於 為邏輯问之6亥增壓率遞減旗標信號，該複數個計數器中之 一第二計數器可經組態以對一時脈計數從而增大一遞減計 數值’ 率遞減旗標信號在增A該遞減計數值時經轉 變至邏輯低，使得該遞減計數m步增A，使得該可 預设之遞增/遞減計數器不啟用該增壓率之一改變。 在該增壓電壓產生電路中，該增壓率遞增參考電壓之— 位準可根據下式來判定：—電源電壓/(該放大器之一放大 率），且該增塵率遞減參考„之—位準可根據下式來判 151662.doc 201140273 —增壓率改變之一單位）/(該 定··該電源電壓*(該增壓率— 放大益之5亥放大率*該增壓率） 在另一—般態樣巾，提供於操作_增壓電壓產生 電路之方法，該增壓電壓產生電路藉由基於—增壓率使一 輸入電壓増壓來產生一增壓電壓，該方法包括：產生目標 為以下之一位準的該輸入電壓：（該增壓電壓之一目標= 壓/一增壓率）；回應於該輸人電壓之該目標位準超出該輸 入電壓之-位準範圍而增A該增壓率；及回應於在該增壓 率減小時該輸入電壓之該目標位準屬於該輸入電壓之；位 準範圍而減小該增壓率。 在該方法中 位準。 該輸入電壓不可具有一高於— 電源電壓之 在該方法中，該增壓率之該減小可回應於該輪入電壓之 該目標位準低於以下之一值而執行：（該增壓率增壓率 改變之一單位）/該增壓率。 在另 般態樣中，提供一種產生一增壓電壓之方法， §玄方法包括：基於一增壓率使一輸入電壓增壓；輪出—增 廢電疋，接收關於該輸入電塵之一位準之一回饋；設定， 增壓率；及回應於以下各項而設定該輸入電壓之該位準： 該增壓電壓之一目標位準及該增壓率。 該方法可進一步包括根據以下之一值來設定該輪入電壓 之一目標位準：（該增壓電壓之該目標位準/該增壓率）。 該方法可進一步包括回應於該輸入電壓之該目標位準超 出該輸入電壓之一位準範圍而增大該增壓率。 J51662.doc 201140273 该方法可進一步包括回應於在該增壓率減小時該輸入電 壓之該目標位準屬於該輸入電壓之該位準範圍而減小該增 壓率。 該方法可進一步包括：將該增壓電壓除以基於該增壓率 判定之一比率；輸出經分壓之電壓；基於該增壓率而在基 於。亥增壓電壓之該目標位準所產生之複數個電壓中選擇一 輸入參考電壓；比較一輸出電壓與一輸入參考電壓產生 一初步輸入電壓；放大該初步輸入電壓；及產生該輸入電 壓。 該方法可進一步包括按以下之一比率對該增壓電壓進行 分壓：ι/(該增壓率* 一放大率）。 該方法可進一步包括根據下式選擇一係該目標位準之輸 入參考電壓：該增壓電壓/(該增壓率* 一放大率 該方法可進一步包括防止該初步輸入電壓過度增大或減 /J、0 該方法可進一步包括回應於該增壓率而在輸入之電壓中 選擇一下箝位電壓》 該方法可進一步包括使該初步輸入電壓之位準穩定。 該方法可進一步包括：產生：—增壓率遞增參考電壓， 及一增壓率遞減參考電壓；回應於該初步輸入電壓高於該 增壓率遞增參考電壓而啟用一增壓率遞増旗標信號；回應 於該初步輸入電壓低於該增壓率遞減參考電壓而啟用一增 壓率遞減旗標信號；及回應於該增壓率遞增旗標信號及 或該增壓率遞減旗標信號而設定該增壓率。 151662.doc •10· 201140273 該方法可進一步包括提供關於該增壓率之一初始值的資 訊。 該方法可進一步包括比較各別輸入參考電壓值與一初始 參考電壓。 該方法可進一步包括：回應於該增壓率遞增旗標信號經 啟用歷時長於一參考時間而增大該增壓率，及回應於該增 壓率遞減旗標信號經啟用歷時長於一參考時間而減小該增 壓率。 在該方法中，該增壓率遞增參考電壓之一位準可根據下 式來判定· 一電源電壓/(放大器之一放大率）；且該增里率 遞減參考電麼之一位準根據下式來判定：該電源電壓* (該 增壓率-一增壓率改變之一單位）/(該放大器之該放大率*該 增壓率）。 其他特徵及態樣可自以下[貫施方式]、圖式及申請專利 範圍而顯而易見。 【實施方式】 k供以下[貫施方式]以輔助讀者獲得對本文中所描述之 方法裝置及/或糸統之全面理解。因此，將向一般熟習 此項技術者建議本文中所描述之系統、裝置及/或方法之 各種改變、修改及等效物。所描述之處理步驟及/或操作 之進展為一實例；然而，步驟及/或操作之順序並不限於 本文中所闡述之順序，且除有必要以特定次序發生之步驟 及/或操作外，步驟及/或操作之順序可如此項技術中所知 地進行改變。又，為了增強清晰度及簡明度，可省略對熟 151662.doc •11 · 201140273 知功能及構造之描述。 圖2為說明根據一實施例之一增壓電壓產生電路的方塊 圖。 參看圖2，增壓電壓產生電路包括一增壓電路200、一增 壓率設定單元210，及一輸入電壓位準設定單元220。 增壓電路200可基於一增壓率BT[a:0]使一輸入電壓VCIN 增壓，且可輸出一係輸出電壓的增壓電壓VOUT。因此， 增壓電壓VOUT可為輸入電壓VCIN乘以增壓率BT[a:0]的乘 積。舉例而言，當增壓率BT[a:0]為「2」且輸入電壓VCIN 為1 V時，增壓電壓VOUT可變為2 V。當增壓率BT[a:0]為 「3」且輸入電壓VCIN為0.8 V時，增壓電壓VOUT可變為 2.4 V。 輸入電壓位準設定單元220可回應於增壓電壓VOUT之目 標位準及增壓率BT[a:0]而設定輸入電壓VCIN之位準。舉 例而言，輸入電壓位準設定單元220可設定藉由將增壓電 壓VOUT之目標位準除以增壓率BT[a:0](例如，增壓電壓 VOUT之目標位準/增壓率BT[a:0])所獲得之值作為輸入電 壓VCIN的目標位準。儘管輸入電壓VCIN之目標位準可為 增壓電壓VOUT之目標位準除以增壓率BT[a:0] ’但輸入電 壓VCIN之位準可能低於藉由將增壓電壓νουτ之目標位準 除以增壓率BT[a:0](例如，增壓電壓VOUT之目標位準/增 壓率BT[a:0])所獲得之值。因為輸入電壓VCIN之目標位準 可能超出電源電壓VDD之位準，所以輸入電壓VCIN不可 高於電源電壓VDD。 151662.doc •12- 201140273 [等式1] VCIN=增壓電壓VOUT之目標位準/增壓率BT[a:0] 增壓率設定單元210可接收關於輸入電壓VCIN之位準之 回饋，且可設定增壓率BT[a:0]。增壓率設定單元210可回 應於輸入電壓VCIN之目標位準處於輸入電壓VCIN不可具 有之位準而增大增壓率BT[a:0]。輸入電壓VCIN之目標位 準可判定為藉由將增壓電壓VOUT之目標位準除以增壓率 BT[a:0](增壓電壓VOUT之目標位準/增壓率BT[a:0])所獲得 的值。回應於藉由將增壓電壓VOUT之目標位準除以增壓 率BT[a:0](例如，增壓電壓VOUT之目標位準/增壓率 BT[a:0])所獲得的值高於電源電壓VDD，輸入電壓VCIN不 可收斂至其目標位準。在此狀況下，增壓率設定單元21 0 可增大增壓率BT[a:0]。可僅在需要提高增壓率BT[a:0]時 提高增壓率BT[a:0]。由於輸入電壓VCIN之目標位準為藉 由將增壓電壓VOUT之目標位準除以增壓率BT[a:0](例如， 增壓電壓VOUT之目標位準/增壓率BT[a:0])所獲得的值， 因此回應於經增大之增壓率BT[a:0]，輸入電壓VCIN之目 標位準亦可減小。 儘管增壓率BT[a:0]可減小一個步長，但增壓率設定單 元210可回應於輸入電壓VCIN之目標位準處於輸入電壓 VCIN可具有之位準而減小增壓率BT[a:0]。由於輸入電壓 VCIN之目標位準為藉由將增壓電壓VOUT之目標位準除以 增壓率BT[a:0](例如，增壓電壓VOUT之目標位準/增壓率 151662.doc •13- 201140273 BT[a:0])所獲得的值，因此回應於經減小之增壓率 BT[a:0] ’輸入電壓VCIN之目標位準可増大。若減小增壓 率BT[a:0]並增大輸入電壓VCIN之目標位準，且輸入電壓 VCIN之經增大之目標位準變為高於電源電壓，則可 再次增大增壓率BT[a:0]。 增壓率設定單元210可執行所有上述操作。換言之，增 壓率設定單元210可僅在需要增大增壓率BT[a:〇]時增大增 壓率BT[a:0]，且增壓率設定單元210可試圖執行用於使增 壓率BT[a:0]減小與可准許之量一樣多的一操作。 增壓操作為用於產生位準高於輸入電壓之位準之電壓的 操作。增壓率變得愈高，則可能消耗愈多電流。因此，回 應於產生具有同一位準的電壓，可藉由減小增壓率來減少 增壓操作所消耗之電流的量。舉例而言，藉由使2 v增壓 1.5倍來產生3 V電壓所消耗的電流較少於藉由使丄v增壓 三倍來產生3 V電壓消耗的電流。根據一實施例，由於經 由增壓率設定單元210及輸入電壓位準設定單元22〇之操作 將增壓率BT[a:〇]設定為最小值，因此可使增壓電壓產生電 路之電流消耗最小化。 圖3為說明圖2之增壓電壓產生電路的詳細方塊圖。 參看圖3 ’增壓率設定單元210可包括一分壓器3 ^、一 旗標信號產生器312、一增壓率控制器313，及一初始值判 定器314。輸入電壓位準設定單元22〇可包括一輸出電壓分 壓器321、一輪入參考電壓選擇器322、一比較器323、一 放大器324、一下箝位電壓選擇器325、一電壓箝326，及 151662.doc • 14· 201140273 一補償電路327。 分壓器311可產生一增壓率遞增參考電壓BTUP_REF及一 增壓率遞減參考電壓btdn__ref。回應於初步輸入電壓 VCIN_F高於增壓率遞增參考電壓BTUP_REF，旗標信號產 生器312可啟用增壓率遞增旗標信號BTUP_FG。回應於初 ' 步輸入電壓VCIN_F低於增壓率遞減參考電壓 BTDN一REF ’旗標信號產生器312可啟用增壓率遞減旗標 信號BTDN_FG。增壓率控制器3丨3可回應於增壓率遞增旗 標信號BTUP_FG及增壓率遞減旗標信號btdN_FG而設定 增壓率BT[a:0]。初始值判定器314可向增壓率控制器313提 供關於增壓率BT[a:〇]之初始值的信號βτ_ινΙ[πι:0]。 輸出電壓分壓器321可將增壓電壓v〇UT除以基於增壓率 BT[a:0]判定之比率’且可輸出至少一經分壓之電壓。輸入 參考電壓選擇器322可基於増壓率BT[a:0]在複數個電壓 VR_REF[m:0]中選擇一輸入參考電壓vC_REF〇，該複數個 電壓VR—REF[m:0]可基於增壓電壓ν〇υτ之目標位準而產 生。比較器323可比較輸出電壓分壓器321之輸出電壓 VOUT—F與輸入參考電壓選擇器322之輸出電壓 VC一REF0，且可產生初步輸入電壓VCIN_F。放大器324可 放大初步輸入電壓VCIN_F，且可產生輸入電壓VCIN。下 箝位電壓選擇器3 25可選擇一下箝位電壓乂(：]^1)_1)]^〇，且 可輸出一經選擇之下箝位電壓。電壓箝326可將初步輸入 電壓VCIN_F控制為不高於上箝位電壓VCMp_up〇且不低 於下箝位電壓VCMP_DN0，使得初步輸入電壓vciN F不 151662.doc -15- 201140273 會變得過高或過低。補償電路327可有助於使初步輸入電 壓VCIN_F之位準穩定。將參看隨附圖式詳細描述構成元 件之結構及操作。 圖4為說明根據一實施例之一分壓器3 11的示意圖。 參看圖4，分壓器311可包括耦接至電源電壓VDD及接地 之複數個電阻器，及一類比電壓多工器（MUX)401。在以 下實例（A)至（D)中，詳細描述由分壓器3 11產生之增壓率 遞增參考電壓BTUP_REF、增壓率遞減參考電壓 BTDN_REF、上箝位電壓VCMP_UP0及一初始參考電壓 BTINI_REF。 (A)增壓率遞增參考電壓BTUP_REF為用於增大增壓率 BT[a:0]之一參考電壓。可比較增壓率遞增參考電壓 BTUP—REF與初步輸入電壓VCIN_F。比較結果可用以判定 是否增大增壓率BT[a:0]。初步輸入電壓▽(：11^_?為可具有 (例如）輸入電壓VCIN之位準之一半的電壓。回應於與電源 電壓VDD相同之輸入電壓VCIN，不論初步輸入電壓 VCIN—F變得多高，輸入電壓vciN皆不可能變得更高。簡 言之’當初步輸入電壓VCIN__F具有為電源電壓VDD/2之 位準時’即使將初步輸入電壓vCIN_F之位準提高成更 高’增壓電壓VOUT亦不可能進一步增大。因此，該點之 電壓可成為增壓率遞增參考電壓btup_ref之位準。增壓 率遞增參考電壓BTUP_REF之位準可設定為電源電壓 VDD/2 ’此係因為放大器324之增壓率可為2。因此，為了 151662.doc _ 16 · 201140273 以一般等式表示增壓率遞增參考電壓BTUP_REF，增壓率 遞增參考電壓BTUP_REF之位準可變為電源電壓VDD/放大 器324之增壓率。 • [等式2] - BTUP_REF=VDD/放大器之增壓率 (B)增壓率遞減參考電壓BTDN_REF為用於減小增壓率 BT[a:0]之參考電壓。可比較增壓率遞減參考電壓 BTDN_REF與初步輸入電壓VCIN—F 〇比較之決定結果可 用以判定是否減小增壓率BT[a:0]。在本文中，m’表示增壓 步長，且m自步長0開始。又，η'表示在0.5與1.5之間的增 壓率。換言之，m之初始值為「0」，且0.5Sn'Sl.5。 以下表1表示增壓步長m’及增壓率iV。輸入電壓VCIN與 等於增壓率η'之因數相乘。 表1 增壓步長m' 增壓率η' 步長〇 1.5 步長1 2 步長2 2.5 步長3 3 步長4 3.5 自表1可見，增壓步長m’與增壓率η'具有根據等式3之關 係。 151662.doc - 17- 201140273 [等式3] n' = (m' + 3)/2 儘管增壓率η'變低一個步長，但基於一點來設定增壓率 遞減參考電壓BTDN_REF，在該點處，初步輸入電壓 VCIN_F之位準低於為電源電壓VDD/2之值。因此，當由 增壓步長m'表示增壓率遞減參考電壓BTDN_REF時，可根 據等式4設定增壓率遞減參考電壓BTDN_REF。 [等式4] BTDN_REF(m')=VDD(m' + 2)/((2*m,)+6) 當由增壓率（η’）表示增壓率遞減參考電壓BTDN_REF 時，可根據等式5設定增壓率遞減參考電壓BTDN_REF。 [等式5] BTDN_REF(n’）=VDD(n’-0.5)/(2*n’） 基於放大器3 24之放大率為2且一個增壓步長之差值為 0.5之假設來獲得等式5中所使用之值。可如以下等式6表 示此等值： [等式6] BTDN_REF(n’)=VDD(n’-增壓率改變之單位）/ (放大器之放大率*η·) 可選擇增壓率遞減參考電壓BTDN_REF之類比電壓多工 151662.doc -18- 201140273 器401可操作以基於放大率BT[a:0]來選擇上述增壓率遞減 參考電壓 BTDN_REF(BTDN_REF[m:0])，該放大率 BT[a:0] 為具有關於放大率η'之資訊的碼。 (C)上箝位電壓VCMP_UP0可輸入至電壓箝326中以便防 止增大在初步輸入電壓VCIN_F之位準不必要地增大且負 載條件或增壓率BT[a:0]改變時初步輸入電壓VCIN_F收斂 至目標值可能花費之時間的問題。初步輸入電壓VCIN_F 滿足以下一點為重要的： [等式7] VCIN_F=VDD/2。 然而，初步輸入電壓VCIN_F可高於該點，且上箝位電 壓VCMP_UP0可用以防止初步輸入電壓VCINJ^^大到高 於該點。因此，可根據等式8設定上箝位電壓 VCMP_UP0。 [等式8] VCMP_UP0=VDD/2+a 本文中，「a」表示可（例如）不大於大約50 mV之容限。 (D)初始參考電壓BTINI_REF為用以在初始增壓操作期 間判定適當增壓率BT[a:0]的參考電壓。在初始操作中’由 於可能需要輪入電壓VCIN以與電源電壓VDD之狀態相同 的狀態開始，因此初始參考電壓BTINI_REF可設定為係電 源電壓VDD/2的值。若考慮到增壓電壓產生電路之操作電 151662.doc •19· 201140273 流而給定某一容限，則初始參考電壓BTINI_REF可設定為 係（電源電壓VDD/2 + β)之值，其中β為大約50 mV之值。 圖5為說明根據一實施例之一旗標信號產生器3 12的示意 圖。 參看圖5，旗標信號產生器312可包括兩個比較器501及 502。第一比較器501可比較初步輸入電壓VCIN_F與增壓 率遞減參考電壓BTDN_REF，且可產生增壓率遞減旗標信 號BTDN—FG。第二比較器502可比較初步輸入電壓VCIN—F 與增壓率遞增參考電壓BTUP_REF，且可產生增壓率遞增 旗標信號BTUP_FG。 回應於初步輸入電壓VCIN_F低於增壓率遞減參考電壓 BTDN_REF，可啟用增壓率遞減旗標信號BTDN_FG以減小 增壓率BT[a:0]。回應於初步輸入電壓VCIN_F高於增壓率 遞增參考電壓BTUP_REF，可啟用增壓率遞增旗標信號 BTUP_FG以增大增壓率BT[a:0]。 回應於初步輸入電壓VCIN_F高於增壓率遞減參考電壓 BTDN_REF且低於增壓率遞增參考電壓BTUP_REF，可皆 停用增壓率遞增旗標信號BTUP_FG及增壓率遞減旗標信號 BTDN—FG。在一實例中，其意謂當前增壓率BT[a:0]為適 當的。 圖6為說明根據一實施例之一輸入參考電壓選擇器322的 示意圖。 參看圖6,輸入參考電壓選擇器322可包括一類比電壓多 工器（MUX)601。 151662.doc -20- 201140273 輸入參考電壓VC_REF0為初步輸入電壓VCIN_F之目標 值。因此，輸入參考電壓VC_REF0可設定為值 VOUTtar/(2n’），其中VOUTtar表示增壓電壓VOUT之目標 值。此係基於放大率為兩倍之假設。可根據等式9來計算 輸入參考電壓VC_REF0。 [等式9] VC_REFO=VOUTtar/(放大器之放大值η，） 當等式9轉換為基於η'及m'之值以獲得輸入至類比電壓多 工器（MUX)601中之值VC_REF[m’]時，根據等式10來設定 VC_REF[m']。 [等式10] VC_REF[m，]=VOUTtar/(m' + 3)。 因此，可如上設定VC_REF[m:0]，且類比電壓多工器 (MUX)601可選擇適於相應增壓率BT[a:0]之電壓作為輸入 參考電壓VC_REF0。 圖7為說明根據一實施例之一初始值判定器3 14的示意 圖。 參看圖7，初始值判定器314可包括m+1個比較器701， 該等比較器701可比較各別VC_REF[m:0]值與初始參考電 壓BTINI_REF。該m+1個比較器701可輸出關於增壓率 BT[a:0]之初始值的信號BT_INI[m:0]。儘管比較器701在圖 式中說明為一構成元件，但比較器701之數目可為m+1或 151662.doc -21 · 201140273 在適當時可為另一數目。第一比較器可比較VC_REF[0]與 初始參考電壓BTINI_REF，且可輸出ΒΤ_ΙΝΙ[0]。最後比 較器可比較VC_REF[m]與初始參考電壓BTINI_REF，且可 輸出 BT一INI[m]。 由於在分壓器311中產生之初始參考電壓BTINI_REF為 (VDD/2 + p)(參見以上實例（D))，因此關於初始值之資訊可 變為關於VC_REF[m:0]是否高於值（VDD/2 + β)的資訊。如 以下表2中所示，可基於VC_REF[m:0]中高於（VDD/2 + β)之 電壓的數目來判定初始增壓率。 表2 BT_INI[m:0] 初始增壓率 2m η 2^2^1 η-0.5 2m+2m-l+2m-2 η-1 ''' ... 2m+2m-l+2m-2+ +2 2 2m+2m-l+2m-2+ +2+l=2m+1-l 1.5 表2展示，當BT_INI[m:0]為（2m+1-l)(例如，在表2之最 後列處）時，當BT_INI[m..O]之所有值為邏輯高時，可採用 最低增壓率（1.5)作為初始增壓率。當BT_INI[m:0]為 (2*m)(例如，在表2之第一列處）時，當僅BT_INI[m]之值 為邏輯高時，可採用最高增壓率（η)作為初始增壓率。 圖8為說明根據一實施例之一增壓率控制器3 13的示意 圖。 151662.doc -22- 201140273 增塵率控制器313可回應於增壓率遞增旗標信號 BTUP_FG經啟用歷時長於一參考時間而增大增壓率 BT[a:0]。增壓率控制器313可回應於增壓率遞減旗標信號 BTDN一FG經啟用歷時長於一參考時間而減小增壓率 BT[a:0]。 增壓率控制器313可包括計數器801及802、比較器803及 804、D型正反器805及806、一初始值解碼器807，及一可 預設之遞增/遞減計數器8〇8。稍後將詳細描述增壓率控制 器3 1 3之元件。 圖9說明計數器801及802之操作。 計數器801及802可在輸入至啟用EN端子之信號 BTUP一FG或BTDN一FG為邏輯高之週期中在時脈ck之上升 緣處執行增大輸出至輸出端子〇UT[b:〇]之碼值 BTUP_CNT[b:0]或 BTDN_CNT[b:〇]的操作。 BTUP_CNT[tr.O]為遞增計數信號；BTDN—CNT[b:〇]為遞減 計數信號。又，回應於輸入至重設RST端子中之為邏輯高 之初始化信號P_ST，輸出至端子〇UT[b:〇]之碼的所有位元 可初始化為0。參看圖9，可理解計數器80 i及8〇2之操作。 輸入至RST端子中之信號為週期信號p_ST，且週期信號 P_ST可在增壓率控制器313改變増壓率BT[a:…之一週期期 間被啟用一次。 回看圖8，比較器803可比較自計數器8〇1輸出之 BTUP_CNT[b:0]與增壓率遞增參考值BTUp—R[b:〇]。回應 於BTUP_CNT[b:0]值大於增壓率遞增參考值 151662.doc -23- 201140273 BTUP_R[b:0]，比較器803可輸出處於邏輯高之增壓遞增啟 用信號BTUP_PEN。回應於BTUP_CNT[b:0]值小於增壓率 遞增參考值BTUP_R[b:0]，比較器803可輸出處於邏輯低之 信號 BTUP_PEN。 比較器804可比較BTDN_CNT[b:0]與增壓率遞減參考值 BTDN_R[b:0]。回應於BTDN_CNT[b:0]值大於增壓率遞減 參考值BTDN_R[b:0]，比較器804可輸出處於邏輯高之信 號BTDN_PEN。回應於BTDN_CNT[b:0]值小於增壓率遞減 參考值BTDN_R[b:0]，比較器804可輸出處於邏輯低之信 號 BTDN_PEN。 隨著增壓率遞增參考值BTUP_R[b:0]及增壓率遞減參考 值BTDN_R[b:0]增大，增壓率遞增旗標信號BTUP_FG及增 壓率遞減旗標信號BTDN_FG之啟用時間變長。 初始值解碼器807可改變在初始值判定器3 14中產生之 BT_INI[m:0]之格式。以下表3表示BT_INI[m:0]及 D_BT_INI[a:0]與藉由前述兩者表示之初始增壓率之間的 關係。 表3 BT_IM[m:0] D_BT_INI[a:0] 初始增壓率 2m 2n-3 η 2m+2m—1 2n-4 n-0.5 2m+2m'x+2m'2 2n-5 n-1 ... ... • · * 2^+2mA+2m'2+...+2 1 2 2m+2m-1+2m-2+. "+2+l=2m+1-l 0 1.5 151662.doc -24- 201140273 圖10說明可預設之遞增/遞減計數器808之操作。回應於 輸入至UP端子中之為邏輯高之信號BTUP_EN，可預設之 遞增/遞減計數器808可在CK端子信號之上升緣處使端子 OUT[a:0]之碼BT[a:0]值增大一，該CK端子信號為P_ST信 號之逆信號。回應於輸入至DN端子中之為邏輯高之信號 BTDN_DN，可預設之遞增/遞減計數器808可在CK端子信 號之上升緣處使端子OUT[a:0]之碼BT[a:0]值減小一。 又，回應於啟用端子PEN之為邏輯高之DC轉換開始信號 DCC_ST，P[a:0]端子之碼 D—BT—INI[a:0]可成為 OUT[a:0] 端子之碼BT[a:0]。簡言之，回應於PEN端子之為邏輯高之 信號，增壓率可初始化為D_BT_INI[a:0]之值。 輸入至PEN端子中之DCC_ST信號可為回應於正起始之 增壓電壓產生電路之操作而啟用至邏輯高的信號。 以下表4表示增壓率碼BT[a_.0](其表示增壓率）與初始增 壓率之間的關係。 表4 BT[a:0] 初始增壓率 0 1.5 1 2 2 2.5 … … 2n-4 n-0.5 2n-3 η 151662.doc - 2$ - 201140273 圖11至圖14說明增壓速率控制器313之操作。圖u說明 增壓率控制器3 1 3之初始操作。圖12說明增壓率控制器3 j 3 之在初始操作之後增大增壓率的操作。圖13說明增壓率控 制器3 13之在初始操作之後減小增壓率的操作。圓丨4說明 增壓率控制器3 13之維持在初始操作期間設定之增壓率的 操作。 參看圖11 ’描述增壓率控制器3 13之初始操作。 在起始增壓電壓產生電路之操作之後，可將DCC_ST信 號啟用至邏輯高。接著，可預設之遞增/遞減計數器8〇8可 將輸入至其P[a:0]端子中iD_BT_INI[2:〇]設定為增壓率 BT[2:0]之初始值。圖11展示D_BT—INI[2:〇]之值為2，且因 此表示增壓率之碼BT[2:0]的值在此實例中為2，且將對應 於BT[2:0]值（2)之增壓率（2.5)設定為增壓率。換言之，在 該所說明實例中增壓率為2.5。應瞭解，給出之值係僅為 了實例目的’且其他輸入值可提供不同輸出值。 圖12說明增壓率控制器313之在初始操作之後增大增壓 率的操作。作為一實例，增壓率遞增參考值BTUp_R[9:… 及增壓率遞減參考值BTDN_R[9:0]可設定為600。 在啟用P—ST信號且p_ST信號經歷遮没週期（p〇rch period)之後，時脈CK可開始進行雙態觸發。回應於為邏 輯高之增壓率遞增旗標信號BTUP_FG，計數器801可對時 脈CK計數，且可逐漸增大BTUP_CNT[9:0]值。回應於收斂 至增壓率遞增參考值（例如，BTUP_R[9:〇]=6〇〇)的增大之 BTUP一CNT[9:〇]值，可將BTUP—PEN信號啟用至邏輯高。 151662.doc -26 - 201140273 BTUP—ΕΝ信號可藉由可經啟用至邏輯高之BtuP_PEN信號 來啟用。回應於可再次啟用之信號，可預設之遞增/ 遞減計數器808可將表示增壓率之碼bT[2:0]值自2增大至 3。因此，增壓率可自2.5增大至3。 圖13說明增壓率控制器3 13之在初始操作之後減小增壓 率的操作。作為一實例，增壓率遞增參考值BTUP_R[9:0] 及增壓率遞減參考值BTDN_R[9:0]可設定為600。 在啟用P_ST信號且P—ST信號經歷遮没週期之後，時脈 CK可開始進行雙態觸發。回應於為邏輯高之增壓率遞減 旗標信號BTDN_FG ’計數器802可對時脈CK計數，且可逐 漸增大8丁〇1^_€>1丁[9:0]值。回應於收斂至增壓率遞減參考 值（例如，BTDN_R[9:〇]=6〇〇)之增大之 BTDN一CNT[9:0] 值’可將BTDN_PEN信號啟用至邏輯高。BTUP_EN信號可 藉由可經啟用至邏輯高之BTDN_PEN信號來啟用。回應於 可再次啟用之P_ST信號，可預設之遞增/遞減計數器808可 將表示增壓率之增壓率碼BT[2:0]值自2減小至1。因此， 增壓率可自2.5減小至2。 圖14說明增壓率控制器313之維持在初始操作期間設定 之增壓率的操作。作為一實例，增壓率遞增參考值 BTUP_R[9:0]及增壓率遞減參考值BTDN_R[9:0]可設定為 600。 在啟用P_ST信號且P_ST信號經歷遮没週期之後，時脈 CK可開始進行雙態觸發。回應於為邏輯高之增壓率遞減 旗標信號BTDN_FG，計數器802可對時脈CK計數，且可逐 151662.doc •27- 201140273 漸增大BTDN_CNT[9:〇]值。在增大btdN_CNT[9:〇]值時， 增壓率遞減旗標信號BTDN_FG可轉變至邏輯低。因此， 例如，BTDN_CNT[9:0]值自值413起可能不再增大。由於 BTDN_CNT[9:0]可能並不收斂至增壓率遞減參考值（例 如’ BTDN_R[9:0] = 600)，因此可不啟用BTUP_PEN信號及 BTUP_EN信號。結果，可預設之遞增/遞減計數器808可不 改變表示增壓率之碼BT[2:0]值。因此，增壓率可維持於 2.5。 在展示於圖14中之實例中，由於啟用增壓率遞減旗標信 號BTDN_FG所在之時間並不收斂至參考時間（例如，600個 時脈循環），因此可能不改變增壓率。換言之，在圖14之 實例中，甚至在600個時脈循環處，BTDN_CNT[9:0]偉停 留在413 ’且將從不到達600，因此將無改變增壓率之信號 產生。 圖15為說明下箝位電壓選擇器325之方塊圖。 下括位電壓選擇益325可包括·一類比多工器 (MUX)1501 ’且可回應於增壓率BT[a:0]在輸入之電壓 VCMP_DN[m:0]中選擇一下箝位電壓vcMP_DN0。 回應於過低之初步輸入電壓VCIN_F及改變之負載條件 或增壓率BT[a:0]，下箝位電壓vCMP_DN0可輸入至電壓 箝326中以防止初步輸入電壓Vcin_f收斂至目標值所花費 之時間增加。 可根據等式11產生輸入至下箝位電壓選擇器3 25中之輸 入電壓 VCMP_DN[m:0]。 151662.doc •28· 201140273 [等式11] VCMP_DN[m']=VC_REF[m']-a，201140273 VI. Description of the Invention: [Technical Field of the Invention] The following description relates to a circuit for generating a boost voltage higher than an input voltage, and a method for operating the boost voltage generating circuit. The present application claims the rights of the Korean Patent Application No. 10-2009-0 003 071, filed on Dec. 17, 2009, and the Korean Patent Application No. 10-2010-003563, filed on Apr. 19, 2010. The entire disclosure of each of the applications is hereby incorporated by reference in its entirety for all purposes. [Prior Art] Different semiconductor devices operate internal circuits by voltages supplied from the outside. Since voltages of different levels are used in the internal constituent elements of the semiconductor device, it is difficult to supply all voltages to be used inside the semiconductor device from outside the device. Therefore, the semiconductor device is equipped with an internal voltage generating circuit to generate voltages of different levels inside the device. In other words, when the level of the power supply voltage supplied from the battery is low and the level of the driving voltage to be used inside the device is higher than the level of the input power supply voltage, the device using the battery power should be able to generate a high level. The voltage at the level of the input supply voltage input from the outside. A voltage DC_DC converter that produces a level higher than the input voltage is divided into a switching mode power supply (SMPS) type using an inductor and a charge pump type using a capacitor. In the case of a driving device, the mobile device typically has a charge pump type because current consumption is not large. 151662. Doc 201140273 Unlike linear power supplies, SMPSi passivated transistors (pa% 11^1134〇〇 switch very fast between the all-on state and the fully-off state (usually between π kHz and 1 MHz)' The wasted energy is minimized. The voltage regulation is provided by varying the ratio of the on-time to the off-time. Underneath, the linear power supply must dissipate excess voltage to regulate the output. This higher efficiency is the primary of the SMPS. Advantages: When a higher efficiency, smaller size, and/or lighter weight is required, a switching regulator is used to replace the linear regulator. Figure 1 is a block diagram showing the voltage, signal, and output voltage of the boost voltage generating circuit. The input voltage VCIN and the boost rate BT[a:0] are input to the boost voltage generating circuit 1A. The boost voltage generating circuit 100 makes the input based on the boost rate indicated by the boost rate BT[a:〇]. The voltage VCIN is boosted and generates boosted electric dust VOUT. For example, when the boost rate BT[a:0] is 2 (which means double or double), the boost voltage generating circuit 100 makes the input voltage VCIN boosts twice (that is, 'doubles the voltage') and produces Piezoelectric dust ν 〇υ τ. The target value of the boost voltage VOUT is the same, but there may be different input voltage enhancement rates BT[a:0] in the boost voltage generating circuit 100. For example, when When the target value of the boost voltage ν 〇υ τ is 3 ν '(a) The boost voltage VOUT of 3 V can be generated by double-pressing (ie, doubling) the input voltage VCIN of 15 ν, or b) The boost voltage VOUT of 3 ν can be generated by boosting the input voltage VCIN of 1 V three times (ie, by a factor of three). However, although the same boost voltage VOUT is generated, the boost voltage is generated. The amount of current consumed by circuit 100 can vary greatly based on how input voltage VCIN and boost rate BT[a:0] are set. 151662. Doc 201140273 However, the conventional power supply benefit does not cause the input voltage VCIN and the boost rate BT[a:0] input to the boost voltage generating circuit 1〇〇 according to the target level of the boost voltage ν〇υτ. Jiahua. SUMMARY OF THE INVENTION In a general aspect, a boost voltage generating circuit is provided, comprising: a boosting circuit configured to: boost an input voltage based on a boost rate, and output a boost voltage a boost rate setting unit configured to receive one of the feedback levels of the input voltage and set the boost rate; and an input voltage level setting unit configured to respond in response to The level of the input voltage is set by the following: one of the target levels of the boost voltage and the boost rate. In the boost voltage generating circuit, the input voltage level setting unit may be further configured to set a target level of the input voltage according to one of the following values: (the target level of the boost voltage / the Supercharge rate). In the boost voltage generating circuit, the boost rate setting unit may be further configured to increase the boost rate in response to the target level of the input voltage exceeding a level of the input voltage. In the boost voltage generating circuit, the boost rate setting unit may be further configured to respond to the target level of the input voltage falling within the level range of the input voltage when the boost rate is decreased The boost rate is small. In the boost voltage generating circuit, the input voltage level setting unit may include. An output voltage divider configured to: divide the boost voltage by a ratio based on the boost rate determination, and output a divided voltage; an input reference voltage selector configured to Based on the boost rate based on 15I662. Doc 201140273 Selecting an input reference voltage from a plurality of voltages generated by the target level of the boost voltage, a comparator configured to: compare one of the output voltage dividers with an output voltage and the input reference One of the voltage selectors outputs a voltage and generates a preliminary input voltage; and an amplifier configured to: amplify the preliminary input voltage 'and generate the input voltage. In the boost voltage generating circuit, the amplifier includes: a comparator configured as a linear regulator; and a plurality of resistors. In the boost voltage generating circuit, the output voltage divider can be further configured to divide the boost voltage by a ratio of: 丨 / (the boost rate * one of the amplifiers) . In the boost voltage generating circuit, the input reference voltage selector may be further configured to input a reference voltage for one of the target levels according to the following formula: the boost voltage / (the boost rate * the amplifier a magnification). In the boost voltage generating circuit, the input voltage level setting unit further includes a voltage clamp configured to prevent the preliminary input voltage from excessively increasing or decreasing. In the boost voltage generating circuit, the voltage clamp can include an analog multiplexer configured to select a lower clamp voltage among the input voltages in response to the boost rate. In the boost voltage generating circuit, the input voltage level setting unit may further include a compensation circuit configured to stabilize the level of the preliminary input voltage. In the boosted voltage generating circuit, the compensation circuit includes a resistor and a capacitor. 151662. Doc 201140273 In the boost voltage generating circuit, the boost rate setting unit may include: a brancher configured to generate: a boost rate increasing reference voltage, and a boost rate decreasing reference voltage; a flag signal generator configured to: responsive to the preliminary turn-in voltage being higher than the boost rate increment reference voltage to enable a boost rate increment flag signal, and responsive to the preliminary input voltage being less than the increase The boost rate decrements the reference voltage to enable a boost rate decrement flag signal; and a boost rate controller 'configured to respond to the boost rate increment flag signal and/or the boost rate down flag signal The boost rate is set. In the boost voltage generating circuit, the boost rate setting unit may further include an initial value determiner configured to provide the boost rate controller with information about an initial value of the 5 boost rate . In the boost voltage generating circuit, the initial value determiner can include a plurality of comparators configured to compare the respective input reference voltage values with an initial reference voltage. In the boost voltage generating circuit, the boost rate controller may be configured to: increase the boost rate in response to the boost rate increment flag signal being enabled for longer than the reference time, and The boost rate is reduced in response to the boost rate decrement flag signal being enabled for longer than a reference time. In the boost voltage generating circuit, the boost rate controller may include: a plurality of counters, a plurality of comparators, a plurality of flip-flops, an initial value decoder, and a preset forward/decrement counter . In the boost voltage generating circuit, the preset up/down counter may be configured to set an initial boost rate signal input to the preset up/down counter to the boost rate An initial value; responded to 151662. Doc 201140273 Logic high of the boost rate increment flag signal, one of the plurality of counters can be configured to count a clock to increase an increment count value 'and in response to the increase The value converges to the boost rate increment reference voltage, and the S-uptable up/down counter can be further configured to enable one of the boost rates to increase. In the boost voltage generating circuit, the preset up/down counter may be configured to set an initial boost rate k number input to the preset up/down counter to the boost rate One of the initial values 丨 is responsive to a decrement flag signal for the logic south, and the second counter can be configured to count the clock to increase a countdown value, and In response to the increased divergence count value converges to the boost rate decrementing reference voltage, the pre-settable up/down counter can be further configured to enable one of the boost rate reductions. In the boost voltage generating circuit, the preset up/down count state may be configured to set an initial boost rate signal input to the preset up/down counter to the boost rate An initial value 回应 and in response to a logic request, the 6th boost rate decrement flag signal, one of the plurality of counters can be configured to count a clock to increase a countdown value The flag signal transitions to a logic low when increasing the A down count value such that the down count m step increases by A such that the preset up/down counter does not enable one of the boost rate changes. In the boosted voltage generating circuit, the boosting rate incrementing reference voltage can be determined according to the following formula: - the power supply voltage / (one of the amplifiers), and the dusting rate is decremented by reference. The level can be judged according to the following formula 151662. Doc 201140273 - one unit of supercharging rate change) / (The setting · · the power supply voltage * (the supercharging rate - the amplification of the 5 Hai magnification * the supercharging rate) in another general condition towel, provided In a method of operating a boost voltage generating circuit, the boost voltage generating circuit generates a boost voltage by pressing an input voltage based on a boost rate, the method comprising: generating a target with one of the following levels The input voltage: (one of the boost voltage targets = pressure / a boost rate); the target level of the input voltage exceeds the - level range of the input voltage to increase the boost rate; and Responding to the target level of the input voltage when the boost rate is decreased belongs to the input voltage; the level is reduced to reduce the boost rate. In the method, the level may not have a higher than - In the method, the decrease in the boost rate may be performed in response to the target level of the turn-in voltage being lower than one of: (the boost rate is changed by one unit) / The supercharging rate. In another aspect, providing a boosting power The method of pressing, the method includes: pressurizing an input voltage based on a supercharging rate; rotating out-increasing the electric power, receiving one feedback on one of the input electric dust levels; setting, the supercharging rate; The level of the input voltage is set in response to the following: one of the target levels of the boost voltage and the boost rate. The method may further include setting a target bit of the wheel-in voltage according to one of the following values The method: (the target level of the boost voltage / the boost rate). The method may further include increasing the boost rate in response to the target level of the input voltage exceeding a level of the input voltage J51662. Doc 201140273 The method can further include reducing the boost rate in response to the target level of the input voltage falling within the level of the input voltage as the boost rate decreases. The method may further include dividing the boosted voltage by a ratio based on the boost rate determination; outputting the divided voltage; based on the boost rate. An input reference voltage is selected from a plurality of voltages generated by the target level of the boost voltage; comparing an output voltage with an input reference voltage to generate a preliminary input voltage; amplifying the preliminary input voltage; and generating the input voltage. The method may further comprise dividing the boost voltage by a ratio of: ι / (the boost rate * a magnification). The method may further include selecting an input reference voltage of the target level according to the following formula: the boost voltage / (the boost rate * a magnification) the method may further comprise preventing the preliminary input voltage from excessively increasing or decreasing / J, 0 The method can further include selecting a clamp voltage in the input voltage in response to the boost rate. The method can further include stabilizing the level of the preliminary input voltage. The method can further include: generating: - The boost rate is increased by a reference voltage, and a boost rate is decreased by a reference voltage; a boost rate flag is enabled in response to the preliminary input voltage being higher than the boost rate increment reference voltage; and the initial input voltage is low in response to the initial input voltage The boost rate decrementing reference voltage is used to enable a boost rate decrement flag signal; and the boost rate is set in response to the boost rate increment flag signal and or the boost rate down flag signal. Doc •10· 201140273 The method may further comprise providing information regarding an initial value of the boost rate. The method can further include comparing the respective input reference voltage values to an initial reference voltage. The method may further include: increasing the boost rate in response to the boost rate increment flag signal being enabled for longer than a reference time, and in response to the boost rate down flag signal being enabled for longer than a reference time Reduce the boost rate. In the method, one of the boost rate increment reference voltage levels can be determined according to the following formula: • a power supply voltage / (one of the amplifiers); and the increment rate is reduced by one of the reference levels. The equation determines: the power supply voltage * (the boost rate - a unit of pressure change rate) / (the amplification factor of the amplifier * the boost rate). Other features and aspects will be apparent from the following description, drawings, and claims. [Embodiment] k is provided in the following [Practical Mode] to assist the reader in obtaining a comprehensive understanding of the method device and/or the system described herein. Accordingly, various changes, modifications, and equivalents of the systems, devices and/or methods described herein will be suggested to those skilled in the art. The described processing steps and/or the progress of the operations are an example; however, the order of steps and/or operations is not limited to the order set forth herein, and unless the steps and/or operations that occur in a particular order are necessary, The order of steps and/or operations can be varied as known in the art. Also, in order to enhance the clarity and conciseness, you can omit the familiar 151662. Doc •11 · 201140273 Description of knowledge and structure. 2 is a block diagram illustrating a boost voltage generating circuit in accordance with an embodiment. Referring to Fig. 2, the boost voltage generating circuit includes a boosting circuit 200, a boosting rate setting unit 210, and an input voltage level setting unit 220. The boost circuit 200 can boost an input voltage VCIN based on a boost rate BT[a:0] and can output a boost voltage VOUT of a series of output voltages. Therefore, the boost voltage VOUT can be the product of the input voltage VCIN multiplied by the boost rate BT[a:0]. For example, when the boost rate BT[a:0] is "2" and the input voltage VCIN is 1 V, the boost voltage VOUT can be changed to 2 V. When the boost rate BT[a:0] is "3" and the input voltage VCIN is 0. At 8 V, the boost voltage VOUT can be changed to 2. 4 V. The input voltage level setting unit 220 can set the level of the input voltage VCIN in response to the target level of the boost voltage VOUT and the boost rate BT[a:0]. For example, the input voltage level setting unit 220 can be configured to divide the target level of the boost voltage VOUT by the boost rate BT[a:0] (eg, the target level/boost rate of the boost voltage VOUT). The value obtained by BT[a:0]) is used as the target level of the input voltage VCIN. Although the target level of the input voltage VCIN may be the target level of the boost voltage VOUT divided by the boost rate BT[a:0] ', the level of the input voltage VCIN may be lower than the target position by the boost voltage νουτ The value obtained by dividing the supercharge rate BT[a:0] (for example, the target level/boost rate BT[a:0] of the boost voltage VOUT). Since the target level of the input voltage VCIN may exceed the level of the power supply voltage VDD, the input voltage VCIN may not be higher than the power supply voltage VDD. 151662. Doc •12- 201140273 [Equation 1] VCIN=target level/boost rate of boost voltage VOUT BT[a:0] The boost rate setting unit 210 can receive feedback on the level of the input voltage VCIN, and can Set the boost rate BT[a:0]. The boost rate setting unit 210 can increase the boost rate BT[a:0] in response to the target level of the input voltage VCIN being at a level that the input voltage VCIN does not have. The target level of the input voltage VCIN can be determined by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (the target level of the boost voltage VOUT/boost rate BT[a:0] ]) The value obtained. In response to a value obtained by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (eg, the target level/boost rate BT[a:0] of the boost voltage VOUT) Above the supply voltage VDD, the input voltage VCIN cannot converge to its target level. In this case, the supercharging rate setting unit 21 0 can increase the supercharging rate BT[a:0]. The boost rate BT[a:0] can be increased only when it is necessary to increase the supercharging rate BT[a:0]. Since the target level of the input voltage VCIN is obtained by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (for example, the target level/boost rate of the boost voltage VOUT BT[a: 0]) The obtained value, therefore, in response to the increased boost rate BT[a:0], the target level of the input voltage VCIN can also be reduced. Although the boost rate BT[a:0] can be reduced by one step, the boost rate setting unit 210 can decrease the boost rate BT in response to the target level of the input voltage VCIN being at a level that the input voltage VCIN can have. [a:0]. Since the target level of the input voltage VCIN is obtained by dividing the target level of the boost voltage VOUT by the boost rate BT[a:0] (for example, the target level/boost rate of the boost voltage VOUT is 151662. Doc •13- 201140273 BT[a:0]) The value obtained, so the target level of the input voltage VCIN can be increased in response to the reduced boost rate BT[a:0] '. If the boost rate BT[a:0] is decreased and the target level of the input voltage VCIN is increased, and the increased target level of the input voltage VCIN becomes higher than the power supply voltage, the boost rate can be increased again. BT[a:0]. The supercharging rate setting unit 210 can perform all of the above operations. In other words, the boost rate setting unit 210 may increase the boost rate BT[a:0] only when it is required to increase the boost rate BT[a:〇], and the boost rate setting unit 210 may attempt to perform the increase The pressure rate BT[a:0] reduces an operation as much as the allowable amount. The boost operation is an operation for generating a voltage having a level higher than the level of the input voltage. The higher the boost rate becomes, the more current may be consumed. Therefore, in response to generating a voltage having the same level, the amount of current consumed by the boosting operation can be reduced by reducing the boost rate. For example, by boosting 2 v 1. The current consumed by 5 times to generate a voltage of 3 V is less than the current consumed by the voltage of 3 V by doubling the voltage of 丄v. According to an embodiment, since the boost rate BT[a:〇] is set to a minimum value by the operation of the boost rate setting unit 210 and the input voltage level setting unit 22, the current consumption of the boost voltage generating circuit can be made. minimize. FIG. 3 is a detailed block diagram illustrating the boost voltage generating circuit of FIG. 2. FIG. Referring to Fig. 3, the boost rate setting unit 210 may include a voltage divider 3^, a flag signal generator 312, a boost rate controller 313, and an initial value determiner 314. The input voltage level setting unit 22A can include an output voltage divider 321 , a wheeled reference voltage selector 322 , a comparator 323 , an amplifier 324 , a lower clamp voltage selector 325 , a voltage clamp 326 , and 151662 . . Doc • 14· 201140273 A compensation circuit 327. The voltage divider 311 can generate a boost rate increment reference voltage BTUP_REF and a boost rate decrement reference voltage btdn__ref. In response to the initial input voltage VCIN_F being higher than the boost rate increment reference voltage BTUP_REF, the flag signal generator 312 can enable the boost rate increment flag signal BTUP_FG. The boost rate decrement flag signal BTDN_FG is enabled in response to the initial step input voltage VCIN_F being lower than the boost rate decrement reference voltage BTDN_REF' flag signal generator 312. The boost rate controller 3丨3 sets the boost rate BT[a:0] in response to the boost rate increase flag signal BTUP_FG and the boost rate down flag signal btdN_FG. The initial value determiner 314 can provide the boost rate controller 313 with a signal βτ_ινΙ[πι:0] regarding the initial value of the supercharging rate BT[a:〇]. The output voltage divider 321 divides the boost voltage v〇UT by the ratio determined based on the boost rate BT[a:0] and outputs at least one divided voltage. The input reference voltage selector 322 may select an input reference voltage vC_REF〇 among the plurality of voltages VR_REF[m:0] based on the rolling rate BT[a:0], and the plurality of voltages VR_REF[m:0] may be based on The target level of the boost voltage ν 〇υ τ is generated. The comparator 323 compares the output voltage VOUT_F of the output voltage divider 321 with the output voltage VC_REF0 of the input reference voltage selector 322, and can generate a preliminary input voltage VCIN_F. Amplifier 324 amplifies the preliminary input voltage VCIN_F and can generate an input voltage VCIN. The lower clamp voltage selector 3 25 can select the clamp voltage 乂(:]^1)_1)]^〇, and can output the clamp voltage after selection. The voltage clamp 326 can control the preliminary input voltage VCIN_F to be not higher than the upper clamp voltage VCMp_up 〇 and not lower than the lower clamp voltage VCMP_DN0, so that the preliminary input voltage vciN F is not 151662. Doc -15- 201140273 will become too high or too low. The compensation circuit 327 can help stabilize the level of the preliminary input voltage VCIN_F. The structure and operation of the constituent elements will be described in detail with reference to the accompanying drawings. 4 is a schematic diagram illustrating a voltage divider 3 11 in accordance with an embodiment. Referring to FIG. 4, voltage divider 311 can include a plurality of resistors coupled to supply voltage VDD and ground, and a analog multiplexer (MUX) 401. In the following examples (A) to (D), the boost rate increment reference voltage BTUP_REF, the boost rate decrement reference voltage BTDN_REF, the upper clamp voltage VCMP_UP0, and an initial reference voltage BTINI_REF generated by the voltage divider 3 11 are described in detail. (A) The boost rate increment reference voltage BTUP_REF is a reference voltage for increasing the boost rate BT[a:0]. The boost rate can be compared to the reference voltage BTUP_REF and the initial input voltage VCIN_F. The comparison result can be used to determine whether or not to increase the supercharging rate BT[a:0]. The initial input voltage ▽(:11^_? is a voltage that can have, for example, one-half of the input voltage VCIN. In response to the same input voltage VCIN as the supply voltage VDD, no matter how high the initial input voltage VCIN-F becomes. The input voltage vciN is unlikely to become higher. In short, 'when the initial input voltage VCIN__F has the level of the power supply voltage VDD/2', even if the level of the preliminary input voltage vCIN_F is raised to a higher 'boost voltage VOUT' It is also impossible to further increase. Therefore, the voltage at this point can be the level of the boost rate increment reference voltage btup_ref. The level of the boost rate increment reference voltage BTUP_REF can be set to the power supply voltage VDD/2 'this is because the amplifier 324 The boost rate can be 2. Therefore, for 151662. Doc _ 16 · 201140273 The boost rate increment reference voltage BTUP_REF is expressed by the general equation, and the level of the boost rate increment reference voltage BTUP_REF can be changed to the boost voltage of the power supply voltage VDD/amplifier 324. • [Equation 2] - BTUP_REF = VDD / Amplifier's boost rate (B) The boost rate decrement reference voltage BTDN_REF is the reference voltage for reducing the boost rate BT[a:0]. The comparison result of the comparable boost rate decrement reference voltage BTDN_REF compared with the preliminary input voltage VCIN_F 可 can be used to determine whether to reduce the boost rate BT[a:0]. In this context, m' denotes a boost step and m starts from step 0. Also, η' means at 0. 5 and 1. The rate of increase between the five. In other words, the initial value of m is "0" and 0. 5Sn'Sl. 5. Table 1 below shows the supercharging step m' and the supercharging rate iV. The input voltage VCIN is multiplied by a factor equal to the boost rate η'. Table 1 boost step m' boost rate η' step 〇 1. 5 steps 1 2 steps 2 2. 5 steps 3 3 steps 4 3. 5 As can be seen from Table 1, the supercharging step m' and the supercharging rate η' have a relationship according to Equation 3. 151662. Doc - 17- 201140273 [Equation 3] n' = (m' + 3)/2 Although the boost rate η' goes low by one step, the boost rate decrement reference voltage BTDN_REF is set based on one point, at this point The initial input voltage VCIN_F is lower than the value of the power supply voltage VDD/2. Therefore, when the boost rate decrement reference voltage BTDN_REF is represented by the boost step m', the boost rate decrement reference voltage BTDN_REF can be set according to Equation 4. [Equation 4] BTDN_REF(m')=VDD(m' + 2)/((2*m,)+6) When the supercharging rate decrementing reference voltage BTDN_REF is represented by the supercharging rate (η'), Equation 5 sets the boost rate decrement reference voltage BTDN_REF. [Equation 5] BTDN_REF(n')=VDD(n’-0. 5) / (2 * n') The amplification factor based on amplifier 3 24 is 2 and the difference between one boost step is 0. The assumption of 5 is to obtain the value used in Equation 5. This value can be expressed as Equation 6 below: [Equation 6] BTDN_REF(n') = VDD (n' - unit of change in supercharging rate) / (magnification of amplifier * η ·) Selectable deceleration rate Analog voltage BTDN_REF analog voltage 151662. Doc -18- 201140273 401 is operable to select the above-described boost rate decrement reference voltage BTDN_REF (BTDN_REF[m:0]) based on the amplification factor BT[a:0], the amplification ratio BT[a:0] having The code of the information of the magnification η'. (C) The upper clamp voltage VCMP_UP0 may be input to the voltage clamp 326 to prevent an increase in the initial input voltage when the level of the preliminary input voltage VCIN_F is unnecessarily increased and the load condition or the boost rate BT[a:0] is changed. The problem that VCIN_F can converge to the target value may take time. It is important that the initial input voltage VCIN_F satisfies the following: [Equation 7] VCIN_F=VDD/2. However, the preliminary input voltage VCIN_F can be higher than this point, and the upper clamp voltage VCMP_UP0 can be used to prevent the preliminary input voltage VCINJ^^ from being larger than this point. Therefore, the upper clamp voltage VCMP_UP0 can be set according to Equation 8. [Equation 8] VCMP_UP0=VDD/2+a Herein, "a" denotes a tolerance which can be, for example, not more than about 50 mV. (D) The initial reference voltage BTINI_REF is a reference voltage for determining the appropriate boost rate BT[a:0] during the initial boost operation. In the initial operation, since the round-up voltage VCIN may be required to start in the same state as the state of the power supply voltage VDD, the initial reference voltage BTINI_REF may be set to a value of the system power supply voltage VDD/2. Considering the operating voltage of the boost voltage generating circuit 151662. Doc •19· 201140273 Given a certain tolerance, the initial reference voltage BTINI_REF can be set to the value of the system (power supply voltage VDD/2 + β), where β is a value of approximately 50 mV. FIG. 5 is a schematic diagram illustrating a flag signal generator 3 12 in accordance with an embodiment. Referring to Figure 5, the flag signal generator 312 can include two comparators 501 and 502. The first comparator 501 can compare the preliminary input voltage VCIN_F with the boost rate decrement reference voltage BTDN_REF, and can generate the boost rate decrement flag signal BTDN_FG. The second comparator 502 can compare the preliminary input voltage VCIN_F with the boost rate increment reference voltage BTUP_REF and can generate a boost rate increment flag signal BTUP_FG. In response to the initial input voltage VCIN_F being lower than the boost rate decrement reference voltage BTDN_REF, the boost rate decrement flag signal BTDN_FG may be enabled to decrease the boost rate BT[a:0]. In response to the initial input voltage VCIN_F being higher than the boost rate increment reference voltage BTUP_REF, the boost rate increment flag signal BTUP_FG may be enabled to increase the boost rate BT[a:0]. In response to the initial input voltage VCIN_F being higher than the boost rate decrement reference voltage BTDN_REF and lower than the boost rate increment reference voltage BTUP_REF, the boost rate increment flag signal BTUP_FG and the boost rate down flag signal BTDN_FG may be disabled. In an example, it means that the current boost rate BT[a:0] is appropriate. FIG. 6 is a diagram illustrating an input reference voltage selector 322 in accordance with an embodiment. Referring to Figure 6, the input reference voltage selector 322 can include an analog voltage multiplier (MUX) 601. 151662. Doc -20- 201140273 The input reference voltage VC_REF0 is the target value of the initial input voltage VCIN_F. Therefore, the input reference voltage VC_REF0 can be set to a value of VOUTtar / (2n'), where VOUTtar represents the target value of the boost voltage VOUT. This is based on the assumption that the magnification is twice. The input reference voltage VC_REF0 can be calculated according to Equation 9. [Equation 9] VC_REFO=VOUTtar/(amplifier value η of the amplifier) When Equation 9 is converted to a value based on η' and m' to obtain a value input to the analog voltage multiplexer (MUX) 601 VC_REF[m When '], VC_REF[m'] is set according to Equation 10. [Equation 10] VC_REF[m,]=VOUTtar/(m' + 3). Therefore, VC_REF[m:0] can be set as above, and the analog voltage multiplexer (MUX) 601 can select a voltage suitable for the corresponding boost rate BT[a:0] as the input reference voltage VC_REF0. FIG. 7 is a schematic diagram illustrating an initial value determiner 314 according to an embodiment. Referring to Fig. 7, initial value determiner 314 can include m+1 comparators 701 that can compare respective VC_REF[m:0] values with an initial reference voltage BTINI_REF. The m+1 comparators 701 can output a signal BT_INI[m:0] regarding the initial value of the supercharging rate BT[a:0]. Although the comparator 701 is illustrated as a constituent element in the drawings, the number of comparators 701 may be m+1 or 151662. Doc -21 · 201140273 Can be another number when appropriate. The first comparator compares VC_REF[0] with the initial reference voltage BTINI_REF and can output ΒΤ_ΙΝΙ[0]. Finally, the comparator compares VC_REF[m] with the initial reference voltage BTINI_REF and can output BT_INI[m]. Since the initial reference voltage BTINI_REF generated in the voltage divider 311 is (VDD/2 + p) (see the above example (D)), the information about the initial value can be changed as to whether VC_REF[m:0] is higher than the value. (VDD/2 + β) information. As shown in Table 2 below, the initial boost rate can be determined based on the number of voltages higher than (VDD/2 + β) in VC_REF[m:0]. Table 2 BT_INI[m:0] initial boost rate 2m η 2^2^1 η-0. 5 2m+2m-l+2m-2 η-1 ''' . . . 2m+2m-l+2m-2+ +2 2 2m+2m-l+2m-2+ +2+l=2m+1-l 1. 5 Table 2 shows that when BT_INI[m:0] is (2m+1-l) (for example, at the last column of Table 2), when BT_INI[m. . When all values of O] are logic high, the lowest boost rate can be used (1. 5) As the initial supercharging rate. When BT_INI[m:0] is (2*m) (for example, at the first column of Table 2), when only the value of BT_INI[m] is logic high, the highest boost rate (η) can be used as Initial boost rate. FIG. 8 is a schematic diagram illustrating a boost rate controller 3 13 in accordance with an embodiment. 151662. Doc -22- 201140273 The dust increase rate controller 313 can increase the boost rate BT[a:0] in response to the boost rate increase flag signal BTUP_FG being enabled for longer than a reference time. The boost rate controller 313 can decrease the boost rate BT[a:0] in response to the boost rate decrement flag signal BTDN-FG being enabled for longer than a reference time. The boost rate controller 313 can include counters 801 and 802, comparators 803 and 804, D-type flip-flops 805 and 806, an initial value decoder 807, and a preset up/down counter 8〇8. The components of the boost rate controller 3 1 3 will be described in detail later. Figure 9 illustrates the operation of counters 801 and 802. The counters 801 and 802 can perform an increase of the output to the output terminal 〇UT[b:〇] at the rising edge of the clock ck in a period in which the signal BTUP-FG or BTDN-FG input to the enable EN terminal is logic high. The operation of the value BTUP_CNT[b:0] or BTDN_CNT[b:〇]. BTUP_CNT[tr. O] is the up count signal; BTDN_CNT[b:〇] is the countdown signal. Further, in response to the initialization signal P_ST input to the logic high in the reset RST terminal, all the bits output to the code of the terminal 〇UT[b:〇] can be initialized to 0. Referring to Figure 9, the operation of counters 80i and 8〇2 can be understood. The signal input to the RST terminal is the periodic signal p_ST, and the periodic signal P_ST can be enabled once during the one-cycle period in which the boost rate controller 313 changes the rolling rate BT [a:.... Referring back to Figure 8, the comparator 803 can compare the BTUP_CNT[b:0] output from the counter 8〇1 with the boost rate increment reference value BTUp_R[b:〇]. The response is that the BTUP_CNT[b:0] value is greater than the boost rate increment reference value 151662. Doc -23- 201140273 BTUP_R[b:0], comparator 803 can output a boost boost enable signal BTUP_PEN at logic high. In response to the BTUP_CNT[b:0] value being less than the boost rate increment reference value BTUP_R[b:0], the comparator 803 can output the signal BTUP_PEN at logic low. Comparator 804 can compare BTDN_CNT[b:0] with a boost rate decrement reference value BTDN_R[b:0]. In response to the BTDN_CNT[b:0] value being greater than the boost rate decrement reference value BTDN_R[b:0], the comparator 804 can output the signal BTDN_PEN at logic high. In response to the BTDN_CNT[b:0] value being less than the boost rate decrement reference value BTDN_R[b:0], the comparator 804 can output the signal BTDN_PEN at a logic low. As the boost rate increment reference value BTUP_R[b:0] and the boost rate decrease reference value BTDN_R[b:0] increase, the boost rate increment flag signal BTUP_FG and the boost rate down flag signal BTDN_FG enable time lengthen. The initial value decoder 807 can change the format of BT_INI[m:0] generated in the initial value determiner 314. Table 3 below shows the relationship between BT_INI[m:0] and D_BT_INI[a:0] and the initial supercharging rate expressed by the foregoing two. Table 3 BT_IM[m:0] D_BT_INI[a:0] Initial boost rate 2m 2n-3 η 2m+2m-1 1n-4 n-0. 5 2m+2m'x+2m'2 2n-5 n-1 . . . . . . • · * 2^+2mA+2m'2+. . . +2 1 2 2m+2m-1+2m-2+. "+2+l=2m+1-l 0 1. 5 151662. Doc -24- 201140273 Figure 10 illustrates the operation of a preset up/down counter 808. In response to the logic high signal BTUP_EN input to the UP terminal, the preset up/down counter 808 can make the code BT[a:0] of the terminal OUT[a:0] at the rising edge of the CK terminal signal. Increasing one, the CK terminal signal is the inverse of the P_ST signal. In response to the signal BTDN_DN input to the logic high in the DN terminal, the preset up/down counter 808 can make the code BT[a:0] of the terminal OUT[a:0] at the rising edge of the CK terminal signal. Decrease one. Further, in response to the DC conversion start signal DCC_ST of the enable terminal PEN being logic high, the code D_BT_INI[a:0] of the P[a:0] terminal can be the code BT of the OUT[a:0] terminal [ a:0]. In short, in response to the logic high signal of the PEN terminal, the boost rate can be initialized to the value of D_BT_INI[a:0]. The DCC_ST signal input to the PEN terminal can be enabled to a logic high signal in response to the operation of the boosting voltage generating circuit that is starting. Table 4 below shows the boost rate code BT[a_. 0] (which indicates the boost rate) and the relationship between the initial pressure increase rate. Table 4 BT[a:0] initial boost rate 0 1. 5 1 2 2 2. 5 ... 2n-4 n-0. 5 2n-3 η 151662. Doc - 2$ - 201140273 Figures 11 through 14 illustrate the operation of the boost rate controller 313. Figure u illustrates the initial operation of the boost rate controller 3 1 3 . Figure 12 illustrates the operation of the boost rate controller 3j3 to increase the boost rate after the initial operation. Figure 13 illustrates the operation of the boost rate controller 3 13 to reduce the boost rate after the initial operation. The circle 4 illustrates the operation of the boost rate controller 3 13 to maintain the boost rate set during the initial operation. The initial operation of the boost rate controller 3 13 is described with reference to FIG. The DCC_ST signal can be enabled to a logic high after the operation of the initial boost voltage generating circuit. Then, the preset up/down counter 8〇8 can set iD_BT_INI[2:〇] input to its P[a:0] terminal to the initial value of the boost rate BT[2:0]. Figure 11 shows that the value of D_BT_INI[2:〇] is 2, and therefore the value of the code BT[2:0] representing the boost rate is 2 in this example and will correspond to the BT[2:0] value. (2) The supercharging rate (2. 5) Set to the boost rate. In other words, the boost rate is 2. in the illustrated example. 5. It should be understood that the values given are for example purposes only and that other input values may provide different output values. Figure 12 illustrates the operation of the boost rate controller 313 to increase the boost rate after the initial operation. As an example, the boost rate increment reference value BTUp_R[9:... and the boost rate decrease reference value BTDN_R[9:0] may be set to 600. After the P-ST signal is enabled and the p_ST signal experiences a p〇rch period, the clock CK can begin to toggle. In response to the logic high increment rate flag signal BTUP_FG, the counter 801 can count the clock CK and can gradually increase the BTUP_CNT[9:0] value. The BTUP-PEN signal can be enabled to a logic high in response to an increase in the BTUP-CNT[9:〇] value that converges to a boost rate increment reference (eg, BTUP_R[9:〇]=6〇〇). 151662. Doc -26 - 201140273 The BTUP-ΕΝ signal can be enabled by a BtuP_PEN signal that can be enabled to logic high. In response to the re-enabling signal, a preset up/down counter 808 can increase the value of the code bT[2:0] representing the boost rate from 2 to 3. Therefore, the boost rate can be from 2. 5 increased to 3. Figure 13 illustrates the operation of the boost rate controller 3 13 to reduce the boost rate after the initial operation. As an example, the boost rate increment reference value BTUP_R[9:0] and the boost rate decrease reference value BTDN_R[9:0] may be set to 600. After the P_ST signal is enabled and the P-ST signal experiences an occlusion period, the clock CK can begin a two-state trigger. In response to the decrement rate of the logic high, the flag signal BTDN_FG' counter 802 counts the clock CK and can gradually increase the value of 8 〇 1 ^ _ > 1 [ [9: 0]. The BTDN_PEN signal can be enabled to a logic high in response to an increase in the BTDN-CNT[9:0] value that converges to the boost rate decrement reference value (eg, BTDN_R[9:〇]=6〇〇). The BTUP_EN signal can be enabled by a BTDN_PEN signal that can be enabled to logic high. In response to the re-enabled P_ST signal, a preset up/down counter 808 can reduce the boost rate code BT[2:0] value representing the boost rate from 2 to 1. Therefore, the supercharging rate can be from 2. 5 is reduced to 2. Fig. 14 illustrates the operation of the boost rate controller 313 to maintain the boost rate set during the initial operation. As an example, the boost rate increment reference value BTUP_R[9:0] and the boost rate decrease reference value BTDN_R[9:0] can be set to 600. After the P_ST signal is enabled and the P_ST signal experiences an occlusion period, the clock CK can begin a two-state trigger. In response to the logic high decrement rate flag signal BTDN_FG, the counter 802 can count the clock CK and can be 151662. Doc •27- 201140273 Increase the value of BTDN_CNT[9:〇]. When the value of btdN_CNT[9:〇] is increased, the boost rate decrement flag signal BTDN_FG can be shifted to a logic low. Thus, for example, the BTDN_CNT[9:0] value may no longer increase from value 413. Since BTDN_CNT[9:0] may not converge to the boost rate decrement reference (eg 'BTDN_R[9:0] = 600), the BTUP_PEN signal and the BTUP_EN signal may not be enabled. As a result, the preset up/down counter 808 may not change the value of the code BT[2:0] indicating the boost rate. Therefore, the boost rate can be maintained at 2. 5. In the example shown in Fig. 14, since the time at which the boost rate decrement flag signal BTDN_FG is enabled does not converge to the reference time (e.g., 600 clock cycles), the boost rate may not be changed. In other words, in the example of Figure 14, even at 600 clock cycles, BTDN_CNT[9:0] stops at 413' and will never reach 600, so there will be no signal to change the boost rate. FIG. 15 is a block diagram illustrating the lower clamp voltage selector 325. The lower bracket voltage selection benefit 325 may include an analog multiplexer (MUX) 1501 ' and may select a clamp voltage vcMP_DN0 in the input voltage VCMP_DN[m:0] in response to the boost rate BT[a:0]. . In response to the low initial input voltage VCIN_F and the changed load condition or boost rate BT[a:0], the lower clamp voltage vCMP_DN0 can be input to the voltage clamp 326 to prevent the preliminary input voltage Vcin_f from converge to the target value. The time increases. The input voltage VCMP_DN[m:0] input to the lower clamp voltage selector 325 can be generated according to Equation 11. 151662. Doc •28· 201140273 [Equation 11] VCMP_DN[m']=VC_REF[m']-a,
其中a=50 mV 下箝位電壓選擇器325可選擇適於增壓率BT[a:0]之輸入 電壓VCMP_DN[m:0]作為下箝位電壓VCMP_DNO。 圖16為說明電壓箝326之方塊圖。 電壓箝326可包括一上箝1601及一下箝1602。 上箝1601可回應初步輸入電壓VCIN_FK變得高於上箝 位電壓VCMP_UPO而自初步輸入電壓VCIN_F在接地端子 之間產生吸收電流（sinking current)，從而防止初步輸入電 壓VCIN_F變得高於上箝位電壓VCMP_UPO。 下箝1602可回應於初步輸入電壓VCIN_F變得低於下箝 位電壓VCMP_DNO而自初步輸入電壓VCIN_F在電源電壓 VDD之間產生驅動電流，從而防止初步輸入電壓VCIN_F 變得高於上箝位電壓VCMP_DNO。 圖17為說明輸出電壓分壓器321之方塊圖。 輸出電壓分壓器321可包括經串列耦接以對增壓電壓 VOUT進行分壓之複數個電阻器，及一類比電壓多工器 (MUX)1701。 回應於為η'之當前增壓率BT[a:0]，可根據等式12計算自 輸出電壓分壓器321輸出之增壓電壓v〇UT_F的位準。 [等式12] V0UT/(2*n，）。 151662.doc -29- 201140273 此係因為在此實例中放大器324之放大率為2。可根據以 下等式13更一般地表示該關係。 [等式13] VOUT_F = (VOUT/(n'*放大器之放大率） 當VOUT/(2*n’）表示為基於m'之值時，可根據等式14來 表達 VOUT/(2 * η')。 [等式14] VOUT_F=VOUT/(m，+ 3)。 類比電壓多工器（MUX)1701可操作以基於增壓率BT[a:0] 選擇適當輸出電壓VOUT_F。 圖18為說明補償電路327之方塊圖。 補償電路327可包括一電阻器Rc及一電容器Cc。補償電 路327可確保一回饋迴路之穩定性，該回饋迴路可藉由將 一極點及/或一零點添加至迴路來產生初步輸入電壓 VCIN_F。 返回參看圖3，比較器323可比較輸出電壓分壓器321之 輸出電壓¥011丁_卩與輸入參考電壓選擇器322之輸出電壓 VC_REF0，且可產生初步輸入電壓VCIN_F。 回應於輸出電壓分壓器321之輸出電壓¥011丁_卩高於輸入 參考電壓VC_REF0，比較器323可減少初步輸入電壓 VCIN_F之位準。回應於輸出電壓分壓器321之輸出電壓 VOUT—F低於輸入參考電壓VC—REF0，比較器323可提高 151662.doc -30- 201140273 初步輸入電壓VCIN—F之位準。 回應於輸出電壓分壓器321之輸出電壓v〇UT—Fi^於輸入 參考電壓VC_REF0 ,可減小初步輸入電壓v_cin_f之位 帛。因此’可減小輸人電壓VCIN之位準。此減小可反映 至輸出電請υτ中’且輸出電壓分壓器321之輸出電壓 VOUT—F亦可減小。初步輸入電位準可收斂至 輸入參考電壓VC_REF0。 回應於輸出電壓分壓器321之輸出電壓ν〇υτ⑽於輸入 參考電壓VC一REF0,可提高初步輸入電壓VCIN-F之位 準。因此，可增大輸入電壓VCIN之位準。此增大可反映 至輸出電壓VOUT中，且輸出電壓分壓器321之輸出電壓 VOUT—F亦可增大。初步輸入電壓VCIN—F之位準可收敛至 輸入參考電壓VC_REF0。 放大器324可包括作為線性調節器之比較器328及兩個電 阻器R。放大器324可使初步輸入電壓vcm—F放大兩倍（例 如，以2進行放大），且可產生輸入電塵vcm。應瞭解可 將放大器324之放大率改變為除兩倍外之放大率。 現將描述增壓電壓產生電路之總體操作。 ' 輸入電壓位準設定單元220可產生目標為（目標輸出電遷/ . 增壓率）之位準的輸入電壓VCIN。換言之，其可根據等式 15控制輸入電壓VCIN之位準。 》 [等式15] VCIN=V〇UTtar/n' 151662.doc 201140273 增壓率設定單元210可回應於輸入電壓VCIN之目標位準 (VOUTtar/n’）處於輸入電壓VCIN*可具有之位準（例如，回 應於目標位準VOUTtar/n’超出電源電壓）而增大增壓率 BT[a:0] ^即使可將增壓率BT[a:〇]減小一個步長，但若輸 入電壓VCIN之目標位準為輸入電壓ν(：ΙΝ*可具有之位準 (例如，輸入電壓VCIN之目標位準低於電源電壓），則增壓 率設定單元210仍可減小增壓率BT[a:0]。 經由輸入電壓位準設定單元22〇及增壓率設定單元2ι〇之 操作，增壓率BT[a:〇]可變得儘可能准許地低，且輸入電壓 VCIN在使得輸入電壓VCINf可超出電源電壓之位準的範 圍内增加至儘可能准許地高。 增壓率BT[a:0]變得愈高，增壓電壓產生電路就可消耗 愈多電流。根據一實施例，經由增壓率設定單元2丨〇及輸 入電壓位準设疋單元220之操作，可使增壓率BT[a:〇]儘可 能准許地減小，且增壓電壓產生電路之電流消耗可減小。 根據一實施例製造之增壓電壓產生電路可使輸入電壓最 大化，且可使增壓率最小化以便產生具有目標位準之增壓 電壓。因此，增壓電壓產生電路可藉由以最小增壓率使輸 入電壓增壓來產生具有目標位準的增壓電壓。 結果，增壓電壓產生電路可維持最小電流消耗。 上文已描述了若干實例。然而，將理解可進行各種修 改。舉例而言，在以不同次序執行所描述技術的情況下及/ 或在所描述系統、架構、器件或電路中之組件以不同方式 進行組合及/或藉由其他組件或其等效物替換或補充的情 151662.doc -32- 201140273 況下，可達成合適結果。舉例而言，在適當時，所描述硬 體器件及/或其組件可經組態以充當一或多個軟體模组以 便執行上文所描述之操作及過程，或反之亦然。過程、功 能、方法及/或軟體可記錄、儲存或固定於一或多個電腦 可讀儲存媒體上，該一或多個電腦可讀儲存媒體包括程式 指令，該等程式指令待由電腦實施以使處理器實行或執行 該等程式指令。該等媒體亦可包括（單獨或與程式指令組 合）資料檔案、資料結構及其類似者。因此，其他實施在 以下申請專利範圍之範齊内。 【圖式簡單說明】 圖1為展示增壓電壓產生電路之電壓、信號及輸出 的方塊圖。 方塊 圖2為說明根據一實施例之一增壓電壓產生電路的 圖。 圖3為說明圖2之增壓電壓產生電路的詳細方塊圖。 圖4為說明根據一實施例之一分壓器的示意圖。 圖5為說明根據一實施例之一旗標信號產生器的八立 圖6為說明根據一實施例之一輸入參考電壓選擇器的_ 意圖。 。、不 圖7為說明根據一實施例之一初始值判定器的示黃圖 圖8為說明根據一實施例之一增壓率控制器的示意圖。 圖9說明計數器之操作。 圖丨〇說明可預設之遞增/遞減計數器之操作。 I51662.doc -33- 201140273 圖11至圖14說明增壓率控制器之操作。 圖15為說明下箝位電壓選擇器之方塊圖 圖16為說明電|箝之方塊圖。 圖17為說明輸出電壓分壓器之方塊圖 圖1 8為說明補償電路之方塊圓。 貝穿圖式及[實施方式]，除非另外描述 式參考數字將理解為指代相同元件 清楚、說明及便利而誇示此等元件 【主要元件符號說明】 100 增壓電壓產生電路 200 增壓電路 210 增壓率設定單元 220 輸入電壓位準設定單 311 分壓器 312 旗標信號產生器 313 增壓率控制器 314 初始值判定器 321 輸出電壓分壓器 322 輸入參考電壓選擇器 323 比較器 324 放大器 325 下箝位電壓選擇器 326 電壓箝 327 補償電路 151662.doc 否則相同之圖 、特徵及結構。可為了 之相對大小及描繪。 •34- 201140273 328 比較器 401 類比電壓多工器（MUX) 501 比較器 502 比較器 601 類比電壓多工器（MUX) 701 比較器 801 計數器 802 計數器 803 比較器 804 比較器 805 D型正反器 806 D型正反器 807 初始值解碼器 808 可預設之遞增/遞減計數器 1501 類比多工器（MUX) 1601 上箝 1602 下箝 BT[2:0] 增壓率 BT[a:0] 增壓率 BTDN_CNT[9:0] 值 BTDN_CNT[b:0] 碼值 BTDN_EN 信號 BTDN_FG 增壓率遞減旗標信號 BT_INI[m:0] 關於增壓率之初始值的信號 151662.doc -35- 201140273The clamp voltage selector 325 at a = 50 mV can select the input voltage VCMP_DN[m:0] suitable for the boost rate BT[a:0] as the lower clamp voltage VCMP_DNO. FIG. 16 is a block diagram showing the voltage clamp 326. The voltage clamp 326 can include an upper clamp 1601 and a lower clamp 1602. The upper clamp 1601 can generate a sinking current between the ground terminals from the preliminary input voltage VCIN_F in response to the initial input voltage VCIN_FK becoming higher than the upper clamp voltage VCMP_UPO, thereby preventing the preliminary input voltage VCIN_F from becoming higher than the upper clamp. Voltage VCMP_UPO. The lower clamp 1602 can generate a drive current between the power supply voltage VDD from the preliminary input voltage VCIN_F in response to the preliminary input voltage VCIN_F becoming lower than the lower clamp voltage VCMP_DNO, thereby preventing the preliminary input voltage VCIN_F from becoming higher than the upper clamp voltage VCMP_DNO . FIG. 17 is a block diagram showing the output voltage divider 321 . The output voltage divider 321 can include a plurality of resistors coupled in series to divide the boost voltage VOUT, and an analog voltage multiplexer (MUX) 1701. In response to the current boost rate BT[a:0] of η', the level of the boost voltage v〇UT_F output from the output voltage divider 321 can be calculated according to Equation 12. [Equation 12] V0UT/(2*n,). 151662.doc -29- 201140273 This is because the amplifier 324 has a magnification of 2 in this example. This relationship can be expressed more generally according to the following Equation 13. [Equation 13] VOUT_F = (VOUT/(n'* amplification factor of amplifier) When VOUT/(2*n') is expressed as a value based on m', VOUT/(2 * η can be expressed according to Equation 14. [Equation 14] VOUT_F=VOUT/(m, + 3) The analog voltage multiplexer (MUX) 1701 is operable to select an appropriate output voltage VOUT_F based on the boost rate BT[a:0]. A block diagram of the compensation circuit 327 is illustrated. The compensation circuit 327 can include a resistor Rc and a capacitor Cc. The compensation circuit 327 can ensure the stability of a feedback loop that can be added by adding a pole and/or a zero point. Returning to the loop to generate the initial input voltage VCIN_F. Referring back to FIG. 3, the comparator 323 can compare the output voltage of the output voltage divider 321 to the output voltage VC_REF0 of the input reference voltage selector 322, and can generate a preliminary input. Voltage VCIN_F. In response to the output voltage of the output voltage divider 321 011 卩 卩 卩 higher than the input reference voltage VC_REF0, the comparator 323 can reduce the level of the preliminary input voltage VCIN_F. In response to the output voltage of the output voltage divider 321 VOUT_F is lower than the input reference voltage VC_REF0, comparator 323 Raise 151662.doc -30- 201140273 Preliminary input voltage VCIN-F level. In response to the output voltage divider 321 output voltage v〇UT-Fi^ input reference voltage VC_REF0, can reduce the initial input voltage v_cin_f Therefore, 'the level of the input voltage VCIN can be reduced. This decrease can be reflected in the output power υτ' and the output voltage VOUT-F of the output voltage divider 321 can also be reduced. The initial input potential can be Converging to the input reference voltage VC_REF0. In response to the output voltage ν 〇υ τ (10) of the output voltage divider 321 at the input reference voltage VC REF0, the level of the preliminary input voltage VCIN-F can be increased. Therefore, the input voltage VCIN can be increased. The increase can be reflected in the output voltage VOUT, and the output voltage VOUT-F of the output voltage divider 321 can also be increased. The level of the preliminary input voltage VCIN_F can converge to the input reference voltage VC_REF0. 324 can include a comparator 328 as a linear regulator and two resistors R. The amplifier 324 can amplify the initial input voltage vcm-F by a factor of two (e.g., amplify by 2) and can generate an input dust vcm. It should be understood that the amplification factor of the amplifier 324 can be changed to a magnification other than twice. The overall operation of the boost voltage generating circuit will now be described. The input voltage level setting unit 220 can generate a target (target output galvanic /. The input voltage VCIN of the level of the boost rate). In other words, it can control the level of the input voltage VCIN according to Equation 15. [Equation 15] VCIN=V〇UTtar/n' 151662.doc 201140273 The boost rate setting unit 210 can respond to the target level of the input voltage VCIN (VOUTtar/n') at a level that the input voltage VCIN* can have. (For example, in response to the target level VOUTtar/n' exceeding the power supply voltage), increase the boost rate BT[a:0] ^ Even if the boost rate BT[a:〇] can be reduced by one step, if input The target level of the voltage VCIN is the input voltage ν (: ΙΝ * can have the level (for example, the target level of the input voltage VCIN is lower than the power supply voltage), then the boost rate setting unit 210 can still reduce the boost rate BT [a:0] By the operation of the input voltage level setting unit 22 and the boost rate setting unit 2, the boost rate BT[a:〇] can become as low as possible, and the input voltage VCIN is The input voltage VCINf can be increased beyond the range of the power supply voltage to the highest possible allowable height. The higher the boost rate BT[a:0] becomes, the more current the boosted voltage generating circuit can consume. For example, the supercharging rate BT[a: can be obtained by the operation of the supercharging rate setting unit 2 and the input voltage level setting unit 220. The reduction as much as possible is permitted, and the current consumption of the boost voltage generating circuit can be reduced. The boost voltage generating circuit fabricated according to an embodiment can maximize the input voltage and can minimize the boost rate to produce The boost voltage of the target level. Therefore, the boost voltage generating circuit can generate the boost voltage having the target level by boosting the input voltage with a minimum boost rate. As a result, the boost voltage generating circuit can maintain the minimum current. A number of examples have been described above. However, it will be understood that various modifications can be made, for example, in the case of performing the described techniques in a different order and/or in the described system, architecture, device or circuit. Suitable results can be achieved by combining in different ways and/or by replacing or supplementing other components or their equivalents. 151662.doc -32-201140273. For example, where appropriate, the hardware devices are described. And/or components thereof can be configured to function as one or more software modules to perform the operations and processes described above, or vice versa. Process, function, method, and/or Or the software can be recorded, stored or fixed on one or more computer readable storage media, the one or more computer readable storage media comprising program instructions to be executed by a computer for causing the processor to perform or execute the Such program instructions. These media may also include (individually or in combination with program instructions) data files, data structures and the like. Therefore, other implementations are within the scope of the following patent application. [Simplified illustration] Figure 1 A block diagram showing the voltage, signal, and output of the boost voltage generating circuit. FIG. 2 is a diagram illustrating a boost voltage generating circuit in accordance with an embodiment. FIG. 3 is a detailed block diagram illustrating the boost voltage generating circuit of FIG. 2. FIG. 4 is a schematic diagram illustrating a voltage divider in accordance with an embodiment. Figure 5 is a diagram illustrating a flag signal generator according to an embodiment. Figure 6 is a diagram illustrating the input of a reference voltage selector according to an embodiment. . No, FIG. 7 is a yellow diagram illustrating an initial value determiner according to an embodiment. FIG. 8 is a schematic diagram illustrating a boost rate controller according to an embodiment. Figure 9 illustrates the operation of the counter. Figure 丨〇 illustrates the operation of the preset up/down counter. I51662.doc -33- 201140273 Figures 11 through 14 illustrate the operation of the boost rate controller. Figure 15 is a block diagram showing the lower clamp voltage selector. Figure 16 is a block diagram showing the electric clamp. Figure 17 is a block diagram showing the output voltage divider. Figure 18 is a block diagram illustrating the compensation circuit. The drawings and the [embodiments] are to be understood as referring to the same elements for clarity, description, and convenience, and such elements are exaggerated. [Main element symbol description] 100 boost voltage generating circuit 200 boost circuit 210 Pressurization rate setting unit 220 Input voltage level setting sheet 311 Voltage divider 312 Flag signal generator 313 Boost rate controller 314 Initial value determiner 321 Output voltage divider 322 Input reference voltage selector 323 Comparator 324 Amplifier 325 lower clamp voltage selector 326 voltage clamp 327 compensation circuit 151662.doc otherwise the same figure, features and structure. It can be used for relative size and depiction. • 34- 201140273 328 Comparator 401 Analog-to-Voltage Multiplexer (MUX) 501 Comparator 502 Comparator 601 Analog-to-Voltage Multiplexer (MUX) 701 Comparator 801 Counter 802 Counter 803 Comparator 804 Comparator 805 D-type Rectifier 806 D-type flip-flop 807 initial value decoder 808 preset increment/decrement counter 1501 analog multiplexer (MUX) 1601 upper clamp 1602 lower clamp BT[2:0] boost rate BT[a:0] increase Voltage rate BTDN_CNT[9:0] Value BTDN_CNT[b:0] Code value BTDN_EN Signal BTDN_FG Boost rate decrement flag signal BT_INI[m:0] Signal for initial value of boost rate 151662.doc -35- 201140273
BTDN_PEN BTDN_R[b:0] BTDN_REF BTDN_REF[m:0] BTINI_REF BTUP_CNT[9:0] BTUP_CNT[b:0] BTUP_EN BTUP_FG BTUP_PEN BTUP_R[b:0] BTUP_REF Cc CK D_BT_INI[2:0] D_BT_INI[a:0] DCC_ST DC DN EN OUT[a:0] OUT[b:0] P[a:0] P_ST PEN 增壓率遞減啟用信號 增壓率遞減參考值 增壓率遞減參考電壓 增壓率遞減參考電壓 初始參考電壓 值 碼值 信號 增壓率遞增旗標信號 增壓遞增啟用信號 增壓率遞增參考值 增壓率遞增參考電壓 電容器 時脈/端子 碼 碼 轉換開始信號 端子 啟用端子 端子 輸出端子 端子 初始化信號 啟用端子 151662.doc -36- 201140273 R 電阻器 Rc 電阻器 RST 重設端子 UP 端子 VC_REF0 輸入參考電壓/輸出電壓 VCIN 輸入電壓 VCIN_F 初步輸入電壓 VCMP_DN[m:0] 輸入電壓 VCMP_DN0 下箝位電壓 VCMP_UP0 上箝位電壓 VDD 電源電壓 VOUT 增壓電壓 VOUT_F 輸出電壓 VR_REF[m:0] 電壓 151662.doc ·37·BTDN_PEN BTDN_R[b:0] BTDN_REF BTDN_REF[m:0] BTINI_REF BTUP_CNT[9:0] BTUP_CNT[b:0] BTUP_EN BTUP_FG BTUP_PEN BTUP_R[b:0] BTUP_REF Cc CK D_BT_INI[2:0] D_BT_INI[a:0 ] DCC_ST DC DN EN OUT[a:0] OUT[b:0] P[a:0] P_ST PEN Pressurization rate decrement enable signal boost rate decrement reference value boost rate decrement reference voltage boost rate decrement reference voltage initial Reference voltage value code value signal boost rate increment flag signal boost boost enable signal boost rate increment reference value boost rate increment reference voltage capacitor clock / terminal code code start signal terminal enable terminal terminal output terminal terminal initialization signal enable Terminal 151662.doc -36- 201140273 R Resistor Rc Resistor RST Reset Terminal UP Terminal VC_REF0 Input Reference Voltage / Output Voltage VCIN Input Voltage VCIN_F Preliminary Input Voltage VCMP_DN[m:0] Input Voltage VCMP_DN0 Lower Clamp Voltage VCMP_UP0 Upper Pliers Bit voltage VDD Supply voltage VOUT Boost voltage VOUT_F Output voltage VR_REF[m:0] Voltage 151662.doc ·37·