TW200810331A - Circuit of charge pump - Google Patents

Abstract

A circuit of charge pump includes a plurality of diode equivalent networks, at least a boost capacitance network, and at least a reverse current cut-off circuit. The diode equivalent networks are electrically connected in series. A node is formed between two diode equivalent networks. Each node corresponds to a voltage-boosting step, in which the low voltage side of the diode equivalent network with a lowest voltage-boosting step is an input end of the circuit of charge pump. The input end receives an input voltage signal. One end of each of the boost capacitance network is separately connected electrically to one of the nodes. Another end of each of the boost capacitance network is separately connected electrically to a clock signal. Each of the reverse current cut-off circuits is separately connected electrically to the diode equivalent networks, in which the reverse current cut-off circuits include at least two conductive paths, which form a closed loop according to the switching of clock signal in each voltage-boosting step.

Description

200810331 IX. Description of the invention: - [Technical field to which the invention pertains], Japanese-made charge-charge circuit, especially a charge boost circuit that improves the efficiency and reliability of the circuit by a reverse current cut-off circuit. [Prior Art] A charge pump is a circuit that realizes buck-boost by a charge accumulation effect on a capacitor. With the development of various portable and flash memory devices and applications, the system requires a high voltage 2 power supply voltage, and the power supply policy is derived from the power supply. A type of charge boost circuit is used as a solution. A boost type charge boost circuit capable of stabilizing the voltage drop or generating an output higher than the power supply voltage, see FIG. 1 , is a schematic diagram of a conventional dual phase charge boost circuit 100, the charge boost circuit 100 includes a set of diode-connected MOS transistors and a plurality of capacitors, wherein the structures of the N-type MOS transistors have a threshold voltage Vt, and the capacitors are respectively charged Connected to the two n-type MOS semiconductors. The working principle is to use a pair of inverted clock signals p 1 and p 2 to alternately charge the capacitors to achieve supercharging. According to the current path, the circuit cycle (cl〇ck cycle) can be divided. In order to set the period (setup peri〇d) and the pumping period (in the setting phase), the clock signal %1 is at a low level (low), and the dual-time charge boost circuit is turned on. In a charging path 110, the N-type MOS transistor on the first charging path 110 is turned on until the voltage value on the first node 120 reaches vin-vt, and the voltage of the k-cell C1 is also charged to Vin_vt. Then, in the boosting stage 5 200810331 & 纣, the pulse signal $ i is a high level (), in this embodiment, = the voltage value of the clock signal arrives in the boosting phase, which will cause the voltage of the power supply c 1 Therefore, ν φ is raised, so that the voltage value on the first node 1 reaches vin+(v(^vt), and when the voltage value of the node 120 is greater than the threshold voltage value Vt of the n-type MOS transistor, the same is also turned on. The second charging path H0 causes the voltage value on a second node 13 to reach = ηη + (J p _Vt) - Vt. Similarly, the voltage value at the first node 130 at the next set period is obtained. Reach Vin + 2 (v %. In summary, the output voltage value of a dual-time charge boost circuit with n nodes can be expressed as:

Vout = Vin+N*(V(p .Vt)-Vt ........ ( 1-1 ). 曰 From the relationship of 1-1, it can be found that it is limited by the MOS transistor structure. In the presence of the threshold voltage vt (thresh〇][dv〇hage) effect, the boosting efficiency of the charge boosting circuit i 00 is thus reduced, resulting in inefficient system efficiency, especially in the case of low supply voltage conditions, the critical voltage effect is The impact of system performance will be very obvious, making the charge boost circuit 100 not suitable for low voltage operation, and the poor efficiency of boosting in general circuit applications necessitates more power consumption to compensate. A large number of shortcomings. 々 For this reason, many improvements to the charge booster circuit have been proposed. See Figure 2, an improved charge booster circuit disclosed in U.S. Patent No. 6,670,884 B2, The structure of the improved charge boosting circuit 200 is substantially the same as that of the charge boosting circuit 1 , except that the diode in the improved charge boosting circuit 200 is connected to the MOS semiconductor crystal system to the vacant metal oxide semiconductor. The crystal (Depleti〇n-type MQS Transistor) was implemented. The advantage is as follows: Depleti〇n-type N.channel M〇s Transist〇r is exemplified by 200810331, whose threshold voltage value is a negative value, and its characteristics make the depleted N-channel MOS semiconductor The channel of the crystal is continuously maintained in conduction state unless the voltage between the gate source stages (Vgs) is applied with a voltage lower than the threshold voltage. The improved charge boosting circuit is utilized by the characteristics of the above-described depleted gold-oxygen half-body transistor. 200 can avoid the influence of the system performance degradation caused by the threshold voltage Vt effect, so that the output voltage of the improved charge boosting circuit 2〇〇 is higher than that of the charge boosting circuit 100 of the same order. The characteristics of the above-mentioned depleted MOS transistor also cause the improved charge boosting circuit 200 to switch between the operating clocks, and when the voltage of the node a has been boosted, the depleted N-channel MOS transistors Still unable to turn off, thus generating a reverse leakage current Iq along a path 21 ,, the reverse leakage current Iq and the charge boosting circuit 1 采用 using a J-type N-channel transistor Enhancement_type N_channel Transistor) The threshold voltage vt causes the same effect of poor boost efficiency, which will cause the system performance to be low. In particular, the reverse leakage current Iq is in the improved charge boost circuit 2〇〇 Overflow is more likely to damage the system and reduce reliability. In order to prevent the reliability from declining, the system often needs to increase the protection circuit. Such measures increase the cost of the system, which is more detrimental to the application and sales of the product. Reducing the reverse leakage current Iq for J, the improved charge boosting circuit=〇 discloses the use of changing the aspect ratio (W/L) parameter of the vacant MOS transistors to reduce the reverse leakage current Iq The method, but the 0 method is only reduced, but the reverse leakage current Iq cannot be completely avoided. The excessively grown transistor aspect ratio is difficult to increase the process. ^^ This can cause electrical interference that cannot be detected during design. In summary, such a method cannot first completely reverse the reverse reverse current, and the increase in the difficulty of the process may increase the production cost. Secondly, the electrical interference that may occur also causes the reliability of the circuit to decrease. For this reason, a charge booster circuit that maintains circuit reliability while completely turning off the reverse reverse current is very desirable. SUMMARY OF THE INVENTION An object of the present invention is to provide a boost charge boost circuit that utilizes a depletion transistor (Depletion_type M〇s core (10) deuteration. Composition equivalent series diodes' The boost charge boosting circuit has no threshold voltage loss to increase the boosting efficiency. Another object of the present invention is to provide a boost charge boosting circuit: the boosting charge boosting circuit includes at least one reverse current blocking circuit, The reverse current cutoff circuit turns off the reverse leakage current to increase the boosting efficiency. Another object of the present invention is to provide a boost charge boosting circuit including at least an "inverse current cutoff circuit, the boosted charge The booster circuit does not need to use a special process, and the other purpose is to save a boost charge. Another purpose is to provide a boost charge booster circuit. The boost charge boost circuit includes at least - reverse current wear voltage, and the reverse current cutoff The circuit cuts off the reverse leakage current to reduce the electrical property and increase the system reliability. Another object of the present invention is to provide a boosted charge 擗厣 Ray Road, which The piezoelectric charge boosting circuit comprises at least a voltage stabilizing circuit, and the output voltage is determined. Fe, :: For the above purpose, the present invention provides a boosted charge boosting electrical complex diode equivalent network, wherein the pole The body-equivalent network system 8 200810331 is a series-connected electric nucleus node, each of which has a diode-equivalent network between the equivalent network of the two poles. At the input end, the wheel enters the pile and you receive an input voltage signal for one of the boost charge boosting circuits; at least one boost capacitor network, and the end points respectively rise with the nodes, and rise to 1 valley, The other end of one of the roads is electrically connected. Each of the boost capacitor network numbers has at least::::: pulse signal electrical connection, wherein the clock signal signal level is accurate and accurate. From this time, ph ^ Γ causes the δ hai input voltage signal to open the voltage level value for each boost I; and to the reverse current cut-off circuit, each one, ν' + ★ must, a separate temple 1^ Current cut-off circuit is controlled by the circuit control - the equivalent network of these diodes: And enable, wherein the reverse current cutoff circuit has at least two conduction paths. By simply demonstrating one of the modes most suitable for implementing the present invention, those skilled in the art will be able to understand this from the following description. The drawings and the description are to be regarded as illustrative and not restrictive. FIG. 3 is a diagram showing one of the embodiments of the present invention. A schematic diagram of a fourth-order charge-pump circuit 3 00, the fourth-order boost charge boost circuit 3 〇〇 includes a first reverse current cut-off circuit 3 1 0a, a second inverse The current cut-off circuit 310b, a third reverse current cut-off circuit 310c, a fourth reverse current cut-off circuit 31 0d, a first equivalent diode 320a, a second equivalent 9 200810331 diode 32〇b, a first a three-equivalent diode 32〇c, a fourth-equivalent body 32〇d, a first boosting capacitor 33 0a, a second boosting capacitor 330b, a third boosting capacitor 330c, and a fourth Boost capacitor 3 3 0d, each of these reverse current cuts 31〇 circuit comprises a pair of open ^ 'the present embodiment, the reverse current blocking circuit 3 such Shu square lines were made - the enhancement N-channel metal oxide semiconductor transistor

Transistor) and an enhanced p-channel CMOS transistor (Enhancement-type P-channd Transistor), but this is not limited to the case, in the present invention, the switch pairs can be turned on by the characteristics Any switch composition, other than an electronic switch formed by a semiconductor component, such as an electromagnetic switch, etc., should be considered as disclosed in the present invention. ^ ΤΓ ΤΓ ML ML ML 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强The source of the transistor, or the respective drain (the core is also electrically connected to the drain of the other-transistor). In addition, each of the sets of reverse current cutoff circuits 31 is electrically connected between the transistors. Connected to ^; in this embodiment, 'each of the equivalent diodes 320 ^ 1 Ν channel M0S transistor (DePletion_type 〇 S = ansistor) 舆 constitutes the cut-off circuit 3i 〇 the enhanced p-crystal 'Whether the enhanced P-channel MOS transistor is conductive: the enhanced version of the two-system two-enhanced p-channel MOS half-channel MOS transistor 2 2 2 310

When the iH milk semiconductor transistor is turned off, the depletion type N 〇 本 施 施 猎 猎 猎 组成 10 10 10 10 10 10 10 10 10 10 10 10 10

The switch pairs control the corresponding depletion type NI~Electric daily rent and the strong type of p ienaM, t into the temple effect diode of the reverse current cutoff circuit channel MOS transistor Can wait for the lack of mf (disabie). In fact, in this embodiment, the circuit between the gate terminal and the gate terminal of the one-electron M body can be implemented only by the same piece, and in addition to using the p-channel transistor, the transistor can be realized by reluctantly i-passing the transistor. The foregoing structure. In addition, in this embodiment, one of the reverse current cutoff circuits 31 is electrically connected to the ground (GND), so that the circuit is reversed from each of the two sides of the Sakizaki-Tokyo, 0i r : ' ^ 忒 寺 效 — — — — — — — — — — — 极 极 极 极 极 极 极 回路 回路 回路 回路 回路It is worth noting that the ground power can be adjusted to any suitable value to the zero voltage. The connection relationship of the fourth-order (four) charge booster 4 3 (10) is as follows: the first equivalent diode 32 〇 a and the second equivalent diode 32 rib = this is connected in series (eGnneeted in sedal), which is connected The endpoint is a first, ie, Nodel, the second equivalent diode 32〇b and the third equivalent pole 32〇c are connected in series with each other, and the connection end point is a second node 〇de2, The third equivalent diode 32〇c and the fourth equivalent diode=〇d are connected in series with each other, and the connection end point is a third node N〇de3, which is the source of the equivalent diode 320d The extreme point is the voltage output of the fourth order, the point Vout. μ, in each of the reverse current-cutting circuits, the gates of the bare-type MOS transistors constituting the pair of switches are electrically connected to each other, and the connections = , , , and 4 nodes N〇de4, a 5th node Node5, a 6th node Node6, and a 7th node N〇de7. 11 200810331 The two non-polar or two sources of the two enhanced MOS transistors constituting the reverse current cut-off circuit 310 are electrically connected to each other, and the points are respectively connected to form an eighth node Node8, one The 9th node Node9, a 10th node Node1O, and an 11th node Node11. The first boosting capacitor 33 0a is electrically connected to Node1, the second boosting capacitor 330b is electrically connected to Node2, and the third boosting capacitor 33〇c is electrically connected to Node3, and the fourth boosting capacitor 33〇d and the The fourth-order voltage output Vout is connected. In this embodiment, the boost capacitors 33 are implemented by a depleted N-channel MOS transistor whose source and drain are electrically connected to each other, but are not limited thereto. In fact, anything that is equivalent: an electronic component or combination of circuits with a suitable capacitance value can be considered as a variation of these boost capacitors. The source and the drain of the first boosting capacitor 3 are connected to a 12th node Nodel2, and so on, the source and the drain of the second boosting capacitor 33〇b are connected to the nth node N. 〇del3, the source of the third liter factory capacitor 330c: = The connection point between the poles is the same node as N〇del2. The connection point between the source and the drain of the fourth boosting electric valley 330d is the same node as N〇dei3, and Nodel2 and N〇del3 are respectively connected to a first clock signal source P1 and a second clock. The signal source p 2 , p 1 and p 2 are the inverted pulse signal sources. The high and low levels of the signal sources appear alternately. In this example, the low level voltage value is 〇, and the high level is ^. This is limited, and its low level change can be adjusted according to system needs. The gate of the boost capacitor and the first node Node1, the second node second, the point N〇de3, and the fourth-order voltage output node v〇ut, the fourth-order boost charge increase power 4 3GG work The principle description is as shown in Fig. 12 200810331, which is the invention disclosed in the following figure: the equivalent circuit of the second road 3〇0 in a first-wheel-in state, the ascending reed; Γ / - input human form" , - input voltage signal Vin input ^ What is the boost circuit shift 'this time' is G (can also be ground level or Low level) or low voltage level and 2 is Vp, then the reverse current paraplegic circuit Because of the control, the switch pairs of L in the reverse current blocking circuit are respectively turned on (by (7) 〇 n ) and turned off according to their conduction characteristics, thereby forming different conduction paths, so that different conduction paths are formed.嗲 and so on: the depleted Nit channel crystal between the 32u and 32c diodes: the loop between the source and the source is connected to form a diode connection (D1〇de-connected), the equivalent level The cavity between the body 32 and the 32-d-d-type N-channel transistor is disconnected from the source, so the depleted N-channel electron crystals of 320b and 320d At this time, it is not a diode connection, that is, the equivalent diodes are in a disabled state in the first input state. At this time, since the depleted N-channel transistor in 320a is turned on, the input terminal Vin will A charging current is generated to charge the capacitor 3 3 until the voltage of Nodel Vnodel=Vin. As shown in FIG. 5, the boosting charge boosting circuit 300 disclosed in the present invention is in a second input state. The equivalent circuit is 5. In the second input state, an input voltage signal Vin is input to the boost charge boost circuit 300, at this time %; [is v $ and p 2 is 〇 (ground or L〇w The level of the reverse current cut-off circuit is controlled by the switch, and the switch pairs in the reverse current cut-off circuit are turned on and off (turn 〇 ff) according to their turn-on characteristics, thereby forming Different conduction paths' loops between the gates of the depleted N-channel transistors and the source between the equivalent diodes 320b and 320d are connected to form a diode connection between the special-purpose primary bodies 320a and 320c. Depleted N-channel transistor 13 200810331 Back between gate and source Turned off, so the 32 n and 32 〇 c of the depleted n-channel transistors are not connected to the diode at this time, that is, the equivalent diodes are disabled in the first input state. Input the first clock signal source φ at the N〇de2, and the voltage of the first boost capacitor 33〇a is raised by a level of vp, and the voltage Vn〇dei of the nodel is also raised to Vin+Vp. The second equivalent diode 32〇b is turned on because of the diode connection, and a current 12 is generated through the loop to charge the capacitor 33〇b, and the Vnode2 is also charged to vin+v. In this case, 0Vodel is greater than Vin, and the current is supplied to the current Iq, and in the boosted charge boosting circuit 3〇〇, since the gate of the depleted N-channel transistor in the % 3 20a is 3 丨The switch is turned on to ground, and if there is reverse current generated at this time, the source of the depleted N-channel transistor will be the point of the reverse current iq, which is the point of the point Viη ', thus, the αα α ridge 320a In the middle of the space-deficient Ν channel transistor, the source voltage Vgsl=_Vin, so if t is the gate of the depleted n-channel transistor, the pole voltage is compared with The threshold voltage Vt of the depleted 35N channel transistor is still /J, that is, Vgsl < Vt, then no reverse current will be generated, and the boosting charge boosting circuit 300 achieves an increase in boosting efficiency and a reduction in cost. purpose. Please, as shown in Fig. 6, then the clock signals return to the first input state'. At this time, the second clock signal is used, and Ν_2 will be raised by a Vφ level according to the same principle as described above, so that

In〇de2 = Vin + 2VP. In the third equivalent diode network 320c, the N-channel transistors are also turned on and turned off (tum〇ff) because the switches of the 3 1 0c are respectively turned on, thereby forming different conduction paths. The open y is connected to the one body and turned on, and a charging current 13 is formed through the loop to charge the capacitor 330c to % 〇 to 3 = ^ + 2^. In addition,

Vnodel's electro-ink back to temple is not V ^ soil U is set to Vln, so that Vgs2 = -Vin, at this time the empty 14 200810331 the source voltage of the spent N-channel transistor is compared with the threshold voltage of the depleted N-channel transistor Vt is still small, that is, Vgs2 < Vt, then no reverse current will be generated'. Then the second equivalent diode 320b is turned off, so that the voltages of Node2 and Node3 are maintained. Please refer to Fig. 7, and then the clock signals return to the second input state, as described above, at which time the first clock signal p 1 = V p . Therefore, the voltage of the third boosting capacitor 330a that inputs the first clock signal p1 at N 〇de 1 2 is raised by a level of Vp, and the voltage Vnode3 of n〇de3 is also raised to Vin + 3 V φ. The depleted germanium channel transistor in the fourth equivalent diode 320d is also turned on for the actual diode connection at this time, and a charging current 14 is formed through the loop to charge the capacitor 330d, and Vout is also used by the current. 14 Charge until it is raised to Vin + 3V p. Similarly, when the clock signals return to the second clock signal again, the capacitor 330d is boosted by a voltage value of γφ such that Vout=Vin+4V ρ to achieve the circuit function of the boost output. It should be noted that the reverse current cut-off circuit can be combined with any electronic component or circuit whose on-characteristic characteristics are opposite to each other, and its function is to change the conduction path by using the change of the input clock signal to avoid the aforementioned reverse leakage current phenomenon. occur. Therefore, those skilled in the art should be able to understand that the method for realizing the reverse packet cut-off circuit by using an enhanced N-channel MOS transistor and an enhanced N-channel MOS transistor in the present embodiment One of the methods exemplified for implementing the reverse current cutoff circuit, and not the limitation of the present invention. The invention forms a reverse current cut-off circuit by electrically opposing the switch, thereby preventing the reverse current generated by the boosting from causing energy consumption and affecting the boosting efficiency, and increasing the reliability of the system. 15 200810331 Electricity (4) boost charge

Vout

Vin + N*V φ ........ ( 3-1 ) The ^ (four) charge „the circuit can be adjusted in series until the charge 掏^ r. want & day should (Pumping Voltage Gain) tends to 巳π。 In other words, until the charge boosting gain tends to saturate the number of stages of her circuit can be adjusted as needed, the rise of the "four-stage boost circuit disclosed by circuit 300 is only an embodiment" can not be regarded as the present invention The limit. Debu's tI Ming revealed that the boost charge voltage circuit can be used to boost the critical power plant and reverse leakage in the booster circuit; the adverse effect does not require any guidance on the component size. The path " is also considered to use the existing clock signal in the system to avoid reverse leakage current. Therefore, the advantages disclosed in the present invention and the advantages of high reliability are more suitable for applications in which the power supply is limited, the voltage is low, and the low voltage system is required. It is worth mentioning that the boosting charge boosting circuit 3〇" is transmitted through the voltage regulator circuit (RegulatGO electrical connection, through the voltage input voltage value of the voltage regulator, in order to reduce or change the input power supply Provided to provide a stable output voltage. Example 2 'The various circuits and components mentioned above are only schematic, except for the combination of the implementation, the circuit and the equivalent circuit of the components are 16 200810331 = both should be regarded as the same The private network of various circuits and components; 5 brothers, the equivalent network of the components described in the following::: is the limitation of the invention, by the re-exposed. In addition, 孰 should be regarded as the circuit disclosed in the present invention. Topology, the combination of the components between the two bodies, and the equivalent two-pole energy, but there are many alternative implementations in the same electricity month. For example, the implementation of empty (jfeT), this /, body m can use the junction field effect transistor (GND) rise (four) charge; ^ relative to the ground pressure input Vin negative voltage W, the output voltage is to replace a negative body. J to more negative (four) The available space of p-type p-channel electron crystal::ΐ=:Two people 9 should understand the above pattern And the description of the Bean Beans in the description /, 疋 exemplary and non-limiting. ^ ^ ί tm # ^ ^ ^ Instance-specific, Li: the exact form or the revealed system. Show two two 1 * This First, the description should be regarded as exemplary rather than limiting. The change will be obvious to those skilled in the art. The choice and description of the specific embodiment is for better explanation. (4) Principle and practical application The best mode, thus allowing the business person to understand the invention for various specific embodiments, and with:: various modifications to the specific use or covered practice: Included in the scope of the patent application and its equivalent month 2 otherwise all claims contain their most extensive Pm Γ can be changed by the skilled person, without departing from the scope of the following patent application In addition, there are no components in this disclosure and it is intended to be used by the public, regardless of whether the component or component is explicitly mentioned in the scope of the following patent. In addition, the disclosure of this document Excerpt = to comply with the requirements of the summary rules, The searcher quickly determines the subject of the technology disclosure of any patents issued from this disclosure. It should be 2 to the scope or meaning of the patent application that is not used to explain or limit the scope of the patent application. A schematic diagram of a dual phase charge increase 1 (10) is shown. Fig. 2 is an improved charge boost circuit 200. Fig. 3 is a boost circuit 30 disclosed in one embodiment of the present invention. FIG. 5 is a schematic diagram of an equivalent circuit 4 升压 of a boost charge booster circuit 300 according to one embodiment of the present invention in a first input state. FIG. A schematic diagram of an equivalent circuit 500 of a boost charge boost circuit 300 in a second input state disclosed in one of the embodiments. FIG. 6 is a schematic diagram showing an equivalent circuit when the clock signal of the boost charge boost circuit 300 is restored to the first input state according to one embodiment of the present invention. FIG. 7 is a schematic diagram showing an equivalent circuit when the clock signal of the boost charge boost circuit 300 is restored to the second input state according to one embodiment of the present invention. [Major component symbol description] 18 200810331 p 1 clock signal p 2 clock signal 100 dual time charge boost circuit 11 0 charging path 120 first node 1 3 0 second node 140 second charging path C1 capacitor C2 capacitor C3 Capacitor C4 Capacitor Cout Capacitor 200 Improved Charge Boost Circuit 2 1 0 Path Iq Reverse Leakage Current Vt Threshold Voltage 3 00 Fourth-Order Boost Charge Boost Circuit 310a First Reverse Current Shutdown Circuit 310b Second Reverse Current Shutdown Circuit 310c Three reverse current cutoff circuit 3 10d fourth reverse current cutoff circuit 320a first equivalent diode 320b second equivalent diode 320c third equivalent diode 320d fourth equivalent diode 330a first boost Capacitor 330b second boosting capacitor 19 200810331 330c third boosting capacitor 330d fourth boosting capacitor

Vin input voltage signal

Vout output voltage signal φ 1 first clock signal source or a clock signal ρ 2 second clock signal source or a clock signal 400 fourth-order boost charge boost circuit in the first input state of the equivalent circuit 500 fourth order Equivalent circuit 20 for boosting charge boost circuit in second input state

Claims (1)

200810331 X. Patent application scope: 1. A boosting charge boosting circuit, including ················································· Ii't connect 'Every two of these diode equivalent networks have .. dip--the temple node corresponds to _ liter level, where: the low-voltage side of the diode equivalent network is the (four) = In: 2, the input receives a round of incoming signal; ... the road - the 5 5 boost capacitor network 'each of the boost capacitor networks - the end point: not electrically connected to one of the nodes, Each:: There are at least the alternate barbarism of the signal of the material of the towel, and the arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily arbitrarily The cut-off circuit, each of the reverse current cut-off circuits is electrically connected to an equivalent network of the 4 temples, each of which corresponds to one of the equivalent networks of the diodes (second power loss) "月" (disable) wherein the reverse current cutoff circuits have at least two conduction paths. 2. The boost charge boost circuit as recited in claim ,, wherein the The L-channel is alternately turned on according to the switching of the clock signal in the parent-boost step to avoid reverse reverse current of the boosting charge boosting circuit. 3. The boosting charge boosting circuit as claimed in claim i, The clock signal of each of the two adjacent nodes is opposite in phase. 4. The boost charge boost circuit of claim 1, wherein the reverse current cutoff circuit comprises two electronic switch networks, and the electronic switches The continuity characteristic of the network is opposite, so that one of the electronic switch networks is respectively turned on when the clock signal is switched. 5. The boost charge boost circuit as described in the request item, wherein each of the 21 200810331 The special diode equivalent network is composed of a depleted transistor and one of the two electronic switching networks in the reverse current stopping circuit, and the electronic switching network in the diode network When the road is conducting, the corresponding vacant cell system is a diode connection. 6 The boost charge boost circuit of claim 2, wherein each 兮=diode equivalent network is depleted Type of transistor and the two electrons in the reverse circuit One of the switch networks is composed of a diode connection when the electronic switch network in the diode network is turned on. 7. The request is as described in claim 1. The boosting charge boosting circuit, wherein the inverse=cutting circuit comprises two electronic switching networks, and the electronic switching network==characteristics are respectively turned on when the (four) clock signals are switched respectively. 8. The boost charge boost circuit of claim 2, wherein the inverse 2 cutoff circuit comprises two electronic switch networks, the electronic switches being networked relative to the clock signal One of the electronic switch networks is turned on when switching. 9 · The boost charge boost circuit as described in Item 4, 1: The cut-off circuit includes two electronic switch networks, the same; The directionality is opposite, so that one of the electronic switch networks is turned on when the clock signal is switched. The boost charge boosting circuit of item 1, wherein the inverse wide cutoff circuit comprises a boosted germanium channel MOS transistor to be an reinforced germanium channel MOS transistor, #corresponding to a boost step input When the clock signal is at a low voltage level, the enhanced p-channel is turned on and the enhanced (four) MOS transistor is turned off, and the clock signal is input when the corresponding boost step is input. The bunker is on time 'this increase _ Ρ channel MOS transistor cut-off and the second 22 200810331 enhanced N-channel MOS transistor is turned on. The boosting charge boosting circuit described in claim 2, wherein the current wearing circuit comprises a strong, Y-salt and -oxy semiconductor transistor with a self-contained through-metal oxide semiconductor transistor When the corresponding boosting step VIII: t 4 clock signal is a low voltage level, the enhanced Ρ channel:: the T-shaped transistor is turned on and the enhanced N-channel MOS is electrically connected, when the corresponding boost The clock signal of the step input is high. The enhanced p-channel MOS transistor is turned off and the bare i channel MOS transistor is turned on. 1 2. According to the boosting charge boosting circuit described in Item 4, the bean circuit comprises an enhanced Nii channel MOS semiconductor: 曰: body is a 9-type P-channel MOS transistor, when corresponding When the clock signal of the boosting step two f ^ is a low voltage level, the enhanced P-channel to the oxygen semiconductor transistor is turned on and the enhanced N-channel gold is two SI ΐ, when the corresponding boosting step is input The pulse signal is high, :: the enhanced germanium channel MOS transistor is turned off and the seven strong germanium channel MOS transistors are turned on. The boost charge boosting circuit of claim 8, wherein the source of the enhanced L-to-oxygen semiconductor electric solar cell receives the input voltage signal, 'the enhanced germanium channel MOS semiconductor The transistor and the gate terminal of the enhanced MOS transistor respectively receive the clock signal input by the corresponding boost step. The boost charge booster circuit of claim 9, wherein the source terminal of the enhanced drain channel MOS transistor receives the input voltage signal, the enhanced germanium channel MOS transistor and The closed terminals of the enhanced germanium channel MOS transistors respectively receive the clock signals input by the corresponding boost steps. The boost charge boost circuit of claim 10, wherein the increase is 2008-10-331 = voltage N-channel MOS semiconductor: the body and the clock signal input by the enhanced step. ° The knife does not receive the corresponding boost 16. A boost charge boost circuit, comprising: a complex diode equivalent network, wherein the two poles are connected remotely, - the bean special, The circuit is a series of points, each of which corresponds to a boosting step: ^ has - the input end; the domain side of the tower is (four) one of the charge-charge boosting circuits, the input-regulator circuit' contains the input terminal and the The input electrical output end of the boost charge boosting circuit is electrically connected to an input power, and the wheel receiving end receives two predetermined electric dust levels, and the output terminal outputs the voltage to the voltage circuit. The input terminal; / boosting power to increase at least one boost capacitor network, each of which is electrically connected to - the nodes, each of which - the end point of a"; eight w also Shikou κ, etc. Another network:::, a clock signal electrical connection 'where the clock signal has a voltage level to a 以及 and a low voltage position by 夕 祛 稽 稽 5 5 5 亥 亥 亥 亥 亥 亥 亥曰, cross-linking, so that the input voltage signal rises to the voltage level value at each boosting step; and the complex I self-opening; The circuit, each of the reverse current-cutting circuits are electrically connected to each other, and each of the controls: corresponding to one of the diode-equivalent networks. The current cutoff circuit has at least two conduction paths. ', ^, as described in claim 16, the boost charge boost circuit, wherein the path # is based on each boost): the switching of the clock signals is alternately turned on to avoid the boost charge boost circuit Reverse reverse current. The boost charge boost circuit of claim 16, wherein the clock signal is opposite in phase between every two adjacent nodes. 1 9. The boost charge boost circuit of claim 18, wherein the reverse current cutoff circuit comprises two electronic switch networks, the conductive characteristics of the electronic switch networks being opposite to the clock signal One of the electronic switch networks is turned on when switching. 2. The boost charge boosting circuit of claim 16, wherein each of the f-equivalent equivalent networks is a depleted transistor and the two electronic switching networks of the reverse current cutoff circuits One of the paths is formed. When the electronic switch network in the diode equivalent network is turned on, the depleted transistor is connected to one of the corresponding reverse current cutoff circuits to form a diode connection. ▲] The boost charge boosting circuit of claim 17, wherein each equal-equivalent equivalent network is composed of a depleted transistor and the two electronic switching networks One of the roads is composed of one of the two poles 16 and one of the reverse current cutoff circuits corresponding to the two-pole item 16 when the electronic switch network of the two poles, the second, the second, the middle, the middle, and the second circuit are turned on. The boosting charge boosting circuit, wherein the circuit comprises: two electronic switching networks, and the electronic switching network is opposite to each other, so that the temple is turned on when the clock signal is switched One of the electronic switch networks. The step-up charge boosting circuit described in the above paragraph, wherein the circuit of the circuit comprises two electronic switch networks, and the electronic switch network is electrically opposite, so that when the clock signal is switched Open one of the ones of the electric switch network respectively. κ inverse: the boosted charge boosting circuit, wherein the L circuit comprises two electronic switching networks, and the electrical switching network 25 200810331 has a conductive characteristic opposite to the electronic switching network of the aunt and the like. One; ^ 4 pulse number switching respectively to turn on the 25. If the request item 16, the tenth, the reverse current cutoff circuit package (four) ink charge increase circuit, wherein the same - enhanced p 3 two enhanced N channel The MOS semiconductor transistor MOS transistor 监 监 监 监 监 监 监 监 监 监 监 訏 訏 訏 訏 訏 訏 訏 訏 訏 訏 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强 增强To be high, the enhanced N, 甬22/P pass MOS transistor is turned off and the 26:i/command MOS transistor is turned on. The step-up charge boosting circuit described in FIG. 1/17, wherein the enhanced Nii channel MOS transistor 2:=: channel MOS transistor, when corresponding boost, input When the pulse signal of the day is a low voltage level, the enhanced p-conductor transistor is turned on and the enhanced-type gold-oxide semiconductor body is turned off, when the clock signal input by the corresponding boost step is a high voltage level. The reinforced P-channel MOS transistor is turned off and the reinforced N-channel MOS transistor is turned on. The boost charge boost circuit of claim 19, wherein the reverse current cutoff circuit comprises an enhancement type N-channel MOS transistor and an enhancement type P-channel MOS transistor, corresponding to When the clock signal input by the boosting step is a low voltage level, the enhanced P-channel MOS transistor is turned on and the enhanced N-channel MOS transistor is turned off, and the corresponding boost step is input. When the clock signal is at a high voltage level, the enhanced 蜇p-channel MOS transistor is turned off and the enhanced N-channel MOS transistor is turned on. The boost charge boosting circuit of claim 2, wherein the source terminal of the enhanced P-channel MOS transistor receives the input voltage 26 200810331 signal 'the enhanced p-channel MOS half N The channel MOS: body % steroid and the input terminal of the enhanced step respectively receive a corresponding boost 29. The boost charge as described in claim 24, the strong P it gold oxide Semiconductor power: two-degree Xuanzeng signal, the enhanced original pole & receiving money into the voltage M, s people & pass i虱 + conductor crystal and the bare, the five gas semiconductor transistor gate g & f + the input of the clock signal. And the sigma receives the corresponding boost voltage = the source terminal of the liter charge oxygen semiconductor transistor described in claim 25, and receives the input: the ρ channel MOS transistor and the reinforced oxygen semiconductor transistor The inter-terminal receives the corresponding clock signal input by the corresponding boost I5 white. The boost charge boosting circuit of item 26, wherein each of the packets: 1 comprises a depleted transistor, and the source and the drain of the depleted transistor are electrically connected. The boost charge boosting circuit of claim 29, wherein each f-boost capacitor network is routed to a depletion transistor, and the source and the drain of the depletion transistor are electrically connected. . 33·^二求项} The boosted charge boosting circuit described in 6, wherein each of the boosting, the network routing is formed by a junction field effect transistor (JFET), and the junction field effect transistor The source and the drain are electrically connected. 34. The boost charge boost circuit of claim 29, wherein each boost capacitor network is routed to a junction field effect transistor (JFET), the source of the junction field effect transistor and The bungee is electrically connected. 35. The boost charge boost circuit of claim 16, wherein each of the diode equivalent networks is comprised of a junction field effect transistor (JFET), each of the junction fields The effect transistor (JFET) is connected to one of the corresponding reverse current 27 200810331 cut-off circuits to form a diode. $. The boost charge boosting circuit of claim 29, wherein each of the one poles = equivalent network is composed of a junction field effect transistor (), and the mating field A utility transistor (JFET) is connected to one of the corresponding reverse current cutoff circuits to form a diode. 37·- a boosting unit for a charge boosting circuit, comprising: an equivalent diode network, receiving an input voltage; - a capacitor network, the enchant equivalent binary network money connection, by - the clock money output is higher than a voltage of the input voltage; and a switch pair electrically connected to the equivalent diode network to control whether the equivalent diode network forms a diode connection (enabl) The voltage boosting unit of claim 37, wherein the switch pair controls conduction of the input voltage by the clock signal, the switch pair having at least two conduction paths, the switch pair The clock signal has at least two signal conditions. The boosting unit of claim 38, wherein the conduction paths are alternately turned on according to the change of the clock signal. For one of the voltages of the grounding voltage 40, the boosting unit as described in claim 38, the change blocks the generation of the reverse current. 41. The boosting unit, as described in claim 37, and a ground. Electrical connection 42. As requested in item 4 1 Boosting of the cell, the value is not limited to square 43. The request entry of the said booster unit 38, wherein the channel clock as a high voltage state, and wear / low voltage state. 28 [deg.]