CN102183985B - Circuit for generating boosted voltage and operation method of the same - Google Patents

Abstract

A boosted voltage generation circuit may include: a boosting circuit configured to boost an input voltage based on a boosting rate and output a boosted voltage, a boosting rate setting unit configured to receive a feedback on a level of the input voltage and set a boosting rate, and an input voltage level setting unit configured to set the level of the input voltage in response to a target level of the boosted voltage and the boosting rate.

Description

For generation of circuit and the method for operating thereof of built-up voltage

The cross reference of related application

This application claims the rights and interests of the 10-2009-0126071 korean patent application of application on Dec 17th, 2009 and the 10-2010-0035631 korean patent application of application on April 19th, 2010, the overall disclosure of above-mentioned each patent application case is incorporated herein by reference for all objects.

Technical field

The disclosure relates to a kind of circuit for generation of the built-up voltage higher than input voltage and a kind of method producing circuit for operating described built-up voltage.

Background technology

Different semiconductor devices utilizes and operates internal circuit from the voltage of outside supply.Voltage due to varying level is used in the Inner Constitution assembly of semiconductor devices, be therefore difficult to from device exterior supply treat semiconductor device inside use all voltages.Therefore, semiconductor devices is equipped with internal voltage generating circuit, to produce the voltage of varying level at device inside.

Particularly, when the level of the supply voltage from battery supplied be low and until level higher than input supply voltage of the level of the driving voltage used at device inside time, use the device of battery supply should be able to produce the voltage of level higher than the level of the input supply voltage from outside input.Generation level is divided into switch mode power supply supply (Swtiched Mode Power Supply, the SMPS) type using inductor and the charge pump type making electricity container higher than the voltage DC-DC of the level of input voltage.When mobile device, because current drain is also little, therefore mobile device has charge pump type usually.

Be different from linear power supply supply, the transmission transistor npn npn (pass transistor) of SMPS between all-pass state and complete disconnected state extremely fast (usually between 50kHz and 1MHz) switch, this makes wasted energy minimization.Voltage-regulation is provided by the ratio changing turn-on time and trip time.By contrast, linear power supply supply must dissipate overvoltage with regulation output.Efficiency is higher is the major advantage of SMPS.When needs greater efficiency, reduced size and/or comparatively light weight time, use switch regulator replace linear regulator.

Fig. 1 illustrates that built-up voltage produces the block diagram of the voltage of circuit, signal and output voltage.

Input voltage VCIN and supercharging rate BT [a:0] is inputed to built-up voltage to produce in circuit 100.Built-up voltage produces circuit 100 and makes input voltage VCIN supercharging based on the supercharging rate represented by supercharging rate BT [a:0], and produces built-up voltage VOUT.For example, when supercharging rate BT [a:0] is 2 (this means as twice or double), built-up voltage produces circuit 100 and makes input voltage VCIN supercharging twice (that is, making voltage doubles), and produces built-up voltage VOUT.

Although the desired value of built-up voltage VOUT is identical, produces in circuit 100 at built-up voltage and can there is different input voltage VCIN and supercharging rate BT [a:0].For example, when the desired value of built-up voltage VOUT is 3V, a (namely the built-up voltage VOUT of () 3V by making the input voltage VCIN supercharging twice of 1.5V, double) produce, or the built-up voltage VOUT of (b) 3V produces by making the input voltage VCIN supercharging three times (that is, triplication) of 1V.But although produce identical built-up voltage VOUT, built-up voltage produces the amount of electric current that circuit 100 consumes based on how setting input voltage VCIN and supercharging rate BT [a:0] and can be different greatly.

But normal power supplies supply is not optimized according to the target level of built-up voltage VOUT and is inputed to built-up voltage and produce input voltage VCIN in circuit 100 and supercharging rate BT [a:0].

Summary of the invention

In in general at one, provide a kind of built-up voltage and produce circuit, this built-up voltage produces circuit and comprises: boost pressure circuit, is configured to: make input voltage supercharging based on supercharging rate, and exports a built-up voltage; Supercharging rate setup unit, is configured to: the feedback receiving the level about described input voltage, and sets described supercharging rate; And input voltage level setup unit, be configured to: the level setting described input voltage in response to the following: the target level of described built-up voltage and described supercharging rate.

Produce in circuit at described built-up voltage, described input voltage level setup unit can be further configured to: the target level setting described input voltage according to following value:

(target level/described supercharging rate of described built-up voltage).

Produce in circuit at described built-up voltage, described supercharging rate setup unit can be further configured to: increase described supercharging rate outside the level range exceeding described input voltage in response to the target level of described input voltage.

Produce in circuit at described built-up voltage, described supercharging rate setup unit can be further configured to: reduce described supercharging rate in the described level range falling into described input voltage in response to the target level of the described input voltage when described supercharging rate reduces.

Produce in circuit at described built-up voltage, described input voltage level setup unit can comprise: output voltage voltage divider, is configured to: by described built-up voltage divided by the ratio determined based on described supercharging rate, and exports the voltage through dividing potential drop; Input reference voltage selector switch, is configured to select input reference voltage in the multiple voltages produced at the target level based on described built-up voltage based on described supercharging rate; Comparer, is configured to: the output voltage of more described output voltage voltage divider and the output voltage of described input reference voltage selector switch, and produces elementary input voltage; And amplifier, be configured to: amplify described elementary input voltage, and produce described input voltage.

Produce in circuit at described built-up voltage, described amplifier comprises: comparer, and this comparer is configured to linear regulator; And multiple resistor.

Produce in circuit at described built-up voltage, described output voltage voltage divider can be further configured to: carry out dividing potential drop by following ratio to described built-up voltage:

1/ (magnification of amplifier described in described supercharging rate *).

Produce in circuit at described built-up voltage, described input reference voltage selector switch can be further configured to: select the input reference voltage as described target level according to following formula:

Described built-up voltage/(magnification of amplifier described in described supercharging rate *).

Produce in circuit at described built-up voltage, described input voltage level setup unit comprises voltage clamp further, and this voltage clamp is configured to prevent described elementary input voltage from excessively increasing or reducing.

Produce in circuit at described built-up voltage, described voltage clamp can comprise analog multiplexer, clamping voltage under this analog multiplexer is configured to select in the voltage of input in response to described supercharging rate.

Produce in circuit at described built-up voltage, described input voltage level setup unit can comprise compensating circuit further, and this compensating circuit is configured to the level equalization making described elementary input voltage.

Produce in circuit at described built-up voltage, described compensating circuit comprises resistor and capacitor.

Produce in circuit at described built-up voltage, described supercharging rate setup unit can comprise: voltage divider, is configured to produce supercharging rate rising reference voltage and supercharging rate decline reference voltage; Marking signal generator, be configured to: activate supercharging rate rising flag signal in response to described elementary input voltage higher than described supercharging rate rising reference voltage, and activate supercharging rate decline marking signal in response to described elementary input voltage lower than described supercharging rate decline reference voltage; And supercharging rate controller, be configured in response to described supercharging rate rising flag signal and/or described supercharging rate decline marking signal and set described supercharging rate.

Produce in circuit at described built-up voltage, described supercharging rate setup unit can comprise initial value determiner further, and this initial value determiner is configured to the information providing the initial value about described supercharging rate to described supercharging rate controller.

Produce in circuit at described built-up voltage, described initial value determiner can comprise multiple comparer, and described multiple comparer is configured to more each input reference voltage value and initial reference voltage.

Produce in circuit at described built-up voltage, described supercharging rate controller can be further configured to: be activated to last in response to described supercharging rate rising flag signal and be longer than the reference time and increase described supercharging rate, and is activated to last in response to described supercharging rate decline marking signal and is longer than the reference time and reduces described supercharging rate.

Produce in circuit at described built-up voltage, described supercharging rate controller can comprise: multiple counter, multiple comparer, multiple trigger, initial value code translator and predeterminable rise/fall counter.

Produce in circuit at described built-up voltage, described predeterminable rise/fall counter can be configured to: the initial value by the initial pressurization rate signal sets inputed in described predeterminable rise/fall counter being described supercharging rate; In response to being the high described supercharging rate rising flag signal of logic, the first counter in described multiple counter can be configured to count clock thus increase rising count value; And converging to described supercharging rate rising reference voltage in response to the rising count value of described increase, described predeterminable rise/fall counter can be further configured to: the increase starting described supercharging rate.

Produce in circuit at described built-up voltage, described predeterminable rise/fall counter can be configured to: the initial value by the initial pressurization rate signal sets inputed in described predeterminable rise/fall counter being described supercharging rate; In response to being the high described supercharging rate decline marking signal of logic, the second counter in described multiple counter can be configured to count clock thus increase decline count value; And converging to described supercharging rate decline reference voltage in response to the rising count value of described increase, described predeterminable rise/fall counter can be further configured to: the reduction starting described supercharging rate.

Produce in circuit at described built-up voltage, described predeterminable rise/fall counter can be configured to: the initial value by the initial pressurization rate signal sets inputed in described predeterminable rise/fall counter being described supercharging rate; And in response to being the high described supercharging rate decline marking signal of logic, the second counter in described multiple counter can be configured to count clock, thus increase decline count value, described supercharging rate decline marking signal is converted to logic low when increasing described decline count value, described decline count value is not increased further, makes described predeterminable rise/fall counter not start the change of described supercharging rate.

Produce in circuit at described built-up voltage, the level of described supercharging rate rising reference voltage can be determined according to following formula:

Supply voltage/(magnification of described amplifier),

And the level of described supercharging rate decline reference voltage can be determined according to following formula:

Described supply voltage * (unit that described supercharging rate-supercharging rate changes)/(described in the magnification * of described amplifier supercharging rate).

In in another is general, provide a kind of method producing circuit for operating built-up voltage, described built-up voltage produces circuit by making input voltage supercharging produce built-up voltage based on supercharging rate, and described method comprises: produce the described input voltage that target is following level:

(target voltage/supercharging rate of described built-up voltage);

Increase described supercharging rate outside the level range exceeding described input voltage in response to the described target level of described input voltage; And reduce described supercharging rate in the level range falling into described input voltage in response to the described target level of the described input voltage when described supercharging rate reduces.

In the process, described input voltage can not have the level higher than supply voltage.

In the process, the reduction of described supercharging rate can perform lower than following value in response to the target level of described input voltage:

(unit that described supercharging rate-supercharging rate changes)/described supercharging rate.

In in another is general, provide a kind of method producing built-up voltage, described method comprises: make input voltage supercharging based on supercharging rate; Export built-up voltage; Receive the feedback about the level of described input voltage; Set described supercharging rate; And the level of described input voltage is set in response to the following: the target level of described built-up voltage and described supercharging rate.

Described method can comprise further: the target level setting described input voltage according to following value:

(target level/described supercharging rate of described built-up voltage).

Described method can comprise further: increase described supercharging rate outside the level range exceeding described input voltage in response to the target level of described input voltage.

Described method can comprise further: reduce described supercharging rate in the level range falling into described input voltage in response to the described target level of the described input voltage when described supercharging rate reduces.

Described method can comprise further: by described built-up voltage divided by the ratio determined based on described supercharging rate; Export the voltage through dividing potential drop; Input reference voltage is selected in the multiple voltages produced at the described target level based on described built-up voltage based on described supercharging rate; Relatively output voltage and input reference voltage; Produce elementary input voltage; Amplify described elementary input voltage; And produce described input voltage.

Described method can comprise further: carry out dividing potential drop by following ratio to described built-up voltage:

1/ (described supercharging rate * magnification).

Described method can comprise further: select the input reference voltage as described target level according to following formula: described built-up voltage/(described supercharging rate * magnification).

Described method can comprise further: prevent described elementary input voltage from excessively increasing or reducing.

Described method can comprise further: clamping voltage under selecting in the voltage of input in response to described supercharging rate.

Described method can comprise further: the level equalization making described elementary input voltage.

Described method can comprise further: produce supercharging rate rising reference voltage and supercharging rate decline reference voltage; Supercharging rate rising flag signal is activated higher than described supercharging rate rising reference voltage in response to described elementary input voltage; Supercharging rate decline marking signal is activated lower than described supercharging rate decline reference voltage in response to described elementary input voltage; And set described supercharging rate in response to described supercharging rate rising flag signal and/or described supercharging rate decline marking signal.

Described method can comprise further: the information providing the initial value about described supercharging rate.

Described method can comprise further: more each input reference voltage value and initial reference voltage.

Described method can comprise further: be activated to last in response to described supercharging rate rising flag signal and be longer than the reference time and increase described supercharging rate, and is activated to last in response to described supercharging rate decline marking signal and is longer than the reference time and reduces described supercharging rate.

In the process, the level of described supercharging rate rising reference voltage can be determined according to following formula:

Supply voltage/(magnification of amplifier);

And the level of described supercharging rate decline reference voltage is determined according to following formula:

Supply voltage * (unit that described supercharging rate-supercharging rate changes)/(described in the magnification * of described amplifier supercharging rate).

According to following detailed description, accompanying drawing and claims, further feature and aspect will be understood.

Accompanying drawing explanation

Fig. 1 illustrates that built-up voltage produces the block diagram of the voltage of circuit, signal and output voltage.

Fig. 2 illustrates that the built-up voltage according to an embodiment produces the block diagram of circuit.

Fig. 3 is the detailed diagram of the built-up voltage generation circuit of key diagram 2.

Fig. 4 illustrates the schematic diagram according to the voltage divider of an embodiment.

Fig. 5 illustrates the schematic diagram according to the marking signal generator of an embodiment.

Fig. 6 illustrates the schematic diagram according to the input reference voltage selector switch of an embodiment.

Fig. 7 illustrates the schematic diagram according to the initial value determiner of an embodiment.

Fig. 8 illustrates the schematic diagram according to the supercharging rate controller of an embodiment.

Fig. 9 illustrates the operation of counter.

Figure 10 illustrates the operation of predeterminable rise/fall counter.

Figure 11 to Figure 14 illustrates the operation of supercharging rate controller.

Figure 15 is the block diagram that lower clamping voltage selector switch is described.

Figure 16 is the block diagram of account for voltage pincers.

Figure 17 is the block diagram that output voltage voltage divider is described.

Figure 18 is the block diagram that compensating circuit is described.

Run through accompanying drawing and detailed description below, unless otherwise indicated, otherwise identical Reference numeral is interpreted as referring to same components, feature and structure.In order to clear, to illustrate and for the purpose of facility, the relative size of these assemblies and describe to exaggerate to some extent.

Embodiment

Following detailed description is provided to be in order to the complete understanding of auxiliary reader's acquisition to method described herein, device and/or system.Therefore, the enlightenment about the various changes of system described herein, device and/or method, amendment and equivalent will will be obtained to those of ordinary skill in the art.Described treatment step and/or the progress of operation are example; But the order of step and/or operation is not limited to set forth order herein, and except the step being necessary to occur with certain order and/or operation, the order of step and/or operation can change as known in the art.In addition, in order to strengthen sharpness and concisely spend, the description to known function and structure can be omitted.

Fig. 2 illustrates that the built-up voltage according to an embodiment produces the block diagram of circuit.

Referring to Fig. 2, built-up voltage produces circuit and comprises boost pressure circuit 200, supercharging rate setup unit 210, and input voltage level setup unit 220.

Boost pressure circuit 200 can make input voltage VCIN supercharging based on supercharging rate BT [a:0], and the exportable built-up voltage VOUT as output voltage.Therefore, built-up voltage VOUT can be the product that input voltage VCIN is multiplied by supercharging rate BT [a:0].For example, when supercharging rate BT [a:0] is " 2 " and input voltage VCIN is 1V, built-up voltage VOUT can be changed into 2V.When supercharging rate BT [a:0] is " 3 " and input voltage VCIN is 0.8V, built-up voltage VOUT can be changed into 2.4V.

Input voltage level setup unit 220 can set the level of input voltage VCIN in response to the target level of built-up voltage VOUT and supercharging rate BT [a:0].For example, input voltage level setup unit 220 can by the target level by the value that the target level of built-up voltage VOUT obtains divided by supercharging rate BT [a:0] (such as, the target level/supercharging rate BT [a:0] of built-up voltage VOUT) being set as input voltage VCIN.Although the target level of input voltage VCIN can be the target level of built-up voltage VOUT divided by supercharging rate BT [a:0], but the level of input voltage VCIN can lower than the value by being obtained divided by supercharging rate BT [a:0] (such as, the target level/supercharging rate BT [a:0] of built-up voltage VOUT) by the target level of built-up voltage VOUT.Because the target level of input voltage VCIN may exceed the level of supply voltage VDD, so input voltage VCIN can not higher than supply voltage VDD.

[equation 1]

Target level/supercharging rate the BT [a:0] of VCIN=built-up voltage VOUT

Supercharging rate setup unit 210 can receive the feedback of the level about input voltage VCIN, and can set supercharging rate BT [a:0].Supercharging rate setup unit 210 can be in response to the target level of input voltage VCIN level that input voltage VCIN can not have and increase supercharging rate BT [a:0].The target level of input voltage VCIN can be defined as the value by being obtained divided by supercharging rate BT [a:0] (target level/supercharging rate BT [a:0] of built-up voltage VOUT) by the target level of built-up voltage VOUT.In response to passing through by the target level of built-up voltage VOUT divided by supercharging rate BT [a:0] (such as, target level/supercharging rate the BT [a:0] of built-up voltage VOUT) and obtain value higher than supply voltage VDD, input voltage VCIN can not converge to its target level.In this case, supercharging rate setup unit 210 can increase supercharging rate BT [a:0].Only can improve supercharging rate BT [a:0] when needs improve supercharging rate BT [a:0].Target level due to input voltage VCIN is by by the target level of built-up voltage VOUT divided by supercharging rate BT [a:0] (such as, target level/supercharging rate the BT [a:0] of built-up voltage VOUT) and the value of acquisition, therefore in response to the supercharging rate BT [a:0] through increasing, the target level of input voltage VCIN also can reduce.

Although supercharging rate BT [a:0] can reduce a step-length, supercharging rate setup unit 210 can be in response to the target level of input voltage VCIN level that input voltage VCIN can have and reduce supercharging rate BT [a:0].Target level due to input voltage VCIN is by by the target level of built-up voltage VOUT divided by supercharging rate BT [a:0] (such as, target level/supercharging rate the BT [a:0] of built-up voltage VOUT) and the value of acquisition, therefore, in response to the supercharging rate BT [a:0] through reducing, the target level of input voltage VCIN can increase.If reduce supercharging rate BT [a:0] and increase the target level of input voltage VCIN, and the target level through increasing of input voltage VCIN becomes higher than supply voltage VDD, then again can increase supercharging rate BT [a:0].

Supercharging rate setup unit 210 can perform all mentioned operations.In other words, supercharging rate setup unit 210 only can increase supercharging rate BT [a:0] when needs increase supercharging rate BT [a:0], and supercharging rate setup unit 210 can be attempted to perform for making supercharging rate BT [a:0] reduce and the as many operation of amount that can permit.

Blower operations is for generation of the operation of level higher than the voltage of the level of input voltage.Supercharging rate becomes higher, then may consume more multiple current.Therefore, in response to producing the voltage with same level, the amount of the electric current that blower operations consumes is reduced by reducing supercharging rate.For example, the electric current by making 1V supercharging three doubly produce 3V voltage consumption is comparatively less than by make 2V supercharging 1.5 doubly produce electric current that 3V voltage consumes.According to an embodiment, because supercharging rate BT [a:0] is set as minimum value by the operation via supercharging rate setup unit 210 and input voltage level setup unit 220, therefore, the current drain that built-up voltage can be made to produce circuit minimizes.

Fig. 3 is the detailed diagram of the built-up voltage generation circuit of key diagram 2.

Referring to Fig. 3, supercharging rate setup unit 210 can comprise voltage divider 311, marking signal generator 312, supercharging rate controller 313 and initial value determiner 314.Input voltage level setup unit 220 can comprise output voltage voltage divider 321, input reference voltage selector switch 322, comparer 323, amplifier 324, lower clamping voltage selector switch 325, voltage clamp 326 and compensating circuit 327.

Voltage divider 311 can produce supercharging rate rising reference voltage BTUP_REF and supercharging rate decline reference voltage BTDN_REF.In response to elementary input voltage VCIN_F higher than supercharging rate rising reference voltage BTUP_REF, marking signal generator 312 can activate supercharging rate rising flag signal BTUP_FG.In response to elementary input voltage VCIN_F lower than supercharging rate decline reference voltage BTDN_REF, marking signal generator 312 can activate supercharging rate decline marking signal BTDN_FG.Supercharging rate controller 313 can set supercharging rate BT [a:0] in response to supercharging rate rising flag signal BTUP_FG and supercharging rate decline marking signal BTDN_FG.Initial value determiner 314 can provide signal BT_INI [m:0] about the initial value of supercharging rate BT [a:0] to supercharging rate controller 313.

Output voltage voltage divider 321 can by built-up voltage VOUT divided by the ratio determined based on supercharging rate BT [a:0], and at least one voltage through dividing potential drop exportable.Input reference voltage selector switch 322 can select input reference voltage VC_REF0 based on supercharging rate BT [a:0] in multiple voltage VR_REF [m:0], and described multiple voltage VR_REF [m:0] can produce based on the target level of built-up voltage VOUT.Comparer 323 can compare the output voltage VO UT_F of output voltage the voltage divider 321 and output voltage VC_REF0 of input reference voltage selector switch 322, and can produce elementary input voltage VCIN_F.Amplifier 324 can amplify elementary input voltage VCIN_F, and can produce input voltage VCIN.Lower clamping voltage selector switch 325 can select lower clamping voltage VCMP_DN0, and exportable by the lower clamping voltage selected.Elementary input voltage VCIN_F control can be not higher than upper clamping voltage VCMP_UP0 and be not less than lower clamping voltage VCMP_DN0 by voltage clamp 326, makes elementary input voltage VCIN_F can not become too high or too low.Compensating circuit 327 can contribute to the level equalization making elementary input voltage VCIN_F.Structure and the operation of constituent components is described in detail with reference to accompanying drawing.

Fig. 4 illustrates the schematic diagram according to the voltage divider 311 of an embodiment.

Referring to Fig. 4, voltage divider 311 can comprise the multiple resistor and analog voltage multiplex adapter (MUX) 401 that are coupled to supply voltage VDD and ground.At following instance (A) in (D), describe in detail produced by voltage divider 311 supercharging rate rising reference voltage BTUP_REF, supercharging rate decline reference voltage BTDN_REF, upper clamping voltage VCMP_UP0 and initial reference voltage BTINI_REF.

(A) supercharging rate rising reference voltage BTUP_REF is the reference voltage for increasing supercharging rate BT [a:0].Supercharging rate rising reference voltage BTUP_REF and elementary input voltage VCIN_F can be compared.Comparative result can with determine whether to increase supercharging rate BT [a:0].Elementary input voltage VCIN_F is the voltage of the half of the level can with (such as) input voltage VCIN.In response to the input voltage VCIN identical with supply voltage VDD, no matter how high elementary input voltage VCIN_F become, input voltage VCIN neither may become higher.In brief, when the level of elementary input voltage VCIN_F is supply voltage VDD/2, even if improve into higher by the level of elementary input voltage VCIN_F, built-up voltage VOUT also can not increase further.Therefore, the voltage of this point can become the level of supercharging rate rising reference voltage BTUP_REF.Because the supercharging rate of amplifier 324 can be 2, so the level of supercharging rate rising reference voltage BTUP_REF can be set as supply voltage VDD/2.Therefore, in order to represent supercharging rate rising reference voltage BTUP_REF with general equation, the level-variable of supercharging rate rising reference voltage BTUP_REF is: the supercharging rate of supply voltage VDD/ amplifier 324.

[equation 2]

The supercharging rate of BTUP_REF=VDD/ amplifier

(B) supercharging rate decline reference voltage BTDN_REF is the reference voltage for reducing supercharging rate BT [a:0].Supercharging rate decline reference voltage BTDN_REF and elementary input voltage VCIN_F can be compared.Determination result relatively can with determine whether to reduce supercharging rate BT [a:0].In this article, m ' expression supercharging step-length, and m starts from step-length 0.In addition, n ' represents the supercharging rate between 0.5 and 1.5.In other words, the initial value of m is " 0 ", and 0.5≤n '≤1.5.

Following table 1 represents supercharging step-length m ' and supercharging rate n '.Input voltage VCIN and the fac-tor equaling supercharging rate n '.

Table 1

Supercharging step-length m '	Supercharging rate n '
		Step-length 0	1.5
Step-length 1	2
		Step-length 2	2.5
Step-length 3	3
		Step-length 4	3.5

As seen from Table 1, supercharging step-length m ' and supercharging rate n ' have the relation according to equation 3.

[equation 3]

n′＝(m′+3)/2

Level based on elementary input voltage VCIN_F sets supercharging rate decline reference voltage BTDN_REF, although supercharging rate n ' step-down step-length lower than the point of the value for supply voltage VDD/2.Therefore, when representing supercharging rate decline reference voltage BTDN_REF by supercharging step-length m ', supercharging rate decline reference voltage BTDN_REF can be set according to equation 4.

[equation 4]

BTDN_REF(m′)＝VDD(m′+2)/((2＊m′)+6)

When being represented supercharging rate decline reference voltage BTDN_REF by supercharging rate (n '), supercharging rate decline reference voltage BTDN_REF can be set according to equation 5.

[equation 5]

BTDN_REF(n′)＝VDD(n′-0.5)/(2＊n′)

Based on the magnification of amplifier 324 for 2 and the hypothesis that the difference of a supercharging step-length is 0.5 obtains the value used in equation 5.These available following equatioies 6 represent:

[equation 6]

BTDN_REF (n ')=VDD (unit that n '-supercharging rate changes)/

(the magnification * n ' of amplifier)

The analog voltage multiplex adapter 401 of supercharging rate decline reference voltage BTDN_REF can be selected to be operable as: select above-mentioned supercharging rate decline reference voltage BTDN_REF (BTDN_REF [m:0]) based on magnification BT [a:0], described magnification BT [a:0] is for having the code of the information about magnification n '.

(C) upper clamping voltage VCMP_UP0 can input in voltage clamp 326, so as the level preventing from increasing as elementary input voltage VCIN_F unnecessarily increase and loading condition or supercharging rate BT [a:0] change time elementary input voltage VCIN_F converge to the problem of the time increase that desired value may spend.It is important that elementary input voltage VCIN_F meets lower point:

[equation 7]

VCIN_F＝VDD/2。

But elementary input voltage VCIN_F can higher than this point, and upper clamping voltage VCMP_UP0 can be used for preventing elementary input voltage VCIN_F from increasing to higher than this point.Therefore, upper clamping voltage VCMP_UP0 can be set according to equation 8.

[equation 8]

VCMP_UP0＝VDD/2+a

At this, " a " represents and (such as) can be not more than the tolerance limit of about 50mV.

(D) initial reference voltage BTINI_REF be with operate at initial pressurization during determine the reference voltage of suitable supercharging rate BT [a:0].In initial operation, due to input voltage VCIN may be needed to start with the state identical with the state of supply voltage VDD, therefore initial reference voltage BTINI_REF can be set as the value as supply voltage VDD/2.If consider, built-up voltage produces the operating current of circuit and given a certain tolerance limit, then initial reference voltage BTINI_REF can be set as the value as (supply voltage VDD/2+ β), and wherein β is the value of about 50mV.

Fig. 5 illustrates the schematic diagram according to the marking signal generator 312 of an embodiment.

Referring to Fig. 5, marking signal generator 312 can comprise two comparers 501 and 502.First comparer 501 can more elementary input voltage VCIN_F and supercharging rate decline reference voltage BTDN_REF, and can produce supercharging rate decline marking signal BTDN_FG.Second comparer 502 can more elementary input voltage VCIN_F and supercharging rate rising reference voltage BTUP_REF, and can produce supercharging rate rising flag signal BTUP_FG.

In response to elementary input voltage VCIN_F lower than supercharging rate decline reference voltage BTDN_REF, supercharging rate decline marking signal BTDN_FG can be activated, to reduce supercharging rate BT [a:0].In response to elementary input voltage VCIN_F higher than supercharging rate rising reference voltage BTUP_REF, supercharging rate rising flag signal BTUP_FG can be activated, to increase supercharging rate BT [a:0].

In response to elementary input voltage VCIN_F higher than supercharging rate decline reference voltage BTDN_REF and lower than supercharging rate rising reference voltage BTUP_REF, can by both supercharging rate rising flag signal BTUP_FG and supercharging rate decline marking signal BTDN_FG deactivation.In one example, this means that current booster rate BT [a:0] is suitable.

Fig. 6 illustrates the schematic diagram according to the input reference voltage selector switch 322 of an embodiment.

Referring to Fig. 6, input reference voltage selector switch 322 can comprise analog voltage multiplex adapter (MUX) 601.

Input reference voltage VC_REF0 is the desired value of elementary input voltage VCIN_F.Therefore, input reference voltage VC_REF0 can be set as value VOUTtar/ (2n '), and wherein VOUTtar represents the desired value of built-up voltage VOUT.This is the hypothesis of twice based on magnification.Input reference voltage VC_REF0 can be calculated according to equation 9.

[equation 9]

VC_REF0=VOUT _tar/ (the value of magnification n ' of amplifier)

When equation 9 is converted to value based on n ' and m ' to obtain value VC_REF [m '] that input in analog voltage multiplex adapter (MUX) 601, set VC_REF [m '] according to equation 10.

[equation 10]

VC_REF[m′]＝VOUT _tar/(m′+3)。

Therefore, VC_REF [m:0] can be set as described above, and analog voltage multiplex adapter (MUX) 601 can select the voltage being suitable for corresponding supercharging rate BT [a:0], as input reference voltage VC_REF0.

Fig. 7 illustrates the schematic diagram according to the initial value determiner 314 of an embodiment.

Referring to Fig. 7, initial value determiner 314 can comprise m+1 comparer 701, and these comparers 701 can more each VC_REF [m:0] value and initial reference voltage BTINI_REF.The signal BT_INI [m:0] of the exportable initial value about supercharging rate BT [a:0] of a described m+1 comparer 701.Although comparer 701 is illustrated a constituent components in the drawings, the quantity of comparer 701 can be m+1 or can be another quantity in due course.First comparer can compare VC_REF [0] and initial reference voltage BTINI_REF, and exportable BT_INI [0].Last comparer can compare VC_REF [m] and initial reference voltage BTINI_REF, and exportable BT_INI [m].

Because the initial reference voltage BTINI_REF produced in voltage divider 311 is (VDD/2+ β) (see above example (D)), therefore can be changed into about VC_REF [m:0] whether higher than the information of value (VDD/2+ β) about the information of initial value.As shown in Table 2 below, initial pressurization rate can be determined based in VC_REF [m:0] higher than the quantity of the voltage of (VDD/2+ β).

Table 2

BT_INI[m:0]	Initial pressurization rate
		2 m	n
2m+2 m-1	n-0.5
		2 m+2 m-1+2 m-2	n-1
...	...
		2 m+2 m-1+2 m-2+...+2	2
2 m+2 m-1+2 m-2+...+2+1＝2 m+1-1	1.5

Table 2 illustrates, when BT_INI [m:0] be (2m+1-1) (such as, last column place at table 2) time, when all values of BT_INI [m:0] is logic height, minimum supercharging rate (1.5) can be adopted as initial pressurization rate.When BT_INI [m:0] is (2*m) (such as, the first row place at table 2), when the value of only BT_INI [m] is logic height, most high pressure-charging rate (n) can be adopted as initial pressurization rate.

Fig. 8 illustrates the schematic diagram according to the supercharging rate controller 313 of an embodiment.

Supercharging rate controller 313 can be activated to last in response to supercharging rate rising flag signal BTUP_FG and is longer than the reference time and increases supercharging rate BT [a:0].Supercharging rate controller 313 can be activated to last in response to supercharging rate decline marking signal BTDN_FG and is longer than the reference time and reduces supercharging rate BT [a:0].

Supercharging rate controller 313 can comprise counter 801 and 802, comparer 803 and 804, D flip-flop (D-flip-flop) 805 and 806, initial value code translator 807 and predeterminable rise/fall counter 808.The assembly of supercharging rate controller 313 will be described in detail after a while.

Fig. 9 illustrates the operation of counter 801 and 802.

Counter 801 and 802 can be perform increase in the cycle that logic is high to export the code value BTUP_CNT [b:0] of lead-out terminal OUT [b:0] or the operation of BTDN_CNT [b:0] at the rising edge place of clock CK at signal BTUP_FG or BTDN_FG inputing to enable EN terminal.BTUP_CNT [b:0] is rising count signal; BTDN_CNT [b:0] is decline count signal.In addition, in response to the initializing signal P_ST high for logic inputed in reset RST terminal, all positions exporting the code of terminal OUT [b:0] to can be initialized as 0.Referring to Fig. 9, the operation of counter 801 and 802 can be understood.The signal inputed in RST terminal is periodic signal P_ST, and periodic signal P_ST can be activated once during supercharging rate controller 313 changes the one-period of supercharging rate BT [a:0].

Refer again to Fig. 8, comparer 803 can relatively from BTUP_CNT [b:0] and supercharging rate rising reference value BTUP_R [b:0] of counter 801 output.Be greater than supercharging rate rising reference value BTUP_R [b:0] in response to BTUP_CNT [b:0] value, comparer 803 is exportable is in the high supercharging rising enable signal BTUP_PEN of logic.Supercharging rate rising reference value BTUP_R [b:0] is less than, the exportable signal BTUP_PEN being in logic low of comparer 803 in response to BTUP_CNT [b:0] value.

Comparer 804 can compare BTDN_CNT [b:0] and supercharging rate decline reference value BTDN_R [b:0].Be greater than supercharging rate decline reference value BTDN_R [b:0] in response to BTDN_CNT [b:0] value, comparer 804 is exportable is in the high signal BTDN_PEN of logic.Supercharging rate decline reference value BTDN_R [b:0] is less than, the exportable signal BTDN_PEN being in logic low of comparer 804 in response to BTDN_CNT [b:0] value.

Along with supercharging rate rising reference value BTUP_R [b:0] and supercharging rate decline reference value BTDN_R [b:0] increase, the activationary time of supercharging rate rising flag signal BTUP_FG and supercharging rate decline marking signal BTDN_FG is elongated.

Initial value code translator 807 can change the form of the BT_INI [m:0] produced in initial value determiner 314.Following table 3 represents BT_INI [m:0] and D_BT_INI [a:0] and by the relation between both initial pressurization rates of representing aforementioned.

Table 3

BT_INI[m:0]	D_BT_INI[a:0]	Initial pressurization rate
			2 m	2n-3	n

2 m+2 m-1	2n-4	n-0.5
			2 m+2 m-1+2 m-2	2n-5	n-1
...	...	...
			2 m+2 m-1+2 m-2+...+2	1	2
2 m+2 m-1+2 m-2+...+2+1＝2 m+1-1	0	1.5

Figure 10 illustrates the operation of predeterminable rise/fall counter 808.In response to the signal BTUP_EN high for logic inputed in UP terminal, predeterminable rise/fall counter 808 can make code BT [a:0] value of terminal OUT [a:0] increase one at the rising edge place of CK terminal signals, described CK terminal signals is the inverse signal of P_ST signal.In response to the signal BTDN_DN high for logic inputed in DN terminal, predeterminable rise/fall counter 808 can make code BT [a:0] value of terminal OUT [a:0] subtract one at the rising edge place of CK terminal signals.

In addition, in response to enable terminal PEN is the DC conversion start signal DCC_ST that logic is high, and the code D_BT_INI [a:0] of P [a:0] terminal can become the code BT [a:0] of OUT [a:0] terminal.In brief, in response to PEN terminal is the signal that logic is high, and supercharging rate can be initialized as the value of D_BT_INI [a:0].

The DCC_ST signal inputed in PEN terminal can be in response to the built-up voltage that is activated produces the operation of circuit and is activated to the high signal of logic.

Following table 4 represents the relation between supercharging rate code BT [a:0] (representing supercharging rate) and initial pressurization rate.

Table 4

BT[a:0]	Initial pressurization rate
		0	1.5
1	2
		2	2.5
...	...
		2n-4	n-0.5
2n-3	n

Figure 11 to Figure 14 illustrates the operation of rate of pressurization controller 313.Figure 11 illustrates the initial operation of supercharging rate controller 313.Figure 12 illustrates that supercharging rate controller 313 increases the operation of supercharging rate upon initial operation.Figure 13 illustrates that supercharging rate controller 313 reduces the operation of supercharging rate upon initial operation.Figure 14 illustrates the operation of the supercharging rate set during supercharging rate controller 313 maintains initial operation.

Referring to Figure 11, the initial operation of supercharging rate controller 313 is described.

After the operation starting built-up voltage generation circuit, can by high to logic for DCC_ST signal activation.Then, the D_BT_INI [2:0] inputed in its P [a:0] terminal can be set as the initial value of supercharging rate BT [2:0] by predeterminable rise/fall counter 808.Figure 11 illustrates that the value of D_BT_INI [2:0] is 2, and the value therefore representing the code BT [2:0] of supercharging rate is 2 in this example, and the supercharging rate (2.5) corresponding to BT [2:0] value (2) is set as supercharging rate.In other words, in shown example, supercharging rate is 2.5.Should be appreciated that, the value provided is only in order to exemplary object, and other input value can provide different output valves.

Figure 12 illustrates that supercharging rate controller 313 increases the operation of supercharging rate upon initial operation.As an example, supercharging rate rising reference value BTUP_R [9:0] and supercharging rate decline reference value BTDN_R [9:0] can be set as 600.

At activation P_ST signal and after P_ST signal experience edge cycle (porch period), clock CK can start to carry out bifurcation triggering (toggling).In response to being the high supercharging rate rising flag signal BTUP_FG of logic, counter 801 can count clock CK, and can increase BTUP_CNT [9:0] value gradually.In response to BTUP_CNT [9:0] value of increase converging to supercharging rate rising reference value (such as, BTUP_R [9:0]=600), can by high to logic for BTUP_PEN signal activation.BTUP_EN signal activates by being activated to the BTUP_PEN signal that logic is high.In response to the P_ST signal that can again activate, predeterminable rise/fall counter 808 can will represent that code BT [2:0] value of supercharging rate increases to 3 from 2.Therefore, supercharging rate can increase to 3 from 2.5.

Figure 13 illustrates that supercharging rate controller 313 reduces the operation of supercharging rate upon initial operation.As an example, supercharging rate rising reference value BTUP_R [9:0] and supercharging rate decline reference value BTDN_R [9:0] can be set as 600.

Activation P_ST signal and P_ST signal experience the edge cycle after, clock CK can start to carry out bifurcation triggering.In response to being the high supercharging rate decline marking signal BTDN_FG of logic, counter 802 can count clock CK, and can increase BTDN_CNT [9:0] value gradually.In response to BTDN_CNT [9:0] value of increase converging to supercharging rate decline reference value (such as, BTDN_R [9:0]=600), can by high to logic for BTDN_PEN signal activation.BTUP_EN signal activates by being activated to the BTDN_PEN signal that logic is high.In response to the P_ST signal that can again activate, predeterminable rise/fall counter 808 can will represent that supercharging rate code BT [2:0] value of supercharging rate is decreased to 1 from 2.Therefore, supercharging rate can be decreased to 2 from 2.5.

Figure 14 illustrates the operation of the supercharging rate set during supercharging rate controller 313 maintains initial operation.As an example, supercharging rate rising reference value BTUP_R [9:0] and supercharging rate decline reference value BTDN_R [9:0] can be set as 600.

Activation P_ST signal and P_ST signal experience the edge cycle after, clock CK can start to carry out bifurcation triggering.In response to being the high supercharging rate decline marking signal BTDN_FG of logic, counter 802 can count clock CK, and can increase BTDN_CNT [9:0] value gradually.When increasing BTDN_CNT [9:0] value, supercharging rate decline marking signal BTDN_FG can be converted to logic low.Therefore, such as, BTDN_CNT [9:0] value may no longer increase from value 413.Because BTDN_CNT [9:0] may not converge to supercharging rate decline reference value (such as, BTDN_R [9:0]=600), BTUP_PEN signal and BTUP_EN signal therefore can not be activated.As a result, predeterminable rise/fall counter 808 can not change code BT [2:0] value representing supercharging rate.Therefore, supercharging rate can be maintained at 2.5.

Be illustrated in the example in Figure 14, because the time activated residing for supercharging rate decline marking signal BTDN_FG does not converge to the reference time (such as, 600 dock cycles), therefore may not changing supercharging rate.In other words, in the example of Figure 14, even at 600 dock cycles places, BTDN_CNT [9:0] value still rests on 413, and never will arrive 600, is therefore produced by the signal not changing supercharging rate.

Figure 15 is the block diagram that lower clamping voltage selector switch 325 is described.

Lower clamping voltage selector switch 325 can comprise analog multiplexer (MUX) 1501, and clamping voltage VCMP_DN0 under can selecting in the voltage VCMP_DN [m:0] of input in response to supercharging rate BT [a:0].

In response to loading condition or the supercharging rate BT [a:0] of too low elementary input voltage VCIN_F and change, lower clamping voltage VCMP_DN0 can input in voltage clamp 326, and converge to the time that desired value spends increases to prevent elementary input voltage VCIN_F.

The input voltage VCMP_DN [m:0] inputed in lower clamping voltage selector switch 325 can be produced according to equation 11.

[equation 11]

VCMP_DN[m′]＝VC_REF[m′]_a，

Wherein a ≈ 50mV

Lower clamping voltage selector switch 325 can select the input voltage VCMP_DN [m:0] being suitable for supercharging rate BT [a:0], as lower clamping voltage VCMP_DNO.

Figure 16 is the block diagram of account for voltage pincers 326.

Voltage clamp 326 can comprise pincers 1601 and lower pincers 1602.

Upper pincers 1601 can become to produce between ground terminal from elementary input voltage VCIN_F higher than upper clamping voltage VCMP_UPO in response to elementary input voltage VCIN_F and sink electric current (sinking current), thus prevents elementary input voltage VCIN_F from becoming higher than upper clamping voltage VCMP_UPO.

Lower pincers 1602 can produce drive current in response to elementary input voltage VCIN_F becomes lower than lower clamping voltage VCMP_DNO from elementary input voltage VCIN_F between supply voltage VDD, thus prevents elementary input voltage VCIN_F from becoming higher than upper clamping voltage VCMP_DNO.

Figure 17 is the block diagram that output voltage voltage divider 321 is described.

Output voltage voltage divider 321 can comprise and being coupled with multiple resistor built-up voltage VOUT being carried out to dividing potential drop and analog voltage multiplex adapter (MUX) 1701 by serial.

In response to the current booster rate BT [a:0] for n ', the level of the built-up voltage VOUT_F exported from output voltage voltage divider 321 can be calculated according to equation 12.

[equation 12]

VOUT/(2＊n′)。

This is because the magnification of amplifier 324 is 2 in this example.More generally above-mentioned relation can be represented according to following equation 13.

[equation 13]

VOUT_F=(VOUT/ (magnification of n ' * amplifier)

When VOUT/ (2*n ') is expressed as the value based on m ', VOUT/ (2*n ') can be expressed according to equation 14.

[equation 14]

VOUT_F＝VOUT/(m′+3)。

Analog voltage multiplex adapter (MUX) 1701 is operable as: select suitable output voltage VO UT_F based on supercharging rate BT [a:0].

Figure 18 is the block diagram that compensating circuit 327 is described.

Compensating circuit 327 can comprise resistor Rc and capacitor Cc.Compensating circuit 327 can guarantee the stability of backfeed loop, and described backfeed loop is by being added into loop to produce elementary input voltage VCIN_F by limit (pole) and/or zero point (zero).

Again referring to Fig. 3, comparer 323 can compare the output voltage VO UT_F of output voltage the voltage divider 321 and output voltage VC_REF0 of input reference voltage selector switch 322, and can produce elementary input voltage VCIN_F.

In response to the output voltage VO UT_F of output voltage voltage divider 321 higher than input reference voltage VC_REF0, comparer 323 can reduce the level of elementary input voltage VCIN_F.In response to the output voltage VO UT_F of output voltage voltage divider 321 lower than input reference voltage VC_REF0, comparer 323 can improve the level of elementary input voltage VCIN_F.

In response to the output voltage VO UT_F of output voltage voltage divider 321 higher than input reference voltage VC_REF0, the level of elementary input voltage VCIN_F can be reduced.Therefore, the level of input voltage VCIN can be reduced.This reduction can be reflected in output voltage VO UT, and the output voltage VO UT_F of output voltage voltage divider 321 also can reduce.The level of elementary input voltage VCIN_F can converge to input reference voltage VC_REF0.

In response to the output voltage VO UT_F of output voltage voltage divider 321 lower than input reference voltage VC_REF0, the level of elementary input voltage VCIN_F can be improved.Therefore, the level of input voltage VCIN can be increased.This increase can be reflected in output voltage VO UT, and the output voltage VO UT_F of output voltage voltage divider 321 also can increase.The level of elementary input voltage VCIN_F can converge to input reference voltage VC_REF0.

Amplifier 324 can comprise two resistor R and the comparer 328 as linear regulator.Amplifier 324 can make elementary input voltage VCIN_F amplify twice (such as, amplifying with 2), and can produce input voltage VCIN.Should be appreciated that, the magnification of amplifier 324 can be changed into the magnification except twice.

Now the overall operation of built-up voltage generation circuit will be described.

Input voltage level setup unit 220 can produce the input voltage VCIN that target level is (target output voltage/supercharging rate).In other words, it can carry out the level of control inputs voltage VCIN according to equation 15.

[equation 15]

VCIN＝VOUT _tar/n′

Supercharging rate setup unit 210 can be in response to the target level of input voltage VCIN (VOUTtar/n ') level (such as, exceeding supply voltage in response to target level VOUTtar/n ') that input voltage VCIN can not have and increase supercharging rate BT [a:0].Even if supercharging rate BT [a:0] can be reduced a step-length, if but the level that the target level of input voltage VCIN is input voltage VCIN can not be had (such as, the target level of input voltage VCIN is lower than supply voltage), supercharging rate setup unit 210 still can reduce supercharging rate BT [a:0].

Via the operation of input voltage level setup unit 220 and supercharging rate setup unit 210, supercharging rate BT [a:0] can become and allow low as far as possible, and input voltage VCIN is increased to and allows high as far as possible in the scope making input voltage VCIN may not exceed the level of supply voltage.

Supercharging rate BT [a:0] becomes higher, and built-up voltage produces circuit just can consume more multiple current.According to an embodiment, via the operation of supercharging rate setup unit 210 and input voltage level setup unit 220, supercharging rate BT [a:0] can be made to allow ground to reduce as far as possible, and the current drain that built-up voltage produces circuit can reduce.

Producing circuit according to the built-up voltage of an embodiment manufacture can make input voltage maximize, and supercharging rate can be made to minimize to produce the built-up voltage with target level.Therefore, built-up voltage produces circuit by making input voltage supercharging to produce the built-up voltage with target level with minimum supercharging rate.

As a result, built-up voltage produces circuit and can maintain minimal current consumption.

Above some examples are described.But, understanding can be carried out various amendment.For example, assembly when performing described technology with different order and/or in described system, framework, device or circuit carries out combining and/or being replaced by other assembly or its equivalent or supplemented by different way, suitable result can be realized.For example, when in place, described hardware device and/or its assembly can be configured to serve as one or more software module, to perform operation as described above and process, or vice versa.Described process, function, method and/or software can record, store or be fixed in one or more computer-readable storage media, one or more computer-readable storage media described comprises programmed instruction, and these programmed instruction are treated by computer-implemented to make processor carry out or perform these programmed instruction.Described medium also can comprise (combining ground separately or with programmed instruction) data file, data structure etc.Therefore, other embodiment also within the scope of the appended claims.

Claims (39)

1. built-up voltage produces a circuit, and it comprises:

Boost pressure circuit, this boost pressure circuit is configured to:

Input voltage supercharging is made based on supercharging rate; And

Export built-up voltage;

Supercharging rate setup unit, this supercharging rate setup unit is configured to:

Receive the feedback about the level of described input voltage; And

Set described supercharging rate; And

Input voltage level setup unit, this input voltage level setup unit is configured to the level setting described input voltage in response to the following:

The target level of described built-up voltage; And

Described supercharging rate.

2. built-up voltage as claimed in claim 1 produces circuit, and wherein said input voltage level setup unit is further configured to: the target level setting described input voltage according to following value:

(target level/described supercharging rate of described built-up voltage).

3. built-up voltage as claimed in claim 2 produces circuit, and wherein said supercharging rate setup unit is further configured to: increase described supercharging rate outside the level range exceeding described input voltage in response to the target level of described input voltage.

4. built-up voltage as claimed in claim 3 produces circuit, and wherein said supercharging rate setup unit is further configured to: reduce described supercharging rate in the described level range falling into described input voltage in response to the target level of the described input voltage when described supercharging rate reduces.

5. built-up voltage as claimed in claim 1 produces circuit, and wherein said input voltage level setup unit comprises:

Output voltage voltage divider, this output voltage voltage divider is configured to:

By described built-up voltage divided by the ratio determined based on described supercharging rate; And

Export the voltage through dividing potential drop;

Input reference voltage selector switch, this input reference voltage selector switch is configured to: select input reference voltage in the multiple voltages produced at the target level based on described built-up voltage based on described supercharging rate;

Comparer, this comparer is configured to:

The output voltage of more described output voltage voltage divider and the output voltage of described input reference voltage selector switch; And

Produce elementary input voltage; And

Amplifier, this amplifier is configured to:

Amplify described elementary input voltage; And

Produce described input voltage.

6. built-up voltage as claimed in claim 5 produces circuit, and wherein said amplifier comprises:

Comparer, this comparer is configured to linear regulator; And

Multiple resistor.

7. built-up voltage as claimed in claim 5 produces circuit, and wherein said output voltage voltage divider is further configured to: carry out dividing potential drop by following ratio to described built-up voltage:

1/ (magnification of amplifier described in described supercharging rate *).

8. built-up voltage as claimed in claim 7 produces circuit, and wherein said input reference voltage selector switch is further configured to: select the input reference voltage as described target level according to following formula:

Described built-up voltage/(magnification of amplifier described in described supercharging rate *).

9. built-up voltage as claimed in claim 5 produces circuit, and wherein said input voltage level setup unit comprises voltage clamp further, and this voltage clamp is configured to prevent described elementary input voltage from excessively increasing or reducing.

10. built-up voltage as claimed in claim 9 produces circuit, and wherein said voltage clamp comprises analog multiplexer, and this analog multiplexer is configured to: clamping voltage under selecting in the voltage of input in response to described supercharging rate.

11. built-up voltages as claimed in claim 9 produce circuit, and wherein said input voltage level setup unit comprises compensating circuit further, and this compensating circuit is configured to the level equalization making described elementary input voltage.

12. built-up voltages as claimed in claim 11 produce circuit, and wherein said compensating circuit comprises:

Resistor; And

Capacitor.

13. built-up voltages as claimed in claim 5 produce circuit, and wherein said supercharging rate setup unit comprises:

Voltage divider, this voltage divider is configured to produce:

Supercharging rate rising reference voltage; And

Supercharging rate decline reference voltage;

Marking signal generator, this marking signal generator is configured to:

Supercharging rate rising flag signal is activated higher than described supercharging rate rising reference voltage in response to described elementary input voltage; And

Supercharging rate decline marking signal is activated lower than described supercharging rate decline reference voltage in response to described elementary input voltage; And

Supercharging rate controller, this supercharging rate controller is configured to: set described supercharging rate in response to described supercharging rate rising flag signal and/or described supercharging rate decline marking signal.

14. built-up voltages as claimed in claim 13 produce circuit, and wherein said supercharging rate setup unit comprises initial value determiner further, and this initial value determiner is configured to: the information providing the initial value about described supercharging rate to described supercharging rate controller.

15. built-up voltages as claimed in claim 14 produce circuit, and wherein said initial value determiner comprises multiple comparer, and described multiple comparer is configured to: more each input reference voltage value and initial reference voltage.

16. built-up voltages as claimed in claim 13 produce circuit, and wherein said supercharging rate controller is further configured to:

Be activated to last in response to described supercharging rate rising flag signal and be longer than the reference time and increase described supercharging rate; And

Be activated to last in response to described supercharging rate decline marking signal and be longer than the reference time and reduce described supercharging rate.

17. built-up voltages as claimed in claim 16 produce circuit, and wherein said supercharging rate controller comprises:

Multiple counter;

Multiple comparer;

Multiple trigger;

Initial value code translator; And

Predeterminable rise/fall counter.

18. built-up voltages as claimed in claim 17 produce circuit, wherein:

Described predeterminable rise/fall counter is configured to: the initial value by the initial pressurization rate signal sets inputed in described predeterminable rise/fall counter being described supercharging rate;

In response to being the high described supercharging rate rising flag signal of logic, the first counter in described multiple counter is configured to: count clock, thus increases rising count value; And

Converge to described supercharging rate rising reference voltage in response to the rising count value increased, described predeterminable rise/fall counter is further configured to: the increase starting described supercharging rate.

19. built-up voltages as claimed in claim 17 produce circuit, wherein:

Described predeterminable rise/fall counter is configured to: the initial value by the initial pressurization rate signal sets inputed in described predeterminable rise/fall counter being described supercharging rate;

In response to being the high described supercharging rate decline marking signal of logic, the second counter in described multiple counter is configured to: count clock, thus increases decline count value; And

Converge to described supercharging rate decline reference voltage in response to the decline count value increased, described predeterminable rise/fall counter is further configured to: the reduction starting described supercharging rate.

20. built-up voltages as claimed in claim 17 produce circuit, wherein:

Described predeterminable rise/fall counter is configured to: the initial value by the initial pressurization rate signal sets inputed in described predeterminable rise/fall counter being described supercharging rate; And

In response to being the high described supercharging rate decline marking signal of logic, the second counter in described multiple counter is configured to count clock thus increase decline count value, described supercharging rate decline marking signal is converted to logic low when increasing described decline count value, described decline count value is not increased further, makes described predeterminable rise/fall counter not start the change of described supercharging rate.

21. built-up voltages as claimed in claim 13 produce circuit, wherein:

The level of described supercharging rate rising reference voltage is determined according to following formula:

Supply voltage/(magnification of described amplifier); And

The level of described supercharging rate decline reference voltage is determined according to following formula:

Described supply voltage * (unit that described supercharging rate-supercharging rate changes)/

(described in the magnification * of described amplifier supercharging rate).

22. 1 kinds produce the method for circuit for operating built-up voltage, and described built-up voltage produces circuit by making input voltage supercharging produce built-up voltage based on supercharging rate, and described method comprises:

Produce the input voltage that target is following level:

(target voltage/supercharging rate of described built-up voltage);

Increase described supercharging rate outside the level range exceeding described input voltage in response to the target level of described input voltage; And

Described supercharging rate is reduced in the described level range falling into described input voltage in response to the target level of the described input voltage when described supercharging rate reduces.

23. methods as claimed in claim 22, wherein said input voltage does not have the level higher than supply voltage.

24. methods as claimed in claim 22, the target level that the reduction of wherein said supercharging rate is in response to described input voltage performs lower than following value:

(unit that described supercharging rate-supercharging rate changes)/described supercharging rate.

25. 1 kinds of methods producing built-up voltage, comprise:

Input voltage supercharging is made based on supercharging rate;

Export built-up voltage;

Receive the feedback about the level of described input voltage;

Set described supercharging rate; And

The level of described input voltage is set in response to the following:

The target level of described built-up voltage; And

Described supercharging rate.

26. methods as claimed in claim 25, comprise: the target level setting described input voltage according to following value further:

(target level/described supercharging rate of described built-up voltage).

27. methods as claimed in claim 26, comprise further: increase described supercharging rate outside the level range exceeding described input voltage in response to the target level of described input voltage.

28. methods as claimed in claim 27, comprise further: reduce described supercharging rate in the described level range falling into described input voltage in response to the target level of the described input voltage when described supercharging rate reduces.

29. methods as claimed in claim 25, comprise further:

By described built-up voltage divided by the ratio determined based on described supercharging rate;

Export the voltage through dividing potential drop;

Input reference voltage is selected in the multiple voltages produced at the target level based on described built-up voltage based on described supercharging rate;

Relatively output voltage and input reference voltage;

Produce elementary input voltage;

Amplify described elementary input voltage; And

Produce described input voltage.

30. methods as claimed in claim 29, comprise: carry out dividing potential drop by following ratio to described built-up voltage further:

1/ (described supercharging rate * magnification).

31. methods as claimed in claim 30, comprise further: select the input reference voltage as described target level according to following formula:

Described built-up voltage/(described supercharging rate * magnification).

32. methods as claimed in claim 29, comprise further: prevent described elementary input voltage from excessively increasing or reducing.

33. methods as claimed in claim 32, comprise further: clamping voltage under selecting in the voltage of input in response to described supercharging rate.

34. methods as claimed in claim 32, comprise: the level equalization making described elementary input voltage further.

35. methods as claimed in claim 29, comprise further:

Produce supercharging rate rising reference voltage and supercharging rate decline reference voltage;

Supercharging rate rising flag signal is activated higher than described supercharging rate rising reference voltage in response to described elementary input voltage;

Supercharging rate decline marking signal is activated lower than described supercharging rate decline reference voltage in response to described elementary input voltage; And

Described supercharging rate is set in response to described supercharging rate rising flag signal and/or described supercharging rate decline marking signal.

36. methods as claimed in claim 35, comprise: the information providing the initial value about described supercharging rate further.

37. methods as claimed in claim 36, comprise: more each input reference voltage value and initial reference voltage further.

38. methods as claimed in claim 35, comprise further:

Be activated to last in response to described supercharging rate rising flag signal and be longer than the reference time and increase described supercharging rate; And

Be activated to last in response to described supercharging rate decline marking signal and be longer than the reference time and reduce described supercharging rate.

39. methods as claimed in claim 35, wherein:

The level of described supercharging rate rising reference voltage is determined according to following formula:

Supply voltage/(magnification of amplifier); And

The level of described supercharging rate decline reference voltage is determined according to following formula:

Described supply voltage * (unit that described supercharging rate-supercharging rate changes)/

(described in the magnification * of described amplifier supercharging rate).