TWI490958B - 用於具整合被動元件之積體電路封裝之方法與系統 - Google Patents

用於具整合被動元件之積體電路封裝之方法與系統 Download PDF

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Publication number
TWI490958B
TWI490958B TW098118901A TW98118901A TWI490958B TW I490958 B TWI490958 B TW I490958B TW 098118901 A TW098118901 A TW 098118901A TW 98118901 A TW98118901 A TW 98118901A TW I490958 B TWI490958 B TW I490958B
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Taiwan
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die
bond pads
layer
solder
conductive layer
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TW098118901A
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English (en)
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TW201009967A (en
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Anindya Poddar
Ashok Prabhu
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Nat Semiconductor Corp
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Publication of TW201009967A publication Critical patent/TW201009967A/zh
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Description

用於具整合被動元件之積體電路封裝之方法與系統
本發明一般相關於一積體電路(integrated circuit，IC)的封裝。尤其是，描述用於包含整合被動元件之IC封裝的方法和系統。
有一些習知用於積體電路(integrated circuit，IC)晶粒封裝的製程。例如，許多IC封裝利用一已加蓋或自一金屬片蝕刻之金屬引線架以提供至外部元件的電氣互連。該晶粒可藉接合線、焊料凸塊或其他適合的電氣連接的方式電氣連接至該引線架。一般來說，當移除經曝露的引線架的所選部分以促進至外部元件的電氣連接時，該晶粒和該部分引線架以一模塑材料膠封以在該晶粒的主動方面上保護該敏感電子組件。
該完成的IC封裝往往安裝到印刷電路板(printed circuit board，PCB)上。該PCB是用來機械支持和電氣連接電子組件，其包括使用導電通路或軌跡之IC封裝，通常從形成薄板的銅片蝕刻到一非導電基板。在許多應用中，沿一些軌跡定位各種非主動(或被動)元件以打斷在該晶粒和一外部元件或電力供應器之間的某些信號傳輸路徑是理想的。舉例來說，一個或多個電阻、電容及/或電感往往安裝到該PCB上。例如，一旁路電容通常用來將該電路的某一部分解耦成另一個。更具體地說，一旁路電容可用於繞過該電力供應器或其他電路的高阻抗組件。
不幸的是，該信號傳輸路徑的延長長度，在電路中自己造成提高的寄生電阻和電感。舉例來說，在應用中利用具有接合線的引線架，該給定信號的路徑長度是大致相等於該接合線長度、該引線的長度、該將引線與一被動元件耦合的軌跡的長度、該被動元件的長度和將該被動元件與一外部元件耦合的長度之總和。在諸如高速模擬數位轉換器(analog to digital converter，ADC)的高速應用中，較高電阻和增加的電感尤其是嚴重的問題，其中將該工作頻率最大化和將該時間延遲最小化是理想的。
直到現有用於IC元件封裝的排列和方法是有效的工作時，於將該IC元件大小最小化和改善該IC元件的電氣性能此兩者需要繼續努力。
在某一方面，描述用於積體電路晶粒封裝的方法，致使每個封裝包含一具有一整合被動元件安置於該晶粒上之晶粒。首先，提供一包括多個積體電路晶粒的晶圓。該每個晶粒的主動表面包括一第一組接合墊和一第二組接合墊。於該晶粒的主動表面上沉積第一導電層。隨後，然後於該第一導電層上沉積第二導電阻擋層。然後於該第二導電阻擋層上沉積第三焊料可濕性導電層。然後移除第一導電層、第二導電阻擋層和第三焊料可濕性導電層不位在每個晶粒的第一組接合墊或第二組接合墊的部分。隨後，移除第二導電阻擋層和第三焊料可濕性導電層位在每個晶粒的第二組接合墊的部分。然後於第三焊料可濕性導電層位在每個晶粒的第一組接合墊的部分上沉積一層焊料。然後於該每個晶粒的主動表面上定位非主動電氣組件，如此將自該非主動電氣元件的電極定位在沉積於該晶粒的第一組接合墊上的焊料附近。然後回焊該焊料以將該非主動電氣組件的電極與多個第一組接合墊電氣和物理連接。然後該晶圓可單一化以提供個別積體電路晶粒，每個積體電路晶粒具有一安置於該晶粒的表面上的一被動元件。
本發明一般相關於一積體電路(integrated circuit，IC)的封裝。尤其是，描述用於包含整合被動元件之IC封裝的方法和系統。
在下面描述中，闡明許多具體的細節以提供一本發明的透徹了解。然而，這將為熟知本發明的技術領域中該技藝人士所察知的，可以在未描述該具體細節的部分或全部下實行。在其他情況下，為了避免對本發明的不必要妨礙，眾所周知的製程步驟沒有詳細說明。
下列描述重點在一IC封裝的生產，包括一具有第一組焊料可濕性接合墊以及第二組用於電氣連接至接合線之經排列的接合墊之晶粒。排列該第一組焊料可濕性接合墊以用於自一非主動(被動)電氣元件通過焊料接點可直接與電極(或引線)連接，當透過接合線以引線或其他自一適合的基板(諸如一引線架以促進與外部元件連接)的接觸連接該第二組接合墊。各種本發明實施例將參考圖1至9敘述。
參考最初的圖1，並進一步參考圖2至3，一個按照本發明的特別實施例的用於準備封裝用的IC晶粒的製程100將敘述於下。最初，製造一包括大量的晶粒的半導體晶圓200。眾所周知的技藝中，大多晶圓和晶粒以矽(Si)形成，雖然任何其他適當的半導體材料也可以使用。圖2說明一合適的晶圓200的圖解上部圖。然而該圖解說明於圖2的晶圓200只顯示少數IC晶粒202，這將為熟知該技藝人士所察知的，該技藝中晶圓的此狀態通常會有幾百至幾千晶粒形成於上，並且預估在未來晶圓中甚至將達到更高的元件密度。該晶粒202一般形成在一行和列的二維陣列中，該陣列藉刻劃線203(也稱為鋸開的道)將每個行/列與相當緊鄰的行/列分離。每個晶粒202在自該晶圓200單一化後將成為一IC組件。
一IC晶粒202一般有多個位於形成於該晶粒的半導體基板之主動電路中的金屬層。通常將中間介電層插入在該金屬層之間以物理和電氣分離該金屬層。在該介電層適當的地點上形成電氣導電孔洞，為了在理想的位置電氣連接金屬層的特定部分。該各種金屬層可在該IC晶粒之間作為接地/電力平面及/或作為信號選路互連來使用。各種材料可用於形成該介電層和金屬層。例如，鋁(Al)和銅(Cu)經常被用來作為該金屬層的材料和(在以Si為基底的元件中)二氧化矽、氮化矽及/或其他氧化物和氮化物是常用來形成該介電層。留下所選的部分最高金屬層以通過在每個晶粒202的主動表面204上的該最外介電層或鈍化層的各種開洞曝露以形成作為該晶粒的電氣接觸的複數個接合墊(以下也稱為「I/O墊」)206和208(集合該晶粒202的主動表面204以形成該晶圓的主動表面)。在該說明的實施例中，每個晶粒202包括6個內部接合墊206和16個周圍接合墊208；然而根據該特定應用的需要，該接合墊206和208的數量、大小和佈局可能大大地改變。此外，雖然該內部接合墊206和周圍接合墊208的曝露部分以方形幾何說明，熟知該領域中技藝人士將察知該接合墊也可以其他幾何形狀假定，例如矩形或圓圈。
熟悉該領域的人士將察知，使用焊料凸塊的I/O墊和電接合的晶粒可在該晶粒的原來主動晶粒上的原來的接合墊，但也可是使用習知重新分配技術已自原來的接合墊重新分配的接合墊。特別是，該原來的接合墊往往分配在自該晶粒的周圍邊緣一指定距離的晶粒周圍附近。這接合墊配置通常是適用於大多數線接合的應用，但是，它可能有利於使用金屬重新分配線重新分配一些或全部的原本的接合墊以形成一個理想的I/O接合墊206和208的最終陣列佈局。
在步驟102中，將第一金屬層310沉積到該晶圓200的主動表面上。圖3A和3B分別說明在沉積金屬層310之前和之後的一部分晶粒202的圖解橫截側面。該金屬層310較佳覆蓋該晶圓200的整個主動表面，或者至少覆蓋形成該晶粒202的主動表面。該金屬層310的厚度較佳是在約1微米的等級，雖然較薄和較厚的金屬層可以是適當的和允許的。在某一特別的實施例中，該金屬層310的厚度是約1.0微米。雖然可用任何合適的製程以沉積金屬層310，例如濺射或蒸發，在某一較佳的實施例中將該金屬層濺射到該晶圓200的主動表面。在該說明的實施例中，該等內部接合墊206及周圍接合墊208由鋁形成且該金屬層310由鋁或一合適的鋁合金形成。例如，該鋁合金可以是約99.5%的鋁和0.5%的銅之合金，雖然其他鋁和銅合金以及其它材料也可能是合適的。
下列該金屬層310的應用，將在步驟104中的第二金屬層312沉積到該金屬層310上。再者，在某一較佳的實施例中，將該金屬層312濺射到該金屬層310上。在該說明的實施例中，該金屬層312完全覆蓋該金屬層310。該金屬層312作為一擴散阻擋層材料，其具有適合防止金屬離子通過金屬層312的擴散或遷移的材料特性和一厚度。例如，在某一實施例中該金屬層312的厚度是約0.8微米，雖然再者，較薄或較厚的金屬層可以是合適的和允許的。例如，一種作為金屬層312使用的合適材料是鎳和釩合金(NiV)。從下面的討論將較明瞭該金屬層312的目的。
在步驟106中，將第三焊料可濕性金屬層314沉積在該第二金屬層312上。較佳地，將該焊料可濕性金屬層314濺射在該金屬層312上，致使它完全覆蓋該金屬層312。一約0.3微米的焊料可濕性金屬層厚度已顯示為有效運作。較佳地，該焊料可濕性金屬層314由一可濕性的各種焊料材料(如錫和鉛)的材料形成。例如，在該說明的實施例中，該焊料可濕性金屬層314由銅形成。
一般情況下，用於所有上述金屬層310、312和314的適當厚度將取決於所用的材料以形成該個別的層。
在某一實施例中，在步驟108中將一光阻遮罩316沉積到該晶圓200的主動表面。在該說明的實施例中，將該光阻遮罩316圖案化，致使只藉該遮罩將該接合墊206和208覆蓋，如圖3C所示。然後在步驟110中蝕刻未藉該遮罩316所覆蓋的區域中的該金屬層310、312和314，如圖3D所示。然後在步驟112中將該遮罩316的殘留部分(即，覆蓋該等接合墊206和208的部分)移除。以這種方式，只有該等接合墊206和208仍然藉該等金屬層310、312和314覆蓋。這裡應當注意的是形成在每個內部接合墊206上的金屬層310、312和314的堆疊是作為一適合接受焊料並促進一與相關接觸連接的焊料接點的凸塊下金屬化堆疊(underbump metallurgy stack，UBM)318。因此，較佳地將UBM 318圖案化以便可看到上述該晶粒202的主動面204是循環的。
在步驟114中將第二光阻遮罩320沉積和圖案化在該晶圓的主動表面上，致使只有未藉該遮罩320覆蓋的周圍接合墊208，如圖3E所示。在步驟116中，然後將在該周圍接合墊208上金屬層312和314的部分蝕刻和移除。在 該實施例說明的圖3F中，少量的第一金屬層也可以移除以確保該等金屬層312和314完全自該接合墊208移除。例如，在某一實施例中，覆蓋在每個接合墊208的金屬層310的大約0.2微米蝕刻和移除。隨後，在步驟118中將該遮罩320的殘留部分自該晶圓的主動表面移除。
如圖4所示，該產生的晶圓200包括每個有一些內部接合墊206和一些周圍接合墊208的晶粒202，其中該內部接合墊206藉焊料可濕性UBM 318覆蓋並且每個周圍接合墊208有著適合作為線接合的表面。在步驟120中將焊料凸塊322沉積在該UBM堆疊318上，如圖3G所示。該焊料凸塊322可以任何適當的方式沉積，並且一般由錫(Sn)和鉛(Pb)的混合物組成。例如，該焊料凸塊可使用一針狀點膠劑以應用於該焊料膏的形式。焊料膏一般包括一焊料混合以及流量，從而進一步促進焊料漫延過該UBM 318的接合表面。
根據各種實施例，然後將一個或多個能表面安置的被動電子組件324定位於每個晶粒202的主動表面204上。被動是指該組件不是主動的，換言之，該被動元件無法功率增益。合適的被動元件324可包括，例如：電容器、電阻、電感器和晶體(諸如用於時機目的之石英)等等。將該被動元件324直接定位到每個晶粒202的表面，在安置到PCB之後的在晶粒及相關的外部元件之間的信號傳輸路徑可大大減少。如前所述，普遍渴望將至和從晶粒和外部元件和其他接觸的長度信號傳輸路徑最小化。習知地，被動元件定位在該PCB上的IC封裝的外側。然而，根據本發明的實施例，各種被動元件直接定位到該晶粒202(在封裝該晶粒之前)的表面以有效消除從該晶粒到該被動元件324幾乎整個傳輸路徑長度。在運作期間中，各種信號可經由在透過該周圍接合墊208的IC封裝的傳輸出之前在晶粒202的表面上的該被動元件的路徑傳輸，或者反過來說，在經該周圍接合墊到該晶粒的信號傳輸到該晶粒中的主動電路之前可透過該被動元件。
在該說明的實施例中，單一被動元件324定位在每個晶粒122的主動表面204上。尤其是，引線接觸326定位在對應的內部接合墊206上。在步驟124中，回焊該焊料凸塊322以形成焊料接點328，其將該被動元件324物理和電氣連接到各自的晶粒202。在某一實施例中，在回焊期間中，該焊料可濕性金屬層314擴散到該焊料接點。這是由於對在該焊料的錫而言在該金屬層314的銅的親和力所致。該金屬層314仍然緊黏到該焊料，並防止進一步擴散以及各自接合墊206的焊料接點328的分離。
在該說明實施例中雖然只有單一被動元件324定位上在每個晶粒202的主動表面上，應該注意的是，在其他實施例中，兩個或兩個以上被動元件可定位到每個晶粒的主動表面上。此外，該定位到每個晶粒的被動元件可以承擔各種各樣的形狀和大小。因此，基於一特定應用的要求，該接合墊206的佈局和結構可廣泛多個改變。
在步驟126中，然後該晶圓200可以單一化以產出個別的晶粒202。該晶圓200可以任何合適的方式單一化。舉例來說，該晶圓200可使用鋸子、鋼切割(鋸)、雷射切割或電漿切割沿該刻劃線203以單一化。
一用於封裝該晶粒202的製程500現在以參考圖5-7描述。每個經單一化的晶粒202可定位和接附在一合適基板的晶粒接附區中。例如，在該說明的實施例中，在步驟502中將每個晶粒202定位到一引線架面板上。
關於圖6A-C，根據將敘述的本發明不同的實施例，一適合用於封裝積體電路的示範引線架面板600。圖6A說明一以帶形式排列的引線架面板600的圖解上部圖。該引線架面板600可作為一有一些元件區的二維陣列602的金屬結構配置。例如，引線架面板600可以銅或一合適的銅合金形成。如較詳細的接續的圖6B所示，每個二維陣列602包含複數個元件區604、每個用於使用在單一IC封裝中的配置以及每個藉細微結合棒606的連接。
每個元件區域604包括一些引線608，每個藉該結合棒606在一末端支持。在該說明的實施例中，每個元件區域604包括16個引線608，其中從一晶粒黏接墊610的4個側邊之各者擴展到的四個引線(熟知此技藝的人士將認知到此配置是一典型的無引線引線架封裝(leadless leadframe package，LLP)配置)。該晶粒黏接墊610藉晶粒黏接墊支持棒612部分支持以從該晶粒黏接墊的角落擴展至接合棒606。每個引線608包括一在該引線架的頂部表面上的導電線接合表面614和一在該引線架的底部(背部)表面上的封裝接觸表面616。該引線608可蝕刻、半蝕刻或以相關該封裝接觸表面的其他方式薄化，以便提供電氣連接以在PCB上接觸，同時限制在該引線架的底部表面上的該曝露導電區域以及提供模塑鎖定特徵。在一些實施例中，也渴望以蝕刻或其他方式薄化引線架的頂部。此外，一膠帶可黏接到該引線架平面600的底部表面。在以模塑材料封膠該引線架平面600期間，此帶可能有助於提供用於引線架特徵的結構性支持和額外援助。
這將為熟知該技藝領域之人士所明瞭的，雖然已描述和說明一特定引線架平面600，該描述的方法可以適用於利用一極為廣泛的其他引線架平面或條配置以及其他基板封裝晶粒202，致使基板使用球柵陣列(ball-grid array，BGA)封裝配置。此外，雖然描述提到引線架平面600的頂部和底部表面，應明瞭到這上下文是單純意圖用於描述該結構並且沒有界定或限制相對的其他封裝組件的引線架之方向。
圖7A-C說明在製程500期間的各種步驟中該引線架平面600的某一元件區域604的圖解橫截面。在該實施例以圖7A說明之，通過一合適的晶粒黏接材料730的方式，例如，環氧樹脂或黏著膜，將該晶粒202物理地黏接在該晶粒黏接墊610。在實施例中不使用晶粒黏接墊於其中，每個晶粒202直接定位到該一黏著帶736。
在將該晶粒202黏接到引線架平面600之後，在步驟504中，在該晶粒的主動表面上的該周圍接合墊208電氣連接到藉金屬(如金)黏合線732的方式的引線608。應當注意的是，雖然本發明的觀點是特別適合用於利用接合線封裝晶粒，然而可以使用任何合適的電氣連接。
在步驟506中該黏接線732、晶粒202、被動元件324和部分引線架平面是以一模塑材料(複合物)734封膠。該模塑化合物通常是一具有較低的熱膨脹係數之非導電塑膠或樹脂。在一較佳的實施例中，以模塑將該整個植入的引線架平面600放置和封膠實質同時進行。在另一實施例中，可配置該模塑，致使每個二維陣列602作為單一單元封膠。但是，應明瞭到少數的晶粒202也可在任何一個時候封膠。還應理解，幾乎所有的模塑系統可用於封膠該黏接晶粒202和引線架平面600。例如，一膜輔助模塑(film assisted molding，FAM)系統可用於封膠該黏接晶粒202和被動元件324。該黏接膜防止模塑複合物入侵到該晶粒黏接墊610的背部表面和在該引線608的表面上的封裝接觸表面616。
後來，該模塑化合物734可在一加熱爐固化(例如，如果該模塑複合物是一種熱固性塑膠)並且該黏著帶736可移除。在固化模塑複合物734之後，可焊料電鍍該封裝接觸表面616以促進在一PCB或其他基板上對應接觸表面之連接。在一些實施例中，也焊料電鍍該晶粒黏接墊610的背部表面以促進至PCB的外部連接。
在步驟508中，然後可將該封膠引線架平面600單一化，以產生多種個別IC封裝738，如圖7C所示。再者，該封膠引線架平面600可以任何合適的方式單一化。例如，該引線架平面600可使用鋸子、鋼切割(鋸開)、雷射切割和電漿切割沿該結合棒606單一化以生產個別IC封裝738。經封裝單一化，在該IC封裝738黏接到PCB或其他基板之前可檢查及/或測試之。熟知該領域之技藝人士將認知到，所描述的方法可以用來生產無引線引線架封裝(leadless leadframe package，LLP)或四元平面封裝無引線(quad-flat-pack-no-lead，QFN)封裝。然而，許多其他封裝類型，例如，也可產生雙列直插式封裝(dual inline package，DIP)。
圖8A-C說明一替代實施例中該金屬層310、312和314沉積在一額外的鈍化層840上的步驟。圖8A說明一與圖3A所說明的該晶圓200相同的橫截面。如圖8B所示，在該替代實施例中，在沉積金屬層310、312和314之前，該額外的鈍化層840沉積在該晶圓200的主動表面上。例如，一苯環丁烯(benzocyclobutene，BCB)形成的鈍化層840可以分拆或以其他方式沉積和圖案化到環繞該接合墊206和208的區域中的該晶圓的主動表面上。在如圖8B所示的實施例中，沉積該鈍化層840，致使重疊和覆蓋每個接合墊206和208的周圍邊界。然後如以往將該金屬層310、312和314如圖8C所示沉積在該鈍化層840上。然後該製程可繼續在製程100中概述。
圖9A-F說明在還有另一實施例中。該製程如以往以如圖9A所示的一個合適的晶圓200開始。然而，在這替代實施例中，如圖9B所示的橫截面中，首先將一導電晶種層942沉積在該晶圓200的整個主動表面上。該晶種層942是用於一隨後的電鍍步驟。任何合適的材料可以用來形成該晶種層942。例如，在某一實施例中，該晶種層942由一鈦-銅-鈦層堆疊形成。然後一遮罩944沉積和圖案化在該晶圓的主動表面上，如圖9C所示，其環繞該接合墊206和208的區域。隨後，如圖9D所示，將該晶圓的主動表面電鍍以沉積一銅或其他合適金屬的導電層946在該接合墊206和208上。根據該特定的應用，該層946的厚度可以改變，但厚度範圍在大約5至15微米已被證明為有效運作的。應當注意的是，在一些應用中，該銅層946可有利圖案化，以便重新分配部分或全部的接合墊206和208。在部分或全部接合墊206或208將重新分配的實施例中，圖案化該遮罩致使該銅層946形成一從接合墊206及/或208至理想的分配地點之導電軌跡。例如，在說明圖9D的實施例中，圖案化該遮罩944致使允許一從一內部接合墊206延伸到重新分配接合墊位置950之銅軌跡部分948的沉積。
該遮罩944和部分的晶種層942沒有重疊在該接合墊206和208或該軌跡948，然後如圖9E所示將重新分配接合墊位置950移除。在該說明的實施例中，然後一BCB鈍化層952沉積在環繞該銅層946的區域中。在如圖9所示的實施例層中，該BCB鈍化層952延伸到該接合墊950的周圍部分，並且覆蓋該相關的軌跡948和接合墊206。
在該鈍化層952的沉積之後，然後該接合墊206(或如果重新分配時的接合墊950)的曝露表面可能會焊料電鍍。該銅層946的厚度是足夠的，致使只有一小部分的銅吸收到該焊料，因此防止由該接合墊206或950所致的焊料接點分離。在其他的實施例中，該製程可能會繼續圖1的製程100中所概要的。更具體地說，在這其他實施例中該金屬層310、312和314可沉積在該銅層946和鈍化層952上，而不是直接沉積在該接合墊206和208上，此種情況就如圖3A-H所示的實施例。
上述說明，用於解釋的目的，使用具體的術語以提供對本發明的深入了解。然而，將為熟知該技術人士所察知的是，並不需要該具體的細節以實踐本發明。因此，上述本發明的具體實施例的說明是用於呈現說明和描述的目的。他們不意圖擴大或限制本發明的確切揭露形式。這將為在該技術領域中具有通常知識者所察知的，在上述技術中許多修改和變化是有可能的。例如，在該晶圓單一化之後可將該被動元件安置到該晶粒的主動表面。此外，該金屬層310、312和314可自行用來重新分配部分或全部接合墊206和208。
為了最佳地解釋本發明的原則和它的實際應用，選擇和介紹該實施例，因此使其他熟知該領域的技術人士能充分以各種修改來利用本發明和各種實施例以適用於該特定用途的設想。其意味著，該發明的範圍是藉以下申請專利範圍和等效物所界定。
100．．．製程
102-126．．．製程100的步驟
200．．．晶圓
202．．．晶粒
203．．．刻劃線
204．．．主動表面
206．．．接合墊
208．．．接合墊
310．．．金屬層
312．．．金屬層
314．．．金屬層
316．．．遮罩
318．．．UBM
320．．．遮罩
322．．．焊料凸塊
324．．．被動組件
326．．．引線接觸
328．．．焊料接點
500．．．製程
502-508．．．製程500的步驟
600．．．引線架平面
602．．．二維陣列
604．．．元件陣列
606．．．結合棒
608．．．引線
610．．．晶粒黏接墊
612．．．晶粒黏接墊支持棒
614．．．導電線接合表面
616．．．封裝接觸表面
730．．．晶粒黏接材料
732．．．接合線
734．．．模塑化合物
736．．．膠帶
738．．．IC封裝
840．．．鈍化層
942．．．晶種層
944．．．遮罩
946．．．層
948．．．軌跡
950．．．接合墊
952．．．鈍化層
為了更好地理解本發明，應參照上述提及的詳細說明並採取相關聯的所附圖式，其中：
圖1是一按照本發明實施例說明一準備用於封裝的IC的製程之流程圖；
圖2說明一按照本發明實施例一適用的範例晶圓的圖解上視圖；
圖3A-H說明在圖1製程中的各種步驟之圖2晶圓的部分之圖解橫截側面視圖；
圖4說明一按照本發明的實施例在該被動元件接附之後的圖2的晶圓之圖解上視圖；
圖5是一個按照本發明的實施例說明一用於封裝IC晶粒的製程之流程圖；
圖6A-C說明一按照本發明的實施例的一適合用於封裝IC晶粒的引線架平面之圖解上視圖；
圖7A-C說明在圖5的製程中的各個步驟之IC晶粒的圖解橫截側面視圖；
圖8A-C說明按照本發明的替代實施例的圖2晶圓的部分之圖解橫斷截側面視圖；
圖9A-F說明按照本發明的替代實施例的圖2晶圓的部分之圖解橫斷截側面視圖。
相似的參考數字參照於整個圖式的對應部分。
100．．．製程
102-126．．．製程100的步驟

Claims (20)

  1. 一種封裝積體電路元件的方法，其包括：提供一積體電路晶圓，該晶圓包括多個積體電路晶粒，每個晶粒有一主動表面和一背部表面，該每個晶粒的主動表面包括一第一組接合墊和一第二組接合墊，該晶粒的背部表面結合形成該晶圓的背部表面；於該晶粒的主動表面上沉積第一導電層；於該第一導電層上沉積第二導電阻擋層；於該第二導電阻擋層上沉積第三焊料可濕性導電層；移除第一導電層、第二導電阻擋層和第三焊料可濕性導電層不位在每個晶粒的第一組接合墊或第二組接合墊上的部分；移除第二導電阻擋層和第三焊料可濕性導電層位在每個晶粒的第二組接合墊上的部分；於第三焊料可濕性導電層位在每個晶粒的第一組接合墊上的部分上沉積一層焊料；於該每個晶粒的主動表面上定位一非主動電氣組件，如此將自該非主動電氣元件的電極定位於沉積在該晶粒的多個第一組接合墊上的焊料附近；回焊該焊料以將非主動電氣組件的電極與多個第一組接合墊電氣和物理連接。
  2. 如申請專利範圍第1項之方法，進一步包括單一化該晶圓以提供多個個別積體電路晶粒，該晶粒各有物理和電氣連接到其主動表面之一非主動組件。
  3. 如申請專利範圍第2項之方法，進一步包括將多個第二組接合墊電氣連接到具有接合線的相關引線架之相關引線。
  4. 如申請專利範圍第1項之方法，其中，該非主動電氣組件是一被動組件，其選自於由一電容器、一電阻器和一電感器所組成之群組。
  5. 如申請專利範圍第1項之方法，其中，該非主動電氣組件是一用於計時目的之晶體。
  6. 如申請專利範圍第1項之方法，其中，每一個移除步驟包括在該晶粒的部分主動表面上沉積一遮罩和蝕刻未被該遮罩覆蓋部分的金屬層。
  7. 如申請專利範圍第1項之方法，其中，該第一導電層包括鋁或鋁合金。
  8. 如申請專利範圍第1項之方法，其中，該第二導電阻擋層包括一鎳和釩的合金。
  9. 如申請專利範圍第1項之方法，其中，該第三層包括銅或銅合金。
  10. 如申請專利範圍第1項之方法，其中，該第一組接合墊和該第二組接合墊以鋁或鋁合金形成。
  11. 如申請專利範圍第1項之方法，其中，每個接合墊是藉一鈍化層與所有其他接合墊水平分離。
  12. 如申請專利範圍第1項之方法，進一步包括在沉積該第一導電阻擋層之前，於該第一組接合墊的周圍邊緣及該第二組接合墊周圍邊緣上形成一鈍化層。
  13. 如申請專利範圍第12項之方法，其中，該鈍化層以苯環丁烯(benzocyclobutene，BCB)形成。
  14. 如申請專利範圍第1項之方法，進一步包括在每個晶粒的主動表面上定位第二非主動組件，並且將自第二非主動組件的電極與其他多個第一組接合墊物理和電氣連接。
  15. 如申請專利範圍第1項之方法，其中，於自第一組接合墊的每個接合墊上，該等第一導電層、該第二導電阻擋層和第三焊料可濕性導電層形成一凸塊下金屬化堆疊。
  16. 如申請專利範圍第1項之方法，進一步包括將具有第一導電層、第二導電阻擋層和第三焊料可濕性導電層的部分的多個第一組接合墊及/或第二組接合墊重新分配。
  17. 一種封裝積體電路元件的方法，其包括：提供一積體電路晶圓，該晶圓包括多個積體電路晶粒，每個晶粒有一主動表面和一背部表面，每個晶粒的主動表面包括第一組接合墊和第二組接合墊，該晶粒的背部表面結合形成該晶圓的背部表面；於該晶粒的主動表面上沉積第一導電晶種層；於該第一導電晶種層上沉積並圖案化一遮罩以致使該第一組接合墊和該第二組接合墊沒有被該遮罩所覆蓋；於第一導電晶種層未被該遮罩覆蓋的部分上沉積第二導電層；移除該遮罩； 於至少未被該第二導電層覆蓋的晶粒主動表面的部分上沉積一鈍化層；於第二導電層與每個晶粒的第一組接合墊電氣連接的部分上沉積一層焊料；於該每個晶粒的主動表面上定位一非主動電氣組件，致使將自該非主動電氣組件的電極定位於該焊料的附近；回焊該焊料以將該非主動電氣組件的電極與該多個第一組接合墊電氣和物理連接。
  18. 如申請專利範圍第17項之方法，其中，該第二導電層以銅形成，並且其中該第二導電層以一電鍍製程沉積。
  19. 如申請專利範圍第17項之方法，其中，該鈍化層以苯環丁烯(benzocyclobutene，BCB)形成。
  20. 如申請專利範圍第17項之方法，進一步包括將具有第二導電層之部分的多個第一組接合墊及/或第二組接合墊重新分配。
TW098118901A 2008-07-02 2009-06-06 用於具整合被動元件之積體電路封裝之方法與系統 TWI490958B (zh)

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