TWI487452B - Circuit board and manufacturing method thereof - Google Patents

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board having a large degree of freedom in circuit layout and a method of fabricating the same.

In recent years, with the rapid development of electronic technology, the high-tech electronics industry has come out one after another, making more humanized and better-functioning electronic products constantly innovating and designing towards light, thin, short and small trends. A circuit board having conductive lines is usually disposed in these electronic products.

For commonly known circuit boards, the manufacturing method is generally to form a first layer of conductor layers on both sides of the core layer. Then, the conductor layer is patterned to form a first wiring layer. Next, the dielectric layer and the second conductor layer are respectively laminated on both sides of the core layer by lamination, so that the dielectric laminate is bonded between the core layer and the second layer conductor layer. Then, openings are formed in the second conductor layer and the dielectric layer, respectively, to expose the first wiring layer. Next, an electroplating process is performed to plate copper in the opening to form a conductive via. Thereafter, the second layer of conductor layers is patterned to form a second wiring layer connected to the first circuit layer via the via holes on the dielectric layer. Of course, more layers of the circuit layer can be formed in the same manner depending on actual needs.

Since the above method symmetrically forms a plurality of wiring layers on both sides of the core layer, the manufactured wiring board has an even-numbered wiring layer. However, the above manufacturing methods often limit the layout of the circuit (circuit The degree of freedom of the layout, that is, the circuit board having the even-numbered circuit layers must be fabricated. Furthermore, in order to avoid the problem of warpage of the circuit board during the manufacturing process of the circuit board or during the assembly of the electronic component, the layout of the circuit on both sides of the core layer of the conventional circuit board and the thickness of the dielectric layer must be The use of symmetrical design, in this way, also limits the freedom of line layout design.

The present invention provides a circuit board having a large degree of freedom in line layout.

The invention provides a method for manufacturing a circuit board for fabricating the above circuit board.

The present invention provides a circuit board including a first dielectric layer, a first patterned metal foil layer, a first line pattern, at least one first conductive via, a stacked structure, a second dielectric layer, a second patterned metal foil layer, a second line pattern and at least one second conductive via. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned metal foil layer is disposed on the first surface of the first dielectric layer and exposes a portion of the first surface. The first line pattern is buried in the second surface of the first dielectric layer. The first conductive via is integrally formed with the first trace pattern, wherein one end of the first conductive via passes through the first dielectric layer to connect the first patterned metal foil layer, and the first conductive via and the first patterned metal foil layer There is an interface between them. The laminated structure is disposed on the second surface of the first dielectric layer and covers the first line pattern and the other end of the first conductive via. The laminated structure includes at least one internal connected structure and One less patterned conductor layer. The inner via structure electrically connects the first line pattern and the pattern conductor layer of the stacked structure away from the first line pattern. The second dielectric layer is disposed on the stacked structure. The second patterned metal foil layer is disposed on the second dielectric layer and exposes a portion of the second dielectric layer. The second line pattern is disposed on the second patterned metal foil layer and conformally disposed with the second patterned metal foil layer. The second conductive via is integrally formed with the second trace pattern, wherein one end of the second conductive via passes through the second dielectric layer to electrically connect the stacked structure, and the other end of the second conductive via is substantially cut from the second trace pattern Qi.

The present invention also provides a method of fabricating a circuit board comprising the following steps. Separating a first dielectric layer on a first metal foil layer and a second metal foil layer, wherein each of the first dielectric layers has a first surface and a second surface opposite to each other A glue layer bonds the first metal foil layer and the second metal foil layer. The glue layer is located at the periphery of the first metal foil layer and the second metal foil layer to form a closed space with the first metal foil layer and the second metal foil layer. Forming a hydrophobic film on the second surface of the first dielectric layer, respectively. Irradiating a first laser beam to the hydrophobic film to form a first intaglio pattern penetrating the hydrophobic film on the second surface of the first dielectric layer, and respectively forming at least one through the first dielectric layer The first through hole, wherein the first through hole exposes a portion of the first metal foil layer and a portion of the second metal foil layer, respectively. The hydrophobic film is subjected to an activation step and the hydrophobic film is removed after the activation step. Forming a first line pattern in the first intaglio pattern, and simultaneously forming at least one first conductive via in the first through hole. One end of the first conductive via is respectively connected to a portion of the first metal foil layer and a portion of the second metal foil layer exposed by the first through hole, and the first conductive via is respectively connected to the first metal foil layer and the second gold There is a first interface and a second interface between the foil layers. The hydrophobic film is removed to expose the second surface of the first dielectric layer, respectively. And laminating a laminated structure on the second surface of the first dielectric layer, wherein the laminated structure respectively covers the first line pattern and the other end of the first conductive via. Each of the stacked structures includes at least one inner communicating structure and at least one patterned conductor layer. The inner via structure electrically connects the first line pattern and the pattern conductor layer of the stacked structure away from the first line pattern. A second dielectric layer and a third metal foil layer on the second dielectric layer are respectively laminated on the laminated structure. The second dielectric beam is irradiated to the second dielectric beam to form at least one second through hole sequentially passing through the third metal foil layer and the second dielectric layer, wherein the second through holes respectively expose the partial stack Layer structure. Forming a conductive material in the second through hole and extending over the second dielectric layer. Separating the first metal foil layer and the second metal foil layer such that the laminated structure and the second dielectric layer, the third metal foil layer and the conductive material thereon are respectively located on the first metal foil layer and the second metal foil layer . Removing a portion of the first metal foil layer and a portion of the second metal foil layer to form a first patterned metal foil layer on the first surface of the first dielectric layer, respectively, and removing a portion of the third metal foil layer, And partially forming a second patterned metal foil layer and a second line pattern on the second dielectric layer to form at least one second conductive via in the second through hole. One end of the second conductive via is respectively connected to a portion of the stacked structure exposed by the second via, and the second conductive via is integrally formed with the second trace pattern.

Based on the above, the present invention uses a laser beam to irradiate a laser beam to form an intaglio pattern and a through hole, and then forms a line pattern in the intaglio pattern and forms a conductive hole in the through hole. Therefore, the circuit board of the present invention can have Fine lines with better reliability. Furthermore, since the present invention uses a coreless technology to form a wiring board, it has better production efficiency and is suitable for mass production. In addition, the circuit pattern (and fine lines) on the circuit board is not formed by the conventional method of pressing the conductive layer, so that the degree of freedom of the circuit board layout can be effectively improved.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1K are schematic cross-sectional views showing a method of fabricating a circuit board according to an embodiment of the present invention. For convenience of explanation, FIG. 1A(a) and FIG. 1A(b) respectively show a perspective view of the first metal foil layer and the second metal foil layer being adhered through the adhesive layer. Referring to FIG. 1A, in accordance with the method for fabricating a circuit board of the present embodiment, first, a first metal foil layer 110a and a second metal foil layer 110b are provided, wherein the first metal foil layer 110a is bonded by a glue layer 10. And the second metal foil layer 110b. Here, the glue layer 10 is located at the periphery of the first metal foil layer 110a and the second metal foil layer 110b to form a closed space R with the first metal foil layer 110a and the second metal foil layer 110b. For example, the adhesive layer 10 may have a continuous frame pattern (please refer to FIG. 1A(a)), and the continuous frame pattern and the first metal foil layer 110a and the second metal foil layer 110b surround the flat closed space. R. In this way, in the subsequent wet process (such as development, etching, cleaning, etc.), foreign objects (such as developer, etching solution, cleaning agent, etc.) are less likely to pass through the adhesive layer 10 into the closed space R, and thus to the first The metal foil layer 110a and the second foil layer 110b cause damage.

In the present embodiment, the material of the adhesive layer 10 is, for example, a solder resist ink, a chemical resistant tape or a pure gum material, and the width of the adhesive layer 10 is, for example, 12 mm. It should be noted that, in other embodiments, referring to FIG. 1A(b), the adhesive layer 10b may also be a discontinuous frame-shaped pattern, that is, a plurality of air guiding holes H are present in the discontinuous frame-shaped pattern ( At least 6 or more), wherein each of the air guiding holes H has a length of, for example, 10 mm to 15 mm, and a width of, for example, 1 mm to 3 mm. Further, the center line average roughness (Ra) and the ten point average roughness (Rz) of the first metal foil layer 110a and the second metal foil layer 110b are both larger than 3 μm. Among them, the definition of the roughness can be referred to the latest edition of the Japanese Industrial Standard JIS B 0601.

Next, referring to FIG. 1B, a first dielectric layer 120 is respectively laminated on the first metal foil layer 110a and the second metal foil layer 110b, wherein each of the first dielectric layers 120 has a first surface opposite to each other. 122 and a second surface 124, and the first metal foil layer 110a and the second metal foil layer 110b are respectively located on the first surface 122 of the first dielectric layer 120.

Next, referring to FIG. 1C, a hydrophobic film 20 is formed on the second surfaces 124 of the first dielectric layers 120, respectively. Here, the hydrophobic film 20 is a thermally polymerizable material and is an oligomerized polymer material. The hydrophobic film 20 may contain a plurality of polymerized monomers before aging, and a baking step is used to promote its low polymerization. After the polymerization, the hydrophobic film 20 may contain various polymer groups, such as an epoxy group modified by (artificial) rubber, an acrylic group, a quinone imine group, and a guanamine group, and the like. Containing auxiliaries, defoamers and wetting agents as needed. Therefore, after polymerization, the hydrophobic film 20 is an oligomerized copolymer. For example, the hydrophobic film 20 may be cured by a baking step of 70 ° C to 120 ° C for 30 minutes so that the hydrophobic film 20 has a thickness of 0.5 μm to 30 μm (micrometers). It should be noted that the maturation step of the hydrophobic film 20 does not involve photoinitiation polymerization. The hydrophobic film 20 is not patterned using a photo-image transfer method, so the hydrophobic film 20 is not a photoresist.

Next, referring to FIG. 1C and FIG. 1D, the hydrophobic film 20 is irradiated with a first laser beam L1 to form a first intaglio pattern C1 penetrating through the hydrophobic films 20 to the first dielectric layer 120, respectively. The second surfaces 124 are formed on the second surface 124 and form at least one first through hole T1 passing through the first dielectric layers 120, respectively. The first through holes T1 expose a portion of the first metal foil layer 110a and a portion of the second metal foil layer 110b, respectively. It should be noted that after the first laser beam L1 is irradiated to the hydrophobic film 20, residues may be left on the patterned hydrophobic film 20, which may hinder the subsequent formation of electrical connection quality. A pre-processing step is performed to remove the residue. The pretreatment step may use a plasma treatment, an organic solvent such as an alcohol, an ether, dimethyl hydrazine (DMSO) or nitrogen, nitrogen-dimethylformamide (DMF), etc., which can swell the pattern. The hydrophobic film 20 is an oxidizing agent such as sulfuric acid/hydrogen peroxide and permanganate. Therefore, the hydrophobic film 20 must be resistant to attack by an organic solvent or an oxidizing agent. In addition, an acid such as sulfuric acid or a weak base may also be used in the pretreatment step, so that the hydrophobic film 20 is also resistant to attack by acid or weak base.

Then, the hydrophobic film 20 is further subjected to an activation step, that is, seeding is performed. a step of forming a layer (not shown). Due to the material properties of the hydrophobic film 20, the seed layer is allowed to be formed in the first intaglio pattern C1, and the seed layer is allowed to cover the portion of the first dielectric layer 120 exposed by the first intaglio pattern C1. The two surfaces 124 are on the surface of the hydrophobic film 20. For example, the second surface 124 of the portion of the first dielectric layer 120 exposed by the first intaglio pattern C1 is immersed in a solution containing a noble metal, such as at least platinum, palladium, gold or rhodium, so that the formed crystal The seed layer completely covers the first intaglio pattern C1 and the second surface 124 of the portion of the first dielectric layer 120 exposed by the first intaglio pattern C1. Of course, the formed seed layer may also selectively cover only the first intaglio pattern C1 and the second surface of a portion of the first dielectric layer exposed by the first intaglio pattern C1.

Next, the hydrophobic film 20 is completely removed. Since a part of the seed layer (not shown) covers the hydrophobic film 20, when the hydrophobic film 20 is completely removed, the seed layer located on the portion of the hydrophobic film 20 is also removed. For example, chemical or physical methods can be used to remove the hydrophobic film 20. The chemical method may be to use an alkaline solution to remove the hydrophobic film 20. The alkaline solution can be a strong inorganic base such as sodium hydroxide. The alkaline solution may have a pH greater than 11, preferably between 11 and 13. The physical method can be responsible for or assist in removing the hydrophobic film 20. For example, physical methods include the use of brushing, grinding, plasma processing, and ultrasonics.

Next, referring to FIG. 1E, a first line pattern 130 is formed in the first recess patterns C1, and at least one first conductive via 140 is formed in the first through holes T1, respectively, wherein the seed layer ( Not shown) located in the first line pattern 130 and the first intaglio patterns C1, And located in the first line pattern 130 and the first through holes T1. In particular, one end of each of the first conductive vias 140 of the present embodiment is respectively connected to a portion of the first metal foil layer 110a and a portion of the second metal foil layer 110b exposed by the first through hole T1, and the first conductive vias 140 are respectively There is a first interface S1 and a second interface S2 between the first metal foil layer 110a and the second metal foil layer 110b. These hydrophobic films 20 are then removed to expose the second surfaces 124 of the first dielectric layers 120, respectively.

Next, referring to FIG. 1F, a stacked structure 150 is respectively pressed onto the second surfaces 124 of the first dielectric layers 120, wherein the stacked structures 150 respectively cover the first wiring patterns 130 and the first conductive layers. The other end of the tunnel 140. In detail, each of the stacked structures 150 of the present embodiment includes at least one insulating layer 152 (only three are schematically shown in FIG. 1F) and at least one patterned conductor layer 154 (only three are schematically illustrated in FIG. 1F). And at least one inner communication structure 156 extending through the insulating layer 152 (only three are schematically shown in FIG. 1F). The insulating layer 152 and the pattern conductor layers 154 are sequentially stacked on the first wiring pattern 130, and the pattern conductor layers 154 are buried in the plurality of third surfaces 152a of the insulating layers 152, respectively. Here, the inner communication structures 156 are integrally formed with the pattern conductor layers 154, and one end of the inner communication structure 156 closest to the first line pattern 130 passes through the corresponding insulation layer 152 to connect the first line patterns 130. In addition, the orthographic projections of the inner via structures 156 across the adjacent two of the insulating layers 152 on the first line pattern 130 do not overlap, and the other ends of the inner via structures 156 are substantially lower than the insulating layers 152, respectively. The third surface 152a. Of course, in an embodiment, please refer to the circuit board 100e of FIG. 5A. The orthographic projections of the inner communication structures 156 respectively passing through the adjacent two of the insulating layers 152 on the first line pattern 130 overlap. That is, the stacked form of the inner communication structures 156 of the wiring board 100e is a vertical stacked hole design. Furthermore, in another embodiment, the other ends of the inner communicating structures 156 can also substantially align the third surfaces 152a of the insulating layers 152, respectively, and are not limited thereto.

It should be noted that, in this embodiment, the step of forming each of the stacked structures 150 is performed, for example, by repeating at least once (here, three times) to form the hydrophobic films 20 (refer to the steps of FIG. 1C). The first indentation pattern C1 and the first through holes T1 (please refer to the step of FIG. 1D), the formation of the first line patterns 130 and the first conductive vias 140, and the steps of removing the hydrophobic films 20 (please refer to the figure) Step 1E). Here, the number of the insulating layer 152, the pattern conductor layer 154 and the inner communicating structure 156 of the laminated structure 150 is not limited, and the hydrophobic film 20 can be repeatedly formed and formed in accordance with the use requirement, and the first concaves are formed. The pattern C1 and the first through holes T1 are formed, and the first wiring patterns 130 and the first conductive vias 140 are formed and the hydrophobic film 20 is removed.

Next, referring to FIG. 1G, a second dielectric layer 160 and a third metal foil layer 170a on the second dielectric layer 160 are respectively laminated on the stacked structures 150. Here, the second dielectric layer 160 covers the third surface 152a of the insulating layer 152 relatively far from the first line patterns 130, the pattern conductor layer 154, and the other end of the inner communication structure 156.

Next, referring to FIG. 1H, these third metal foil layers 170a are performed. These third metal foil layers 170a' are formed by copper etching to improve the ease of the laser through holes. Then, the second dielectric layer 160 is irradiated with a second laser beam L2 to form at least one second through hole T2 sequentially passing through the third metal foil layer 170a' and the second dielectric layer 160, The second through holes T2 respectively expose a part of the laminated structures 150. Next, a sub-layer 175a is formed on the third metal foil layers 170a' and the second through holes T2, respectively. Wherein, the thickness of each of the third metal foil layers 170a' plus each seed layer 175a is approximately equal to the thickness of the first metal foil layer 110a or the thickness of the second metal foil layer 110b.

Next, referring to FIG. 1I, a plating step is performed to plate a conductive material 180a into the second through holes T2 and extend over the seed layers 175a. Next, a copper reduction etching is performed to form a conductive material 180a', the seed layers 175a', and the third metal foil layers 170a", wherein the thickness of the conductive material 180a' plus the thickness of the seed layers 175a' and the third The thickness of the metal foil layer 170a" may be approximately equal to the thickness of the first metal foil layer 110a or the second metal foil layer 110b. That is, the overall thickness of the conductive material 180a', the seed layers 175a', and the third metal foil layers 170a" may be thinned to be close to the thickness of the first metal foil layer 110a or the second metal foil layer 110b.

Of course, referring to FIG. 1I', when performing copper reduction etching, it is also possible to leave only a portion of the conductive material 180' located in the second through holes T2, the seed layers 175a', and the third metal foil layers 170a". The thickness of each of the third metal foil layers 170a" plus each seed layer 175a' is approximately equal to the thickness of the first metal foil layer 110a or the thickness of the second metal foil layer 110b. Alternatively, please refer to FIG. 1I". When performing copper reduction etching, it is also possible to leave only a portion of the conductive material 180' located in the second through holes T2 and the third metal foil layers 170", and each of the third The thickness of the metal foil layer 170a" is approximately equal to the thickness of the first metal foil layer 110a or the thickness of the second metal foil layer 110b.

Next, referring to FIG. 1I and FIG. 1J, the first metal foil layer 110a and the second metal foil layer 110b are separated to form the 150 structures 150 and the second dielectric layers 160 thereon, and the third metal. The foil layer 170a" and the conductive material 175a' are respectively located on the first metal foil layer 110a and the second metal foil layer 110b. There are many ways to separate the first metal foil layer 110a and the second metal foil layer 110b. In this embodiment, the glue layer 10 and a portion of the first metal foil layer partially overlapping the glue layer 10 may be cut along the plurality of cutting lines Y by, for example, a computer numerical control (CNC) milling technique. 110a, second metal foil layer 110b, these first dielectric layers 120, these stacked structures 150, these second dielectric layers 160, these third metal foil layers 170a" and these seed layers 175a', making the first The metal foil layer 110a is separated from the second metal foil layer 110b.

Hereinafter, the first dielectric layer 120, the first wiring pattern 130, the first conductive via 140, the stacked structure 150, the second dielectric layer 160, and the third metal are sequentially stacked on the first metal foil layer 110a and above. The foil layer 170a", the seed layer 175a' and the conductive material 180a' are exemplified. Then, a patterned photoresist layer 30 is formed on the conductive material 180a' and the first metal foil layer 110a, wherein the patterned photoresist The layer 30 exposes a portion of the conductive material 180a' and the first metal foil layer 110a, respectively.

Thereafter, referring to FIG. 1K, the patterned photoresist layer 30 is an etching mask, and a portion of the conductive material 180a' exposed to the patterned photoresist layer 30 and the seed layer 175a' and the third metal underneath are patterned. a second patterned metal foil layer 170 and a patterned seed layer 175 and a second line pattern 180 are formed on the second dielectric layer 160, and a portion of the first metal foil layer 110a. Forming at least one second conductive via 190 connecting the second trace pattern 180 in the second via hole T2, and forming a first patterned metal foil layer 110 on the first surface 122 of the first dielectric layer 120. One end of the second conductive via 190 is connected to a portion of the stacked structure 150 exposed by the second through hole T2. The second conductive via 190 is integrally formed with the second trace pattern 180, and the other end of the second conductive via 190 and the second trace are formed. The pattern 180 is substantially aligned. Finally, the patterned photoresist layer 30 is removed, and the fabrication of the wiring board 100a of the present embodiment is completed.

Referring to FIG. 1K , the circuit board 100 a of the present embodiment includes a first patterned metal foil layer 110 , a first dielectric layer 120 , a first line pattern 130 , a first conductive via 140 , and a stacked structure 150 . a second dielectric layer 160, a second patterned metal foil layer 170, a patterned seed layer 175, a second line pattern 180, and a second conductive via 190. The first dielectric layer 120 has a first surface 122 and a second surface 124 opposite to each other, wherein the first patterned metal foil layer 110 is disposed on the first surface 122 of the first dielectric layer 120 to expose a portion of the first surface 122. The first line pattern 130 is buried in the second surface 124 of the first dielectric layer 120. The first conductive via 140 is integrally formed with the first trace pattern 130, wherein one end of the first conductive via 140 passes through the first dielectric layer 120 to connect the first patterned metal foil layer 130, and the first conductive via 140 and the first conductive via 140 Between the patterned metal foil layers 110 Interface S1. The stacked structure 150 is disposed on the second surface 124 of the first dielectric layer 120 and covers the second surface 124, the first line pattern 130 and the other end of the first conductive via 140. The laminated structure 150 includes the insulating layers 152 sequentially stacked, the patterned conductor layers 154, and the inner via structures 156 respectively penetrating the insulating layer 152. The insulating layers 152 are interleaved with the pattern conductor layers 154 on the first wiring patterns 130, and the pattern conductor layers 154 are respectively buried in the third surfaces 152a of the insulating layers 152, and the internal via structures 156 are respectively The pattern conductor layer 154 is integrally formed. One end of the inner communication structure 156 closest to the first line pattern 130 passes through the corresponding insulating layer 152 to connect the first line patterns 130, and the other ends of the inner communication structures 156 may be substantially lower than or aligned with the insulating layers 152. These third surfaces 152a. A first top surface 156a of each inner communication structure 156 is not flush with a second top surface 154a of each patterned conductor layer 154, and a portion of the first top surface 156a is lower than the second top surface 154a. The second dielectric layer 160 is disposed on the stacked structure 150. The second patterned metal foil layer 170 is disposed on the second dielectric layer 160 and exposes a portion of the second dielectric layer 160. The second line pattern 180 is disposed on the second patterned metal foil layer 170 and conformally disposed with the second patterned metal foil layer 170. The patterned seed layer 175 is disposed between the second patterned metal foil layer 170 and the second wiring pattern 180, and between the second dielectric layer 160 and the patterned conductor layer 154 of the outermost layer of the stacked structure 150. The second conductive via 190 is integrally formed with the second trace pattern 180, wherein one end of the second conductive via 190 passes through the second dielectric layer 160 to connect the stacked structure 150, and the second conductive via 190 is integrated with the second trace pattern 180. Forming.

Hereinafter, the circuit board 100b will be separately described in different embodiments. Production of 100c, 100d. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

2A-2C are cross-sectional views showing a partial step of a method of fabricating a circuit board according to another embodiment of the present invention. The manufacturing method of the circuit board 100b of the present embodiment is similar to that of the circuit board 100a of the previous embodiment, but the main difference between the two is that after the step of FIG. 1H, the seed layers 175a' are formed separately. After the third metal foil layer 170a" and the second through holes T2, please refer to FIG. 2A, respectively forming a first patterned photoresist layer 40 on the seed layers 175a'. Among them, the first patterned lights The resist layer 40 exposes a portion of the seed layers 175a', respectively, wherein the first patterned photoresist layers 40 expose portions of the seed layers 175a', respectively.

Next, referring to FIG. 2A and FIG. 2B, the first patterned photoresist layer 40 is a plating mask to respectively plate a plating material 182a on the seed layers 175a'. Then, the first patterned photoresist layer 40 is removed, and the adhesive layer 10 and the first metal foil layer 110a partially overlapping the adhesive layer 10 are cut along a plurality of cutting lines Y by, for example, a CNC milling technique. a second metal foil layer 110b, the first dielectric layer 120, the stacked structures 150, the second dielectric layers 160, the third metal foil layers 170a" and the seed layers 175a', and the first metal foil layer 110a is separated from the second metal foil layer 110b. Next, a second patterned photoresist layer 50 is formed on the first metal foil layer. On 110a.

Thereafter, referring to FIG. 2B and FIG. 2C, a portion of the seed layer 175a' not covered by the plating material 182a and a portion of the third metal foil layer 170a" below it are removed, and a second dielectric layer 160 is formed on the second dielectric layer 160. a second patterned metal foil layer 170, a second line pattern 182 and at least one second conductive via 190, and between the second patterned metal foil layer 170 and the second line pattern 182 and the second dielectric layer 160 A patterned seed layer 175 between the second conductive vias 190, wherein the second trace pattern 182 is connected to the second conductive via 190, and the second trace 182 is integrally formed with the second conductive via 190. Meanwhile, the second pattern is patterned. The photoresist layer 50 is an etching mask, and a portion of the first metal foil layer 110a exposed outside the second patterned photoresist layer 50 is etched to form a first pattern on the first surface 122 of the first dielectric layer 120. The metal foil layer 110. At this time, the first patterned metal foil layer 130 and the first conductive via 140 have an interface S1. Thus, the fabrication of the wiring board 100b has been completed.

Of course, the processes illustrated in FIGS. 2A-2C are for illustrative purposes only, and some of the steps are common techniques in current circuit board processes. Those skilled in the art can adjust the sequence of steps according to actual conditions, omit or add possible steps to meet the process requirements, and will not be described one by one here.

3A-3I are cross-sectional views showing a partial step of a method of fabricating a circuit board according to another embodiment of the present invention. The manufacturing method of the circuit board 100c of the present embodiment is similar to that of the circuit board 100a of the previous embodiment, but the main difference between the two is that after the step of FIG. 1E, the hydrophobic film 20 is removed to be exposed separately. After these second surfaces 124 of the first dielectric layer 120 are formed, please refer to FIG. 3A, respectively, and press one The insulating layer 152c and a fourth metal foil layer 153c on the insulating layer 152c are on the second surface 124 of the first dielectric layer 110. Here, the thickness of the fourth metal foil layer 153c is between 2 micrometers and 5 micrometers. It should be noted that the purpose of using the ultra-thin metal foil layer (ie, the fourth metal foil layer 153c) here is to reduce the time for subsequent etching (refer to the step of FIG. 3D), and the side etching effect can be effectively reduced.

Next, referring to FIG. 3B, the fourth metal foil layer 153c is respectively irradiated with a third laser beam L3 to form at least one third through hole T3 sequentially passing through the fourth metal foil layer and the insulating layer 152c. The third through holes T3 expose a portion of the first line patterns 130.

Next, referring to FIG. 3B, a sub-layer 155c is formed on the fourth metal foil layer 153c and the third through holes T3, respectively, and a patterned photoresist layer 60 is formed on the seed layers 155c.

Next, referring to FIG. 3C, the patterned photoresist layer 60 is a plating mask to respectively plate a pattern conductor layer 154c and at least one internal communication structure 156c on the seed layers 155c. The inner communication structures 156c are correspondingly located in the third through holes T3, and the pattern conductor layers 154c are respectively connected to the inner communication structures 156c.

Next, referring to FIG. 3D, the first patterned photoresist layer 60 and a portion thereof are removed from the seed layer 155c and the fourth metal foil layer 153c. The method of removing a portion of the seed layer 155c and the fourth metal foil layer 153c under the first patterned photoresist layer 60 is, for example, an etching method. At this time, the other ends of the inner communicating structures 156c are substantially higher than a third surface 151 of the insulating layers 152c, respectively, and the patterned conductor layers 154c protrude from these third surfaces 151 of these insulating layers 152c, respectively.

Next, referring to FIG. 3E, the steps of FIG. 3A to FIG. 3D may be repeated at least once (here, three times) to form a stack of the second surfaces 124 respectively pressed onto the first dielectric layers 120. The layer structure 150c, wherein the stacked structures 150c cover the first line patterns 130 and the other ends of the first conductive vias 140, respectively. Here, the number of the insulating layer 152c, the pattern conductor layer 154c, and the inner communicating structure 156c of the laminated structure 150c is not limited, and the number of steps of the steps of FIGS. 3A to 3D may be sequentially increased or decreased according to the use requirements. Here, the orthographic projections of the inner communication structures 156c passing through the adjacent two insulating layers 152c on the first line patterns 130 respectively overlap. Of course, in other embodiments, please refer to the circuit board 100f of FIG. 5B, wherein the orthographic projections of the inner communication structures 156c passing through the adjacent two of the insulating layers 152c on the first line patterns 130 do not overlap.

Furthermore, the manner in which the partial insulating layer 152c, the pattern conductor layer 154c, and the inner via structure 156c in the laminated structure 150c can be formed by using the steps as shown in FIG. 1C to FIG. 1E, that is, forming the hydrophobic film 20 and forming The first recess pattern C1 and the first through holes T1 form the first line patterns 130 and the first conductive vias 140 and the steps of removing the hydrophobic films 20. In short, the present embodiment does not limit the types and layers of the insulating layers 152, 152c, the pattern conductor layers 154, 154c and the inner connecting structures 156, 156c, and those skilled in the art can refer to the foregoing embodiments. The description, according to the actual needs, and the above-mentioned process method is selected to achieve the desired technical effect.

Next, referring to FIG. 3E, a second dielectric layer 160 and a third metal foil layer 170a on the second dielectric layer 160 are respectively laminated on the stacked structures 150c. Here, the second dielectric layer 160 covers the third surface 151 of the insulating layer 152c relatively far from the first line patterns 130, the pattern conductor layer 154c, and the other end of the inner communication structure 156c.

Next, referring to FIG. 3F, the second dielectric layer 160 is irradiated with a second laser beam L2 to form at least one second through hole T2 passing through the second dielectric layers 160, respectively. The holes T2 expose a portion of these laminated structures 150c, respectively. Next, a sub-layer 175a is formed on the third metal foil layers 170a and the second through holes T2, respectively. In other embodiments, the third metal foil layer 170a' is also subjected to copper reduction etching prior to the step of Fig. 3F, with the purpose of improving the ease of the laser via. Moreover, each third metal foil layer may also be formed after the second laser beam L2 is irradiated and the seed layer 175a' is formed on the third metal foil layer 170a' and the second through holes T2. The thickness of 170a' plus the thickness of each seed layer 175a' is approximately equal to the thickness of the first metal foil layer 110a or the thickness of the second metal foil layer 110b, please refer to FIG. 3F'.

Next, referring to FIG. 3G, a plating step is performed to plate a conductive material 180a into the second through holes T2 and extend over the seed layers 175a. Next, referring to FIG. 3G', a copper reduction etching may be performed to form a conductive material 180a', the seed layers 175a', and the third metal foil layers 170a', wherein the thickness of the conductive material 180a' plus the seed layers 175a' The thickness and thickness of these third metal foil layers 170a' may be approximately equal to the thickness of the first metal foil layer 110a or the second metal foil layer 110b. Also That is, the overall thickness of the conductive material 180a', the seed layers 175a', and the third metal foil layers 170a' may be thinned to be close to the thickness of the first metal foil layer 110a or the second metal foil layer 110b.

Next, please refer to FIG. 3G′ and FIG. 3H simultaneously, separating the first metal foil layer 110a and the second metal foil layer 110b, wherein the adhesive layer 10 and the portion can be cut along a plurality of cutting lines Y by, for example, a CNC milling technique. a first metal foil layer 110a, a second metal foil layer 110b, the first dielectric layer 120, the stacked structures 150c, the second dielectric layers 160, and the third metal foil layers 170a' overlapping the adhesive layer 10. The seed layer 175a' and the conductive material 180a' separate the first metal foil layer 110a from the second metal foil layer 110b.

Hereinafter, the first dielectric layer 120, the first wiring pattern 130, the first conductive via 140, the stacked structure 150c, the second dielectric layer 160, and the third metal are sequentially stacked on the first metal foil layer 110a and above. The foil layer 170a', the seed layer 175a', and the conductive material 180a' are exemplified. Next, a patterned photoresist layer 30 is formed on the conductive material 180a' and the first metal foil layer 110a, respectively, wherein the patterned photoresist layer 30 exposes a portion of the conductive material 180a' and the first metal foil layer 110a, respectively.

Thereafter, referring to FIG. 3I, the patterned photoresist layer 30 is an etching mask, and a portion of the conductive material 180a' exposed to the patterned photoresist layer 30 and the seed layer 175a' and the third metal underneath are patterned. a second patterned metal foil layer 170 and a patterned seed layer 175 and a second line pattern 180 are formed on the second dielectric layer 160, and a portion of the first metal foil layer 110a is formed on the second dielectric layer 160. Forming at least one second conductive via 190 connecting the second wiring pattern 180 in the second through hole T2, and the first dielectric layer 120 The first surface 122 forms a first patterned metal foil layer 110. Here, one end of the second conductive via 190 is connected to a portion of the stacked structure 150c exposed by the second through hole T2, the second conductive via 190 is integrally formed with the second wiring pattern 180, and the other end of the second conductive via 190 is The second line pattern 180 is substantially aligned. Finally, the patterned photoresist layer 30 is removed, and the fabrication of the wiring board 100c of the present embodiment is completed.

Referring to FIG. 3I, the circuit board 100c of the embodiment includes a first patterned metal foil layer 110, a first dielectric layer 120, a first circuit pattern 130, a first conductive via 140, and a stacked structure 150c. a second dielectric layer 160, a second patterned metal foil layer 170, a patterned seed layer 175, a second line pattern 180, and a second conductive via 190. The first dielectric layer 120 has a first surface 122 and a second surface 124 opposite to each other, wherein the first patterned metal foil layer 110 is disposed on the first surface 122 of the first dielectric layer 120 to expose a portion of the first surface 122. The first line pattern 130 is buried in the second surface 124 of the first dielectric layer 120. The first conductive via 140 is integrally formed with the first trace pattern 130 disposed above the first conductive via 140, wherein one end of the first conductive via 140 passes through the first dielectric layer 120 to connect the first patterned metal foil layer 110, The first conductive via 140 has a first interface S1 between the first patterned metal foil layer 110 and the first patterned metal foil layer 110. The stacked structure 150c is disposed on the second surface 124 of the first dielectric layer 120 and covers the second surface 124, the first line pattern 130 and the other end of the first conductive via 140. The laminated structure 150c includes the insulating layers 152c, the fourth metal foil layers 153c, the seed layers 155c, the pattern conductor layers 154c, and the inner connecting structures respectively penetrating the insulating layer 152c. 156c. The insulating layer 152c, the fourth metal foil layer 153c, the seed layers 155c, and the pattern conductor layers 154c are sequentially interleaved on the first wiring pattern 130, and the pattern conductor layers 154c protrude from the insulating layers 152c, respectively. These third surfaces 151. These inner communicating structures 156c are integrally formed with the pattern conductor layers 154c, respectively. One end of the inner communication structure 156c closest to the first line pattern 130 passes through the corresponding insulating layer 152c to connect the first line patterns 130, and the other ends of the inner communication structures 156c may substantially protrude from the first of the insulating layers 152c. Three surfaces 151. The second dielectric layer 160 is disposed on the stacked structure 150c. The second patterned metal foil layer 170 is disposed on the second dielectric layer 160 and exposes a portion of the second dielectric layer 160. The second line pattern 180 is disposed on the second patterned metal foil layer 170 and conformally disposed with the second patterned metal foil layer 170. The patterned seed layer 175 is disposed between the second patterned metal foil layer 170 and the second wiring pattern 180, and between the second dielectric layer 160 and the patterned conductor layer 154c of the outermost layer of the stacked structure 150c. The second conductive via 190 is integrally formed with the second trace pattern 180, wherein one end of the second conductive via 190 passes through the second dielectric layer 160 to connect the stacked structure 150c, and the second conductive via 190 is integrated with the second trace pattern 180. Forming.

4A-4C are cross-sectional views showing a partial step of a method of fabricating a circuit board according to another embodiment of the present invention. The manufacturing method of the circuit board 100d of the present embodiment is similar to the manufacturing method of the circuit board 100c of the foregoing embodiment, but the main difference between the two is that after the step of FIG. 3F, the seed layer 175a is formed separately. After the three metal foil layers 170a and the second through holes T2, please refer to FIG. 4A, respectively. A first patterned photoresist layer 40 is on the seed layers 175a. Wherein, the first patterned photoresist layers 40 respectively expose a portion of the seed layers 175a. Here, before the first patterned photoresist layer 40 is formed, a copper reduction etching is performed so that the thickness of each seed layer 175a' plus the thickness of the third metal foil layer 170a' under it is approximately equal to the first The thickness of the metal foil layer 110a. Of course, the third metal foil layer 170a' may be subjected to copper-reduction etching before the seed layer 175a' is formed, and the order of copper-reduction etching is not limited herein.

Next, referring to FIG. 4A and FIG. 4B, the first patterned photoresist layer 40 is a plating mask to respectively plate a plating material 184d on the seed layers 175a. Then, the first patterned photoresist layer 40 is removed, and the adhesive layer 10 and the first metal foil layer 110a partially overlapping the adhesive layer 10 are cut along a plurality of cutting lines Y by, for example, a CNC milling technique. a second metal foil layer 110b, the first dielectric layer 120, the stacked structures 150c, the second dielectric layers 160, the third metal foil layers 170a', the seed layers 175a' and the plating material 184d, A metal foil layer 110a is separated from the second metal foil layer 110b. Next, a second patterned photoresist layer 50 is formed on the first metal foil layer 110a.

Thereafter, referring to FIG. 4B and FIG. 4C, a portion of the seed layer 175a' not covered by the plating material 184d and a portion of the third metal foil layer 170a" below it are removed, and a second dielectric layer 160 is formed on the second dielectric layer 160. a second patterned metal foil layer 170, a second wiring pattern 184 and at least one second conductive via 190, and between the second patterned metal foil layer 170 and the second wiring pattern 184 and the second dielectric layer 160 a pattern between the second conductive vias 190 The seed layer 175 is formed, wherein the second circuit pattern 184 is connected to the second conductive via 190, and the second trace 184 is integrally formed with the second conductive via 190. At the same time, the second patterned photoresist layer 50 is used as an etching mask to etch a portion of the first metal foil layer 110a exposed outside the second patterned photoresist layer 50, and on the first surface of the first dielectric layer 120. A first patterned metal foil layer 110 is formed over 122. At this time, the first patterned metal foil layer 130 and the first conductive via 140 have an interface S1. So far, the production of the circuit board 100d has been completed.

Of course, the processes illustrated in FIGS. 4A-4C are for illustrative purposes only, and some of the steps are common techniques in current circuit board processes. Those skilled in the art can adjust the sequence of steps according to actual conditions, omit or add possible steps to meet the process requirements, and will not be described one by one here.

In summary, the present invention uses a laser beam to irradiate a laser beam to form an intaglio pattern and a through hole, and then forms a line pattern in the intaglio pattern and forms a conductive hole in the through hole. Therefore, the wiring board of the present invention can have a fine line of better reliability. Furthermore, since the present invention uses a coreless technology to form a wiring board, it has better production efficiency and is suitable for mass production. In addition, the circuit pattern (and fine lines) on the circuit board is not formed by the conventional method of pressing the conductive layer, so that the degree of freedom of the circuit board layout can be effectively improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10, 10b‧‧‧ glue layer

20‧‧‧hydrophobic film

30, 60‧‧‧ patterned photoresist layer

40‧‧‧First patterned photoresist layer

50‧‧‧Second patterned photoresist layer

100a, 100b, 100c, 100d, 100e, 100f‧‧‧ circuit boards

110‧‧‧First patterned metal foil layer

110a‧‧‧First metal foil layer

110b‧‧‧Second metal foil layer

120‧‧‧ dielectric layer

122‧‧‧ first surface

124‧‧‧ second surface

130‧‧‧First line pattern

140‧‧‧First conductive tunnel

150‧‧‧Laminated structure

151, 152a‧‧‧ third surface

152, 152c‧‧‧ insulation

153c‧‧‧Four metal foil layer

154, 154c‧‧‧ patterned conductor layer

154a‧‧‧Second top

155c‧‧‧ seed layer

156, 156c‧‧‧ connected structure

156a‧‧‧First top surface

160‧‧‧Second dielectric layer

170‧‧‧Second patterned metal foil layer

170a, 170a’, 170a”‧‧‧ Third metal foil layer

175‧‧‧ patterned seed layer

175a, 175a’‧‧‧ seed layer

180, 182, 184‧‧‧ second line pattern

180a, 180a’‧‧‧ conductive materials

182a, 184d‧‧‧ plating materials

190‧‧‧Second conductive tunnel

C1‧‧‧ Intaglio pattern

H‧‧‧ air vent

L1‧‧‧first laser beam

L2‧‧‧second laser beam

L3‧‧‧third laser beam

S1‧‧‧ first interface

S2‧‧‧ second interface

T1‧‧‧ first through hole

T2‧‧‧ second through hole

T3‧‧‧Second hole

R‧‧‧closed space

Y‧‧‧ cutting line

1A to 1K are schematic cross-sectional views showing a method of fabricating a circuit board according to an embodiment of the present invention.

2A-2C are cross-sectional views showing a partial step of a method of fabricating a circuit board according to another embodiment of the present invention.

3A-3I are cross-sectional views showing a partial step of a method of fabricating a circuit board according to another embodiment of the present invention.

4A-4C are cross-sectional views showing a partial step of a method of fabricating a circuit board according to another embodiment of the present invention.

5A is a cross-sectional view of a circuit board according to an embodiment of the present invention.

FIG. 5B is a cross-sectional view showing a circuit board according to another embodiment of the present invention.

100a‧‧‧ circuit board

110‧‧‧First patterned metal foil layer

120‧‧‧ dielectric layer

122‧‧‧ first surface

124‧‧‧ second surface

130‧‧‧First line pattern

140‧‧‧First conductive tunnel

150‧‧‧Laminated structure

152‧‧‧Insulation

152a‧‧‧ third surface

154‧‧‧patterned conductor layer

156‧‧‧Internal connected structure

160‧‧‧Second dielectric layer

170‧‧‧Second patterned metal foil layer

175‧‧‧ patterned seed layer

180‧‧‧second line pattern

190‧‧‧Second conductive tunnel

T2‧‧‧ second through hole

S1‧‧‧ first interface

Claims (13)

A method of manufacturing a circuit board, comprising: pressing a first dielectric layer on a first metal foil layer and a second metal foil layer, wherein each of the first dielectric layers has a first surface opposite to each other And a second surface, and the first metal foil layer and the second metal foil layer are bonded by a glue layer, wherein the glue layer is located at a periphery of the first metal foil layer and the second metal foil layer to Forming a closed space between the first metal foil layer and the second metal foil layer; forming a thermal polymerizable hydrophobic film on the second surfaces of the first dielectric layers; a laser beam to form a first indentation pattern penetrating the hydrophobic films on the second surfaces of the first dielectric layers, and respectively forming through the first dielectric layers At least one first through hole, wherein the first through holes respectively expose a portion of the first metal foil layer and a portion of the second metal foil layer; performing an activation step on the hydrophobic films and moving back after the activation step In addition to the hydrophobic films; respectively forming a first line pattern for the And forming at least one first conductive via in the first through hole, wherein one end of the first conductive vias respectively connect the exposed portions of the first vias to the first a metal foil layer and a portion of the second metal foil layer, and the first conductive vias respectively have a first interface and a second interface between the first metal foil layer and the second metal foil layer; respectively a second layer of the second dielectric layer On the surface, the stacked structures respectively cover the first circuit patterns and the other ends of the first conductive vias, wherein each of the stacked structures includes at least one interconnecting structure and at least one patterned conductor layer, and the inner layer The communication structure electrically connects the first line pattern and the layered structure away from the pattern conductor layer of the first line pattern, a first top surface of the inner communication structure and a second top surface of the pattern conductor layer are not Flush, and a portion of the first top surface is lower than the second top surface; respectively pressing a second dielectric layer and a third metal foil layer on the second dielectric layer The second dielectric layer is irradiated with a second laser beam to sequentially form at least one second through hole through the third metal foil layer and the second dielectric layers, respectively. The second through holes respectively expose a portion of the stacked structures; forming a conductive material in the second through holes and extending over the second dielectric layers; separating the first metal foil layer and the a second metal foil layer such that the stacked structures and the second layers thereof a layer, the third metal foil layer and the conductive material are respectively located on the first metal foil layer and the second metal foil layer; and removing a portion of the first metal foil layer and a portion of the second metal foil layer to Forming a first patterned metal foil layer on the first surfaces of the first dielectric layers, respectively, and removing a portion of the third metal foil layer and a portion of the conductive material to form a second pattern respectively Forming a metal foil layer and a second line pattern on the second dielectric layers, and forming at least one second conductive via in the second via holes, wherein one ends of the second conductive vias respectively And connecting the portions of the stacked structures exposed by the second through holes, and the second conductive holes are integrally formed with the second circuit patterns. The method for fabricating a circuit board according to claim 1, wherein each of the laminated structures further comprises at least one insulating layer, the inner connecting structure penetrating the insulating layer, and the insulating layer and the patterned conductor layer are sequentially stacked On the first line pattern, the pattern conductor layer is embedded or protruded from a third surface of the insulating layer, and the inner communication structure is integrally formed with the pattern conductor layer, and one end of the inner communication structure passes through the An insulating layer is connected to the first line pattern. The method for fabricating a circuit board according to claim 2, wherein the at least one insulating layer comprises a plurality of insulating layers, and the at least one interconnecting structure comprises a plurality of interconnecting structures respectively penetrating the adjacent two of the insulating layers The orthographic projections of the inner communication structures on the first line patterns overlap. The method for fabricating a circuit board according to claim 2, wherein the at least one insulating layer comprises a plurality of insulating layers, and the at least one interconnecting structure comprises a plurality of interconnecting structures respectively penetrating the adjacent two of the insulating layers The orthographic projections of the inner connecting structures on the first line patterns do not overlap. The method of fabricating a circuit board according to claim 2, wherein the other end of the inner communication structure is substantially higher, lower than or tangential to the third surface of the insulating layer. The method for fabricating a circuit board according to claim 1, wherein the step of forming the laminated structures comprises: sequentially forming the hydrophobic films at least once, and irradiating the first lasers with the hydrophobic films. Forming the first intaglio patterns by the light beam, The hydrophobic film performs the activation step, and after the activating step, the hydrophobic film is removed to form the first line patterns and the first conductive vias. The method for fabricating a circuit board according to claim 1, wherein the step of forming each of the laminated structures comprises: repeating steps (a)-(f) at least sequentially, the steps are: (a) Pressing an insulating layer and a fourth metal foil layer on the insulating layer on the second surface of the first dielectric layer; (b) irradiating the fourth metal foil layer with a third laser beam, Forming at least one third through hole through the insulating layer, wherein the third through hole exposes a portion of the first line pattern; (c) forming a sublayer on the fourth metal foil layer and the third through (d) forming a patterned photoresist layer on the seed layer; (e) using the patterned photoresist layer as a plating mask to plate a patterned conductor layer and at least one interconnecting structure for the seeds a layer, wherein the pattern conductor layer is connected to the inner via structure, and the pattern conductor layer is integrally formed with the inner via structure; and (f) removing the patterned photoresist layer and a portion thereof, the seed layer and a portion thereof The fourth metal foil layer. The method for manufacturing the circuit board according to the first aspect of the invention, further comprising: after forming the second through holes, respectively forming a sub-layer on the third metal foil layers and the second through holes Inside; Performing a plating step of plating the conductive material into the second through holes and extending over the seed layers; performing a first copper reduction etching step to increase the thickness of each of the third metal foil layers The thickness of each of the seed layers and the thickness of the conductive material are less than or equal to the thickness of the first metal foil layer or the thickness of the second metal foil layer; after separating the first metal foil layer and the second metal foil layer, Forming a patterned photoresist layer on the conductive material and the first metal foil layer respectively; using the patterned photoresist layer as an etching mask, etching a portion exposed to the patterned photoresist layer to conduct the conductive a material and a seed layer thereof and the third metal foil layer and a portion of the first metal foil layer, and the second patterned metal foil layer and a patterned seed thereon are formed on the second dielectric layer a layer and the second line pattern, forming the second conductive via connecting the second line pattern in the second via hole, and forming the first patterned metal foil on the first surface of the first dielectric layer a layer; and removing the patterned photoresist layer. The method for fabricating a circuit board according to claim 8, further comprising: performing a second copper-reduction etching step before forming the seed layers or after forming the seed layers, so that the seed layers are The thickness plus the thickness of each of the third metal foil layers is less than or equal to the thickness of the first metal foil layer or the thickness of the second metal foil layer. The method for manufacturing the circuit board according to the first aspect of the patent application includes: After forming the second through holes, respectively forming a sub-layer on the second dielectric layers and the second through holes; performing a copper reduction etching step to increase the thickness of each of the seed layers The thickness of the third metal foil layer is less than or equal to the thickness of the first metal foil layer or the thickness of the second metal foil layer; forming a first patterned photoresist layer on the seed layer, respectively; The photoresist layer is a plating mask to respectively plate a plating material on the seed layers; before separating the first metal foil layer and the second metal foil layer, removing the first patterned photoresist layer; After separating the first metal foil layer and the second metal foil layer, forming a second patterned photoresist layer on the first metal foil layer; removing portions of the seed layer not covered by the plating material And a portion of the third metal foil layer and the lower portion of the second dielectric layer, the second patterned metal foil layer, the second circuit patterns and the second conductive vias, and Between the second patterned metal foil layer and the second line patterns and a plurality of patterned seed layers between the second dielectric layer and the second conductive vias, wherein the second trace patterns are connected to the second conductive vias; and the second patterned photoresist layer is an etch mask And etching a portion of the first metal foil layer exposed outside the second patterned photoresist layer, and forming the first patterned metal foil layer on the first surface of the first dielectric layer. The method for fabricating a circuit board according to claim 10, wherein the step of performing the copper reduction etching is before forming the seed layers or It is after the formation of the seed layers. The method for manufacturing a circuit board according to claim 1, wherein the adhesive layer has a continuous frame shape. The method for fabricating a circuit board according to claim 1, wherein the adhesive layer has a discontinuous frame shape.