TWI484639B - Thin film transistor - Google Patents

Description

Thin film transistor

The present invention relates to a thin film transistor and a method of manufacturing the thin film transistor, and a display device using the same.

As a field effect transistor, it is known that a channel formation region in a thin film transistor is located in a semiconductor layer which is formed on a substrate having an insulating surface. Techniques for using amorphous germanium, microcrystalline germanium, and polycrystalline germanium for a semiconductor layer in a thin film transistor have been disclosed (see Patent Documents 1 to 5). A typical application of a thin film transistor is a liquid crystal television device, and a thin film transistor is used as a switching transistor for a pixel constituting a display screen.

[reference]

[Patent Literature]

[Patent Document 1] Japanese Laid-Open Patent Application No. 2001-053283

[Patent Document 2] Japanese Laid Open Patent Application No. H5-129608

[Patent Document 3] Japanese Laid-Open Patent Application No. 2005-049832

[Patent Document 4] Japanese Laid Open Patent Application No. H7-131030

[Patent Document 5] Japanese Laid-Open Patent Application No. 2005-191546

A thin film transistor in which a channel is formed using an amorphous germanium layer has problems such as low field-effect mobility and small on-current. On the other hand, a thin film transistor using a microcrystalline germanium layer to form a channel has a large off current and thus cannot obtain sufficient although its field effect mobility is higher than that of a thin film transistor using an amorphous germanium layer forming channel. The problem of switching characteristics.

A thin film transistor using a polysilicon layer in a channel formation region is characterized by having a much higher field effect mobility and a large on current than the above two thin film transistors. Because of this characteristic, the thin film transistor can be used not only as a switching transistor but also as a driving circuit requiring high speed operation.

However, a thin film transistor formed using a polycrystalline germanium layer requires a crystallization treatment of a semiconductor layer, which has a problem of higher manufacturing cost than a thin film transistor formed using a non-antimony layer. For example, the laser annealing technique included in the process of forming a polycrystalline germanium layer has a problem that a large screen liquid crystal panel cannot be efficiently manufactured because the irradiation area of the laser light is small.

The glass substrate for manufacturing a liquid crystal panel grows in size as follows: 3rd generation (550mm × 650mm), 3.5th generation (600mm × 720mm or 620mm × 750mm), 4th generation (680mm × 880mm or 730mm × 920mm), 5th generation (1100mm × 1300mm), 6th generation (1500mm × 1850mm), 7th generation (1870mm × 2200mm), and 8th generation (2200mm × 2400mm). From now on, the size of the glass substrate is expected to grow to the ninth generation (2400 mm × 2800 mm or 2450 mm × 3050 mm) and the 10th generation (2950 mm × 3400 mm). The increase in the size of the glass substrate is based on the concept of minimizing cost design.

However, the technology for manufacturing a thin film transistor which can be operated at a high speed on a large-sized mother glass substrate such as the 10th generation (2950 mm × 3400 mm) at a high capacity has not yet been established, which is an industrial problem.

Accordingly, it is an object of embodiments of the present invention to provide a high throughput manufacturing method for a thin film transistor having good electrical characteristics.

According to an embodiment of the invention, a thin film transistor includes a gate insulating layer covering a gate electrode; a semiconductor layer in contact with the gate insulating layer; and an impurity semiconductor layer in contact with a portion of the semiconductor layer and forming a source region and a drain region. The semiconductor layer includes a microcrystalline semiconductor layer formed on the gate insulating layer side and a nitrogen-containing microcrystalline semiconductor region contacting the microcrystalline semiconductor layer.

According to another embodiment of the present invention, a thin film transistor includes a gate insulating layer covering a gate electrode; a semiconductor layer in contact with the gate insulating layer; and an impurity semiconductor layer in contact with a portion of the semiconductor layer and forming a source region and a drain region. The semiconductor layer includes a microcrystalline semiconductor layer formed on the gate insulating layer side and a nitrogen-containing microcrystalline semiconductor region contacting the microcrystalline semiconductor layer, and a nitrogen-containing amorphous semiconductor region contacting the microcrystalline semiconductor region.

The side view of the nitrogen concentration of the semiconductor layer obtained by SIMS increases from the gate insulating layer to the impurity semiconductor layer to a maximum value and then decreases. Alternatively, the nitrogen concentration of the semiconductor layer obtained by SIMS is increased from the gate insulating layer to the impurity semiconductor layer to a maximum value and then substantially constant. Alternatively, the side view of the nitrogen concentration obtained by SIMS has a maximum value in the semiconductor layer. The maximum value at this time is in the range of 1 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , more preferably in the range of 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ¹ atoms / cm ³ .

According to another embodiment of the present invention, a thin film transistor includes a gate insulating layer; a microcrystalline semiconductor layer in contact with the gate insulating layer; a mixed layer in contact with the microcrystalline semiconductor layer; and a layer containing the amorphous semiconductor in contact with the mixed layer and A source region and a drain region in contact with a layer containing an amorphous semiconductor. The mixed layer and the layer containing the amorphous semiconductor each contain nitrogen.

According to another embodiment of the present invention, a thin film transistor includes a gate insulating layer; a microcrystalline semiconductor layer in contact with the gate insulating layer; a mixed layer in contact with the microcrystalline semiconductor layer; and a layer containing an amorphous semiconductor in contact with the mixed layer; a source region and a drain region in contact with a layer containing an amorphous semiconductor. The side view of the nitrogen concentration obtained by SIMS has a peak concentration in the mixed layer.

The peak concentration of the nitrogen concentration side view is in the range of 1 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , more preferably 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ range between. The mixed layer includes an amorphous semiconductor region and a microcrystalline semiconductor region. Here, the microcrystalline semiconductor region comprises semiconductor crystal grains and/or conical or square pyramidal crystal regions having a diameter of between 1 nm and 10 nm.

Further, the mixed layer and the layer containing the amorphous semiconductor each contain a nitrogen, NH group or NH ₂ group.

In addition, in the mixed layer and the layer containing the amorphous semiconductor, the semiconductor atom between the interface between the adjacent microcrystalline semiconductor region (that is, the grain boundary) and the interface between the microcrystalline semiconductor region and the amorphous semiconductor region is suspended. The key is cross-coupled with the NH group, so the number of defects is reduced to form a path for transporting carriers. Alternatively, the dangling bonds terminate in the NH ₂ group and thus the number of defects is reduced.

As a result, in the thin film transistor, when a voltage is applied to the source and the drain electrode, the resistance between the gate insulating layer and the source and drain regions is lowered, thereby increasing the on-current and field-effect mobility of the thin film transistor. The layer containing the amorphous semiconductor is formed using a well-ordered semiconductor layer having less defects and located at the edge of the valence band energy band which is steep. Therefore, the band gap becomes wider, and the channel current does not easily flow. Therefore, by providing a layer containing an amorphous semiconductor on the back channel side, the off current of the thin film transistor can be lowered.

Here, unless the method of measuring the concentration is mentioned, the concentration is measured by a secondary ion mass spectrometer (SIMS).

It should be noted that the on current refers to the current flowing between the source electrode and the drain electrode when the thin film transistor is turned on. For example, taking an n-channel thin film transistor as an example, the on-current refers to a current flowing between the source electrode and the drain electrode when the gate voltage of the thin film transistor is higher than the threshold voltage.

In addition, the off current refers to the current flowing between the source electrode and the drain electrode when the thin film transistor is turned off. For example, taking an n-channel thin film transistor as an example, the off current refers to a current flowing between the source electrode and the drain electrode when the thin film transistor gate voltage is lower than the threshold voltage.

As described above, a thin film transistor having a small off current and a large on current can be manufactured with high productivity.

The embodiments will be described in detail below with reference to the drawings. It is to be understood that the invention is not limited by the following description, and that the mode and details may be modified in various ways without departing from the spirit and scope of the invention. Therefore, the disclosure of the present invention should not be construed as being limited to the following embodiments. It is to be noted that the same or similar functional portions are denoted by the same reference numerals in the drawings, and will not be described again.

(Example 1)

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing an embodiment of a thin film transistor. The thin film transistor shown in FIG. 1 includes a gate electrode 103 on a substrate 101, a semiconductor layer 115 on the gate insulating layer 105, and an impurity semiconductor as a source region and a drain region contacting the upper surface of the portion of the semiconductor layer 115. A layer 127, and a wiring 125 contacting the impurity semiconductor layer 127. The semiconductor layer 115 includes a microcrystalline semiconductor layer 115a, a mixed layer 115b, and a layer 129c containing an amorphous semiconductor, which are sequentially stacked on the gate insulating layer 105.

A high heat resistant glass substrate, a ceramic substrate, a plastic substrate or the like which is sufficient to withstand the process temperature in the process can be used as the substrate 101. In this example, the substrate does not require optical transmission characteristics, and a metal substrate having an insulating layer on its surface, such as a stainless steel alloy substrate, can be used. As the glass substrate, for example, bismuth borate, aluminum borosilicate glass, aluminosilicate glass or the like, an alkali-free glass substrate can be used. Further, the glass substrate 101 may use a glass substrate having any of the following dimensions: 3rd generation (550 mm × 650 mm), 3.5th generation (600 mm × 720 mm or 620 mm × 750 mm), 4th generation (680 mm × 880 mm or 730 mm × 920 mm) , 5th generation (1100mm × 1300mm), 6th generation (1500mm × 1850mm), 7th generation (1870mm × 2200mm), 8th generation (2200mm × 2400mm), 9th generation (2400mm × 2800mm or 2450mm × 3050mm) The 10th generation (2950mm × 3400mm).

The gate electrode 103 may be formed in a single layer or a stacked layer using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, tantalum or niobium or an alloy material containing any of these materials as its main part. Alternatively, a semiconductor layer which is typically doped with a polycrystalline germanium doped with an impurity such as phosphorus, or an AgPdCu alloy may be used.

A two-layer structure for the gate electrode 103, a two-layer structure in which a molybdenum layer is stacked on an aluminum layer, a two-layer structure in which a molybdenum layer is stacked on a copper layer, and a titanium nitride layer or a tantalum nitride layer are stacked on a copper layer. The upper double layer structure or the double layer structure in which the titanium nitride layer and the molybdenum layer are stacked are preferable. The three-layer structure for the gate electrode 103 is preferably a tungsten layer or a tungsten nitride layer, an alloy of aluminum and tantalum or an alloy layer of aluminum and titanium, and a titanium nitride or titanium layer. When a metal layer as a barrier layer is stacked on a layer having low resistance, the resistance is low and diffusion of a metal element from the metal layer to the semiconductor layer can be prevented.

In order to improve the adhesion between the gate electrode 103 and the substrate 101, a nitride layer containing any of the above metal elements may be provided between the substrate 101 and the gate electrode 103.

The gate insulating layer 105 may be formed of a single layer or a laminate by any one of a ruthenium oxide layer, a tantalum nitride layer, a hafnium oxynitride layer, and a hafnium oxide layer by a CVD method, a sputtering method, or the like.

In this specification, bismuth oxynitride contains more oxygen than nitrogen. In this case, it is measured by Raspford backscattering analysis (RBS) and hydrogen forward scattering analysis (HFS). The oxygen and nitrogen contained in bismuth oxynitride. Preferably, helium and hydrogen are 50 at.% to 70 at.%, 0.5 at.% to 15 at.%, 25 at.% to 35 at.%, and 0.1 at.% to 10 at.%, respectively. Moreover, niobium oxynitride contains more nitrogen than oxygen, in this case by RBS and HFS, and niobium oxynitride contains oxygen, nitrogen, helium and hydrogen preferably 5 at.% to 30 at.%, respectively. 20at.% to 55at.%, 25 at.% to 35 at.%, and 10at.% to 30 at.%. Note that the percentage of oxygen, nitrogen, helium and hydrogen falls within the above range, and the total number of atoms contained in the ruthenium oxynitride or niobium oxynitride is defined at 100 at.%.

2A and 2B show the structure of the semiconductor layer 115, respectively. 2A and 2B are enlarged views of portions from the gate insulating layer 105 to the impurity semiconductor layer 127 as the source region and the drain region in Fig. 1, respectively.

As shown in FIG. 2A, in the semiconductor layer 115, a microcrystalline semiconductor layer 115a, a mixed layer 115b, and a layer 129c containing an amorphous semiconductor are stacked.

The microcrystalline semiconductor contained in the microcrystalline semiconductor layer 115a is a semiconductor having a crystal structure (including single crystal and polycrystalline). A microcrystalline semiconductor is a semiconductor having a third state, a crystalline semiconductor which is stable in terms of free energy and has a small range of order, and a lattice deformed in a columnar crystal or a tapered crystal which is positively grown on the surface of the substrate. For example, it is between 2 nm and 200 nm, preferably between 10 nm and 80 nm, and more preferably between 20 nm and 50 nm. Thus, in some instances, the grain boundaries are formed in the interface of columnar crystals or cone or cube-shaped crystals.

A typical example of a microcrystalline semiconductor is microcrystalline germanium, whose peak shifts in Raman Spectrum to a lower value than 520 cm ^{-1 which} represents a single crystal germanium. That is, the peak value of the microcrystalline germanium in the Raman spectrum is between 520 cm ^-1 representing a single crystal germanium and 480 cm ^-1 representing an amorphous germanium. The microcrystalline semiconductor may contain at least 1 at.% hydrogen or halogen to terminate the dangling bonds. Moreover, a rare gas element such as helium, neon, argon, krypton or xenon may be contained to promote lattice deformation, and the stability of the minute crystal may be enhanced to obtain a favorable microcrystalline semiconductor. Such a description of microcrystalline semiconductors can be found, for example, in U.S. Patent No. 4,409,134.

The concentration of oxygen and nitrogen measured by the secondary ion mass spectrometer in the microcrystalline semiconductor layer 115a is set to be less than 1 × 10 ¹⁸ atoms/cm ³ , which is preferable because the crystallinity of the microcrystalline semiconductor layer 115a is improved. .

The mixed layer 115b and the layer 129c containing an amorphous semiconductor each contain nitrogen. The mixed layer 115b contains nitrogen in a concentration of from 1 × 10 ²⁰ atoms/cm ³ to 1 × 10 ²¹ atoms/cm ³ , preferably from 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / Cm ³ .

As shown in FIG. 2A, the mixed layer 115b includes a microcrystalline semiconductor region 108a and an amorphous semiconductor region 108b filled between the microcrystalline semiconductor regions 108a. Specifically, the mixed layer 115b includes a microcrystalline semiconductor region 108a that is projected from the microcrystalline semiconductor layer 115a in a projecting manner, and an amorphous semiconductor region 108b that includes a semiconductor of the same type as the layer 129c containing the amorphous semiconductor. The straight dashed line between the microcrystalline semiconductor layer 115a and the mixed layer 115b and the straight dashed line between the mixed layer 115b and the layer 129c containing the amorphous semiconductor each represent an interface between the two layers; however, in the practical example, the micro The interface between the crystalline semiconductor layer 115a and the mixed layer 115b and the interface between the mixed layer 115b and the layer 129c containing the amorphous semiconductor are not determined.

The microcrystalline semiconductor region 108a includes a microcrystalline semiconductor having a conical or square pyramid shape or a projection shape, and its tail end is narrowed from the gate insulating layer 105 to the layer 129c containing an amorphous semiconductor. Note that the microcrystalline semiconductor region 108a may also include a microcrystalline semiconductor having a conical or square pyramidal shape or a projection shape, the width of which increases from the gate insulating layer 105 to the layer 129c containing the amorphous semiconductor.

Further, in some examples, a semiconductor crystal having a diameter of from 1 nm to 10 nm, preferably from 1 nm to 5 nm, is used as a microcrystalline semiconductor region in the amorphous semiconductor region 108b of the mixed layer 115b.

Alternatively, as shown in FIG. 2B, in some examples, the mixed layer 115b includes a microcrystalline semiconductor region 108c and a sequentially formed microcrystalline semiconductor region 108a. The microcrystalline semiconductor region 108c having a uniform thickness is located on the microcrystalline semiconductor layer 115a, and the microcrystalline semiconductor region 108a has a shape of a cone or a square pyramid or a projection, and its tail end is changed from the gate insulating layer 105 to the layer 129c containing the amorphous semiconductor. narrow.

As shown in FIG. 2A, the microcrystalline semiconductor region 108a included in the mixed layer 115b is continuously formed of the microcrystalline semiconductor layer 115a. Further, as shown in FIG. 2B, the microcrystalline semiconductor region 108c included in the mixed layer 115b is continuously formed from the microcrystalline semiconductor layer 115a.

Further, the amorphous semiconductor region 108b included in the mixed layer 115b contains semiconductor characteristics substantially the same as those of the amorphous semiconductor-containing layer 129c.

According to the above description, the interface between the region formed using the microcrystalline semiconductor and the region formed using the amorphous semiconductor may correspond to the interface between the microcrystalline semiconductor region 108a and the amorphous semiconductor region 108b in the mixed layer; The cross-sectional boundary between the microcrystalline semiconductor region and the amorphous semiconductor region can be described as uneven or jagged.

In this example, the microcrystalline semiconductor region 108a includes a projected semiconductor die whose tail end is narrowed from the gate insulating layer 105 to the amorphous semiconductor containing layer 129c. The proportion of the microcrystalline semiconductor region in the mixed layer 115b is higher in a region closer to the microcrystalline semiconductor layer 115a than in a region close to the layer 129c containing the amorphous semiconductor. The reason is as follows. The microcrystalline semiconductor region 108a is formed to have a film thickness from the surface direction of the microcrystalline semiconductor layer 115a. The microcrystalline semiconductor film is formed by adding a gas containing nitrogen to the source gas, or by adding a gas containing nitrogen to the source gas and reducing the flow rate of hydrogen to decane from the conditions. The growth of the semiconductor crystal grains in the microcrystalline semiconductor region 108a is suppressed, the semiconductor crystal grains become a microcrystalline semiconductor region of a cone or a square pyramid, and the amorphous semiconductor is gradually deposited. This is because the solubility of nitrogen in the microcrystalline semiconductor region is less than the solubility of nitrogen in the amorphous semiconductor region.

To reduce the off current of the thin film transistor, the total thickness of the microcrystalline semiconductor layer 115a and the mixed layer 115b, that is, from the interface between the microcrystalline semiconductor layer 115a and the gate insulating layer 105 to the mixed layer 115b can be projected ( The distance of the tip end of the projection portion is set to be from 3 nm to 80 nm, preferably from 5 nm to 50 nm.

The layer 129c containing an amorphous semiconductor contains nitrogen and is a semiconductor having substantially the same characteristics as the amorphous semiconductor region 108b included in the mixed layer 115b. Moreover, the layer 129c containing an amorphous semiconductor may include a semiconductor crystal having a diameter of from 1 nm to 10 nm, preferably from 1 nm to 5 nm. The layer 129c containing the amorphous semiconductor is a semiconductor layer, and is measured by a CPM (Constant photocurrent method) or a photoluminescence spectroscopy to have a smaller energy at the edge of the Urbach than the conventional amorphous semiconductor layer. Has a small amount of defect absorption spectrum. That is, the layer 129c containing the amorphous semiconductor is a well-ordered semiconductor layer which has less defects than the conventional amorphous semiconductor layer and the energy-end tail at the edge of the valence band is steep. Since the energy-thin tail at the edge of the valence band energy band in the layer 129c containing the amorphous semiconductor is steep, the band gap is wide and the channel current is less likely to flow. Therefore, by providing the layer 129c containing the amorphous semiconductor on the back channel side, the off current of the thin film transistor can be lowered. Further, by providing the layer 129c containing an amorphous semiconductor, the on-current and field-effect mobility of the thin film transistor can be increased.

It is to be noted that the amorphous semiconductor included in the layer 129c containing an amorphous semiconductor is typically amorphous germanium.

Further, the mixed layer 115b and the layer 129c including the amorphous semiconductor may each include a NH group or a NH ₂ group as a typical example of nitrogen.

As shown in FIG. 3, the mixed layer 115b is interposed between the microcrystalline semiconductor layer 115a and the impurity semiconductor layer 127, and the layer 129c containing the amorphous semiconductor is not interposed between the mixed layer 115b and the impurity semiconductor layer 127. The mixed layer 115b includes a microcrystalline semiconductor region 108a and an amorphous semiconductor region 108b filled in the space of the microcrystalline semiconductor region 108a. Specifically, the mixed layer 115b includes a microcrystalline semiconductor region 108a and an amorphous semiconductor region 108b extending from the microcrystalline semiconductor layer 115a in a projected manner. As shown in the structure of Fig. 3, it is preferable that the ratio of the microcrystalline semiconductor region 108a in the mixed layer 115b is low. More preferably, the proportion of the microcrystalline semiconductor region 108a in the mixed layer 115b is low in a region between the pair of impurity semiconductor layers 127, that is, a carrier flow region. As a result, the off current of the thin film transistor can be lowered. Further, in the mixed layer 115b, the electric resistance in the vertical direction (film thickness direction), that is, the resistance between the semiconductor layer and the source or the drain region can be lowered, and the on-current and field effect migration of the thin film transistor The rate can be increased.

It should be noted that the mixed layer 115b in FIG. 3 may also include the microcrystalline semiconductor region 108c as shown in FIG. 2B.

Alternatively, as shown in FIG. 4A, the standard amorphous semiconductor layer 129d is interposed between the layer 129c containing the amorphous semiconductor and the impurity semiconductor layer 127. Further, the standard amorphous semiconductor layer 129d may be interposed between the mixed layer 115b and the impurity semiconductor layer 127 as shown in FIG. 4B. With such a structure, the off current of the thin film transistor can be lowered.

It should be noted that the mixed layer 115b in FIGS. 4A and 4B may also include the microcrystalline semiconductor region 108c as shown in FIG. 2B.

The concentration of the impurity element in the semiconductor layer 115 of the thin film transistor in the present embodiment, particularly the concentration of nitrogen and hydrogen measured by SIMS, will be described with reference to FIGS. 5, 6, and 7.

Fig. 5 is a side view showing the secondary ion intensity of ruthenium, and the concentration of hydrogen, nitrogen, oxygen, carbon and fluorine measured by SIMS in the depth direction of the gate insulating layer 105 and the semiconductor layer 115 formed on the substrate. Specifically, the secondary ion intensity and hydrogen and nitrogen of the gate insulating layer 105 and the germanium constituting the microcrystalline semiconductor layer 115a of the semiconductor layer 115 shown in FIG. 1, the mixed layer 115b, and the layer 129c containing the amorphous semiconductor are shown. Side view of the distribution concentration of oxygen, carbon and fluorine.

In this embodiment, SIMS profile measurement is performed by using a PHI ADEPT-1010 quadrupole SIMS instrument manufactured by ULVAC-PHI. In combination with the primary Cs ⁺ beam of 1.0 keV, the primary Cs ⁺ beam radiation of 1.0 keV begins with the surface of layer 129c containing the amorphous semiconductor.

The horizontal axis represents the depth. The layer 129c containing an amorphous semiconductor is formed at a portion from a depth of 200 nm to a depth of 235 nm, the mixed layer 115b is formed at a portion from a depth of 235 nm to a depth of 255 nm, and the microcrystalline semiconductor layer 115a is formed at a portion from a depth of 255 nm to a depth of 260 nm, and the gate insulating layer 105 It is formed in a portion from a depth of 260 nm to a depth of 300 nm.

The vertical axis on the left side represents the concentration of hydrogen, nitrogen, oxygen, carbon and fluorine, and the right vertical axis represents the secondary ion intensity of ruthenium. It should be noted that the concentration of hydrogen, nitrogen, oxygen, carbon and fluorine is measured on the semiconductor layer 115, and thus the gate insulating layer is not accurate. Further, the precise concentration of the interface between the gate insulating layer 105 and the microcrystalline semiconductor layer 115a is not shown.

The nitrogen concentration side view has an increased concentration from the microcrystalline semiconductor layer 115a to the mixed layer 115b. In the mixed layer 115b, the concentration continuously increases from the microcrystalline semiconductor layer 115a and then gradually decreases. In other words, the concentration has a peak (maximum value) in the mixed layer 115b. The nitrogen concentration at this time is from 1 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , preferably from 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ .

The nitrogen concentration is a constant value in the layer 129c containing the amorphous semiconductor. The side view of the nitrogen concentration in the microcrystalline semiconductor layer 115a and the gate insulating layer 105 has a self-microcrystalline semiconductor layer 115a to the gate insulating layer 105 due to the effect of the knockback effect, the surface roughness, and the nitrogen remaining in the SIMS measuring device. One tail. However, the actual nitrogen concentration in the microcrystalline semiconductor layer 115a and the gate insulating layer 105 is lower than that shown in FIG.

The side view of the hydrogen concentration increases from the interface mixed layer 115b interposed between the microcrystalline semiconductor layer 115a and the mixed layer 115b. The hydrogen concentration is substantially constant in the layer 129c containing the amorphous semiconductor. The peak hydrogen concentration at the interface between the gate insulating layer 105 and the microcrystalline semiconductor layer 115a is caused by charging. Therefore, the peak position of the hydrogen concentration side view can be set at the interface between the gate insulating layer 105 and the microcrystalline semiconductor layer 115a. Since the charging shows that the above interface has a peak in the secondary ion intensity of the crucible.

The oxygen concentration side view has a reduced concentration from the microcrystalline semiconductor layer 115a to the mixed layer 115b. The oxygen concentration is substantially constant in the layer 129c containing the amorphous semiconductor.

The side view of the fluorine concentration has a reduced concentration from the microcrystalline semiconductor layer 115a to the mixed layer 115b. The fluorine concentration is substantially constant in the layer 129c containing the amorphous semiconductor. The peak of the fluorine concentration side view between the gate insulating layer 105 and the microcrystalline semiconductor layer 115a is caused by fluorine remaining in the chamber, and is introduced into the film when the microcrystalline semiconductor layer 115a is deposited.

The semiconductor layer shown in FIG. 5 is characterized in that the nitrogen concentration has a peak in the mixed layer 115b and is flat (having a certain value) in the layer 129c containing the amorphous semiconductor, and further, the hydrogen concentration is increased in the mixed layer 115b. And it is a fixed value in the layer 129c containing an amorphous semiconductor.

Alternatively, in the model diagram of the side view of the nitrogen concentration in the depth direction obtained by SIMS in Fig. 6, the nitrogen concentration side view has an increase from the microcrystalline semiconductor layer 115a to the mixed layer 115b. In some examples, in the mixed layer 115b, the side view of the nitrogen concentration continuously increases from the microcrystalline semiconductor layer 115a and then becomes flat in the mixed layer 115b and the layer 129c containing the amorphous semiconductor. At this time, the side view of the nitrogen concentration has the maximum concentration in the mixed layer 115b and the layer 129c containing the amorphous semiconductor. The nitrogen concentration having the maximum value is in the range of 1 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , preferably 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ .

Alternatively, in the model diagram of the hydrogen and nitrogen in the depth direction concentration side view obtained by SIMS in Fig. 7, the side view of the nitrogen concentration increases from the microcrystalline semiconductor layer 115a to the mixed layer 115b. The side view of the nitrogen concentration continuously increases from the microcrystalline semiconductor layer 115a in the mixed layer 115b and then decreases, and in some cases, continuously decreases in the layer 129c containing the amorphous semiconductor. In some examples, the nitrogen concentration side view has a peak concentration (maximum value) in the mixed layer 115b. The peak nitrogen concentration falls within the range of 1 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , preferably 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ .

5 and 7 each show a mode in which the maximum value of the side view of the nitrogen concentration is not present in the interface between the microcrystalline semiconductor layer 115a to the mixed layer 115b but in the mixed layer 115b. However, without the above limitation, the nitrogen concentration side view has a maximum value in the interface between the microcrystalline semiconductor layer 115a and the mixed layer 115b.

It is to be noted that the side view of the nitrogen concentration of the microcrystalline semiconductor layer 115a changes during deposition because of the nitrogen concentration contained in the substrate layer or the concentration of nitrogen contained in the processing chamber of the deposition apparatus. When the microcrystalline semiconductor layer 115a containing as much nitrogen as possible is formed, the crystallinity of the microcrystalline semiconductor layer 115a can be improved, and the field effect mobility and the on current of the thin film transistor can be increased.

Hereinafter, the influence of nitrogen or oxygen contained in the microcrystalline layer on crystal growth will be explained.

The crystallization process of the ruthenium containing an impurity element (N atom or O atom) in this example is calculated by classical molecular dynamics simulation. In the molecular dynamics simulation, the experimental potential characteristic measurement interaction between atoms is defined, and the force acting on each atom is evaluated. The laws of classical mechanics are applied to each atom and the laws of Newton's motion are solved numerically, and the motion of each atom (changed by time) can be surely tracked.

Here, in order to estimate the crystal growth of germanium after the germanium crystal nucleus is generated in the amorphous germanium layer, an example in which the amorphous germanium layer does not contain any impurity element and the amorphous germanium layer contain an impurity element (N atom or O atom). The calculation model of the example of FIG. 8 is shown in FIGS. 8A to 8C.

The model shown in Fig. 8A is such that the crystal nucleus 141 is formed in an amorphous germanium layer containing no impurity element, and the single crystal germanium having a plane orientation (100) grows from the crystal nucleus 141.

The model shown in Fig. 8B is such that the crystal nucleus 141 is formed in an amorphous germanium layer containing 0.5 at.% of the O atom 147, that is, the ratio of the impurity element is about 2.5 × 10 ²⁰ atoms/cm ³ and has a plane orientation (100). The single crystal germanium grows from the crystal nucleus 141.

The model shown in Fig. 8C is such that the crystal nucleus 141 is formed in an amorphous germanium layer containing 0.5 at.% of N atoms 145, that is, the ratio of the impurity elements is about 2.5 × 10 ²⁰ atoms/cm ³ and has a plane orientation (100). The single crystal germanium grows from the crystal nucleus 141.

The classical molecular dynamics simulations in the three computational models shown in Figures 8A through 8C were performed at 1025 °C.

9A to 9C show the structure of Fig. 8A changed by simulation. Specifically, FIG. 9A shows the model after 0 seconds, FIG. 9B shows the model after 0.5 nanoseconds at 1025 ° C, and FIG. 9C shows the model after 1 nanosecond at 1025 ° C.

10A to 10C show the structure of Fig. 8B changed by simulation. Specifically, Fig. 10A shows the model after 0 seconds, Fig. 10B shows the model after 0.5 nanoseconds at 1025 °C, and Fig. 10C shows the model after 1 nanosecond at 1025 °C.

11A to 11C show the structure of Fig. 8C changed by simulation. Specifically, Fig. 11A shows the model after 0 seconds, Fig. 11B shows the model after 1 nanosecond at 1025 °C, and Fig. 11C shows the model after 2 nanoseconds at 1025 °C.

Table 1 shows the crystal growth rate of each enthalpy under each calculation model.

The growth region of the crystal nucleus 141 as shown in Fig. 9A is enlarged to the growth region 151a of the single crystal germanium in Fig. 9B and the growth region 151b of the single crystal germanium in Fig. 9C. Therefore, in the present example, in the case where the amorphous germanium layer does not contain an impurity element, the germanium 143 grows into a crystal.

In this example, the amorphous germanium layer contains O atoms 147, and the grown region of the crystal nucleus 141 as shown in Fig. 10A is enlarged to the growth region 155a of the single crystal germanium in Fig. 10B and the growth region 155b of the single crystal germanium in Fig. 10C. However, compared with the example in which the amorphous germanium layer does not contain an impurity element in FIGS. 9A to 9C, the crystal growth region is small and the crystal growth rate is low. As shown in FIG. 10C, the O atom 147 is bonded to the growth region 155b of the single crystal germanium, and the crystallinity of the entire film is good.

However, when the amorphous germanium layer contains N atoms, the growth region of the crystal nucleus 141 as shown in FIG. 11A is enlarged to the growth region 153a of the single crystal germanium in FIG. 11B and the growth region 153b of the single crystal germanium in FIG. 11C, and 9A to 9C, in the case where the amorphous germanium layer does not contain an impurity element or the amorphous germanium layer in FIG. 10A to 10C contains an O atom 147, the crystal growth region is still small when the time at 1025 ° C is doubled. . Therefore, in the case where the amorphous germanium layer contains N atoms, the crystal growth rate is low. Further, as shown in FIG. 11B and FIG. 11C, the N atom 145 is not bonded to the growth region 153a or 153b of the single crystal germanium, but exists in the interface of the microcrystalline semiconductor region or between the microcrystalline semiconductor region and the amorphous semiconductor region. Interface.

Next, Table 2 shows the bonding distance (Si-Si) between single crystal germanium, SiN and germanium atoms in SiO ₂ , the bonding distance between germanium atoms and nitrogen atoms (Si-N), and germanium atoms and oxygen. The bonding distance between atoms (Si-O).

28A to 28C each show a schematic diagram of a partial structure of a calculation mode in a two-dimensional manner. Fig. 28A is a schematic view of the single crystal crucible shown in Fig. 9C. Figure 28B is a schematic view of the germanium layer region containing O atoms shown in Figure 10C. Figure 28C is a schematic view of the germanium layer region containing N atoms shown in Figure 11C.

In single crystal germanium, both N atoms and O atoms are interstitial impurities. The coordination number of the O atom is 2, and the Si-O bonding distance is shorter than the Si-N bonding distance. Therefore, the O atoms between the bonding Si atoms tend to be substituted and the deformation is relatively small when the Si-O-Si bond is generated. On the other hand, the coordination number of the N atom is 3, and the Si-N bonding distance is longer than the Si-O bonding distance, so that the deformation in the ruthenium layer is easily caused. Therefore, it is highly probable that the inhibition of crystallization of ruthenium by N atoms is more likely than that of O atoms. Fig. 28D is a diagram showing the bonding of O atoms as impurities in the single crystal germanium of the <111> structure to the bonded Si atoms. The impurity O atom exists in the interstitial position of the single crystal germanium and is interposed between the bonded Si atoms having the <111> structure.

Accordingly, because of the deformation caused by the coordination number and the bonding distance between the N atom and the Si atom, the degree of crystallization of the N atom by the N atom is larger than that of the O atom which is also a gap impurity.

According to the above, when the crystal grows in the mixed layer, nitrogen is not bonded to the crystal growth region and is separated from the interface between the different microcrystalline semiconductor regions, and nitrogen suppresses crystal growth. Therefore, crystal growth in the mixed layer is suppressed. Further, nitrogen that is not bonded to the microcrystalline semiconductor region during crystal growth is separated from an interface between different microcrystalline semiconductor regions and an interface between the microcrystalline semiconductor region and the amorphous semiconductor region. Therefore, the nitrogen concentration is increased to an interface between different microcrystalline semiconductor regions and an interface between the microcrystalline semiconductor region and the amorphous semiconductor region. Therefore, nitrogen has a high concentration in the mixed layer.

Further, since nitrogen suppresses crystal growth and the amorphous semiconductor region increases, the hydrogen concentration side view is gradually increased. Since the proportion of bonded germanium atoms in the microcrystalline semiconductor region is high, the hydrogen concentration in this region is low. On the other hand, the proportion of bonded germanium atoms in the amorphous semiconductor region is low, and there are more dangling bonds than the microcrystalline semiconductor regions. Since hydrogen is bonded to dangling bonds, the hydrogen concentration is high. Therefore, a gradual increase in the side view of the hydrogen concentration measured by SIMS indicates a decrease in crystallinity, and a fixed hydrogen concentration indicates formation of an amorphous semiconductor region. Further, the microcrystalline semiconductor region has a conical or square pyramid shape.

Since the mixed layer 115b contains the conical or square pyramidal microcrystalline semiconductor region 108a, when a voltage is applied to the source or the drain electrode, the resistance in the vertical direction (film thickness direction), that is, the microcrystalline semiconductor layer 115a, is mixed. The resistance of the layer 115b and the layer 129c containing the amorphous semiconductor is reduced.

The mixed layer 115b preferably contains nitrogen. This is because when nitrogen, typically the NH group or the NH ₂ group, is interposed between different microcrystalline semiconductor regions in the microcrystalline semiconductor region 108a, or between the microcrystalline semiconductor region 108a and the amorphous semiconductor region 108b. When the interface is bonded to the dangling bond of the helium atom, the defect will be reduced. Therefore, when the nitrogen concentration of the mixed layer 115b is set in the range of 1 × 10 ²⁰ atoms / cm ³ to 1 × 10 ²¹ atoms / cm ³ , preferably 2 × 10 ²⁰ atoms / cm ³ to 1 × 10 ^{At 21} atoms/cm ³ , the dangling bonds of the ruthenium atoms can be easily cross-linked with nitrogen, preferably the NH group, so that the carriers can easily flow. Alternatively, the dangling bonds of the semiconductor atoms at the aforementioned interface may be terminated to the NH ₂ group such that the defect level disappears. Therefore, when the thin film electro-crystallization system is turned on and a voltage is applied to the source electrode or the drain electrode, the resistance in the vertical direction (film thickness direction) is lowered. That is, the field effect mobility and the on current of the thin film transistor can be increased.

Moreover, by reducing the oxygen concentration to be lower than the nitrogen concentration in the mixed layer 115b, the interfacial carrier transport between the microcrystalline semiconductor region 108a and the amorphous semiconductor region 108b is interrupted, and interposed between the semiconductor crystal grains. The defects of the interface will be reduced.

In this method, when a microcrystalline semiconductor layer 115a interposed between the channel formation region and the impurity semiconductor layer 127 as a source or drain region, and a well-ordered semiconductor layer having a small defect itself and a price in the valence band are used When the layer 129c having an edge of the edge of the amorphous semiconductor having a sharp edge is formed to form a channel formation region, the off current of the thin film transistor can be lowered. Further, by providing the layer 129c containing an amorphous semiconductor, the on-current and field-effect mobility of the thin film transistor can be increased. Further, by providing the mixed layer 115b containing the conical or square pyramidal microcrystalline semiconductor region 108a and the layer 129c containing the amorphous semiconductor, the on-current and field-effect mobility of the thin film transistor can be increased.

The impurity semiconductor layer 127 shown in Fig. 1 is formed by using an amorphous germanium to which phosphorus is added, a microcrystalline germanium to which phosphorus is added, or the like. It is to be noted that in the case of forming a thin film transistor by a P-channel thin film transistor, the impurity semiconductor layer 127 is formed using a microcrystalline germanium to which boron is added, an amorphous germanium to which boron is added, or the like. It is to be noted that in the case where the mixed layer 115b or the layer 129c containing the amorphous semiconductor has an ohmic contact with the wiring 125, the impurity semiconductor layer 127 does not have to be formed.

The wiring 125 as shown in FIG. 1 may be formed into a single layer or a stacked layer using any of aluminum, copper, titanium, tantalum, niobium, molybdenum, chromium, niobium, tungsten or the like. An aluminum alloy added to prevent elements of the hillocks may also be used (for example, an A1-Nd alloy which can be used for the gate electrode layer 103). The wiring 125 may also be provided with a stacked structure in which a layer in contact with the impurity semiconductor layer 127 is formed using any element of titanium, tantalum, molybdenum, tungsten or nitrogen, and aluminum or an aluminum alloy is formed therein. Moreover, the stacked layer structure is such that the upper surface and the lower surface of the aluminum or aluminum alloy are each covered by any one of titanium, tantalum, molybdenum, tungsten or nitrogen.

As shown in FIG. 1 , FIG. 2A , FIG. 2B , FIG. 3 , FIG. 4A , FIG. 4B , FIG. 5 , FIG. 6 , and FIG. 7 , the off current can be reduced, and the on current and the field effect mobility can be increased. . Further, since the channel formation region is formed using a microcrystalline semiconductor layer, the thin film transistor is less deteriorated in electrical properties and has higher reliability. Moreover, since the on-current is large, the area of the channel formation region, that is, the area of the thin film transistor can be reduced as compared with the thin film transistor using the amorphous germanium as the channel formation region. Therefore, such a thin film transistor can be highly integrated.

(Example 2)

In this embodiment, a method of manufacturing the thin film transistor of Embodiment 1 will be described with reference to FIGS. 12A to 12C, FIGS. 13A to 13C, and FIGS. 14A-1 to 14B-2.

It is preferred that all of the thin film transistors formed on the same substrate have the same conductivity because the steps of the process can be reduced. Therefore, in the present embodiment, a method of manufacturing an n-channel thin film transistor is described.

First, the manufacturing process of the thin film transistor of Fig. 1 will be described below.

As shown in FIG. 12A, a gate electrode 103 is formed on a substrate 101. Then, a gate insulating layer 105 is formed to cover the gate electrode 103. Thereafter, the first semiconductor layer 106 is formed.

The gate electrode 103 is formed by sputtering or vacuum evaporation using the material of the first embodiment to cover the conductive layer on the substrate 101, and is formed by a lithography method, an inkjet method or the like to form a photomask. On the layer, a photomask is used to etch the conductive layer. Further, the gate electrode 103 is formed by discharging the conductive nano-gel on the substrate of silver, gold, copper or the like by an inkjet method, and baking the conductive nano-gel. Here, the conductive layer is formed on the substrate 101, and then etched using a protective mask formed by the first lithography method, thereby forming the gate electrode 103.

It should be noted that in the lithography method, a protective layer can be applied to the entire surface of the substrate. Alternatively, a protective layer may be printed on the area where the protective mask is to be formed, and then the protective layer is exposed to retain the photoresist and reduce the cost. Alternatively, the protective layer may be exposed using a laser source direct mapping device instead of exposing the protective layer by using an exposure machine.

Further, when the side surface of the gate electrode 103 is tapered, the open circuit of the wiring layer of the semiconductor layer and the step portion formed on the gate electrode 103 can be lowered. In order to form a tapered shape on the side surface of the gate electrode 103, etching may be performed when the size of the protective mask is reduced.

Through the step of forming the gate electrode 103, the gate wiring (scanning line) and the capacitor wiring can also be formed at the same time. It should be noted that the "scanning line" refers to the wiring for selecting pixels, and the "capacitor wiring" refers to the wiring for connecting one of the electrodes of the capacitor in the pixel. However, not limited thereto, the gate electrode 103 is formed in a step of separating one or both of the gate wiring and the capacitor wiring.

The gate insulating layer 105 can be formed by a CVD method, a sputtering method, or the like as used in the material of Embodiment 1. In the process of forming the gate insulating layer 105 by the CVD method, a glow discharge plasma is generated by applying high frequency power or high frequency power in the VHF band, and the frequency of the high frequency power is between 3 MHz and 30 MHz, typically 13.56 MHz. Or 27.12 MHz, the frequency of the high frequency power in the VHF band is between 30 MHz and about 300 MHz, typically 60 MHz. Moreover, the gate insulating layer 105 can be formed using a microwave plasma CVD apparatus having a high frequency (greater than or equal to 1 GHz). When the gate insulating layer 105 is formed by the microwave plasma CVD apparatus, the withstand voltage between the gate electrode and the drain electrode and the source electrode can be increased, and thus, a highly reliable thin film transistor can be obtained.

Moreover, by forming the tantalum oxide layer by the CVD method using the organic germane gas as the gate insulating layer 105, the crystallinity of the first semiconductor layer formed later can be improved, so that the on-current and field-effect mobility of the thin film transistor can be increased. a compound containing ruthenium such as ethyl phthalate (TEOS) (chemical formula: Si(OC ₂ H ₅ ) ₄ ), tetramethyl decane (TMS) (chemical formula: Si(CH ₃ ) ₄ ), organic ruthenium compound (TMCTS), Octamethyl cyclic tetraoxane (OMCTS), hexamethyldioxane (HMDS), triethoxydecane (chemical formula: SiH(OC ₂ H ₅ ) ₃ ) or tri dimethyl decane (chemical formula: SiH(N(CH ₃ ) ₂ ) ₃ ) can be used as an organic decane gas.

The first semiconductor layer 106 is formed using a microcrystalline semiconductor layer, typically a microcrystalline germanium layer, a microcrystalline germanium layer, a microcrystalline germanium layer, or the like. The first semiconductor layer 106 is formed to have a thickness of from 3 nm to 10 nm, preferably from 3 nm to 5 nm. Therefore, in the second semiconductor layer formed later, the length of each of the microcrystalline semiconductor regions formed by the conical or square pyramid projection (projection portion) can be controlled, and the on-current and the off current of the thin film transistor can also be control.

In the reaction chamber of the plasma CVD apparatus, the first semiconductor layer 106 is formed by using a glow discharge plasma containing a deposition gas containing ruthenium or osmium and hydrogen. Alternatively, the first semiconductor layer 106 is formed by using a glow discharge plasma mixed with a deposition gas containing neon or neon, hydrogen, and a rare gas such as helium, neon, argon, xenon or krypton. A mixture obtained by diluting a deposition gas containing cerium or lanthanum with a flow rate of 10 to 2000 times (preferably 10 to 200 times) of hydrogen gas at a flow rate to form a microcrystalline ruthenium, a microcrystalline ruthenium, Microcrystalline germanium or the like.

Typical examples of the deposition gas containing ruthenium or osmium are SiH ₄ , Si ₂ H ₆ , GeH ₄ and Ge ₂ H ₆ .

The deposition rate of the first semiconductor layer 106 can be increased by using a rare gas such as helium, neon, argon, xenon or krypton as the source gas to the first semiconductor layer 106. As the deposition rate increases, the amount of impurities mixed into the first semiconductor layer 106 may decrease, so that the crystallinity of the first semiconductor layer 106 is improved. Therefore, the on-current and field-effect mobility of the thin film transistor are increased, and the throughput of the thin film transistor can also be improved.

When the first semiconductor layer 106 is formed, by applying a frequency of 3 MHz to 30 MHz, typically a high frequency power of 13.56 MHz, a high frequency power having a frequency of 27.12 MHz in the HF band, or a frequency of 30 MHz in the VHF band. Up to about 300 MHz, typically 60 MHz high frequency power, produces glow discharge plasma. Accordingly, the glow discharge plasma is generated by applying high frequency power having a microwave frequency greater than or equal to 1 GHz. The high frequency power or microwave frequency used in the VHF band can increase the deposition rate. Further, by the high frequency power in the VHF band superimposed on the high frequency power in the HF band, the unevenness of the plasma can be lowered when the large-sized substrate is used, the uniformity can be increased, and the deposition rate can be increased.

It should be noted that before the formation of the first semiconductor layer 106, the impurity element in the processing chamber of the CVD device is removed by introducing a deposition gas containing germanium or antimony when the gas in the processing chamber is exhausted. The amount of impurity elements in the gate insulating layer 105 and the first semiconductor layer 106 of the subsequently formed thin film transistor is lowered, and therefore, the electrical properties of the thin film transistor can be improved.

Next, as shown in FIG. 12B, a second semiconductor layer 107 is deposited over the first semiconductor layer 106, thereby forming a mixed layer 107b and a layer 107c containing an amorphous semiconductor. Then, the impurity semiconductor layer 109 and the conductive layer 111 are formed on the second semiconductor layer 107. Thereafter, a second protective mask 113 is formed on the conductive layer 111.

The mixed layer 107b and the layer 107c containing the amorphous semiconductor are formed by using the first semiconductor layer 106 (microcrystalline semiconductor layer) as a seed crystal in a state where the crystal is partially grown.

In the reaction chamber of the plasma CVD apparatus, the second semiconductor layer 107 is formed by using a mixed glow discharge plasma containing a deposition gas of ruthenium or osmium, hydrogen, and a gas containing nitrogen. The nitrogen-containing gas includes, for example, ammonia, nitrogen, nitrogen fluoride, chlorine nitrogen, chloramine or fluoroamine, and the like.

In this example, the flow rate ratio of the deposition gas containing hydrogen or helium to the hydrogen gas is the same as that of forming the microcrystalline semiconductor layer in the example of forming the first semiconductor layer 106, and the gas containing nitrogen is used as the source gas, thereby Crystal growth is more suppressed than the deposition of a semiconductor layer 106. As a result, the mixed layer 107b and the layer 107c containing the amorphous semiconductor which is formed by the well-ordered semiconductor layer and which has a small defect and which is located at the edge of the valence band energy band is steep, is formed in the second semiconductor layer 107.

Here, a typical example of the condition of forming the second semiconductor layer 107 is as follows. The flow rate of hydrogen is 10 to 2000 times, preferably 10 to 200 times, of the deposition gas containing ruthenium or osmium. It is to be noted that, in a typical example of the condition of forming a normal amorphous semiconductor layer, the flow rate of hydrogen is 0 to 5 times that of a deposition gas containing ruthenium or osmium.

A rare gas such as helium, neon, argon, xenon or krypton is introduced into the source gas of the second semiconductor layer 107, thereby increasing the deposition rate of the second semiconductor layer 107.

It is to be noted that when a rare gas such as helium, neon, fluorine, krypton or xenon is introduced into the source gas of the second semiconductor layer 107, the crystallinity of the second semiconductor layer 107 increases and the shutdown current of the thin film transistor increases; Therefore, it is preferred to control the mixing ratio of the deposition gas containing hydrogen, or hydrogen, and the gas containing nitrogen. Typically, the flow rate of the deposition gas containing ruthenium or osmium is increased with respect to hydrogen which increases the amorphous form, whereby the crystallinity and amorphousness of the mixed layer 107b and the layer 107c containing the amorphous semiconductor can be controlled.

In the initial stage of depositing the second semiconductor layer 107, since the nitrogen-containing gas is contained in the source gas, crystal growth is partially suppressed. Therefore, an amorphous semiconductor region is formed when the conical or square pyramidal microcrystalline semiconductor region is grown. Thereafter, the conical or square pyramidal microcrystalline semiconductor region is stopped and the layer containing the amorphous semiconductor is formed. In some examples, the first semiconductor layer 106 is used as a seed to deposit a microcrystalline semiconductor layer over the entire surface of the first semiconductor layer 106 prior to growth of the conical or square pyramidal microcrystalline semiconductor region.

Therefore, the microcrystalline semiconductor layer 115a in FIG. 1 corresponds to the first semiconductor layer 106 in FIG. 12A.

Further, the mixed layer 115b in FIG. 1 corresponds to the mixed layer 107b in the second semiconductor layer 107 in FIG. 12B.

Further, the layer 129c containing the amorphous semiconductor in FIG. 1 corresponds to the layer 107c containing the amorphous semiconductor in the second semiconductor layer 107 in FIG. 12B.

In the reaction chamber of the plasma CVD apparatus, the impurity semiconductor layer 109 is formed by using a mixed glow discharge plasma containing a deposition gas of ruthenium or osmium, hydrogen and phosphine (diluted with hydrogen or decane). The amorphous germanium to which phosphorus is added or the microcrystalline germanium to which phosphorus is added is formed by diluting a deposition gas containing neon or xenon with hydrogen. In the example of fabricating a P-channel thin film transistor, the impurity semiconductor layer 109 can be formed by using a diborane-substituted phosphine glow discharge plasma.

Conductive layer 111 can be formed by using a material similar to wiring 125 in FIG. The conductive layer 111 can be formed by a CVD method (chemical vapor deposition), a sputtering method, or a vacuum evaporation method. Alternatively, the conductive layer 111 may be discharged by using a screen printing method, an inkjet method or the like to discharge silver, gold, copper or the like, and baking the conductive nano-gel. form.

The protective mask 113 is formed by a second lithography process. The protective mask 113 has regions having different thicknesses. Such a protective mask can be formed by using a multi-stage adjustment mask. Due to the reduced number of reticle and process steps, a multi-segment adjustment mask is preferred. In the present embodiment, the multi-stage adjustment mask is used in the process of forming the pattern of the first semiconductor layer 106 and the second semiconductor layer 107 and in forming the source region and the drain region.

The multi-stage adjustment mask is a mask that can be exposed in multiple orders of light; typically, the exposure can be performed in a third order amount of light to provide an exposure area, a half exposure area, and an unexposed area. By using a multi-stage adjustment of the exposure and development steps of the reticle, a reticle having multiple thicknesses (typically two thicknesses) can be formed. Therefore, the number of masks can be reduced by using a multi-stage adjustment mask.

14A-1 and 14B-1 are cross-sectional views of a typical multi-stage adjustment mask. 14A-1 shows the gray dimmer 180 and FIG. 14B-1 shows the halftone mask 185.

The gray dimming cover 180 shown in Fig. 14A-1 includes a light shielding portion 182 formed on the light-transmitting substrate 181 using a light shielding layer, and a diffraction grating portion 183 serving as a light shielding layer pattern.

The diffraction grating portion 183 has a grating, a repeating point, a mesh or the like, the pitch of which is less than or equal to the light resolution limit used as the exposure light source, thereby controlling the light transmittance. The grating, the repeating point or the mesh of the diffraction grating portion 183 can be provided with a gap uniformly or without a gap.

As the light transmission substrate 181, quartz or the like can be used. The light shielding layer and the diffraction grating portion 183 for forming the light shielding portion 182 may be formed using chromium, chromium oxide or the like.

As shown in FIG. 14A-2, the gray dimming cover 180 is exposed to light for exposure, and the light transmittance of the region covered by the light shielding portion 182 is 0%, and the light transmission portion 182 and the region of the diffraction grating portion 183 are not provided. The rate is 100%. The light transmittance of the diffraction grating portion 183 is approximately between 10% and 70%, and can be adjusted by the grating of the diffraction grating, the reverse point, the mesh, or the like.

The half-tone mask 185 shown in FIG. 14B-1 includes a semi-transmissive portion 187 formed on the light-transmitting substrate 186 using a semi-transmissive layer, and a light-shielding portion 188 formed using a semi-shielding layer.

The semi-transmissive portion 187 can be formed using a layer of MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light shielding portion 188 may be formed using a material similar to the light shielding layer of the gray dimming cover, and chromium, chromium oxide or the like is preferred.

As shown in FIG. 14B-2, the halftone mask 185 is exposed to light for exposure, and the light transmittance of the region covered by the light shielding portion 188 is 0%, and the light transmission portion 188 and the region of the semi-light transmitting portion 187 are not provided. The rate is 100%. The light transmittance of the semi-transmissive portion 187 is approximately between 10% and 70%, and can be adjusted by using the kind and thickness of the material.

A photoresist mask having regions of different thicknesses can be formed by using a multi-tone mask and a developer for exposure.

Next, the first semiconductor layer 106, the second semiconductor layer 107, the impurity semiconductor layer 109, and the conductive layer 111 are etched using the photoresist mask 113. Through this procedure, the first semiconductor layer 106, the second semiconductor layer 107, the impurity semiconductor layer 109, and the conductive layer 111 are diced to form the third semiconductor layer 115, the impurity semiconductor layer 117, and the conductive layer 119. The third semiconductor layer 115 includes a microcrystalline semiconductor layer 115a, a mixed layer 115b, and a layer 115c containing an amorphous semiconductor (FIG. 12C).

Next, the photoresist mask 113 is reduced in size to form a separate photoresist mask 123. The use of ashing of oxygen plasma can reduce the size of the photoresist mask. Here, ashing is performed on the photoresist mask 113 to separate the photoresist mask 113 from the gate electrode. According to this, the photoresist mask 123 can be formed (FIG. 13A).

Next, the conductive layer 119 is etched using the photoresist mask 123 to form a wiring 125 as a source and a drain electrode (FIG. 13B). The etching of the conductive layer 119 is preferably performed by wet etching. The conductive layer is isotropically etched by wet etching. As a result, the side surface of the conductive layer is located on the inner side of the photoresist mask 123, thus forming the wiring 125. The wiring 125 serves not only as a source and a drain electrode but also as a signal line. However, the signal line can be separated from the source and drain electrodes.

Next, using the photoresist mask 123, the layer 115c containing the amorphous semiconductor and the impurity semiconductor layer 117 are partially etched. Dry etching is used here. By the above steps, a layer 129c containing a recessed amorphous semiconductor and an impurity semiconductor layer 127 as a source and drain region are formed on the surface (Fig. 13C). The photoresist mask 123 is then removed.

Note that here, the conductive layer 119 is etched by wet etching, and the layer 115c containing the amorphous semiconductor and the impurity semiconductor layer 117 are etched by dry etching. Therefore, the conductive layer 119 is isotropically etched, the side surface of the wiring 125 is not aligned with the side surface of the impurity semiconductor layer 127, and the side surface of the impurity semiconductor layer 127 is located on the outer side with respect to the side surface of the wiring 125.

Alternatively, after etching the conductive layer 119 and removing the photoresist mask 123, the impurity semiconductor layer 117 and the layer 115c containing the amorphous semiconductor are partially etched. The impurity semiconductor layer 117 is etched by etching using the wiring 125 as a mask so that the side surface of the wiring 125 is substantially aligned with the side surface of the impurity semiconductor layer 127.

Next, dry etching is performed. The conditions of the dry etching are set such that the exposed region of the layer 129c containing the amorphous semiconductor is not damaged, and the etching rate for the layer 129c containing the amorphous semiconductor is low. In other words, a condition is applied which makes the layer 129c containing the amorphous semiconductor hardly damaged, and the thickness of the exposed region of the layer 129c containing the amorphous semiconductor hardly decreases. The chlorine-based gas is typically Cl ₂ , CF ₄ , N ₂ or the like as an etching gas. The etching method is not particularly limited, and an inductively coupled plasma (ICP) method, a capacitive coupled plasma (CCP) method, an electron cyclotron resonator (ECR) method, a reactive ion etching method (RIE), or the like can be used. use.

Next, the surface of the layer 129c containing the amorphous semiconductor may be subjected to plasma treatment, typically such as water plasma treatment, ammonia plasma treatment, nitrogen plasma treatment, or the like.

The hydroponic treatment can be introduced into the reaction space by using a gas containing water as a main component such as water vapor (H ₂ O vapor) to generate a plasma.

As described above, after the formation of the impurity semiconductor layer 127, the dry etching is performed without damage to the layer 129c containing the amorphous semiconductor, thereby removing the residue existing on the exposed region of the layer 129c containing the amorphous semiconductor, for example. Impurities. Also, after dry etching, a water plasma treatment is performed to remove the residue of the photoresist mask. By plasma treatment, insulation between the source and the drain region is ensured, and thus the off current of the thin film transistor can be lowered, and the change in electrical properties can be reduced.

Through these steps, a thin film transistor having a channel formation region formed using a microcrystalline semiconductor layer can be fabricated with a small number of masks. Moreover, a thin film transistor having a low off current, a large on current, and a high field effect mobility can be manufactured with high productivity.

(Example 3)

In the present embodiment, a method of manufacturing a thin film transistor different from that of the thin film transistor of Embodiment 2 will be described with reference to FIGS. 12A to 12C, FIGS. 15A to 15C, and FIGS. 16A and 16B.

In Embodiment 2, the gate electrode 103 is formed on the substrate 101. Then, the gate insulating layer 105 is formed to cover the gate electrode 103, and the first semiconductor layer 106 is formed (FIG. 12A). Next, in Embodiment 2, the crystal grows from the first semiconductor layer 106, thereby forming the second semiconductor layer 107 (the mixed layer 107b and the layer 107c containing the amorphous semiconductor). Then, the impurity semiconductor layer 109 is formed on the second semiconductor layer 107 (FIG. 15A). Thereafter, a photoresist mask (not shown) is formed on the impurity semiconductor layer 109.

Next, the second semiconductor layer 107 and the impurity semiconductor layer 109 are etched using a photoresist mask. By this step, the second semiconductor layer 107 and the impurity semiconductor layer 109 are diced to form the second semiconductor layer 115 (the microcrystalline semiconductor layer 115a, the mixed layer 115b and the layer 115c containing the amorphous semiconductor) and the impurity element layer 117 (Fig. 15B).

Next, a conductive layer 111 is formed on the gate insulating layer 105, the second semiconductor layer 115, and the impurity semiconductor layer 117 (FIG. 15C).

Then, a photoresist mask (not shown) is formed on the conductive layer 111, and the conductive layer 111 is etched using a photoresist mask to form a wiring 133 as a source and a drain electrode (FIG. 16A).

Next, the impurity semiconductor layer 117 is partially etched to form an impurity semiconductor layer 127 as a source region and a drain region. Further, the layer 115c containing an amorphous semiconductor is partially etched, thereby forming a layer 129c containing an amorphous semiconductor having a depressed portion (Fig. 16B).

Through the above steps, a thin film transistor can be fabricated.

After the wiring 133 is formed, the impurity semiconductor layer 117 and the layer 115c containing the amorphous semiconductor are partially etched without removing the photoresist mask; however, the impurity semiconductor layer 117 and the layer 115c containing the amorphous semiconductor may be covered by the photoresist. The cover is partially etched after being removed. The impurity semiconductor layer 117 is etched by etching using the wiring 133 as a mask so that the side surface of the wiring 133 is substantially aligned with the side surface of the impurity semiconductor layer 127.

Next, dry etching is performed after the photoresist mask is removed. The dry etching conditions are set such that the exposed region of the layer 129c containing the amorphous semiconductor is not damaged, and the etching rate for the layer 129c containing the amorphous semiconductor is low. In other words, a condition is applied which makes the layer 129c containing the amorphous semiconductor hardly damaged, and the thickness of the exposed region of the layer 129c containing the amorphous semiconductor hardly decreases.

Next, the surface of the layer 129c containing the amorphous semiconductor may be irradiated with water plasma, ammonia plasma, nitrogen plasma, or the like.

The hydroponic treatment can be introduced into the reaction space by using a gas containing water as a main component such as water vapor (H ₂ O vapor) to generate a plasma.

As described above, after the formation of the layer 129c containing the amorphous semiconductor, dry etching is performed without damage to the layer 129c containing the amorphous semiconductor, thereby removing, for example, the exposed region of the layer 129c containing the amorphous semiconductor. Impurities of the residue. Also, after dry etching, a water plasma treatment is performed to remove the residue of the photoresist mask. By plasma treatment, insulation between the source region and the drain region is ensured, and thus the off current of the thin film transistor can be reduced, and the change in electrical properties can be reduced.

Through these steps, a thin film transistor having a channel formation region formed using a microcrystalline semiconductor layer can be fabricated. Moreover, a thin film transistor having a low off current, a large on current, and a high field effect mobility can be manufactured with high productivity.

(Example 4)

In the present embodiment, a series of steps from the step of forming the gate insulating layer to the step of forming the impurity semiconductor layer can be applied to the embodiments 2 and 3, which will be described with reference to the timing chart of FIG. It should be noted that the gate insulating layer is formed in the case where the tantalum nitride layer is stacked on the tantalum nitride layer.

First, the substrate 101 having the gate electrode 103 is heated in the processing chamber in the CVD apparatus, and the source gas for depositing the tantalum nitride layer is introduced into the processing chamber (pretreatment 201 in Fig. 17). In this example, the source gas was introduced and stabilized, the SiH ₄ flow rate was 40 sccm, the H ₂ flow rate was 500 sccm, the N ₂ flow rate was 550 sccm, and the NH ₃ flow rate was 140 sccm, the pressure in the processing chamber was 100 Pa, and the substrate temperature was 280. At °C, the output is 370 W. In this case, plasma discharge is performed, thereby forming a tantalum nitride layer having a thickness of about 110 nm. Thereafter, only the supply of SiH ₄ was stopped, and after a few seconds (5 seconds in this embodiment), the plasma discharge was stopped (SiN 203 was formed in Fig. 17). This is because when the plasma discharge is stopped in the state where SiH ₄ is still present in the processing chamber, a granular compound or a powdery compound containing cerium as a main component is formed to lower the yield.

Next, the source gas for depositing the tantalum nitride layer is depleted, and the source gas for depositing the tantalum nitride oxide layer is introduced into the processing chamber (gas replacement 205 in Fig. 17). In the example here, the source gas is introduced and stabilized, the SiH ₄ flow rate is 30 sccm, the N ₂ O flow rate is 1200 sccm, the pressure in the processing chamber is 40 Pa, the substrate temperature is 280 ° C, the output is 50 W, and the plasma is discharged. This was carried out, whereby a niobium oxynitride layer having a thickness of about 110 nm was formed. Thereafter, similar to the formation of the tantalum nitride layer, only the supply of SiH ₄ was stopped, and after a few seconds (5 seconds in this embodiment), the plasma discharge was stopped (SiON 207 was formed in Fig. 17).

Through the above steps, the gate insulating layer 105 is formed. After the gate insulating layer 105 is formed, the substrate 101 is carried outside the processing chamber (unloading 205 in Fig. 17).

After the substrate 101 is placed outside the processing chamber, for example, NF ₃ gas is introduced into the processing chamber to clean the inside of the chamber (clean processing 227 in FIG. 17). Thereafter, a process of forming an amorphous germanium layer in the processing chamber (precoat process 229 in Fig. 17) is performed. The amorphous germanium layer is thereby formed on the inner wall of the processing chamber by this treatment. Thereafter, the substrate 101 is loaded into the reaction chamber (loaded 231 in FIG. 17).

Next, a source gas for depositing the first semiconductor layer 106 is introduced into the processing chamber (instead of the gas 209 in FIG. 17). Then, the first semiconductor layer 106 is formed on the gate insulating layer 105. In the example here, the source gas is introduced and stabilized, the SiH ₄ flow rate is 10 sccm, the H ₂ flow rate is 1500 sccm, and the Ar flow rate is 1500 sccm, the pressure in the processing chamber is 280 Pa, the substrate temperature is 280 ° C, and the output is 50 W. The slurry discharge was carried out in this case, whereby a microcrystalline germanium layer having a thickness of about 5 nm as the first semiconductor layer 106 was formed. Thereafter, similar to the formation of the tantalum nitride layer or the like as described above, only the supply of SiH ₄ is stopped, and after a few seconds (5 seconds in this embodiment), the plasma discharge is stopped (the first in FIG. 17) Formation of the semiconductor layer 211).

Next, nitrogen gas is supplied to the surface of the first semiconductor layer 106. Here, the surface of the first semiconductor layer 106 is exposed to ammonia to supply nitrogen gas (herein referred to as "rinsing treatment") (flushing treatment 213 in Fig. 17). Moreover, hydrogen can be contained in ammonia. Alternatively, nitrogen can be introduced into the processing chamber in place of ammonia. Alternatively, both ammonia and nitrogen are introduced into the processing chamber. In this example, the pressure in the processing chamber was between 20 Pa and 30 Pa, the substrate temperature was 280 ° C, and the processing time was 60 seconds. Note that in the process of this process, the substrate 101 is only exposed to ammonia. However, plasma processing can also be performed. Thereafter, these gases are exhausted and a gas for depositing the second semiconductor layer 107 is introduced (the replacement gas 215 in Fig. 17).

Next, a second semiconductor layer 107 is formed. In this example, the source gas is introduced and stabilized, the SiH ₄ flow rate is 30 sccm, the H ₂ flow rate is 1500 sccm, the process chamber pressure is 280 Pa, the substrate temperature is 280 ° C, and the RF power source frequency is 13.56 MHz. The RF power source The output power was 50 W, and plasma discharge was carried out in this case, whereby a second semiconductor layer 107 having a thickness of about 150 nm was formed.

In the step of forming the second semiconductor layer 107, the ammonia introduced into the processing chamber by the rinsing treatment is decomposed by the plasma discharge, and then the nitrogen obtained by the decomposition of ammonia is introduced into the second semiconductor layer 107 at the time of deposition. To form a mixed layer each containing nitrogen and a layer containing an amorphous semiconductor. Moreover, the NH group or the NH ₂ group is formed by decomposition of ammonia, and therefore, the dangling bonds are cross-linked with the NH group when the second semiconductor layer 107 is deposited. Alternatively, the dangling button can terminate in the NH ₂ group. Note that in this example, nitrogen is introduced into the processing chamber as a nitrogen-containing gas, and the reaction occurs between the nitrogen gas and the hydrogen contained in the source gas of the second semiconductor layer 107 by plasma discharge to generate an NH group or NH _{2 .} Group. Different dangling bonds in the second semiconductor layer 107 are cross-linked to the NH group. Further, different dangling bonds in the second semiconductor layer 107 terminate in the NH ₂ group and the number of defects disappears.

Thereafter, similar to the formation of the tantalum nitride layer or the like, only the supply of SiH ₄ is stopped, and after a few seconds (5 seconds in this embodiment), the plasma discharge is stopped (the formation of the second semiconductor layer 217 in Fig. 17) ). Thereafter, these gases are exhausted and a gas for depositing the impurity semiconductor layer 109 is introduced (instead of the substitution gas 219 in Fig. 17).

In the second semiconductor layer 107 formed by the above method, the nitrogen concentration measured by the secondary ion mass spectrometer is as described in Embodiment 1, and the nitrogen is isolated in the microcrystalline semiconductor region in the initial deposition of the second semiconductor layer 107. Interface. Thereafter, nitrogen is contained in the amorphous semiconductor layer. However, as the second semiconductor layer 107 is deposited, the amount of nitrogen in the processing chamber of the CVD apparatus is reduced. Therefore, after the nitrogen concentration has a peak in the mixed layer 107b, the deposition direction of the layer 107c containing the amorphous semiconductor is reduced.

It is noted that ammonia is supplied into the processing chamber forming the second semiconductor layer 217 as indicated by a broken line 235a of FIG. As shown by the broken line 235b of Fig. 17, nitrogen gas substituted for ammonia is supplied. Alternatively, both ammonia and nitrogen are introduced into the processing chamber. Alternatively, nitrogen fluoride, chlorine nitrogen, chloramine, fluoroamine or the like may be supplied to replace ammonia and nitrogen. As a result, the concentration of nitrogen in the second semiconductor layer 107 is increased, so that the dangling bonds in the second semiconductor layer 107 are cross-linked, resulting in a decrease in the number of defects. In addition, the dangling bond is terminated and the number of defects is reduced.

In the second semiconductor layer 107 formed by the above method, the nitrogen concentration measured by the secondary ion mass spectrometer has a peak value (maximum value) in the mixed layer 107b, and is fixed in the deposition direction of the layer 107c containing the amorphous semiconductor. .

Alternatively, in the formation of the second semiconductor layer 217, a rare gas is used as the source gas as indicated by the broken line 236. As a result, the generation rate of the second semiconductor layer 107 is increased.

Next, the impurity semiconductor layer 109 is formed on the entire surface of the second semiconductor layer 107. In the subsequent process, the impurity semiconductor layer 109 is patterned to the impurity semiconductor layer 127 which is the source and drain regions. First, a source gas for depositing the impurity semiconductor layer 109 is introduced into the processing chamber. In this example, the source gas was introduced and stabilized, the SiH ₄ flow rate was 100 sccm, and the mixed gas flow rate of pH ₃ to 0.5 vol% diluted with hydrogen was 170 sccm. Further, the pressure in the processing chamber was 280 Pa, the substrate temperature was 280 ° C, and the output was 60 W. In this case, plasma discharge was performed, whereby a phosphorus-containing amorphous germanium layer having a thickness of about 50 nm was formed. Thereafter, only the supply of SiH ₄ is stopped in a manner similar to that of the foregoing tantalum nitride layer or the like, and after a few seconds (5 seconds in this embodiment), the plasma discharge is stopped (the impurity semiconductor layer in Fig. 17). Formation of 221). These gases are then depleted (depleted 223 in Figure 17).

As described above, the components contained on the impurity semiconductor layer 109 can be formed.

Through the above steps, a microcrystalline semiconductor region containing nitrogen and an amorphous semiconductor region containing nitrogen are formed. That is, a conical or square pyramidal microcrystalline semiconductor region and a well-ordered semiconductor layer having a sharp defect with a small defect and a valence band edge in the valence band can be formed. As a result, a thin film transistor having a large on-current and a high field-effect mobility and a small off current can be manufactured.

(Example 5)

In the present embodiment, a series of steps from the step of forming the gate insulating layer to the step of forming the impurity semiconductor layer will be described, which can be applied to the embodiments 2 and 3.

In the present embodiment, the second semiconductor layer 107 is formed inside the clean processing chamber, and then the inner wall of the chamber is covered with a tantalum nitride layer, whereby nitrogen is contained in the second semiconductor layer 107 and the nitrogen concentration is controlled. . The method of forming the gate insulating layer 105 is similar to that of Embodiment 4; therefore, a series of steps from the step of forming the first semiconductor layer 106 to the step of forming the impurity semiconductor layer 109 will be described below with reference to FIG.

The first semiconductor layer 106 is formed on the entire surface of the gate insulating layer 105. First, the source gas used to deposit the first semiconductor layer 106 is introduced into the processing chamber. In this example, a microcrystalline germanium layer having a thickness of about 5 nm was formed as the first semiconductor layer 106 in a manner similar to that of the embodiment 2. Thereafter, the plasma discharge is stopped (formation of the first semiconductor layer 211 in Fig. 18). Then, the substrate 101 is carried outside the processing chamber (unloading 225 in Fig. 18).

After the substrate 101 is placed outside the processing chamber, for example, NF ₃ gas is introduced into the processing chamber and cleaned inside the processing chamber (clean processing 227 in FIG. 18). Thereafter, a process of forming a tantalum nitride layer in the processing chamber (precoat process 233 in FIG. 18) is performed. The tantalum nitride layer is formed in a manner similar to the tantalum nitride layer as the gate insulating layer in Embodiment 2. By this treatment, a tantalum nitride layer is formed on the inner wall surface of the processing chamber. Thereafter, the substrate 101 is loaded into the processing chamber (load 231 in Fig. 18).

It is noted that the cleansing process 227 does not have to be performed, which can improve production.

Next, a source gas for depositing the second semiconductor layer 107 is introduced into the processing chamber (instead of the gas 215 in FIG. 18). Then, the second semiconductor layer 107 is formed. Here, as in Embodiment 2, the second semiconductor layer 107 is formed to have a thickness of 150 nm. Thereafter, the plasma discharge is stopped (the formation of the second semiconductor layer 217 in Fig. 18).

In the step of forming the second semiconductor layer 107, when the tantalum nitride layer formed in the processing chamber is exposed to the plasma, the nitrogen gas is dissociated and introduced into the deposited second semiconductor layer 107. Therefore, a mixed layer containing nitrogen and a layer containing an amorphous semiconductor are formed. Moreover, when the tantalum nitride layer is exposed to the plasma, the NH group or the NH ₂ group is formed; therefore, the dangling bonds are cross-linked with the NH group when the second semiconductor layer 107 is deposited. Alternatively, the dangling button can terminate in the NH ₂ group.

In the second semiconductor layer 107 formed by the above method, the nitrogen concentration measured by the secondary ion mass spectrometer is as described in Embodiment 1, and the nitrogen is isolated in the microcrystalline semiconductor region in the initial deposition of the second semiconductor layer 107. Interface. Thereafter, nitrogen is contained in the amorphous semiconductor layer. However, as the second semiconductor layer 107 is deposited, the amount of nitrogen in the processing chamber of the CVD apparatus is reduced. Therefore, after the nitrogen concentration has a peak in the mixed layer 107b, the deposition direction of the layer 107c containing the amorphous semiconductor is reduced.

It is to be noted that, as shown by a broken line 237a of Fig. 18, in the formation of the second semiconductor layer 217, ammonia is supplied to the processing chamber. As shown by the broken line 237b, nitrogen gas substituted for ammonia is supplied. Alternatively, both ammonia and nitrogen are introduced into the processing chamber. Alternatively, nitrogen fluoride, chlorine nitrogen, chloramine, fluoroamine or the like may be supplied to replace ammonia and nitrogen. As a result, the concentration of nitrogen in the second semiconductor layer 107 is increased, so that the dangling bonds of the second semiconductor layer 107 are cross-linked, resulting in a decrease in the number of defects. Alternatively, the dangling bonds of the second semiconductor layer 107 are terminated and the number of defects is reduced.

In the second semiconductor layer 107 formed by the above method, the nitrogen concentration measured by the secondary ion mass spectrometer has a peak value (maximum value) in the mixed layer 107b, and is fixed in the deposition direction of the layer 107c containing the amorphous semiconductor. .

Alternatively, in the formation of the second semiconductor layer 217, a rare gas is used as the source gas as indicated by a broken line 238. As a result, the generation rate of the second semiconductor layer 107 is increased.

Then, these gases are exhausted and a gas for depositing the impurity semiconductor layer 109 is introduced (instead of the substitution gas 219 in Fig. 18). As in the embodiment 1, the impurity semiconductor layer 109 (formation of the impurity semiconductor layer 221 in Fig. 18) is formed. Thereafter, the source gas of the impurity semiconductor layer 109 is exhausted (depletion 223 in FIG. 18).

Through this step, the ammonia introduced into the processing chamber in the precoating treatment is dissociated by the plasma discharge so that the plasma contains nitrogen. Moreover, when the tantalum nitride layer formed on the inner wall of the processing chamber is exposed to the plasma, a portion of the tantalum nitride layer is dissociated to cause nitrogen in the plasma. As a result, the second semiconductor layer may contain nitrogen.

Further, in this example, a nitrogen-containing gas is supplied into the processing chamber where the second semiconductor layer 107 is formed, and a NH group or an NH ₂ group is generated. As described above, the dangling bonds included in the semiconductor layer are cross-linked to the NH group. Moreover, the dangling bonds included in the semiconductor layer may terminate in the NH ₂ group. Therefore, a nitrogen-containing gas is supplied to form the second semiconductor layer 107 in the processing chamber to form a semiconductor layer containing the NH group in which the dangling bonds are cross-linked. Moreover, a semiconductor layer including dangling bonds terminating in the NH ₂ group can be formed. Further, a microcrystalline semiconductor region containing nitrogen is formed in the mixed layer.

In addition, the concentration of nitrogen is controlled and a second semiconductor layer is formed by covering the germanium nitride layer on the inner wall of the processing chamber before forming the second semiconductor layer.

Further, by covering the tantalum nitride layer on the inner wall of the processing chamber, it is possible to prevent elements or the like contained in the inner wall of the processing chamber from being mixed to the second semiconductor layer 107.

It should be noted that, as described above, the processing chamber forming the second semiconductor layer 107 is the same as the processing chamber forming the first semiconductor layer 106, and the clean processing and the pre-coating processing are performed after forming the first semiconductor layer 106; This embodiment can be implemented in combination with any of Embodiments 2 to 4. That is, after the first semiconductor layer 106 is deposited, a tantalum nitride layer is formed in the processing chamber and the rinsing process 213 is further performed.

Through the above steps, a microcrystalline semiconductor region containing nitrogen and an amorphous semiconductor region containing nitrogen are formed. That is, a conical or square pyramidal microcrystalline semiconductor region and a well-ordered semiconductor layer having a sharp defect with a small defect and a valence band edge in the valence band can be formed. As a result, a thin film transistor having a large on-current and a high field-effect mobility and a small off current can be manufactured.

(Example 6)

In the present embodiment, a series of steps from the step of forming the gate insulating layer to the step of forming the impurity semiconductor layer will be described, which can be applied to the embodiments 2 and 3.

In the present embodiment, nitrogen gas as a deposition gas is introduced into the processing chamber in which the second semiconductor layer 107 is formed, and the nitrogen concentration of the second semiconductor layer 107 is controlled. The series of steps from the step of forming the gate insulating layer 105 to the step of forming the first semiconductor layer 106 is similar to that of Embodiment 1. Here, a series of steps from the step of forming the first semiconductor layer 106 to the step of forming the impurity semiconductor layer 109 are as follows with reference to FIG.

The first semiconductor layer 106 is formed on the entire surface of the gate insulating layer 105. First, the gas used to deposit the first semiconductor layer 106 is introduced into the processing chamber. In this example, a microcrystalline germanium layer having a thickness of about 5 nm was formed as the first semiconductor layer 106 in a manner similar to that of the embodiment 1. Thereafter, the plasma discharge is stopped (formation of the first semiconductor layer 211 in Fig. 19). Then, the gas exhausted and the gas for depositing the second semiconductor layer 107 is introduced (the replacement gas 215 in Fig. 19).

Next, a second semiconductor layer 107 is formed. In this example, the source gas was introduced and stabilized, the SiH ₄ flow rate was 30 sccm, the H ₂ flow rate was 1425 sccm, and the 1000 ppm NH ₃ (diluted with hydrogen) flow rate was 25 sccm, the process chamber pressure was 280 Pa, and the substrate temperature was At 280 ° C, the RF power source frequency is 13.56 MHz, and the RF power source output power is 50 W. The plasma discharge is carried out in this case, whereby a second semiconductor layer 107 having a thickness of about 150 nm is formed.

Through this step, the ammonia is dissociated by the plasma discharge so that the plasma contains nitrogen and thus the second semiconductor layer contains nitrogen. In addition, when the NH group is generated in the plasma, dangling bonds are cross-linked when the second semiconductor layer is deposited. Further, when the NH ₂ group is generated in the plasma, the dangling bonds are terminated when the second semiconductor layer is deposited (the formation of the second semiconductor layer 217 in FIG. 19).

Note that as indicated by the dashed line 232, nitrogen may be supplied to the processing chamber to replace ammonia as a nitrogen-containing gas in the formation of the second semiconductor layer 217. Alternatively, both ammonia and nitrogen are supplied to the processing chamber. Alternatively, nitrogen fluoride, chlorine nitrogen, chloramine, fluoroamine or the like may be supplied to replace ammonia and nitrogen. As a result, the concentration of nitrogen in the second semiconductor layer 107 is increased, so that the dangling bonds in the second semiconductor layer 107 are cross-linked, resulting in a decrease in the number of defects. Further, the dangling bonds of the second semiconductor layer 107 are terminated and the number of defects is reduced.

In the second semiconductor layer 107 formed by the above method, the nitrogen concentration measured by the secondary ion mass spectrometer has a peak value (maximum value) in the mixed layer 107b, and is deposited in the deposition direction of the layer 107c containing the amorphous semiconductor. Acridine.

Alternatively, in the formation of the second semiconductor layer 217, a rare gas is used as the source gas as indicated by a broken line 234. As a result, the generation rate of the second semiconductor layer 107 is increased.

Thereafter, these gases are exhausted and a gas for depositing the impurity semiconductor layer 109 is introduced (instead of the substitution gas 219 in Fig. 19). The impurity semiconductor layer 109 is formed in a manner similar to that in Embodiment 2 (the impurity semiconductor layer 221 formed in FIG. 19). Thereafter, the source gas of the impurity semiconductor layer 109 is exhausted (depletion 223 in FIG. 19).

Through the above steps, a microcrystalline semiconductor region containing nitrogen and an amorphous semiconductor region containing nitrogen are formed. That is, a conical or square pyramidal microcrystalline semiconductor region and a well-ordered semiconductor layer having a sharp defect with a small defect and a valence band edge in the valence band can be formed. As a result, a thin film transistor having a large on-current and a high field-effect mobility and a small off current can be manufactured.

(Example 7)

In the present embodiment, a series of steps from the step of forming the gate insulating layer to the step of forming the impurity semiconductor layer will be described with reference to FIG. 20, which can be applied to Embodiments 2 and 3.

In the embodiment, in the method for forming the second semiconductor layer 107, after the first semiconductor layer 211 in the second embodiment is formed, the nitrogen-containing gas is introduced into the processing chamber by the cleaning process 213. Further, a nitrogen-containing gas is again introduced into the processing chamber (i.e., in the formation of the second semiconductor layer 217) in the formation of the second semiconductor layer 107 as shown by the solid line 239a (Fig. 20). Here ammonia acts as a nitrogen-containing gas. As indicated by the broken line 239b, ammonia can be replaced with nitrogen. Alternatively, both ammonia and nitrogen are introduced into the processing chamber. Alternatively, nitrogen fluoride, chlorine nitrogen, chloramine, fluoroamine or the like may be supplied to replace ammonia and nitrogen. As a result, at the initial stage of deposition and at the time of deposition of the second semiconductor layer 107, the nitrogen concentration becomes high so that the number of defects is reduced.

Further, in the method of adding nitrogen to the second semiconductor layer 107, after the formation of the first semiconductor layer 106 in Embodiment 5, a tantalum nitride layer is formed in the processing chamber. Further, in the formation of the second semiconductor layer 107, a nitrogen-containing gas is again introduced into the processing chamber. Here ammonia acts as a nitrogen-containing gas. Nitrogen can also be replaced by nitrogen. Alternatively, both ammonia and nitrogen can be used. Alternatively, nitrogen fluoride, chlorine nitrogen, chloramine, fluoroamine or the like may be supplied to replace ammonia and nitrogen. As a result, at the initial stage of deposition and at the time of deposition of the second semiconductor layer 107, the nitrogen concentration becomes high so that the number of defects is reduced.

Thereafter, these gases are exhausted and a gas for depositing the impurity semiconductor layer 109 is introduced (instead of the substitution gas 219 in Fig. 20). The impurity semiconductor layer 109 is formed in a manner similar to that in Embodiment 2 (the impurity semiconductor layer 221 formed in FIG. 20). Thereafter, the source gas of the impurity semiconductor layer 109 is exhausted (depletion 223 in FIG. 20).

Through the above steps, a microcrystalline semiconductor region containing nitrogen and an amorphous semiconductor region containing nitrogen are formed. That is, a conical or square pyramidal microcrystalline semiconductor region and a well-ordered semiconductor layer having a sharp defect with a small defect and a valence band edge in the valence band can be formed. As a result, a thin film transistor having a large on-current and a high field-effect mobility and a small off current can be manufactured.

(Example 8)

In this embodiment, the channel length of the thin film transistor is less than or equal to 10 μm. One mode that reduces the resistance of the source and drain regions of the thin film transistor will be described below. This is described using Embodiment 1, however this mode can be applied to any other suitable embodiment.

In the case of using a microcrystalline germanium to which phosphorus is added or a microcrystalline germanium to which boron is added to form the impurity semiconductor layer 109, as in the second semiconductor layer 107 shown in FIG. 12B, the microcrystalline semiconductor layer is typically interposed between the mixed layer 107b or The microcrystalline layer between the layer 107c of the amorphous semiconductor and the impurity semiconductor layer 109, whereby the layer having a low density is not formed at the initial stage of deposition of the impurity semiconductor layer 109, and the impurity semiconductor layer 109 can be combined with the crystallite as a seed crystal The semiconductor layer grows, and therefore, the interface characteristics can be improved. As a result, the electrical resistance between the interface between the impurity semiconductor layer 109 and the mixed layer 107b or the layer 107c containing the amorphous semiconductor can be lowered. Accordingly, the amount of current flowing through the source region, the semiconductor layer, and the drain region of the thin film transistor is increased and the on current and the field effect mobility can be increased.

(Example 9)

In the present embodiment, the element substrate and the display device including the element substrate to which any of Embodiments 1 to 8 are applied will be described below. The display device is exemplified as a liquid crystal display device, a light-emitting display device, an electronic paper, and the like. The thin film transistor described in any of the above embodiments can be used as an element substrate of any other display device. A liquid crystal display device including the thin film transistor described in Embodiment 1 herein, which is typically a vertical alignment (VA) mode liquid crystal display device, will be described with reference to FIGS. 25 and 26.

Fig. 25 is a cross-sectional view showing a pixel portion of a liquid crystal display device. The thin film transistor 303 and the capacitor 305 fabricated by any of the above embodiments are formed on the substrate 301. Further, a pixel electrode 309 is formed on the insulating layer 308 on the thin film transistor 303. The source or drain electrode 307 of the thin film transistor 303 and the pixel electrode 309 are connected to each other in an opening formed in the insulating layer 308. The alignment film 311 is formed on the pixel electrode 309.

The capacitor 305 includes a capacitor wiring 304, a gate insulating layer 306, and a pixel electrode 309 which are formed simultaneously with the gate electrode 302 of the thin film transistor 303.

The stack including the components from the substrate 301 to the alignment film 311 is referred to as an element substrate 313.

The anti-substrate 321 has a colored layer 325 and a light shielding layer 323 for blocking light incident on the thin film transistor 303. Further, a planarization layer 327 is formed on the light shielding layer 323 and the coloring layer 325. The counter electrode 329 is formed on the planarization layer 327 and the alignment film 331 is formed on the counter electrode 329.

It should be noted that the light shielding layer 323, the colored layer 325, and the planarization layer 327 on the counter substrate 321 function as a filter. It should be noted that one or both of the light shielding layer 323 and the planarization layer 327 need not be formed on the counter substrate 321 .

The filter layer has a function of preferentially transmitting light of a predetermined wavelength range in the light wave range of visible light. In general, a filter layer that preferentially transmits light of a red wavelength range, a filter layer that preferentially transmits light of a blue wavelength range, and a filter layer that preferentially transmits light of a green wavelength range are used in combination as a filter. . However, the filter layer combination is not limited to the above combination.

The substrate 301 and the counter substrate 321 are fixed to each other by a sealing material (not shown), and the liquid crystal layer 343 is filled in a space surrounded by the space of the substrate 301, the counter substrate 321 and the sealing material. In addition, the spacer 341 is used to keep the substrate 301 and the counter substrate 321 at a distance.

The pixel electrode 309, the liquid crystal layer 343, and the counter electrode 329 overlap each other to form a liquid crystal element.

The liquid crystal display device shown in Fig. 26 is different from the liquid crystal display device shown in Fig. 25. Here, the filter layer is not formed on the counter substrate 321 but on the substrate 301 having the thin film transistor 303.

Fig. 26 is a cross-sectional view showing a pixel portion of a liquid crystal display device. The thin film transistor 303 and the capacitor 305 fabricated by any of the above embodiments are formed on the substrate 301.

Further, a filter layer 351 is formed on the insulating layer 308 on the thin film transistor 303. Further, a protective layer 353 is formed on the filter layer 351 to prevent impurities contained in the filter layer 351 from being mixed into the liquid crystal layer 343. The pixel electrode 309 is formed on the filter layer 351 and the protective layer 353. As the filter layer 351, each pixel can form a layer having a function of preferentially transmitting light of a predetermined wavelength range (red light, blue light, or green light). Moreover, since the filter layer 351 also has a function of a planarization layer, uneven alignment of the liquid crystal layer 343 can be suppressed.

The source or drain electrode 307 of the thin film transistor 303 and the pixel electrode 309 are connected to each other in an opening formed in the insulating layer 308, the filter layer 351, and the protective layer 353. The alignment film 311 is formed on the pixel electrode 309.

The capacitor 305 includes a capacitor wiring 304, a gate insulating layer 306, and a pixel electrode 309 which are formed simultaneously with the gate electrode 302 of the thin film transistor 303.

The stack including the components from the substrate 301 to the alignment film 311 is referred to as an element substrate 355.

The counter substrate 321 has a light shielding layer 323 for blocking light incident on the thin film transistor 303 and a planarization layer 327 covering the light shielding layer 323 and the counter substrate 321 . The counter electrode 329 is formed on the planarization layer 327, and the alignment film 331 is formed on the counter electrode 329.

The pixel electrode 309, the liquid crystal layer 343, and the counter electrode 329 overlap each other to form a liquid crystal element.

It should be noted that although the VA mode liquid crystal display device is used herein as a liquid crystal display device, the present invention is not limited thereto. That is, the element substrate formed using the thin film transistor according to Embodiment 1 can be applied to an FFS mode liquid crystal display device, an IPS mode liquid crystal display device, a TN mode liquid crystal display device, and other mode liquid crystal display devices.

In the liquid crystal display device of the present embodiment, the thin film transistor having a large on-current, a high field-effect mobility, and a small off current is used as a pixel transistor, and the image quality of the liquid crystal display device can be improved. Further, even when the thin film transistor is shrunk, the electrical properties of the thin film transistor are not lowered; therefore, the aperture ratio of the liquid crystal display device is increased by reducing the area of the thin film transistor. In addition, the pixel area can be reduced to improve the resolution of the liquid crystal display device.

Further, as shown in the liquid crystal display device of Fig. 26, the light shielding layer 323 and the filter layer 351 are not formed on the same substrate. Therefore, the mask misalignment in the filter layer 351 can be prevented from being formed. Accordingly, it is not necessary to increase the area of the light shielding layer 323 which increases the pixel aperture ratio.

(Embodiment 10)

The element substrate 313 described in Embodiment 9 can be used as a light-emitting display device or a light-emitting device by providing a light-emitting element in which the alignment film 311 is not formed. In the light-emitting display device or the light-emitting device, a light-emitting element utilizing electroluminescence is used as a typical light-emitting element. The luminescent elements utilizing electroluminescence are classified according to whether the luminescent material is an organic component or an inorganic component. Generally, the former refers to an organic EL element and the latter refers to an inorganic EL element.

In the light-emitting display device or the light-emitting device of the embodiment, the thin film transistor having a large on-current and a high field-effect mobility and a small off current is used as a pixel transistor; therefore, the light-emitting display device or the light-emitting device may have better Image quality (eg, high contrast) and low power consumption.

(Example 11)

A display device including the thin film transistor according to any of the above embodiments can be applied to various electronic devices (including entertainment machines). The electronic device is, for example, a television device (also referred to as a television or television receiver), a computer screen or the like, an electronic paper, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone). Device), portable game machine, portable information terminal, sound reproduction device, large game machine such as Pachinko machine and the like. In particular, as described in Embodiments 9 and 10, the thin film transistor according to any of the above embodiments can be applied to a liquid crystal display device, a light-emitting device, an electrophoretic display device or the like, and thus can be used as a display portion of the electronic device. A clear example is as follows.

A semiconductor device including the thin film transistor according to any of the above embodiments can be applied to electronic paper. Electronic paper can be used for electronic devices used in various fields as long as the information can be displayed. For example, electronic paper can be applied to e-book devices, posters, advertisements on vehicles such as trains, digital signage, public information displays (PIDs), various card displays such as credit cards, and the like. Examples of these electronic devices are shown in Figures 27A through 27D.

Fig. 27A shows an example of an electronic book device. For example, the e-book device includes two housings, a housing 1700 and a housing 1701. The housing 1700 is combined with the housing 1701 in a hinge 1704 to allow the e-book device to be opened and closed. With this arrangement, the e-book device can operate as a book on paper.

The display portion 1702 and the display portion 1703 are included in the housing 1700 and the housing 1701, respectively. Display portion 1702 and display portion 1703 can be configured to display an image or a different image. In the case where the display portion 1702 and the display portion 1703 display different images, for example, the display portion on the right side (the display portion 1702 in FIG. 27A) displays characters and the display portion on the left side (display portion 1703 in FIG. 27A) displays a pattern.

Fig. 27A shows an example of a housing 1700 having an operating portion and the like. For example, the housing 1700 has a power source 1705, an operation key 1706, a speaker 1707, and the like. The page can be flipped by operating the key 1706. It should be noted that the keyboard, the pointing device and the like can be disposed on the same plane as the display portion of the housing. The external connection terminal (headphone terminal, USB terminal, connectable to a terminal including an AC adapter and a USB cable or the like), a recording medium insertion portion or the like may be provided on the back or side of the casing. Moreover, the e-book device can have an electronic dictionary function.

The e-book device can transmit and receive data wirelessly. Via wireless transmission, the desired book material or the like can be purchased and downloaded from the e-book server.

Fig. 27B shows an example of a digital photo frame. For example, in the digital photo frame, the display portion 1712 is included in the housing 1711. Various images can be displayed on the display portion 1712. For example, the display portion 1712 can display image data captured by a digital camera or the like as a normal photo frame function.

The digital photo frame has an operation portion, an external connection portion (a USB terminal, a terminal connectable to a USB cable or the like), a recording medium insertion portion, or the like. Although these components can be located on the surface of the display area, it is better to design the digital photo frame on the side or back of the digital photo frame. For example, the memory storing the image data obtained by the digital camera is inserted into the recording medium insertion portion of the digital photo frame, and the image data is transmitted and displayed on the display portion 1712.

The digital photo frame can be configured to wirelessly transmit and receive data. With this architecture, desired image data can be displayed wirelessly.

Fig. 27C shows an example of a television device. In the television device, the display portion 1722 is included in the housing 1721. The display portion 1722 can display an image. Moreover, the housing 1721 is supported by the bracket 1723. The display device of Embodiment 9 or 10 can be applied to the display portion 1722.

The television set can be operated by an operation of the housing 1721 or a separate remote control. The channel or volume can be controlled by the operation of the remote control to control the image displayed on the display portion 1722. Alternatively, the remote controller may have a display portion for displaying data output from the remote controller.

It should be noted that the television device has a receiver, a data machine and the like. A general television broadcast is received by using a receiver. Moreover, when the display device is connected to the communication network via the cable via the cable, either unidirectional (from transmitter to receiver) or bidirectional (between the transmitter and the receiver or between the receivers) ) Data communication can be carried out.

An example of a mobile phone is shown in Fig. 27D. The mobile phone has a display portion 1732, an operation key 1733, an operation key 1737, an external connection port 1734, a speaker 1735, a microphone 1736, and the like included in the housing 1731. Any of the display devices described in Embodiment 9 or 10 can be applied to the display portion 1732.

The display portion 1732 of the mobile phone shown in Fig. 27D is a touch screen. When the display portion 1732 is touched by a finger or the like, the content displayed on the display portion 1732 can be controlled. Further, an operation such as dialing or editing a mail can be performed by touching the display portion 1732 with a finger or the like.

The display portion 1732 mainly has three picture modes. The first mode is a display mode for displaying an image. The second mode is an input mode mainly for inputting information such as text. The third mode is a display-and-input mode in which the display mode is mixed with the input mode.

For example, in an example of dialing or editing a mail, the display portion 1732 selects a character input mode for inputting text so that characters displayed on the screen can be input. In this example, it is preferred to display a keyboard or numeric button on a large area of the screen of display portion 1732.

When the mobile phone has a detecting device for detecting a tilt sensor such as a gyroscope or an acceleration sensor, the display data of the display portion 1732 can be automatically switched by determining the position of the mobile phone (the mobile phone is Landscape mode or portrait mode placed horizontally or vertically).

The picture mode is switched by touching the display portion 1732 or using the operation keys 1737 of the housing 1731. Alternatively, the picture mode can be switched depending on the type of image displayed on the display portion. For example, when the signal displayed on the image of the display portion 1732 is one of the moving image data, the picture mode can be switched to the display mode. When the signal is one of the text data, the picture mode can be switched to the input mode.

In addition, in the input mode, when a signal is detected by the light sensor of the display portion 1732, when the input of the touch display portion 1732 is not performed for a period of time, the picture mode is controlled to switch from the input mode. To display mode.

Display portion 1732 can function as an image sensor. For example, when the display portion 1732 is touched by a palm or a finger, an image of a palm print, a fingerprint, or the like is taken by the image sensor, thereby performing identity authentication. Further, an image of a finger vein, a palm vein or the like can be obtained by providing a backlight or a sensing light source that emits near-infrared light at a display portion.

This embodiment can be implemented in combination with any of the structures described in other embodiments.

[example 1]

In this example, the cross-sectional structure including the insulating layer, the microcrystalline semiconductor layer, the mixed layer, and the layer containing the amorphous semiconductor and the impurity element concentration in the structure will be described with reference to FIGS. 21, 22, 23, and 24.

The method of forming a sample will be described below.

An antimony oxide layer as an insulating layer was formed on the glass substrate (AN100 manufactured by Asahi Glass Co., Ltd.).

Here, the tantalum oxide layer having a thickness of 100 nm is formed by a plasma CVD method. The deposition conditions were as follows: the source gas was introduced and stabilized, the flow rate of tetraethoxy decane (TEOS) was 15 sccm and the oxygen flow rate was 750 sccm, the pressure in the processing chamber was 100 Pa, the temperature of the upper electrode was 300 ° C, and the temperature of the lower electrode was At 297 ° C, the RF power source frequency is 27 MHz, the RF power source power is 300 W, and plasma discharge is performed.

Next, the microcrystalline semiconductor layer, the mixed layer, and the layer containing the amorphous semiconductor are sequentially formed on the insulating layer.

Here, a microcrystalline germanium layer having a thickness of 5 nm was formed as a microcrystalline semiconductor layer. The deposition conditions were as follows: as the source gas, the SiH ₄ flow rate was 10 sccm, the H ₂ flow rate was 1500 sccm, the processing chamber pressure was 280 Pa, the substrate temperature was 280 ° C, the RF power source frequency was 13.56 MHz, and the RF power source power was 50W, the plasma discharge is implemented.

Then, a mixed layer and a layer containing an amorphous semiconductor are formed on the microcrystalline semiconductor layer. In this example, the ruthenium layer containing nitrogen is formed as a mixed layer and a layer containing an amorphous semiconductor at a thickness of 145 nm. The deposition conditions were as follows: as the source gas, the SiH ₄ flow rate was 20 sccm, the H ₂ flow rate was 1475 sccm, and the 1000 ppm NH ₃ (diluted with hydrogen) flow rate was 25 sccm, the processing chamber pressure was 280 Pa, and the substrate temperature was 280 ° C. The RF power source frequency is 13.56 MHz, and the RF power source power is 50 W. Plasma discharge is implemented.

Note that when the ruthenium layer containing nitrogen is deposited on the microcrystalline semiconductor layer under the above conditions, the crystal growth is performed using the microcrystalline semiconductor layer as a seed crystal at the initial stage of deposition. However, the degree of crystallinity is suppressed by the nitrogen of NH ₃ contained in the source gas, and the amorphous semiconductor region is gradually increased. The layer including the microcrystalline semiconductor region becomes a mixed layer, and the crystal does not grow therein and the layer including only the amorphous semiconductor region becomes a layer containing the amorphous semiconductor.

As the protective layer, an amorphous germanium layer having a thickness of 100 nm is formed on a layer containing an amorphous semiconductor. At this time, the deposition conditions were as follows: as the source gas, the flow rate of SiH ₄ was 280 sccm, the flow rate of H ₂ was 300 sccm, the deposition temperature was 280 ° C, the pressure was 170 Pa, the frequency of the RF power source was 13.56 MHz, and the power of the RF power source was 60 W. Slurry discharge.

Figure 21 is a cross-sectional view of a transmission electron microscope (TEM) of the above sample subjected to ion milling and superimposing the results of measuring the impurity element concentration by SIMS. Fig. 22 is an enlarged view showing the microcrystalline semiconductor layer, the mixed layer, and the layer containing the amorphous semiconductor shown in Fig. 21. In Figures 21 and 22, the surface of the protective layer is illuminated by the original ions and thus SIMS measurements are performed.

In this embodiment, a quadrupole mass analyzer PHI ADEPT-1010 manufactured by ULVAC-PHI Incorporated is used as a SIMS measuring device. Further, irradiation with Cs+ as the original ion was performed with an acceleration voltage of 3 kV.

In Figs. 21 and 22, the horizontal axis represents the depth and the left vertical axis represents the concentrations of hydrogen, carbon, nitrogen, oxygen, and fluorine. The vertical axis on the right represents the secondary ion intensity of erbium.

As for the horizontal axis, a portion having a depth of 0 nm to a depth of 100 nm corresponds to the protective layer 167, and a portion having a depth of 100 nm to a depth of about 245 nm substantially corresponds to a region 165 formed under the deposition condition of the layer containing the amorphous semiconductor and the mixed layer, and the depth is A portion from 245 nm to a depth of 250 nm corresponds to the microcrystalline semiconductor layer 163, and has a depth of 250 nm to the right side of the figure corresponding to the insulating layer 161.

According to Fig. 22, lattice fringes were observed in the region of the TEM image from a depth of 225 nm to a depth of about 250 nm, and it was found that the microcrystalline semiconductor region was formed therein. Furthermore, according to the SIMS measurement results, the nitrogen concentration profile has a maximum at a depth of about 240 nm. The reason is as follows. Under the conditions of the layer containing the amorphous semiconductor and the mixed layer, that is, under the condition that the surrounding environment contains nitrogen which inhibits the crystallinity, although the crystal growth in the initial stage of deposition uses the microcrystalline semiconductor layer as the seed crystal, nitrogen is unlikely. Introduced into the microcrystalline semiconductor region; therefore, the concentration of nitrogen in the microcrystalline semiconductor region is low. However, when the crystal grows, the concentration of nitrogen that is not absorbed by the microcrystalline semiconductor region increases, crystal growth is suppressed and the amorphous semiconductor region is formed; therefore, nitrogen is interposed between different microcrystalline semiconductor regions, between the microcrystalline semiconductor region and the amorphous semiconductor. The interface of the zone is precipitated, causing an increase in nitrogen concentration. Since the amorphous semiconductor region contains nitrogen, the nitrogen concentration is a constant value in the region where the crystal does not grow (this is 1 × 10 ²⁰ atoms/cm ³ ), that is, a region containing only the amorphous semiconductor region.

Further, the hydrogen concentration gradually increases from a depth of about 242 nm, showing that the amorphous semiconductor region is gradually increased. Further, since the hydrogen concentration is constant from the depth 213 nm (this is 4 × 10 ²¹ atoms/cm ³ ), the microcrystalline semiconductor region is not formed and the amorphous semiconductor region is formed.

In the microcrystalline semiconductor region, the proportion of bonded germanium atoms is high, and thus the hydrogen concentration is low. On the other hand, in the amorphous semiconductor region, the proportion of bonded germanium atoms is low and the number of dangling bonds of germanium is larger than that of the microcrystalline semiconductor region. Hydrogen bonding is in the dangling bond, and the hydrogen concentration becomes higher in the amorphous semiconductor region. According to the above, the gradual increase in the hydrogen concentration of the concentration profile obtained by SIMS shows a decrease in crystallinity. In addition, the fixed hydrogen concentration indicates the formation of an amorphous semiconductor region. That is, the degree of crystallinity gradually decreases from the interface between the insulating layer and the microcrystalline semiconductor layer to the interface between the microcrystalline semiconductor layer and the mixed layer. And the layer containing the amorphous semiconductor contains an amorphous semiconductor region.

The carbon concentration in the region from 225 nm to 250 nm in depth is about 3×10 ¹⁷ atoms/cm ³ to 7×10 ¹⁹ atoms/cm ³ , and the concentration in the region from 131 nm to 225 nm is about 5×10 ¹⁶ atoms/cm ^{3 .} Up to 3 × 10 ¹⁷ atoms / cm ₃ .

The oxygen concentration in the region from 225 nm to 250 nm in depth is about 2×10 ¹⁷ atoms/cm ³ to 2×10 ¹⁹ atoms/cm ³ , and the concentration in the region from 131 nm to 225 nm is about 4×10 ¹⁶ atoms/cm ^{3 .} Up to 3 × 10 ¹⁷ atoms / cm ³ .

The concentration of fluorine in the region from 225 nm to 250 nm in depth is about 6×10 ¹⁶ atoms/cm ³ to 4×10 ¹⁷ atoms/cm ³ , and the concentration in the region from 131 nm to 225 nm is about 3×10 ¹⁶ atoms/cm ^{3 .} Up to 6 × 10 ¹⁶ atoms / cm ³ .

Next, Fig. 23 shows the results of observing the sample using TEM and superimposing the results of measuring the impurity element concentration by SSDP-SIMS (substrate side depth profile-SIMS). Fig. 24 is an enlarged view showing the microcrystalline semiconductor layer, the mixed layer, and the layer containing the amorphous semiconductor shown in Fig. 23. In Figures 23 and 24, the sample was measured by SSDP-SIMS, the surface of the substrate was illuminated with the original ions and thus SIMS measurements were performed. This measurement is performed to check whether the phenomenon in which the elements on the surface on the surface side are diffused to the substrate (impact effect) lowers the resolution, and the impurity element concentration measurement accuracy, particularly in the mixed layer.

The TEM image is the same as FIG. 21 and FIG. 22; therefore, the SSDP-SIMS measurement results are described herein. It should be noted that the vertical axis and the horizontal axis are the same as those of Figs. 21 and 22.

According to Fig. 24, since the lattice fringes are observed in a region of a depth of about 225 nm to a depth of 250 nm in the TEM image, it is understood that the crystal region is formed. Further, according to the SSDP-SIMS measurement result of Fig. 24, the nitrogen concentration profile has a maximum at a depth of 237 nm. Since the amorphous structure contains nitrogen, the nitrogen concentration is fixed in the region where the crystal does not grow (this is 1 × 10 ²⁰ atoms/cm ³ ), that is, a region containing only the amorphous structure.

In addition, the hydrogen concentration gradually increases from a depth of about 247 nm. Further, the hydrogen concentration was constant from a depth of 212 nm (this is 4 × 10 ²¹ atoms/cm ³ ).

The carbon concentration in the region from 225 nm to 247 nm in depth is about 1×10 ¹⁸ atoms/cm ³ to 2×10 ¹⁹ atoms/cm ³ , and the concentration in the region from 134 nm to 225 nm is about 2×10 ¹⁷ atoms/cm ^{3 .} Up to 1 × 10 ¹⁸ atoms / cm ³ .

The oxygen concentration in the region from 225 nm to 247 nm in depth is about 2×10 ²⁰ atoms/cm ³ to 4×10 ²¹ atoms/cm ³ , and the concentration in the region from 134 nm to 225 nm is about 8×10 ¹⁸ atoms/cm ^{3 .} Up to 2 × 10 ²⁰ atoms / cm ³ .

The concentration of fluorine in the region from 225 nm to 247 nm in depth is about 4×10 ¹⁷ atoms/cm ³ to 8×10 ¹⁷ atoms/cm ³ , and the concentration in the region from 134 nm to 225 nm is about 1×10 ¹⁷ atoms/cm ^{3 .} Up to 4 × 10 ¹⁷ atoms / cm ³ .

In Fig. 24, the oxygen, carbon, and fluorine concentrations are higher than those in Fig. 22 due to the impact effect. However, the nitrogen and hydrogen concentrations are the same as the maximum values of the nitrogen profile and Figs. 22 and 24. Accordingly, in the microcrystalline semiconductor layer, the mixed layer, and the layer containing the amorphous semiconductor described in this example, the nitrogen concentration profile has the maximum concentration in the mixed layer and is constant in the layer containing the amorphous semiconductor. Further, the microcrystalline semiconductor region contained in the mixed layer is contained in a mixed layer containing a nitrogen concentration of 1 × 10 ²⁰ atoms / cm ³ to 2 × 10 ²¹ atoms / cm ³ . Further, the layer containing the amorphous semiconductor contains nitrogen of 1 × 10 ²⁰ atoms/cm ³ .

The present application is based on Japanese Patent Application No. 2009-055549, filed on-

101. . . Substrate

103. . . Gate electrode

105. . . Brake insulation

106. . . Semiconductor layer

107. . . Semiconductor layer

109. . . Impurity semiconductor layer

111. . . Conductive layer

113. . . Photoresist mask

115. . . Semiconductor layer

117. . . Impurity semiconductor layer

119. . . Conductive layer

123. . . Photoresist mask

125. . . wiring

127. . . Impurity semiconductor layer

133. . . wiring

141. . . Crystal nucleus

145. . . Nitrogen atom

147. . . Oxygen atom

161. . . Insulation

163. . . Microcrystalline semiconductor layer

165. . . region

167. . . The protective layer

180. . . Gray dimmer

181. . . Optical transmission substrate

182. . . Shading

183. . . Diffraction grating

185. . . Halftone mask

186. . . Optical transmission substrate

187. . . Semi-transparent part

188. . . Shading

201. . . Pretreatment

203. . . Forming SiN

205. . . Gas replacement

207. . . Forming SiON

209. . . Gas replacement

211. . . Forming a first semiconductor layer

213. . . Cleaning treatment

215. . . Gas replacement

217. . . Forming a second semiconductor layer

219. . . Gas replacement

221. . . Forming an impurity semiconductor layer

223. . . Run out

225. . . Uninstall

227. . . Clean treatment

229. . . Pre-coating treatment

231. . . Load

232. . . dotted line

233. . . Pre-coating treatment

234. . . dotted line

236. . . dotted line

238. . . dotted line

301. . . Substrate

302. . . Gate electrode

303. . . Thin film transistor

304. . . Capacitor wiring

305. . . capacitance

306. . . Brake insulation

307. . . Bipolar electrode

308. . . Insulation

309. . . Pixel electrode

311. . . Orientation film

313. . . Element substrate

321. . . Counter substrate

323. . . Shading layer

325. . . Colored layer

327. . . Flattening layer

329. . . Counter electrode

331. . . Orientation film

341. . . Spacer

343. . . Liquid crystal layer

351. . . Filter layer

353. . . The protective layer

355. . . Element substrate

107b. . . Mixed layer

107c. . . Layer containing amorphous semiconductor

108a. . . Microcrystalline semiconductor region

108b. . . Amorphous semiconductor region

108c. . . Microcrystalline semiconductor region

115a. . . Microcrystalline semiconductor layer

115b. . . Mixed layer

115c. . . Layer containing amorphous semiconductor

129c. . . Layer containing amorphous semiconductor

129d. . . Amorphous semiconductor layer

151a. . . Growing area

151b. . . Growing area

153a. . . Growing area

153b. . . Growing area

155a. . . Growing area

155b. . . Growing area

1700. . . case

1702. . . Display area

1703. . . Display area

1704. . . hub

1705. . . power supply

1706. . . Operation key

1707. . . speaker

1711. . . case

1712. . . Display area

1721. . . case

1722. . . Display area

1723. . . support

1731. . . case

1732. . . Display area

1733. . . Operation key

1734. . . External connection埠

1735. . . speaker

1736. . . microphone

1737. . . Operation key

235a. . . dotted line

235b. . . dotted line

237a. . . dotted line

237b. . . dotted line

239a. . . solid line

239b. . . dotted line

Figure 1 shows a cross-sectional view of a thin film transistor.

2A and 2B are cross-sectional views of a thin film transistor, respectively.

Figure 3 shows a cross-sectional view of a thin film transistor.

4A and 4B are cross-sectional views of a thin film transistor, respectively.

Figure 5 shows a semiconductor layer of a thin film transistor.

Figure 6 shows a semiconductor layer of a thin film transistor.

Figure 7 shows a semiconductor layer of a thin film transistor.

8A to 8C show a semiconductor layer of a thin film transistor.

9A to 9C show a semiconductor layer of a thin film transistor.

10A to 10C show a semiconductor layer of a thin film transistor.

11A to 11C show a semiconductor layer of a thin film transistor.

12A to 12C are cross-sectional views showing a method for fabricating a thin film transistor.

13A to 13C are cross-sectional views showing a method for fabricating a thin film transistor.

14A-1 to 14B-2 show a multi-segment mask applied to a method of manufacturing a thin film transistor.

15A to 15C are cross-sectional views showing a method for fabricating a thin film transistor.

16A and 16B are cross-sectional views showing a method for fabricating a thin film transistor.

Figure 17 is a timing diagram showing the process of fabricating a thin film transistor.

Figure 18 is a timing diagram showing the process of fabricating a thin film transistor.

Figure 19 is a timing diagram showing the process of fabricating a thin film transistor.

Figure 20 is a timing diagram showing the process of fabricating a thin film transistor.

Figure 21 shows the SIMS measurement results.

Figure 22 shows the SIMS measurement results.

Figure 23 shows the SIMS measurement results.

Figure 24 shows the SIMS measurement results.

Figure 25 is a cross-sectional view of the display device.

Figure 26 is a cross-sectional view of the display device.

27A to 27D show an electronic device to which a thin film transistor is applied.

28A to 28D show a semiconductor layer of a thin film transistor

101. . . Substrate

103. . . Gate electrode

105. . . Brake insulation

115. . . Semiconductor layer

115a. . . Microcrystalline semiconductor layer

115b. . . Mixed layer

125. . . wiring

127. . . Impurity semiconductor layer

129c. . . Layer of amorphous semiconductor

Claims (12)

A thin film transistor comprising: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a semiconductor layer on the gate insulating layer and in contact therewith; and an impurity semiconductor layer configured to form a source region and a drain region, which is located on and in contact with a portion of the semiconductor layer, wherein a side view of the concentration of nitrogen in the semiconductor layer obtained by SIMS increases from the side of the gate insulating layer toward the impurity semiconductor layer The maximum concentration is reached and then decreased, and wherein the maximum concentration is greater than or equal to 1 x 10 ²⁰ atoms/cm ³ and less than or equal to 1 x 10 ²¹ atoms/cm ³ . The thin film transistor of claim 1, wherein the region of the semiconductor layer having the largest concentration is closer to the gate insulating layer than to the impurity semiconductor layer. A thin film transistor comprising: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a semiconductor layer on the gate insulating layer and in contact therewith; and an impurity semiconductor layer configured to form a source region and a drain region, which is located on and in contact with a portion of the semiconductor layer, wherein a side view of the concentration of nitrogen in the semiconductor layer obtained by SIMS increases from the side of the gate insulating layer toward the impurity semiconductor layer The maximum concentration is reached and then maintained at a substantially constant value, and wherein the maximum concentration is greater than or equal to 1 x 10 ²⁰ atoms/cm ³ and less than or equal to 1 x 10 ²¹ atoms/cm ³ . A thin film transistor comprising: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a microcrystalline semiconductor layer on the gate insulating layer and in contact therewith; being located on the microcrystalline semiconductor layer a mixed layer contacting; a first layer containing an amorphous semiconductor on and in contact with the mixed layer; and a pair of impurity semiconductor layers formed on the first layer containing the amorphous semiconductor; wherein a nitrogen concentration is The first layer of the microcrystalline semiconductor layer containing the amorphous semiconductor from the side of the gate insulating layer is increased, wherein the nitrogen concentration has a maximum concentration in the mixed layer, wherein the nitrogen concentration is in the first layer containing the amorphous semiconductor The layer has a substantially fixed value, and wherein the maximum concentration is greater than or equal to 1 x 10 ²⁰ atoms/cm ³ and less than or equal to 1 x 10 ²¹ atoms/cm ³ . A thin film transistor comprising: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a microcrystalline semiconductor layer on the gate insulating layer and in contact therewith; located on the microcrystalline semiconductor layer and facing a mixed layer contacting; a first layer containing an amorphous semiconductor on and in contact with the mixed layer; and a pair of impurity semiconductor layers formed on the first layer containing the amorphous semiconductor; wherein a nitrogen concentration is The first layer of the microcrystalline semiconductor layer containing the amorphous semiconductor from the side of the gate insulating layer is increased, wherein the nitrogen concentration has a substantially fixed value in the first layer containing the amorphous semiconductor and is in the mixed layer There is a maximum concentration, and wherein the maximum concentration is greater than or equal to 1 × 10 ²⁰ atoms / cm ³ and less than or equal to 1 × 10 ²¹ atoms / cm ³ . A thin film transistor comprising: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a microcrystalline semiconductor layer on the gate insulating layer and in contact therewith; being located on the microcrystalline semiconductor layer a mixed layer contacting; a first layer containing an amorphous semiconductor on and in contact with the mixed layer; and a pair of impurity semiconductor layers formed on the first layer containing the amorphous semiconductor; wherein a nitrogen concentration is The first layer of the microcrystalline semiconductor layer containing the amorphous semiconductor from the side of the gate insulating layer is increased, wherein the nitrogen concentration has a maximum concentration in the mixed layer, wherein the nitrogen concentration is in the first layer containing the amorphous semiconductor One layer is reduced toward the pair of impurity semiconductor layers, and wherein the maximum concentration is greater than or equal to 1 × 10 ²⁰ atoms / cm ³ and less than or equal to 1 × 10 ²¹ atoms / cm ³ . The thin film transistor according to any one of claims 4 to 6, wherein the mixed layer comprises an amorphous semiconductor region and a microcrystalline semiconductor region. The thin film transistor of claim 7, wherein the microcrystalline semiconductor region comprises a semiconductor crystal having a diameter greater than or equal to 1 nm and less than or equal to 10 nm. The thin film transistor of claim 7, wherein the microcrystalline semiconductor region has a conical or square pyramid shape. The thin film transistor of claim 7, wherein the microcrystalline semiconductor region comprises a conical or square pyramid microcrystalline semiconductor region and a semiconductor crystal having a diameter greater than or equal to 1 nm and less than or equal to 10 nm. The thin film transistor of claim 7, wherein the microcrystalline semiconductor region comprises a conical or square pyramid microcrystalline semiconductor region, wherein a width of the conical or square pyramid microcrystalline semiconductor region is from the gate insulating layer laterally The impurity semiconductor layer is reduced. The thin film transistor according to any one of claims 4 to 6, wherein the nitrogen concentration is obtained by SIMS.