TWI484604B - Metal thermal interface materials and packaged semiconductors comprising the materials - Google Patents
Metal thermal interface materials and packaged semiconductors comprising the materials Download PDFInfo
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/4809—Loop shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Description
本發明是有關於一種適合用作為熱界面材料的金屬熱界面材料，以及使用前述金屬熱界面材料的構裝半導體。The present invention relates to a metal thermal interface material suitable for use as a thermal interface material, and a fabricated semiconductor using the foregoing metal thermal interface material.
構裝半導體，例如高亮度發光二極體、功率絕緣柵電晶體、繪圖晶片和中央處理器等，運作產生越來越高的熱流密度或需要在嚴苛高溫環境下運作，內部產生不均、越來越高的熱流密度，前述熱流密度必須被移除，使構裝半導體的運作溫度低於其最大接面溫度(maximum junction temperature)。為解決前述晶片過熱問題，構裝半導體技術除了朝向多核心、動態電壓/頻率調整或者積體線路微縮化，以減少其運作時產生的熱能；另外，也可應用高散熱性能的散熱元件以及低界面熱阻(或稱熱阻抗，thermal impedance)的熱界面材料，提高構裝半導體的散熱性能，後者是一較簡易可行的解決方案。Semiconductors, such as high-brightness light-emitting diodes, power-insulated gate transistors, graphics chips, and central processing units, operate at higher or higher heat flux densities or require operation in harsh high-temperature environments, resulting in uneven internals. With increasing heat flux density, the aforementioned heat flux density must be removed such that the operating temperature of the fabricated semiconductor is below its maximum junction temperature. In order to solve the above-mentioned wafer overheating problem, the packaged semiconductor technology is not only oriented toward multi-core, dynamic voltage/frequency adjustment or integrated circuit miniaturization to reduce the heat energy generated during its operation; in addition, it can also apply heat dissipation components with low heat dissipation performance and low The thermal interface material of the interface thermal resistance (or thermal impedance) improves the heat dissipation performance of the packaged semiconductor, and the latter is a simple and feasible solution.
熱界面材料應用於構裝半導體的的位置包含，例如構裝積體電路內部的積體電路裸晶(IC die)以及其均熱封蓋元件(heat spreader lid)之間的第一階熱界面，以及構裝積體電路外部的均熱封蓋元件與散熱器之間的第二階熱界面。導熱膏以及低熔點合金是目前所有熱界面材料當中，具有低界面熱阻性能。然而，導熱膏被發現不適用於高熱流密度的構裝半導體，主要原因是其膏狀流體容易固化，致劣化其界面導熱性能，又 或者構裝半導體不同功率運作時的循環熱應力，促使導熱膏因為該循環熱應力被壓擠出熱界面。適合用於熱界面的低熔點合金，具有在該界面從固態轉變為呈奶油狀的相變化特性，又或者在固態狀態即呈現該奶油狀，容易變形使填補界面表面的微孔隙，例如純銦。在室溫為固態的低熔點合金，在熱界面上因為溫度擾動所產生的熔解/凝固反應促成大量吸收與釋放通過界面的熱能，因此具有比導熱膏更低的界面熱阻。習知低熔點合金大部分是共晶合金、接近共晶組成的合金，以及極少數的純金屬，例如純銦。基於共晶組成的緣故，該習知低熔點合金的熔解溫度範圍相當狹窄。熔點低於純銦熔點的習知低熔點合金受限於共晶組成的共晶溫度，無法再調整降低，以及狹窄的熔解溫度範圍特性，限制其在界面上產生熔解/凝固反應的潛熱功效。基於與構裝半導體的運作接面溫度範圍的匹配問題，大部分的低熔點合金因為該固定的共晶溫度、狹窄的熔解溫度範圍，並不是相當適合於熱界面應用。該低熔點合金的侷限性，在歐盟“電子電機設備禁用有毒物質指令(Restriction of the use of certain hazardous substance in EEE,ROHS)”實施後，排除以往發展的由Bi、In、Sn部份或全部元素以及Pb或/和Cd等所組成的合金，更限縮適於熱界面應用的低熔點合金選項。The location of the thermal interface material applied to the packaged semiconductor includes, for example, a first-order thermal interface between the integrated IC die and the heat spreader lid inside the integrated circuit. And constructing a second-order thermal interface between the soaking cap element external to the integrated circuit and the heat sink. Thermal paste and low melting point alloys are among the current thermal interface materials with low interfacial thermal resistance. However, thermal paste has been found to be unsuitable for high heat flux density semiconductors, mainly because its paste fluid is easily cured, which deteriorates its interface thermal conductivity. Or the cyclic thermal stress of the semiconductor operating at different powers is configured to cause the thermal paste to be pressed out of the thermal interface due to the cyclic thermal stress. A low melting point alloy suitable for use in a thermal interface, having a phase change characteristic which changes from a solid state to a creamy state at the interface, or a creamy state in a solid state, which is easily deformed to fill micropores of the interface surface, such as pure indium. . A low melting point alloy that is solid at room temperature has a lower interfacial thermal resistance than a thermal paste because of the melting/coagulation reaction at the thermal interface due to temperature disturbances that contributes to a large amount of absorption and release of thermal energy through the interface. Conventionally, low melting point alloys are mostly eutectic alloys, alloys close to the eutectic composition, and very few pure metals such as pure indium. The melting temperature range of the conventional low melting point alloy is rather narrow based on the eutectic composition. Conventional low melting point alloys having a melting point lower than the melting point of pure indium are limited by the eutectic temperature of the eutectic composition, can no longer be adjusted and lowered, and have a narrow melting temperature range characteristic, limiting the latent heat effect of the melting/solidification reaction at the interface. Based on the matching of the operating junction temperature range of the fabricated semiconductor, most of the low melting point alloys are not quite suitable for thermal interface applications due to the fixed eutectic temperature and narrow melting temperature range. The limitation of the low melting point alloy, after the implementation of the "Restriction of the use of certain hazardous substances in EEE (ROHS)" in the European Union, excludes some or all of Bi, In, and Sn that have been developed in the past. Elements and alloys consisting of Pb or / and Cd are more limited to low melting point alloy options for thermal interface applications.
習知低熔點合金在熱界面應用的侷限性說明如下：放置於積體電路裸晶和與其接合的均熱封蓋元件之間的第一階熱界面材料，須充分滿足以下幾個功能需求：調節該積體電路裸晶與該熱交換散熱元件因為熱膨脹錯置引起的熱應力或扭曲變形、降低積體電路裸晶與該散熱元件之間的界面熱 阻，以及穩固接合積體電路裸晶與該散熱元件。對於熔解溫度高於積體電路裸晶的運作接面溫度的習知低熔點合金，該固態的低熔點合金的楊式係數常高達數十Gpa，不易調節構裝半導體內部的熱扭曲變形或熱應力，將使積體電路裸晶承受脆裂的風險或破壞構裝的結構。該項功能需求排除了大部分的低熔點合金，除了低楊式係數(Young’s Module，又稱彈性係數)的軟質金屬，例如純銦和低溶質組成的In－Ag合金。如果使用熔解溫度低於積體電路裸晶的運作接面溫度的低熔點合金，該合金容易被加熱至高液相比例的狀態，將不易穩定接合積體電路裸晶與其散熱元件。雖然高熱傳導、低楊式係數的純銦和低溶質組成的In－Ag合金普遍用於第一階熱界面，然而純銦和低溶質In－Ag合金在積体電路裸晶運作的過程中始終維持固態，無法發揮其熔解潛熱以吸收大量熱能的效應。此外，目前晶片構裝多改用無鉛焊錫，該無鉛焊錫的熔點普遍高於220℃，焊錫迴流(solder reflow)製程將過度加熱並液化熔點較低的純銦和低溶質組成銦合金，可能引發界面上的純銦和低溶質組成銦合金，例如In－2Ag合金，的凝固收縮孔洞問題。The limitations of the conventional low-melting alloys applied at the thermal interface are as follows: The first-order thermal interface material placed between the bare metal of the integrated circuit and the soaking capping element bonded thereto must fully satisfy the following functional requirements: Adjusting thermal stress or distortion of the integrated circuit die and the heat exchange heat dissipating component due to thermal expansion misalignment, reducing interface heat between the integrated circuit die and the heat dissipating component Resisting, and firmly bonding the integrated circuit die to the heat dissipating component. For a conventional low-melting alloy having a melting temperature higher than a working junction temperature of an integrated circuit bare chip, the solid-type low-melting alloy has a Young's coefficient of up to several tens of Gpa, and it is difficult to adjust the thermal distortion or thermal stress inside the packaged semiconductor. The integrated circuit will be exposed to the risk of brittle fracture or damage to the structure of the structure. This functional requirement excludes most of the low melting point alloys, except for the soft metal of the Young's Module, also known as the elastic coefficient, such as pure indium and low solute In-Ag alloys. If a low melting point alloy having a melting temperature lower than the operating junction temperature of the integrated circuit bare crystal is used, the alloy is easily heated to a high liquid phase ratio, and it is difficult to stably bond the integrated circuit bare crystal and its heat dissipating component. Although In-Ag alloys with high thermal conductivity and low Young's coefficient of pure indium and low solute are commonly used in the first-order thermal interface, pure indium and low-solute In-Ag alloys remain in the process of bare metal operation of integrated circuits. The solid state cannot exert its effect of melting latent heat to absorb a large amount of heat. In addition, the current wafer assembly has been changed to lead-free solder, the melting point of the lead-free solder is generally higher than 220 ° C, the solder reflow process will overheat and liquefy the low melting point of pure indium and low solute composition of indium alloy, may cause Pure indium and low solute on the interface constitute an indium alloy, such as In-2Ag alloy, which has a problem of solidification shrinkage.
應用於第二階熱界面的熱界面材料需求主要是維持穩定、高界面熱傳導效率，因此低熔點合金的熔點越低，熔解溫度範圍越寬廣，越能在熱界面維持半固態，更有效發揮熔解潛熱的效能。大部分構裝半導體的外部界面溫度範圍多介於40℃至100℃之間，由於歐盟ROHS，熔點介於該界面溫度範圍的低熔點合金只有共晶In－Bi－Sn合金、共晶In－Bi合金和共晶Bi－In－Sn合金，然而仍受限於狹窄的熔解溫度範圍特性。 當界面溫度高於該共晶合金的共晶溫度，該合金容易被加熱熔解呈高液相狀態，使溢出熱界面外；當界面溫度低於該合金的共晶溫度，該合金不易熔解、產生足夠液相，使充分填補該界面表面的不規則微孔隙。為使低熔點合金的熔解液相能填補該微孔隙，有使用所謂預燒(burn in)的方法，然普遍應用於晶片構裝製程的迴流(reflow)加熱，在第二階熱界面的預燒程序將增加構裝半導體系統組裝的複雜性；另外，該需要預燒的低熔點合金在熱界面將維持固態，無從發揮其熔解潛熱以吸收大量熱能的效應。The demand for thermal interface materials applied to the second-order thermal interface is mainly to maintain stable and high interfacial heat conduction efficiency. Therefore, the lower the melting point of the low-melting alloy, the wider the melting temperature range, the more the semi-solid state can be maintained at the thermal interface, and the melting is more effectively performed. The efficacy of latent heat. The external interface temperature range of most fabricated semiconductors is between 40 °C and 100 °C. Due to the EU ROHS, the low melting point alloy with melting point between the interface temperature range is only eutectic In-Bi-Sn alloy, eutectic In- Bi alloys and eutectic Bi-In-Sn alloys, however, are still limited by the narrow melting temperature range characteristics. When the interface temperature is higher than the eutectic temperature of the eutectic alloy, the alloy is easily melted and melted to a high liquid state, so that it overflows outside the thermal interface; when the interface temperature is lower than the eutectic temperature of the alloy, the alloy is not easily melted and produced. Sufficient liquid phase to adequately fill the irregular micropores of the interface surface. In order to make the molten liquid phase of the low melting point alloy fill the micropores, a so-called burn in method is used, which is generally applied to the reflow heating of the wafer assembly process, and the second-order thermal interface is pre-processed. The firing process will increase the complexity of the assembly of the semiconductor system; in addition, the low melting point alloy that needs to be calcined will remain solid at the thermal interface, without the effect of exerting its latent heat of fusion to absorb a large amount of thermal energy.
總結以上，習知低熔點合金受限於其固定的共晶熔解溫度不易調整，以及狹窄熔解溫度範圍等的制約，使僅有少數的合金適用於特定構裝半導體的熱界面應用。為解決熔解溫度不易調整、以及狹窄熔解溫度的問題，本案發明人於中華民國專利申請案第096105743號提出一種可調變熔點溫度的金屬熱界面材料及其應用，其中利用鎵元素的添加量多寡來調變熔點溫度，可促成更寬廣區間的優異散熱性能，以克服共晶In－Bi－Sn合金的熔解溫度不夠低所造成的散熱瓶頸問題。然而，由於前述專利申請案之金屬熱界面材料的起始熱熔解溫度均低於60℃，較適於特定的構裝半導體第二階熱界面的應用。當應用在更高溫的熱界面，例如積體電路第一階界面導熱時或產生高熱流量的構裝半導體的第二階熱界面時，該材料容易被加熱至高液相比例的狀態，不易穩定接合電路裸晶與其散熱元件，甚至造成此金屬熱界面材料的熔解液相溢流出熱界面，是其應用上之障礙。To summarize the above, it is known that low melting point alloys are limited by the difficulty in adjusting the fixed eutectic melting temperature and the narrow melting temperature range, so that only a few alloys are suitable for the thermal interface application of a particular packaged semiconductor. In order to solve the problem that the melting temperature is difficult to adjust and the melting temperature is narrow, the inventor of the present invention proposed a metal thermal interface material with adjustable melting point temperature and its application in the patent application No. 096105743 of the Republic of China, wherein the amount of gallium added is used. To adjust the melting point temperature, it can promote the excellent heat dissipation performance in a wider range to overcome the heat dissipation bottleneck caused by the low melting temperature of the eutectic In-Bi-Sn alloy. However, since the initial thermal melting temperature of the metal thermal interface material of the aforementioned patent application is lower than 60 ° C, it is more suitable for the application of the second-order thermal interface of a specific package semiconductor. When applied to a hot interface at a higher temperature, such as a first-order interface of an integrated circuit, or a second-order thermal interface of a semiconductor that generates a high heat flux, the material is easily heated to a high liquid phase ratio, which is difficult to stably bond. The bare crystal of the circuit and its heat dissipating component, and even the melting liquid phase overflowing thermal interface of the metal thermal interface material, are obstacles in its application.
因此，目前亟需開發一種具有寬廣熔點溫度範圍的金屬熱界面材料，使適於構裝半導體的熱界面需求，即使應用在第一階熱界面時亦不會被過度加熱至完全液態，可充分發揮其熔解/凝固的潛熱效應。Therefore, there is an urgent need to develop a metal thermal interface material having a wide melting temperature range, so that the thermal interface requirement for the semiconductor is not excessively heated to a completely liquid state even when applied to the first-order thermal interface. The latent heat effect of its melting/solidification is exerted.
本發明的目的係提供一金屬熱界面材料，其起始熔解溫度可調整至期望的溫度數值，且具有寬廣的熔解溫度範圍，更容易符合熱界面的功能需求。SUMMARY OF THE INVENTION It is an object of the present invention to provide a metal thermal interface material having an initial melting temperature that can be adjusted to a desired temperature value and a wide range of melting temperatures that more readily meet the functional requirements of the thermal interface.
本發明的另一目的係提供一可調整熔解溫度的金屬熱界面材料，其起始熔解溫度可由添加一少量溶質元素而調整降低，並因此拓展其熔解溫度範圍。Another object of the present invention is to provide a metal thermal interface material having an adjustable melting temperature, the initial melting temperature of which can be adjusted to decrease by the addition of a small amount of solute elements, and thus expand its melting temperature range.
本發明的再另一目的係提供具有寬廣熔解溫度範圍特性的金屬熱界面材料，其起始熔解溫度介於構裝半導體的運作接面溫度範圍內，而且熔解為全液態的溫度高於純銦的熔點，當該金屬熱界面材料應用於第一階熱界面時，在構裝晶片迴流加熱階段，不易被過度加熱至完全液態。Still another object of the present invention is to provide a metal thermal interface material having a broad melting temperature range characteristic, the initial melting temperature being within the operating junction temperature range of the packaged semiconductor, and melting to a full liquid state at a higher temperature than pure indium The melting point, when the metal thermal interface material is applied to the first-order thermal interface, is not easily overheated to a completely liquid state during the reflow heating phase of the package wafer.
為達上述與其他目的，本發明提供一金屬熱界面材料，包括：約20~98wt%之銦元素；約0.03~4wt%之鎵元素；以及擇自錫、銀、鉍、鋅之至少一元素；其中上述金屬熱界面材料之起始熔解溫度介於約60~144℃之間。To achieve the above and other objects, the present invention provides a metal thermal interface material comprising: about 20 to 98 wt% of indium element; about 0.03 to 4 wt% of gallium element; and at least one element selected from the group consisting of tin, silver, antimony, and zinc. Wherein the initial thermal melting temperature of the metal thermal interface material is between about 60 and 144 °C.
本發明更提供一種構裝半導體。在一實施例中，該構裝半導體包括：一構裝基板，其表面具有導電線路；一裸晶，設置於構裝基板具有導電線路之表面上；一均熱元件， 設置於積體電路裸晶上方；一散熱器，設置於均熱元件上方；其中裸晶與均熱元件之間設置有第一熱界面材料，且均熱元件與散熱器之間設置有第二熱界面材料；其中第一熱界面材料及/或第二熱界面材料為本發明前述之金屬熱界面材料。The invention further provides a packaged semiconductor. In one embodiment, the package semiconductor includes: a structure substrate having a conductive line on a surface thereof; a die disposed on a surface of the structure substrate having a conductive line; a heat equalizing element, The device is disposed above the bare crystal of the integrated circuit; a heat sink is disposed above the heat equalizing element; wherein a first thermal interface material is disposed between the bare crystal and the heat equalizing element, and a second is disposed between the heat equalizing element and the heat sink The thermal interface material; wherein the first thermal interface material and/or the second thermal interface material is the metal thermal interface material of the foregoing invention.
在另一實施例中，該構裝半導體包括：一多層構裝基板，包括一導熱材料、一介電層於導熱材料上、以及一導電線路於介電層上；一裸晶，電性連接多層構裝基板之導電線路；一散熱器，設置於多層構裝基板之導熱材料下；其中裸晶與多層構裝基板之間設置有第一熱界面材料，且多層構裝基板與散熱器之間設置有第二熱界面材料；且其中第一熱界面材料及/或第二熱界面材料為本發明前述之金屬熱界面材料。In another embodiment, the packaged semiconductor comprises: a multilayer package substrate comprising a heat conductive material, a dielectric layer on the heat conductive material, and a conductive line on the dielectric layer; a die, electrical connection a conductive circuit of the multilayer structure substrate; a heat sink disposed under the heat conductive material of the multilayer structure substrate; wherein the first thermal interface material is disposed between the bare crystal and the multilayer structure substrate, and the multilayer structure substrate and the heat sink A second thermal interface material is disposed therebetween; and wherein the first thermal interface material and/or the second thermal interface material is the metal thermal interface material of the foregoing invention.
在又一實施例中，該構裝半導體包括：一半導體電路元件，運作於一溫度範圍；一均熱元件，具有內表面與背表面，內表面位於半導體電路元件上方；一散熱器，設置於均熱元件背表面的上方；以及，本發明前述之金屬熱界面材料熱界面材料，設置於半導體電路元件至散熱器之熱傳導路徑的界面間。In still another embodiment, the package semiconductor includes: a semiconductor circuit component operating in a temperature range; a heat equalizing component having an inner surface and a back surface, the inner surface being above the semiconductor circuit component; and a heat sink disposed on each of Above the back surface of the thermal element; and the aforementioned metal thermal interface material thermal interface material of the present invention is disposed between the interface of the semiconductor circuit component to the heat conduction path of the heat sink.
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：The above and other objects, features and advantages of the present invention will become more <RTIgt;
本發明之金屬熱界面材料的組成包括分要的銦(In)、鎵(Ga)兩元素以及擇自錫(Sn)、銀(Ag)、鉍(Bi)和鋅(Zn)至少一元素。其中該合金的鎵含量介於約0.03wt%至4wt%之間，銦含量介於約20wt%至98wt%之間，當鎵的含量越高，該金屬的起始熔解溫度越低，熔解溫度範圍越寬廣。其中前述的鉍、錫、鋅和銀等每一元素皆具有與銦構成一共晶合金的特徵，例如高溶質組成的In－33.7Bi、In－48Sn共晶合金，以及低溶質組成的In－2.2Zn、In－3Ag共晶合金。由In－Bi、In－Sn以及In－Bi－Sn相圖，形成固溶體的組成範圍相當寬廣，因此本發明不同組成的金屬熱界面材料的溶劑原子可以是Bi或Sn或In，分別形成Bi合金或Sn合金或In合金。基於以上，本發明的不同組成金屬熱界面材料可以是In－Sn－Ga、Sn－In－Ga、In－Bi－Ga、In－Bi－Sn－Ga、Bi－In－Sn－Ga、In－Bi－Sn－Zn－Ga、In－Bi－Sn－Ag－Zn－Ga和In－Sn－Ag－Ga等合金。The composition of the metal thermal interface material of the present invention comprises two elements of indium (In), gallium (Ga) and at least one element selected from the group consisting of tin (Sn), silver (Ag), bismuth (Bi) and zinc (Zn). Wherein the alloy has a gallium content of between about 0.03 wt% and 4 wt% and an indium content of between about 20 wt% and 98 wt%. The higher the gallium content, the lower the initial melting temperature of the metal, the melting temperature. The wider the range. Each of the foregoing elements such as bismuth, tin, zinc and silver has a characteristic of forming a eutectic alloy with indium, such as a high solute composition of In-33.7Bi, an In-48Sn eutectic alloy, and a low solute composition of In-2.2. Zn, In-3Ag eutectic alloy. The composition range of the solid solution formed by the In-Bi, In-Sn and In-Bi-Sn phase diagrams is quite wide. Therefore, the solvent atoms of the metal thermal interface materials of different compositions of the present invention may be Bi or Sn or In, respectively. Bi alloy or Sn alloy or In alloy. Based on the above, the different constituent metal thermal interface materials of the present invention may be In-Sn-Ga, Sn-In-Ga, In-Bi-Ga, In-Bi-Sn-Ga, Bi-In-Sn-Ga, In-. Alloys such as Bi-Sn-Zn-Ga, In-Bi-Sn-Ag-Zn-Ga, and In-Sn-Ag-Ga.
另外，前述的本發明金屬熱界面材料的組成更可至少再包括其他的元素，例如金、銅、硼、鈦、鋯、鎳、銻、鍺、鈰、鑭、鈧、釔、鉛、鉻、鎘或矽等元素。基本上，雖然本發明金屬熱界面材料的組成符合RoHS ，但本發明並非以此為限，毒害環境元素，例如鉛、鎘、汞等元素在不明顯成為主要溶質元素的條件下，僅是極微量的元素(較佳<0.03wt%)，亦是本發明金屬熱界面材料的其他元素選項。In addition, the composition of the foregoing metal thermal interface material of the present invention may further include at least other elements such as gold, copper, boron, titanium, zirconium, nickel, lanthanum, cerium, lanthanum, cerium, lanthanum, cerium, lead, chromium, Elements such as cadmium or barium. Basically, although the composition of the metal thermal interface material of the present invention is RoHS compliant , the present invention is not limited thereto, and elements toxic to the environment, such as lead, cadmium, mercury, etc., are only extremely polar under the condition that they are not significantly dominant solute elements. Trace elements (preferably <0.03 wt%) are also other elemental options for the metal thermal interface materials of the present invention.
本發明的金屬熱界面材料與習知低熔點合金的熔解特性的差異如下所述：本發明的金屬熱界面材料的熔解溫度雖然由主要的溶劑元素與溶質元素的共晶溫度所影響，仍 可藉由添加0.03wt%至4wt%不等的鎵元素而調整降低，當鎵含量越高，起始熔解溫度越低，同時熔解溫度範圍越大。依據不同合金組成，本發明金屬熱界面材料的起始熔解溫度最低為60℃，最高不大於144℃。當本發明之具有寬廣熔解溫度範圍的金屬熱界面材料應用於第一階熱界面時，構裝半導體運作產生的熱量可使合金更容易被加熱至軟化狀態，使容易調節運作中構裝半導體內部的熱應力，或使合金在界面上產生熔解/凝固反應，快速吸收、傳導高熱流密度。另外，當本發明金屬熱界面材料的主要溶劑原子是Sn時，完全熔解為液態的溫度高於純銦的熔點，在構裝晶片迴流加熱階段，不易被過度加熱至完全液態，可避免金屬液相溢流所引發之周邊電路短路風險。The difference in melting characteristics of the metal thermal interface material of the present invention and the conventional low melting point alloy is as follows: the melting temperature of the metal thermal interface material of the present invention is affected by the eutectic temperature of the main solvent element and the solute element, The decrease can be adjusted by adding a gallium element ranging from 0.03 wt% to 4 wt%, and the higher the gallium content, the lower the initial melting temperature, and the larger the melting temperature range. According to different alloy compositions, the initial thermal melting temperature of the metal thermal interface material of the present invention is at least 60 ° C and no more than 144 ° C. When the metal thermal interface material having a wide melting temperature range of the present invention is applied to the first-order thermal interface, the heat generated by the semiconductor operation can make the alloy more easily heated to a softened state, making it easy to adjust the operation of the semiconductor interior. The thermal stress causes the alloy to melt/coagulate at the interface, rapidly absorbing and conducting high heat flux. In addition, when the main solvent atom of the metal thermal interface material of the present invention is Sn, the temperature of completely melting into a liquid state is higher than the melting point of pure indium, and during the reflow heating phase of the package wafer, it is not easily overheated to a completely liquid state, and the molten metal can be avoided. The risk of short circuiting the peripheral circuit caused by the phase overflow.
以下分別說明本發明的金屬熱界面材料和構裝半導體的實施例。金屬熱界面材料的實施例，主要是用來說明不同金屬熱界面材料的合金組成，以及其熔解溫度的變化，並與習知的低熔點合金比較差異，以彰顯本發明金屬熱界面材料的特徵，而不是用來限制本發明金屬熱界面材料的範圍。以下實施例分別條列In－Bi－Ga合金、In－Sn－Ga合金以及In－Ag－Ga合金的不同組成以及其熔解溫度的數據。Embodiments of the metal thermal interface material and the package semiconductor of the present invention are respectively described below. The embodiment of the metal thermal interface material is mainly used to illustrate the alloy composition of different metal thermal interface materials, as well as the change of the melting temperature thereof, and is compared with the conventional low melting point alloy to demonstrate the characteristics of the metal thermal interface material of the present invention. Rather than limiting the range of metallic thermal interface materials of the present invention. The following examples illustrate the different compositions of In-Bi-Ga alloy, In-Sn-Ga alloy, and In-Ag-Ga alloy, as well as data on their melting temperatures.
為清楚顯現本發明的金屬熱界面材料與習知的低熔點合金的熔解差異，將進行熱分析比較。熱分析是使用Du Pont Instruments 910 示差掃瞄熱卡計；測試金屬樣品壓入鋁製坩鍋內，然後從室溫加熱至完全液態後再降溫至室溫。前述金屬樣品的熱分析聚焦於熔解反應的起始熔解溫度 (initial melting temperature ,Ti )、外插熔解溫度(extrapolated onset melting temperature ,Tonset )和尖峰熔解溫度(peak melting temperature ,Tp )。In order to clearly show the difference in melting of the metal thermal interface material of the present invention and the conventional low melting point alloy, a thermal analysis comparison will be performed. Thermal analysis was performed using a Du Pont Instruments 910 differential scanning calorimeter; the test metal sample was pressed into an aluminum crucible and then heated from room temperature to full liquid before cooling to room temperature. The thermal analysis of metal samples starting melting temperature (initial melting temperature, T i) focused on the melting reaction extrapolated melting temperature (extrapolated onset melting temperature, T onset ) and peak melting temperature (peak melting temperature, T p) .
表一是不同Ga添加量的In－Bi－Ga合金的起始熔解溫度和尖峰熔解溫度的數值，由表中可看出，不同重量組成的In－Bi－Ga合金的起始熔解溫度均隨著鎵的含量增加而降低。但應注意的是，在本發明中為使該In－Bi－Ga合金除是用第二階熱界面外，也能更適用在第一階熱界面，該合金組成需提高In的含量，以及降低Bi的含量，鎵的添加量不應使合金的起始熔解溫度低於60℃。Table 1 shows the values of the initial melting temperature and the peak melting temperature of In-Bi-Ga alloys with different Ga addition amounts. It can be seen from the table that the initial melting temperatures of In-Bi-Ga alloys with different weight compositions follow As the content of gallium increases, it decreases. It should be noted, however, that in the present invention, in addition to the second-order thermal interface, the In-Bi-Ga alloy can be more suitably applied to the first-order thermal interface, and the composition of the alloy needs to increase the content of In, and To reduce the content of Bi, the amount of gallium added should not cause the initial melting temperature of the alloy to be lower than 60 °C.
表二是不同Ga添加量的In－Sn－Ga合金和Sn－In－Ga合金的起始熔解溫度和尖峰熔解溫度的數值。第1圖是In－47.5Sn－1Ga合金(以下簡稱ISG－10)、In－46.6Sn－3Ga合金(以下簡稱ISG－30)和Sn－44In－1Ga合金(以下簡稱SIG－10)的熔解反應與凝固反應的曲線圖。由ISG－10和ISG－30合金的熔解反應的差異清楚顯現添加Ga在降低起始熔解溫度和拓展熔解溫度區間的效果；由SIG－10與ISG－10合金的熔解反應差 異，顯示當溶劑原子由In轉變為熔點較高的Sn時，加熱至完全液態的熔解溫度將提高，而且隨著Sn的組成比例增加，完全液態的熔解溫度將對應增加，可高於純銦的熔點157℃。Table 2 shows the values of the initial melting temperature and the peak melting temperature of the In-Sn-Ga alloy and the Sn-In-Ga alloy in different Ga addition amounts. Fig. 1 is a melting reaction of In-47.5Sn-1Ga alloy (hereinafter referred to as ISG-10), In-46.6Sn-3Ga alloy (hereinafter referred to as ISG-30), and Sn-44In-1Ga alloy (hereinafter referred to as SIG-10). A graph of the reaction with solidification. The difference in melting reaction between ISG-10 and ISG-30 alloy clearly shows the effect of adding Ga on lowering the initial melting temperature and expanding the melting temperature range; the melting reaction difference between SIG-10 and ISG-10 alloy Different, showing that when the solvent atom is changed from In to Sn with a higher melting point, the melting temperature heated to a completely liquid state will increase, and as the composition ratio of Sn increases, the melting temperature of the complete liquid will increase correspondingly, which may be higher than that of pure indium. The melting point of 157 ° C.
表三是不同Ga添加量的In－Ag－Ga合金的起始熔解溫度和尖峰熔解溫度的數值。同樣地，不同重量組成的In－Ag－Ga合金的起始熔解溫度均隨著鎵的含量增加而降低。第2圖是In－3Ag－1Ga合金(以下簡稱IAG－10)、In－3Ag－2Ga合金(以下簡稱IAG－20)和比較用In－3Ag共晶合金(以下簡稱E.In－Ag)的熔解反應與凝固反應的曲線圖，清楚顯現添加Ga對於降低起始熔解溫度的效果。Table 3 is the values of the initial melting temperature and the peak melting temperature of the In-Ag-Ga alloys of different Ga addition amounts. Similarly, the initial melting temperatures of In-Ag-Ga alloys of different weight compositions decrease as the content of gallium increases. 2 is an In-3Ag-1Ga alloy (hereinafter referred to as IAG-10), an In-3Ag-2Ga alloy (hereinafter referred to as IAG-20), and a comparative In-3Ag eutectic alloy (hereinafter referred to as E.In-Ag). The graph of the melting reaction and the solidification reaction clearly shows the effect of adding Ga on lowering the initial melting temperature.
以下將配合第3－4圖說明本發明之金屬熱界面材料的各種應用實施例。應注意的是，圖中所示之散熱器的型式與配置僅為舉例說明之用，並非用以限定本發明之範圍。再者，本發明之金屬熱界面材料亦非僅限於應用在圖中構裝半導體之界面導熱，而是可廣泛應用在各種發熱元件之界面導熱。Various application examples of the metal thermal interface material of the present invention will be described below in conjunction with Figures 3-4. It should be noted that the type and configuration of the heat sink shown in the figures are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, the metal thermal interface material of the present invention is not limited to heat conduction at the interface of the semiconductor in the figure, but can be widely applied to the interface heat conduction of various heating elements.
第3圖顯示本發明之金屬熱界面材料在構裝半導體的應用實施例，其可應用在構裝半導體的第一階及/或第二階界面導熱，尤其特別適合應用在第一階熱界面或產生高熱流量的第二階熱界面。如圖中所示，構裝積體電路元件100包含積體電路裸晶114、與其電性連接的構裝基板(substrate)112。積體電路裸晶114和構裝基板112的電性連接可經由俗稱的C4接合(Controlled Collapse Chip Connection)製程，在積體電路裸晶114的接墊(pads，未顯示)上長成金屬凸塊(metal bumps)116，將積體電路裸晶114的金屬凸塊116和構裝基板112的線路對齊後，以迴流(Reflow)加熱使冶金接合並連接兩者導電電路。雖然實施例中標示電路連接經係由金屬凸塊116在迴流加熱階段的共晶反應，不過積體電路裸晶114也可以和構裝基板112經由其他的方法形成電路連接，例如打線接合(wire bonding)。3 is a view showing an application example of the metal thermal interface material of the present invention in a packaged semiconductor, which can be applied to the first-order and/or second-order interface heat conduction of the packaged semiconductor, and is particularly suitable for application in the first-order thermal interface. Or a second-order thermal interface that produces high heat flux. As shown in the figure, the integrated circuit component 100 includes an integrated circuit die 114 and a substrate 112 electrically connected thereto. The electrical connection between the integrated circuit die 114 and the package substrate 112 can be grown into a metal bump on a pad (not shown) of the integrated circuit die 114 via a commonly known C4 bonding (Controlled Collapse Chip Connection) process. The metal bumps 116 align the metal bumps 116 of the integrated circuit die 114 with the lines of the package substrate 112, and then metallurgically bond and connect the conductive circuits by reflow heating. Although the circuit connection is indicated by the eutectic reaction of the metal bumps 116 during the reflow heating phase, the integrated circuit die 114 may be electrically connected to the package substrate 112 via other methods, such as wire bonding. Bonding).
構裝積體電路元件100包含複數個陣列錫球118設置於構裝基板112底部的表面120。構裝基板112可以經由接墊(pads)、通孔(vias)(未顯示)等結構使金屬凸塊 116和錫球118構成電性連接。經由迴流(Reflow)過程，構裝積體電路元件100和一電路板(未顯示)經由錫球118構成電路連接；雖然實施例中標示構裝積體電路元件100和電路板的電性連接是經由陣列錫球118以及迴流加熱過程，不過也可以由其他的方法形成電路連接，例如錫球118可變更為針腳(pins)形式並且電性連接到電路板的腳座連接器(socket)，或者針腳插入電路板的通孔(via)中進行焊接固定。The package integrated circuit component 100 includes a plurality of array solder balls 118 disposed on a surface 120 of the bottom of the package substrate 112. The structure substrate 112 can be made of metal bumps via a pad, a vias (not shown), or the like. 116 and solder ball 118 form an electrical connection. Through the reflow process, the integrated circuit component 100 and a circuit board (not shown) are electrically connected via the solder balls 118; although the electrical connections of the integrated circuit component 100 and the circuit board are indicated in the embodiment. Via the array solder balls 118 and the reflow heating process, but circuit connections may also be formed by other methods, such as the solder balls 118 being more pin-like and electrically connected to the socket of the board, or The pins are inserted into the vias of the board for soldering.
構裝積體電路元件100運作時，積體電路裸晶114所產生的熱自構裝結構內部移出至環境。為使積體電路裸晶114的背表面適於與具熱交換作用的均熱元件(thermal element)128接合，改善接合面的熱傳導效率，積體電路裸晶114的背表面通常需批覆一或多層的附著層(未顯示)，使適於軟焊(solderable－wettable)，該附著層可以由鉻、釩、金、鎳、鋯、鈦等純金屬或其合金層所構成。均熱元件128例如是圖中所示之均熱封蓋元件(Integrated Heat Spreader(IHS)lid)，其材質可以是一高熱導的金屬或陶瓷或鋁基複合材料。此外，均熱元件128表面並可批覆適合軟焊的一或多數層金屬(未顯示)例如銅、鎳，或者含金屬的有機材料層，使適於軟焊接合。When the integrated circuit component 100 is constructed, the heat generated by the integrated circuit die 114 is internally removed from the structure to the environment. In order to make the back surface of the integrated circuit die 114 suitable for bonding with the heat exchange thermal element 128, the heat transfer efficiency of the joint surface is improved, and the back surface of the integrated circuit die 114 is usually required to be approved. A multi-layered adhesion layer (not shown) is suitable for solderable-wettable, and the adhesion layer may be composed of a pure metal such as chromium, vanadium, gold, nickel, zirconium or titanium or an alloy layer thereof. The heat equalizing element 128 is, for example, an integrated heat spreader (IHS) lid, which may be made of a highly thermally conductive metal or ceramic or aluminum matrix composite. In addition, the surface of the heat equalizing element 128 may be coated with one or more layers of metal (not shown) suitable for soldering, such as copper, nickel, or a layer of organic material containing metal, suitable for soft soldering.
為儘可能降低積體電路裸晶114和均熱元件128的界面熱阻以及穩定接合積體電路裸晶114和均熱元件128，本發明的第一熱界面材料TIM1設置於其熱界面間。為容易調節積體電路裸晶114和均熱元件128的接合界面的熱 應力，通常第一熱界面材料TIM1需具有低楊式係數，除了在積體電路裸晶114運作時維持固態的軟質金屬外，例如本發明的低溶質組成的In－2Ag－0.5Ga合金和In－2Zn－2Ga合金，室溫下即容易變形，在積體電路運作時可被加熱至呈軟化狀態或產生少量的液相，另外In－46Sn－2Ga合金或Sn－40In－3Ga合金則較容易被加熱呈現較多液相比例的半固態。本發明中，第一熱界面材料TIM1之厚度可依照散熱模組的型式與裸晶的操作條件而調整，在一實施例中，第一熱界面材料TIM1之厚度介於200－400μm。為了在迴流加熱過程，控制第一熱界面材料TIM1的界面接合厚度，在均熱元件128和構裝基板112之間以及第一熱界面材料TIM1的外圍，可使用環型墊片(未顯示)，墊片除了維持第一熱界面材料TIM1的界面接合厚度外，也有減緩第一熱界面材料TIM1氧化速率的功效。此外，為增加積體電路裸晶114與構裝基板112的接合強度，可在積體電路裸晶114與構裝基板(substrate)112的電路接點的間隙填充樹脂類底膠(未顯示)。另外為加強構裝積體電路元件100的構造強度，可使用一焊錫合金156使其冶金接合構裝基板112和均熱元件128，也可以經由焊錫膏固化或螺絲接合構裝基板112和均熱元件128。在均熱元件128上方，功能上同樣是熱交換的散熱器138具有許多鰭片，且其底板表面與均熱元件128的上表面連接成一導熱通道。散熱器138藉由第二熱界面材料TIM2接合均熱元件128。雖然本發明的金屬熱界面材料特 別適用於積體電路裸晶114和均熱元件128的間的第一階熱界面，但是本發明的金屬熱界面材料也可適用於均熱元件128與散熱器138之間的第二階熱界面。除此之外，第二熱界面材料TIM2亦可使用其他的金屬熱界面材料、散熱凝膠或散熱膏等。In order to minimize the interfacial thermal resistance of the integrated circuit die 114 and the heat equalizing element 128 and to stably bond the integrated circuit die 114 and the heat equalizing element 128, the first thermal interface material TIM1 of the present invention is disposed between its thermal interfaces. To easily adjust the heat of the joint interface of the integrated circuit die 114 and the heat equalizing element 128 Stress, usually the first thermal interface material TIM1 needs to have a low Young's coefficient, except for the soft metal that maintains the solid state when the integrated circuit die 114 operates, such as the low solute composition of the In-2Ag-0.5Ga alloy and In- of the present invention. 2Zn-2Ga alloy is easily deformed at room temperature, and can be heated to a softened state or a small amount of liquid phase during operation of the integrated circuit. In addition, In-46Sn-2Ga alloy or Sn-40In-3Ga alloy is easier to be The heating exhibits a semi-solid state with a greater proportion of liquid phase. In the present invention, the thickness of the first thermal interface material TIM1 can be adjusted according to the type of the heat dissipation module and the operating conditions of the bare crystal. In one embodiment, the thickness of the first thermal interface material TIM1 is between 200 and 400 μm. In order to control the interfacial bonding thickness of the first thermal interface material TIM1 during the reflow heating process, a ring spacer (not shown) may be used between the heat equalizing element 128 and the constituent substrate 112 and the periphery of the first thermal interface material TIM1. In addition to maintaining the interfacial bonding thickness of the first thermal interface material TIM1, the spacer also has the effect of slowing the oxidation rate of the first thermal interface material TIM1. In addition, in order to increase the bonding strength between the integrated circuit die 114 and the package substrate 112, a resin-based primer (not shown) may be filled in the gap between the circuit contacts of the integrated circuit die 114 and the substrate 112. . In addition, in order to enhance the structural strength of the integrated circuit component 100, a solder alloy 156 may be used to metallurgically bond the substrate 112 and the heat equalizing element 128, or the substrate 112 and soaking may be configured by solder paste curing or screwing. Element 128. Above the soaking element 128, the heat sink 138, which is also functionally heat exchanged, has a plurality of fins and its bottom surface is connected to the upper surface of the heat equalizing element 128 as a thermally conductive channel. The heat sink 138 engages the heat equalizing element 128 by the second thermal interface material TIM2. Although the metal thermal interface material of the present invention is It is not applicable to the first-order thermal interface between the integrated circuit die 114 and the heat equalizing element 128, but the metal thermal interface material of the present invention is also applicable to the second-order heat between the heat equalizing element 128 and the heat sink 138. interface. In addition, the second thermal interface material TIM2 may also use other metal thermal interface materials, heat-dissipating gels or thermal greases.
雖然第3圖顯示單一積體電路晶片構裝，但事實上，同樣的構裝技術手段也可以適用於多積體電路晶片構裝的實施。此外，第3圖構裝積體電路元件的電路接點分布於構裝基板112的上、下表面，然而基於不同構裝半導體的產品特性或技術進展，某些構裝半導體的所有電路接點亦可安排在構裝基板112的同一表面上，例如光電半導體的構裝。再者，因應構裝半導體的散熱考量或構裝元件簡化，構裝結構內的各元件的組合方式也可做各種整併或配置改變，例如構裝半導體結構的構裝基板112和均熱元件128整併為一具有導電線路、介電層與熱交換、均熱材料的多層構裝基板材料，例如金屬芯印刷電路板(MCPCB)的構造。因此本發明的金屬熱界面材料亦非僅限應用於圖中積體電路裸晶的第一熱界面材料TIM1，相反地，該金屬熱界面材料可廣泛應用在各種電子元件或其他任何發熱元件至一散熱器的熱傳導路徑的任何熱界面間。Although Figure 3 shows a single integrated circuit wafer package, in fact, the same construction techniques can be applied to the implementation of a multi-integrated circuit wafer package. In addition, the circuit contacts of the integrated circuit component of FIG. 3 are distributed on the upper and lower surfaces of the package substrate 112. However, based on the product characteristics or technological advancement of different semiconductors, some circuit contacts of some semiconductors are mounted. It may also be arranged on the same surface of the package substrate 112, such as the structure of an optoelectronic semiconductor. Furthermore, in view of the heat dissipation considerations of the packaged semiconductor or the simplification of the component, the combination of the components in the package structure can also be variously adjusted or configured, such as the package substrate 112 and the heat spreader component of the semiconductor structure. 128 is a multi-layered substrate material having a conductive line, a dielectric layer and a heat exchange, soaking material, such as a metal core printed circuit board (MCPCB). Therefore, the metal thermal interface material of the present invention is not limited to the first thermal interface material TIM1 of the integrated circuit in the figure. On the contrary, the metal thermal interface material can be widely applied to various electronic components or any other heating element to A heat transfer path between any thermal interface of a heat sink.
第4圖顯示一使用多層構裝基板310的構裝半導體200，如圖中所示構裝半導體200包含複數個光電半導體裸晶502、一承載座124、多層構裝基板310以及散熱器338。承載座124包括一高導熱散熱塊(slug)416、散熱塊部分 表面的電絕緣層417、與光電半導體裸晶502電性連接的鑲崁片(submount)403、複數個連接鑲崁片403表面的金屬線214與金屬線214電性連接的複數個導電接腳215，導電接腳215由電絕緣層417內部往外突穿。多層構裝基板310包括一均熱板片320、一介電層330於均熱板片320上、以及一導電線路350於介電層330上，並與導電接腳215電性聯接。鑲崁片403和高導熱散熱塊(slug)416可由矽、鑽石、氧化鋁、鎢、鉬、銅、鋁或氮化硼等高導熱材料或複合材料組成。光電半導體裸晶502，例如發光二極體(LED)裸晶或雷射二極體裸晶的接墊(pads,未顯示)，經由焊錫迴流製程形成的Au/Sn共晶結合或銀膠結合的方式電性連接矽鑲崁片403表面預先規劃製作的導電線路(未顯示)，並經由金屬線214以及導電接腳215與多層構裝基板310的導電線路350形成電迴路。4 shows a packaged semiconductor 200 using a multilayer package substrate 310. As shown, the packaged semiconductor 200 includes a plurality of optoelectronic semiconductor die 502, a carrier 124, a multilayer package substrate 310, and a heat sink 338. The carrier 124 includes a high thermal block (slug) 416 and a heat sink portion. The surface of the electrically insulating layer 417, the submount 403 electrically connected to the optoelectronic semiconductor die 502, the plurality of metal wires 214 connecting the surface of the gusset 403 and the plurality of conductive pins electrically connected to the metal wire 214 215, the conductive pin 215 protrudes outward from the inside of the electrically insulating layer 417. The multilayer package substrate 310 includes a heat spreader sheet 320, a dielectric layer 330 on the heat spreader sheet 320, and a conductive trace 350 on the dielectric layer 330, and is electrically coupled to the conductive pins 215. The gusset 403 and the high thermal conductivity slug 416 may be composed of a highly thermally conductive material or composite material such as tantalum, diamond, alumina, tungsten, molybdenum, copper, aluminum or boron nitride. Photoelectric semiconductor bare crystal 502, such as light-emitting diode (LED) bare or laser diode bare pads (pads, not shown), formed by Au/Sn eutectic bonding or silver-gel bonding via solder reflow process The conductive connection (not shown) is pre-planned on the surface of the 矽 崁 403, and an electrical circuit is formed between the conductive line 350 of the multilayer structure substrate 310 via the metal line 214 and the conductive pin 215.
應可理解的是，第4圖所示之構裝方式僅為舉例說明之用，熟悉此技術人士自當可使用各種構裝方式來形成電迴路。例如，雖然在第4圖所繪示之實施例中，光電半導體裸晶502與鑲崁片(submount)403彼此導電，但另一構裝實施例也可以使彼此之間不導電，方式為金屬線214變更為焊接在光電半導體裸晶502上，並電性連接至導電接腳215，如此光電半導體裸晶502與多層構裝基板310的導電線路350形成電迴路。It should be understood that the configuration shown in FIG. 4 is for illustrative purposes only, and those skilled in the art can use various configurations to form an electrical circuit. For example, although in the embodiment illustrated in FIG. 4, the optoelectronic semiconductor die 502 and the submount 403 are electrically conductive to each other, another embodiment may also be non-conductive to each other in a metal manner. The wire 214 is modified to be soldered to the optoelectronic semiconductor die 502 and electrically connected to the conductive pin 215 such that the optoelectronic semiconductor die 502 and the conductive trace 350 of the multilayer package substrate 310 form an electrical circuit.
光電半導體裸晶502運作產生的高熱流密度主要傳導至高導熱的散熱塊(slug)416，再經由熱界面材料101將 熱流傳導分散至均熱板片320，再經由填補在均熱板片320外表面的另一熱界面材料102傳導至散熱器338，最後至環境。而本發明的金屬熱界面材料可作為散熱塊(slug)416與多層構裝基板310之間的熱界面材料101，也可作為多層構裝基板310與散熱器338之間的熱界面材料102。The high heat flux generated by the operation of the optoelectronic semiconductor die 502 is mainly conducted to the high thermal conductivity slug 416, and then via the thermal interface material 101. The heat flow is dispersed to the heat equalizing plate 320 and then conducted to the heat sink 338 via another thermal interface material 102 that is filled over the outer surface of the soaking plate 320, and finally to the environment. The metal thermal interface material of the present invention can be used as the thermal interface material 101 between the heat slug 416 and the multilayer package substrate 310, and can also serve as the thermal interface material 102 between the multilayer package substrate 310 and the heat sink 338.
構裝半導體的熱管理系統除了前述不同的金屬熱界面材料的熱界面應用、單或多晶片構裝、電路接點的安排以及不同元件整併或配置的差異變化外，均熱元件和散熱器同樣能有不同的變化，例如均熱元件內部具有微通道結構(micro－channel structure)，或是一平板式熱管(vapor chamber)；此外散熱器的底板可以設置熱管，或者散熱器也可以是一循環水冷的熱控冷板(cold plates，俗稱水冷散熱器)。The thermal management system for fabricating semiconductors, in addition to the thermal interface applications of the various metal thermal interface materials described above, single or multi-chip packages, arrangement of circuit contacts, and variations in the integration or configuration of different components, soaking elements and heat sinks It can also have different changes, such as a micro-channel structure inside the heat-receiving element or a flat-plate heat chamber; in addition, the bottom plate of the heat sink can be provided with a heat pipe, or the heat sink can also be a Circulating water-cooled cold-controlled cold plates (commonly known as water-cooled radiators).
綜上所述，本發明提供了一種金屬熱界面材料，其組成包括必要的銦(In)、鎵(Ga)兩元素以及擇自錫(Sn)、銀(Ag)、鉍(Bi)和鋅(Zn)之至少一元素。該金屬熱界面材料具有寬廣的熔解溫度範圍，因此可更廣泛地應用在不同工作溫度之發熱元件，且其起始熔解溫度在60℃以上。而雖然以上實施例之描述皆以電子元件之散熱應用為主，但本發明之金屬熱界面材料可廣泛應用在任何發熱元件之熱管理系統上，包括(但不限於)：電子元件、光電元件、熱電元件、微機電元件等。In summary, the present invention provides a metal thermal interface material comprising the necessary indium (In), gallium (Ga) elements and selected from tin (Sn), silver (Ag), bismuth (Bi) and zinc. At least one element of (Zn). The metal thermal interface material has a wide melting temperature range, so that heating elements at different operating temperatures can be more widely used, and the initial melting temperature is above 60 °C. While the above description of the embodiments is mainly based on the heat dissipation application of electronic components, the metal thermal interface material of the present invention can be widely applied to the thermal management system of any heating element, including but not limited to: electronic components, photovoltaic components , thermoelectric components, microelectromechanical components, etc.
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above in several preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art, The scope of protection of the present invention is defined by the scope of the appended claims, unless otherwise claimed.
100‧‧‧構裝積體電路元件100‧‧‧Building integrated circuit components
112‧‧‧構裝基板112‧‧‧Packing substrate
114‧‧‧積體電路裸晶114‧‧‧Integrated circuit bare crystal
116‧‧‧金屬凸塊116‧‧‧Metal bumps
118‧‧‧陣列錫球118‧‧‧Array solder balls
120‧‧‧構裝基板底部表面120‧‧‧The bottom surface of the substrate
128‧‧‧均熱元件128‧‧‧Heating element
156‧‧‧焊錫合金156‧‧‧ solder alloy
TIM1‧‧‧第一熱界面材料TIM1‧‧‧ first thermal interface material
TIM2‧‧‧第二熱界面材料TIM2‧‧‧ second thermal interface material
101‧‧‧熱界面材料101‧‧‧ Thermal interface materials
102‧‧‧熱界面材料102‧‧‧ Thermal interface materials
124‧‧‧承載座124‧‧‧ bearing seat
200‧‧‧構裝半導體200‧‧‧Building semiconductor
214‧‧‧金屬線214‧‧‧Metal wire
215‧‧‧導電接腳215‧‧‧Electrical pins
310‧‧‧多層構裝基板310‧‧‧Multilayer substrate
320‧‧‧均熱板片材料320‧‧‧Homothermal sheet material
330‧‧‧介電層330‧‧‧ dielectric layer
338‧‧‧散熱器338‧‧‧heatsink
350‧‧‧導電線路350‧‧‧Electrical circuit
403‧‧‧鑲崁片403‧‧‧Inlay
416‧‧‧散熱塊416‧‧‧heat block
417‧‧‧電絕緣層417‧‧‧Electrical insulation
502‧‧‧光電半導體裸晶502‧‧‧Optoelectronic semiconductor die
第1圖為本發明的金屬熱界面材料ISG－10和ISG－30與SIG－10合金的熔解反應與凝固反應的熱流變化曲線。Figure 1 is a graph showing the heat flow curves of the melting reaction and solidification reaction of the metal thermal interface materials ISG-10 and ISG-30 and SIG-10 alloys of the present invention.
第2圖為本發明的金屬熱界面材料IAG－10和IAG－20與習知In－3Ag合金的熔解反應與凝固反應的熱流變化曲線。Fig. 2 is a heat flow curve of the melting reaction and solidification reaction of the metal thermal interface materials IAG-10 and IAG-20 of the present invention and the conventional In-3Ag alloy.
第3圖顯示本發明的金屬熱界面材料在構裝半導體的應用實施例。Figure 3 shows an embodiment of the application of the metal thermal interface material of the present invention to a packaged semiconductor.
第4圖顯示本發明的金屬熱界面材料在構裝半導體的另一應用實施例。Figure 4 shows another application embodiment of the metal thermal interface material of the present invention in the fabrication of a semiconductor.
100‧‧‧構裝積體電路100‧‧‧Building integrated circuits
114‧‧‧積體電路裸晶114‧‧‧Integrated circuit bare crystal
112‧‧‧構裝基板112‧‧‧Packing substrate
116‧‧‧金屬凸塊116‧‧‧Metal bumps
118‧‧‧陣列錫球118‧‧‧Array solder balls
120‧‧‧構裝基板的底部表面120‧‧‧The bottom surface of the substrate
128‧‧‧均熱元件128‧‧‧Heating element
156‧‧‧焊錫合金156‧‧‧ solder alloy
138‧‧‧散熱器138‧‧‧heatsink
TIM1‧‧‧第一熱界面材料TIM1‧‧‧ first thermal interface material
TIM2‧‧‧第二熱界面材料TIM2‧‧‧ second thermal interface material
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| TW097142026A TWI484604B (en) | 2008-10-31 | 2008-10-31 | Metal thermal interface materials and packaged semiconductors comprising the materials |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097142026A TWI484604B (en) | 2008-10-31 | 2008-10-31 | Metal thermal interface materials and packaged semiconductors comprising the materials |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201017837A TW201017837A (en) | 2010-05-01 |
| TWI484604B true TWI484604B (en) | 2015-05-11 |
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| TWI411691B (en) * | 2010-12-22 | 2013-10-11 | Ind Tech Res Inst | Metal thermal interface material and heat dissipation device |
| TWI719885B (en) * | 2020-04-13 | 2021-02-21 | 建準電機工業股份有限公司 | Chip device with uniform temperature heat dissipation structure |
| CN115041799B (en) * | 2022-05-25 | 2023-01-24 | 云南前沿液态金属研究院有限公司 | Alloy material for low-temperature welding of indium tin oxide film and welding method |
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| TW200822324A (en) * | 2006-11-15 | 2008-05-16 | Ind Tech Res Inst | Melting temperature adjustable metal thermal interface materials and use thereof |
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| TW200822324A (en) * | 2006-11-15 | 2008-05-16 | Ind Tech Res Inst | Melting temperature adjustable metal thermal interface materials and use thereof |
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