TWI483372B - 穿矽通孔及其製作方法 - Google Patents

穿矽通孔及其製作方法 Download PDF

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TWI483372B
TWI483372B TW101114388A TW101114388A TWI483372B TW I483372 B TWI483372 B TW I483372B TW 101114388 A TW101114388 A TW 101114388A TW 101114388 A TW101114388 A TW 101114388A TW I483372 B TWI483372 B TW I483372B
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Yu Shan Chiu
Kuo Hui Su
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Nanya Technology Corp
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Description

穿矽通孔及其製作方法
本發明係有關於半導體技術領域，特別是有關於一種用於堆疊晶片間連結的穿矽通孔(或稱直通矽晶穿孔；through-silicon via,TSV)及其製作方法。
穿矽通孔係一種貫穿矽基材的導體結構，用來連接他晶片的穿矽通孔或連接層的半導體連結技術，其製作方法大體上係在晶圓階段於各晶片預定處形成垂直通孔，再於各通孔內形成絕緣層，在絕緣層上形成晶種層，然後以電鍍方法將通孔填滿金屬，再以晶背研磨使穿矽通孔的一端曝露出來。
在晶圓經過切割成各個單獨晶片後，至少兩個晶片即可以透過穿矽通孔被垂直的堆疊在一封裝基板上，形成三維立體晶片封裝。接著，在將封裝基板表面及堆疊晶片膜封起來，最後將焊接錫球植於封裝基板的下表面。
通常，穿矽通孔的製作過程中，必須在凹入導孔內形成連續的銅晶種層，舉例來說，美國專利公開號2009/0226611 A1即披露了這樣的作法，其教導若要順利的在積體電路的凹入導孔內填入無縫的完整銅金屬結構，就必須在凹入導孔的內表面覆蓋一平坦且連續的銅晶種層。
另外，美國專利公開號2010/0200412 A1教導在穿矽通孔開口處不適合形成明顯較厚的晶種層，這是因為在穿矽通孔開口處形成厚的晶種層將造成在穿矽通孔開口處較低的阻值，並導致高的區域沈積率。
隨著穿矽通孔的尺寸越做越小，要形成無空隙或無縫的電鍍銅穿矽通孔結構的難度也越來越高。因此，目前該技術領域仍需要一種改良之製程方法，用以有效的形成無空隙或無縫的電鍍銅穿矽通孔結構。
為達上述目的，本發明一方面提供一種穿矽通孔，包含有：一絕緣層，連續的襯墊一凹入導孔結構的一側壁；一阻障層，連續的覆蓋著該絕緣層；一不連續晶種層，包含一第一部位，位於該凹入導孔結構的一端開口處；一不連續介電層，部分覆蓋住該凹入導孔結構的該側壁；以及一導電層，填入該凹入導孔結構。
本發明另一方面提供一種穿矽通孔，包含有：一絕緣層，連續的襯墊一凹入導孔結構的一側壁；一阻障晶種層，連續的覆蓋著該絕緣層；一不連續介電層，部分覆蓋住該凹入導孔結構的該側壁；以及一銅金屬層，填入該凹入導孔結構。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
第1A圖至第1F圖為依據本發明實施例所繪示於半導體基材上製作穿矽通孔的剖面示意圖。首先，如第1A圖所示，提供一半導體基材10，例如矽基材，其具有一前端面10a及一後端面10b，其中後端面10b將於後續製程中進行晶背研磨。通常，含有如電晶體或內連線結構等電路元件的積體電路係被製作在半導體基材10前端面10a，為簡化說明，這些電路元件並未被繪示出來。在完成電路元件及內連線結構之製作後，接著在半導體基材10前端面10a上毯覆沈積一保護絕緣層12，例如矽氧層或氮化矽層。接著，在保護絕緣層12及半導體基材10中蝕刻出一凹入導孔結構11。
前述之凹入導孔結構11通常具有高深寬比(high aspect ratio)，例如，深度對寬度的深寬比介於5至20之間。凹入導孔結構11此刻並未貫通基材的全部厚度，其包含有一接近垂直的側壁11a及一底部表面11b。在側壁11a及底部表面11b上可以形成有一均厚的絕緣層14，例如矽氧層。絕緣層14亦可以延伸覆蓋保護絕緣層12的上表面。繼之，於絕緣層14上形成一均厚的阻障層16，例如氮化鉭(TaN)、氮化鈦(TiN)、氮化碳鉭(TaCN)或鈦鎢合金(TiW)等。根據本發明之一實施例，阻障層16係為一連續層，亦即，凹入導孔結構11的全部側壁11a及底部表面11b均連續的被阻障層16覆蓋住。根據本發明之一實施例，前述之阻障層16可以利用物理氣相沈積(physical vapor deposition,PVD)法形成。
如第1B圖所示，接著在凹入導孔結構11內形成一不連續晶種層20，例如，鎢晶種層或銅晶種層。根據本發明之一實施例，不連續晶種層20可以包含一較厚的第一部位20a，其位於凹入導孔結構11的上端開口處附近，以及一第二部位20b，其僅形成在凹入導孔結構11的底部表面11b。第一部位20a與第二部位20b係互不相連，亦即，在第一部位20a與第二部位20b之間有明顯中斷不連續特徵。根據本發明之一實施例，側壁11a的下部並未被不連續晶種層20所覆蓋住。上述不連續晶種層20可以利用一低階梯覆蓋率PVD(low step-coverage PVD)製程形成，在PVD製程中，可以關閉RF功率偏壓，而將鎢直接沈積於底部表面11b。
如第1C圖所示，在形成不連續晶種層20之後，接著於不連續晶種層20的第一部位20a上覆蓋一不連續介電層22，例如，氧化矽、氮化矽或氧化鋁等，並且使不連續介電層22延伸覆蓋住未被不連續晶種層20覆蓋住的側壁11a下部。根據本發明之一實施例，不連續晶種層20的第二部位20b並未被不連續介電層22覆蓋住，以方便後續的銅電鍍製程的進行。上述不連續介電層22可以利用化學氣相沈積(chemical vapor deposition,CVD)法或原子層沈積(atomic layer deposition,ALD)法形成。根據本發明之一實施例，不連續介電層22的厚度可介於5至200埃。
如第1D圖所示，接著進行一銅電鍍製程，將凹入導孔結構11填滿一銅金屬層30。由於側壁11a被不連續介電層22覆蓋住，因此銅電鍍係由位於底部表面11b的不連續晶種層20的第二部位20b的上表面開始進行，故又可稱為「底部電鍍法」。根據本發明之一實施例，上述銅電鍍製程可以是無電電鍍(electroless plating)製程。此外，在其它實施例中，鎳、鈀或鈷亦可以用來填入凹入導孔結構11。
如第1E圖所示，在銅電鍍製程之後，進行一化學機械研磨(chemical mechanical polishing,CMP)製程，以研磨前端面10a。在研磨過程中，位於凹入導孔結構11之外的絕緣層14、阻障層16、不連續晶種層20的第一部位20a、不連續介電層22以及銅金屬層30將被移除，如此形成一平坦化的前端面10a。化學機械研磨製程之後，保護絕緣層12的上表面會被顯露出來。此時，保護絕緣層12可以作為一研磨停止層。
如第1F圖所示，在平坦化的前端面10a上接著沈積至少一介電層110以及至少一墊層122，其中，墊層122形成在介電層110上，可以是一打線連接墊層或一凸塊墊層。在介電層110可以形成至少一保護鈍化層120，且在保護鈍化層120中可以有一開口120a顯露出部分的墊層122的表面。墊層122可以電連接至下方的銅金屬層30。繼之，對半導體基材10的後端面10b進行晶背研磨，以顯露出銅金屬層30，如此即完成連通前端面10a與後端面10b的穿矽通孔100。然後，可以在顯露出來的銅金屬層30上形成一焊接錫球160，用以將前端面10a上的電路連接至一電路板或外部元件。
仍然參閱第1F圖，結構上，本發明穿矽通孔100包含有一均厚的絕緣層14，其連續的襯墊凹入導孔結構11的側壁11a；一阻障層16，連續的覆蓋住絕緣層14；一不連續晶種層20，包含一第一部位20a，位於凹入導孔結構11的一端開口處；一不連續介電層22，部分覆蓋住凹入導孔結構11的側壁11a；以及一鍍銅金屬層30，填入凹入導孔結構11。
第2A圖至第2C圖為依據本發明另一實施例所繪示於半導體基材上製作穿矽通孔的剖面示意圖。同樣的，如第2A圖所示，提供一半導體基材10，例如矽基材，其具有一前端面10a及一後端面10b，其中後端面10b將於後續製程中進行晶背研磨。通常，含有如電晶體或內連線結構等電路元件的積體電路係被製作在半導體基材10前端面10a，為簡化說明，這些電路元件並未被繪示出來。在完成電路元件及內連線結構之製作後，接著在半導體基材10前端面10a上毯覆沈積一保護絕緣層12，例如矽氧層或氮化矽層。接著，在保護絕緣層12及半導體基材10中蝕刻出一凹入導孔結構11。
前述之凹入導孔結構11通常具有高深寬比，例如，深度對寬度的深寬比介於2至20之間。凹入導孔結構11此刻並未貫通基材的全部厚度，其包含有一接近垂直的側壁11a及一底部表面11b。在側壁11a及底部表面11b上可以形成有一均厚的絕緣層14，例如矽氧層。絕緣層14亦可以延伸覆蓋保護絕緣層12的上表面。繼之，於絕緣層14上形成一均厚的阻障晶種層16’，例如釕(Ru)或鎢(W)等。根據本發明之一實施例，阻障晶種層16’係為一連續層，亦即，凹入導孔結構11的全部側壁11a及底部表面11b均連續的被阻障晶種層16’覆蓋住。根據本發明之一實施例，前述之阻障晶種層16’可以利用物理氣相沈積法形成。
如第2B圖所示，接著在阻障晶種層16’的上部覆蓋一不連續介電層22，例如，氧化矽，在底部表面11b上的阻障晶種層16’並未被不連續介電層22覆蓋住，以方便後續的銅電鍍製程的進行。上述不連續介電層22可以利用化學氣相沈積法或原子層沈積法形成。根據本發明之一實施例，不連續介電層22的厚度可介於5至200埃。
如第2C圖所示，接著進行一銅電鍍製程，將凹入導孔結構11填滿一銅金屬層30。由於側壁11a被不連續介電層22覆蓋住，因此銅電鍍係由位於底部表面11b的阻障晶種層16’開始進行。根據本發明之一實施例，上述銅電鍍製程可以是無電電鍍製程。此外，在其它實施例中，鎳、鈀或鈷亦可以用來填入凹入導孔結構11。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10．．．半導體基材
10a．．．前端面
10b．．．後端面
11．．．凹入導孔結構
11a．．．側壁
11b．．．底部表面
12．．．保護絕緣層
14．．．絕緣層
16．．．阻障層
16’．．．阻障晶種層
20．．．不連續晶種層
20a．．．第一部位
20b．．．第二部位
22．．．不連續介電層
30．．．銅金屬層
100．．．穿矽通孔
110．．．介電層
120．．．保護鈍化層
120a．．．開口
122．．．墊層
160．．．焊接錫球
第1A圖至第1F圖為依據本發明實施例所繪示於半導體基材上製作穿矽通孔的剖面示意圖。
第2A圖至第2C圖為依據本發明另一實施例所繪示於半導體基材上製作穿矽通孔的剖面示意圖。
10．．．半導體基材
10a．．．前端面
10b．．．後端面
11a．．．側壁
12．．．保護絕緣層
14．．．絕緣層
16．．．阻障層
20a．．．第一部位
22．．．不連續介電層
30．．．銅金屬層
100．．．穿矽通孔
110．．．介電層
120．．．保護鈍化層
120a．．．開口
122．．．墊層
160．．．焊接錫球

Claims (10)

  1. 一種穿矽通孔，包含有：一絕緣層，連續的襯墊一凹入導孔結構的一側壁；一阻障層，連續的覆蓋著該絕緣層；一不連續晶種層，包含一第一部位，位於該凹入導孔結構的一端開口處；一不連續介電層，部分覆蓋住該凹入導孔結構的該側壁；以及一導電層，填入該凹入導孔結構。
  2. 如申請專利範圍第1項所述之穿矽通孔，其中該導電層係為一鍍銅金屬層。
  3. 如申請專利範圍第1項所述之穿矽通孔，其中該絕緣層包含有氧化矽或氮化矽。
  4. 如申請專利範圍第1項所述之穿矽通孔，其中該阻障層包含有氮化鉭、氮化鈦、氮化碳鉭或鈦鎢合金。
  5. 如申請專利範圍第1項所述之穿矽通孔，其中該不連續晶種層包含有鎢。
  6. 如申請專利範圍第1項所述之穿矽通孔，其中該不連續晶種層係 為PVD鎢。
  7. 如申請專利範圍第1項所述之穿矽通孔，其中該不連續介電層包含有氧化矽。
  8. 如申請專利範圍第1項所述之穿矽通孔，其中該不連續介電層將該不連續晶種層的該第一部位與該導電層隔離。
  9. 如申請專利範圍第1項所述之穿矽通孔，其中該不連續晶種層具有一第二部位，且該第二部位不被該不連續介電層覆蓋。
  10. 如申請專利範圍第1項所述之穿矽通孔，其中該不連續介電層的厚度介於5至200埃。
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