TWI480870B - Semiconductor device - Google Patents

Description

Semiconductor device

The present invention relates to a semiconductor device in which a thin film magnetic memory element is stacked on a substrate, and the thin film magnetic body changes the magnetoresistance effect of the electric resistance by a magnetization direction.

MRAM (Magnetoresistive Random Access Memory) is attracting attention as a low-power consumption non-volatile RAM (random access memory) that can operate at high speed. MRAM is a type of thin film magnetic memory device that utilizes a magnetization direction to change the magnetoresistance effect of a resistor. A TMR element (a tunneling magnetoresistive element) is generally used as a magnetoresistive element in an MRAM.

The TMR element is a magnetoresistive element having a tunnel junction structure formed by a fixed magnetization layer composed of a ferromagnetic thin film and a free magnetization layer sandwiching a thin insulating layer. The TMR element memorizes the information of "1" and "0" according to whether the magnetization directions of the two layers are parallel or anti-parallel.

When the data is read, the sense current (data read current) flows into the TMR element, and the difference in tunnel resistance caused by the magnetization direction is detected. In order to control the ON/OFF of the sensing current, an access transistor connected in series with the TMR element is provided. The gate of the access transistor is connected to the word line.

A method of inverting a magnetization direction of a free magnetization layer when data is written, a method of inverting a magnetization direction by a magnetic field caused by current induction, and a method of injecting a spin polarization current by a conventional method .

The method of current-induced magnetic field is to simultaneously flow current to the bit line and the digit line which are mutually intersected, and utilize the induced synthetic magnetic field. The TMR element disposed near the intersection of the bit line and the digit line has a size of a combined magnetic field that is induced to be outside the star curve, causing magnetization reversal.

On the other hand, in the spin injection method, the TMR element directly flows into the bit line current above the threshold to invert the magnetization direction of the free magnetization layer.

When a current flows from the free magnetization layer to the direction of the fixed magnetization layer, electrons that hold and rotate in the same direction as the magnetization layer are injected into the free magnetization layer through the tunnel insulating film. At this time, the injected electrons affect the spin torque of the free magnetization layer, and the magnetization direction of the free magnetization layer changes to the same direction as the fixed magnetization layer.

Conversely, when the current flows from the fixed magnetization layer to the direction of the free magnetization layer, the electrons that hold and fix the reverse rotation of the magnetization layer are reflected in the tunnel insulating film. At this time, the reflected electrons affect the spin torque of the free magnetization layer, and the magnetization direction of the free magnetization layer changes to the opposite direction to the fixed magnetization layer.

Other methods for writing data include a combination of a spin injection method and a current induced magnetic field method.

For example, JP-A-2007-109313 (Patent Document 1) discloses that a write current is supplied to a selected bit line by a digit line drive circuit at the time of data writing. By the current induced magnetic field, the magnetization direction of the free magnetization layer of the memory cell coupled to the digit line is set to the opposite direction of the fixed magnetization layer. Then, by the bit line current from the write drive circuit, the polarization spin of the fixed magnetization layer is injected into the free magnetization layer in the same direction as the polarization spin, and only the writing of the data "1" is performed. . This spin injection is performed in parallel on the memory cell in which the data "1" is written.

Further, for example, in a memory array in which a plurality of TMR memory cells are arranged in a matrix, bit lines and word lines are arranged corresponding to the memory cells, and bit lines are arranged corresponding to the memory cells. The digit lines and word lines are sometimes divided into a plurality of configurations.

For example, Japanese Laid-Open Patent Publication No. 2003-77267 (Patent Document 2) discloses a technique of subdividing the entire memory cell array into memory cell blocks arranged in a matrix of m rows × n columns (m, n is a natural number). In each memory block, the TMR memory cells are arranged in a matrix. In each line of each memory cell, the sub-word line for reading the configuration data and the writing digit line for writing data are used. That is, the write digit line is arranged in each block of the memory block independently corresponding to each memory cell row. Further, as the row selection upper bit signal line, the main word line system and the sub word line and the write bit line are set in a hierarchical manner. The main character line is tied to each of the plurality of memory cells, and n memory cell blocks adjacent to each other in the row direction are commonly configured.

Patent Document 1: JP-A-2007-109313

Patent Document 2: JP-A-2003-77267

In the prior art disclosed in Japanese Laid-Open Patent Publication No. 2003-77267 (Patent Document 2), it is necessary to use a driving circuit for sub-word lines and write digit lines, independent of the line decoding circuit, and individually set in each memory cell. Each block of the block. Therefore, as the number of memory cells is increased as the memory array is subdivided, the circuit area of the drive circuit of the memory array becomes larger.

Further, in terms of speeding up the reading speed of the data, it is preferable to increase the number of memory cells and to make the length of the sub-word lines shorter. The reason for this is that the sub-word line for gate voltage control of the access transistor is formed by using polysilicon or polycrystalline germanium in the same wiring layer of the gate. As a result of using these materials, the resistance of the sub-word line becomes larger as compared with the metal wiring, and a signal transmission delay occurs when the data is read. That is, in the above-described conventional technique, it is difficult to achieve both an improvement in data reading speed and a reduction in circuit area.

As for the MRAM using the magnetoresistance effect, it is possible to perform high-speed data writing/reading as one of the features. Therefore, in order to achieve differentiation with flash memory, MRAM is also expected to be able to perform higher speed data writing/reading.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device which can reduce the area of a word line driving circuit while performing high speed data reading.

The semiconductor device of the present invention includes a memory array including a plurality of memory cells arranged in a matrix and dividing into a plurality of blocks in the row direction. Wherein, each of the plurality of memory cells includes: a magnetoresistive element whose resistance corresponds to magnetic material data; and a switching element connected in series to the magnetoresistive element and having a control electrode. The thin film magnetic memory device of the present invention further includes: a plurality of bit lines; a plurality of bit lines; a plurality of digital lines; and a plurality of piling word lines. Among them, a plurality of bit lines are respectively provided corresponding to the memory array of the memory array, and each of the first data writing currents necessary for writing the inflowing magnetic material data. Most of the digit lines are individually arranged for each of the plurality of blocks, and the second data write current flows in the direction intersecting with the first data write current to perform the magnetic gas. The writing of the data. The plurality of digital element lines are connected to a plurality of control electrodes included in the memory cell row corresponding to the memory array, and are formed of a conductive layer having a first sheet resistance. Most of the piling word lines are respectively corresponding to the memory cells of the memory array, and are commonly disposed in a plurality of blocks, each of which is formed of a conductive layer having a second sheet resistance smaller than the first sheet resistance, in a plurality of positions. It is electrically connected to the word line set on the corresponding memory cell line.

(Best form of implementing the invention)

Embodiments of the present invention will be described below with reference to the drawings. In addition, the same or equivalent portions are denoted by the same reference numerals, and the repeated description is omitted.

Further, in the following embodiments, an MRAM in which the magnetization of the free magnetization layer is reversed by a current-induced magnetic field is described. However, the present invention is also applicable to a method in which a magnetic field induced by a current is combined with spin injection to perform data writing. MRAM.

(First Embodiment) FIG. 1 is a schematic plan view showing an example of a configuration of a semiconductor device 1 according to a first embodiment of the present invention.

The semiconductor device 1 includes a microcomputer unit 2, an SRAM (Static Random Access Memory) unit 3, an analog circuit unit 4, and a pulse generation unit 5 formed on a semiconductor substrate SUB. The semiconductor device 1 is a semiconductor integrated circuit called a system LSI (Large Scale Integrated Circuit) in which a memory circuit, an analog circuit, and a digital circuit are stacked on one semiconductor substrate.

The microcomputer unit 2 of Fig. 1 includes an MRAM unit 6 as a memory circuit. Conventionally, a plurality of types of memory such as a flash memory or a DRAM (Dynamic Random Access Memory) are mixed on a microcomputer as a memory such as a ROM (Read Only Memory) and a RAM. With the characteristics of high speed, low power consumption, non-volatile, and unlimited number of rewrites of MRAM, in the semiconductor device 1, a variety of memory devices thereof are replaced by MRAM. Further, in Fig. 1, the SRAM unit 3 is provided independently of the MRAM unit 6, but the SRAM unit 3 may be replaced by an MRAM.

Fig. 2 is a block diagram showing the overall configuration of the MRAM unit 6 of Fig. 1. Referring to FIG. 2, the MRAM unit 6 performs random access of the memory array 10 in response to the command signal CMD, the clock signal CLK, and the address signal ADD, thereby performing writing of the write data Din and reading of the read data Dout. Out.

The MRAM unit 6 includes: a control circuit 140 for controlling the overall operation of the MRAM unit 6 in response to the command signal CMD and the pulse signal CLK; the memory array 10 having a plurality of memory cells MC arranged in a matrix; and an input and output circuit 150, for inputting and writing data Din and reading data Dout.

Each memory cell MC includes a TMR element and an access transistor ATR. In order to perform data reading and data writing on the majority of the memory cells MC, the memory array 10 is provided with a plurality of digital element lines WL, digit lines DL, and bit lines BL. The word line WL and the digit line DL are arranged in the row direction corresponding to the memory cell row, and the bit line BL is arranged in the column direction corresponding to the memory cell row.

The input/output circuit 150 includes an address signal latch circuit 153, a write data latch circuit 151, and a read data for temporarily holding the address signal ADD, the write data Din, and the read data Dout. Latch circuit 152.

The MRAM section 6 additionally includes a sense amplifier 20, a row decoder (row decoding circuit, row selection circuit) 40, a word line driver (word line driver circuit) 50, a bit line driver (digital line driver circuit) 60, and a column. A decoder (column decoding circuit, column selection circuit) 70, and a bit line driver (bit line driving circuit) 80.

The sense amplifier 20 is used for detecting and amplifying the difference between the passing current of the selected memory cell and the reference current when the data is read. The sense amplifier 20 outputs a signal for detection and amplification to the read data latch circuit 152.

The row decoder 40 receives the address signal ADD from the address signal latch circuit 153 and decodes the row address signal RA indicated by the address signal ADD. The row decoder 40 outputs a row selection signal of the decoding result in response to the command signal CMD (read permission signal RE, write permission signal WE) of the control circuit 140. The row select signal is used to perform row selection of the memory array 10.

The word line driver 50 receives the row selection signal from the row decoder 40 for data activation, and performs activation processing of the corresponding word line.

The digit line driver 60 receives the row selection signal from the row decoder 40 at the time of data writing, and flows in the corresponding direction of the write data Din from the write data latch circuit 151 on the corresponding digit line DL. Current.

The column decoder 70 receives the address signal ADD supplied from the address signal latch circuit 153, and decodes the column address signal CA indicated by the address signal ADD. The column decoder 70 outputs a column selection signal of the decoding result in response to the command signal CMD (read permission signal RE, write permission signal WE) supplied from the control circuit 140. The column select signal is used to perform column selection of the memory array 10.

The bit line driver 80 receives the column selection signal supplied from the column decoder 70, and causes the data write current to flow into the corresponding bit line BL at the time of data writing.

The MRAM unit 6 additionally includes a reference power source 160 that generates various reference voltages for supply to the sense amplifier 20, the row decoder 40, the word line driver 50, the digit line driver 60, the column decoder 70, and the bit elements. Line driver 80 and the like.

FIG. 3 is a circuit diagram showing a schematic configuration of each of the memory cells MC constituting the memory array 10 of FIG.

Referring to FIG. 3, the memory cell MC includes: a TMR element whose resistance changes corresponding to the magnetic material data; and an access transistor ATR. Among them, the TMR element is a magnetoresistive element, and has a transmission-bonding structure in which a fixed magnetization layer made of a ferromagnetic thin film and a free magnetization layer are used to hold a thin insulating layer. Typically, a field effect transistor is used as the access transistor ATR.

The bit line BL, the digit line DL, the word line WL, and the source line SL are arranged for the TMR element. As shown in FIG. 3, the TMR element has one end connected to the bit line BL and the other end connected to the drain of the access transistor ATR. The source of the access transistor ATR is connected to the ground node GND via the source line SL. Further, the gate of the access transistor ATR is connected to the word line WL.

When the data is written, the digit line DL of the memory cell row (hereinafter also referred to as the selection row) corresponding to the selected memory cell to be written into the data, and the memory cell array (hereinafter also referred to as the selection column) corresponding to the selected memory cell are selected. The bit line BL flows into the data write current, respectively. Wherein, the current direction flowing into the bit line BL can be switched according to the written data. The direction of magnetization of the free magnetization layer is determined by the direction of current flowing into the bit line BL.

At the time of reading the data, the word line WL corresponding to the selected memory cell is activated to a high voltage state, and the access transistor ATR is turned on. As a result, the sense current (data read current) flows from the bit line BL to the source line SL via the TMR element and the access transistor ATR. Further, the high voltage state and the low voltage state of the two values of the following address signals, signal lines, and data are H (high) level and L (low) level, respectively.

The source line SL, the bit line BL, and the digit line DL are formed using a metal wiring layer, and the word line WL is integrated with the gate of the access transistor ATR for improving the accumulation degree or simplifying the process. Therefore, the word line WL is formed using polycrystalline germanium or polycrystalline germanide or the like.

Fig. 4 is a plan view showing an example of the arrangement of the respective sections of the MRAM unit 6 of Fig. 2; Hereinafter, the left-right direction of FIG. 4 is the row direction X or the X direction, and the up-and-down direction is the column direction Y or the Y direction.

Referring to Fig. 4, memory array 10 is divided into a plurality of memory arrays having the same configuration and disposed on substrate SUB. In the case of FIG. 4, the eight memory arrays 10_0 to 10_7 are arranged in two rows in the row direction X and two columns in the column direction Y. Each of the memory arrays 10_0 to 10_7 includes a plurality of memory cells MC arranged in a matrix in the X and Y directions. As will be described later, each of the memory arrays 10_0 to 10_7 is divided into a plurality of memory blocks BK in the X direction.

The column decoder 70 is disposed on both sides of the column direction Y of each of the memory arrays 10_0 to 10_7. For example, column decoders 70_0 and 70_1 are provided on both sides of the column direction Y of the memory array 10_0. Further, the row decoder 40 is disposed in the column direction Y so as to extend substantially in the center in the row direction X.

The sense amplifier 20 is disposed at the center of two sets of memory arrays adjacent to each other in the column direction Y. In FIG. 4, for example, the sense amplifier 20_0 is disposed in the center of the memory arrays 10_0 and 10_1. The other sense amplifiers 20_1 to 20_3 are also configured in the same manner.

In the MRAM portion 6 shown in FIG. 4, the bit lines BL to which the sense amplifiers 20_1 to 20_3 are connected are formed by means of an open bit line in which the sense amplifiers 20_1 to 20_3 are wired on both sides. . In addition, the present invention is also applicable to the manner in which the bit line BL is in a faulted bit line manner in which the sense amplifier 20 bends the wiring in the same direction.

The control circuit 140 and the input/output circuit 150 are disposed at one end of the column direction Y of the MRAM unit 6.

Fig. 5 is an explanatory view showing the configuration of the memory array 10_0 of Fig. 4. Fig. 5 shows the memory array 10_0 as a representative of the memory arrays 10_0 to 10_7 of the MRAM unit 6 of Fig. 4.

Referring to Fig. 5, memory array 10_0 includes k (k is an integer of 2 or more) memory blocks BK<0> to BK<k-1> (collectively referred to as memory blocks BK) arranged in the row direction X.

Each of the memory blocks BK includes a plurality of memory cells MC arranged in a matrix in the X and Y directions. As shown in FIG. 5, each of the memory blocks BK has m × n rows (m, n is an integer of 2 or more) in the X direction, and 1 column (1 is an integer of 2 or more) in the Y direction. The memory cell MC is configured. Therefore, in the memory array 10_0, the memory cells MC are arranged in the x direction in the X direction and in the Y direction in the k × 1 column. Further, as will be described later, the parameter m indicates the number of main digit lines MDL.

For example, assuming that m=64, n=4, k=4, and 1=128, each memory block BK has a configuration of 256 characters × 128 bits, and the memory capacity of each memory block BK is 32K bits. Therefore, the memory capacity of the memory array 10_0 becomes 128K bits, and the memory capacity of the entire MRAM portion 6 of Fig. 4 becomes 1M bits.

The memory array 10_0 additionally includes a plurality of bit lines BL, sub bit lines SDL, main digit lines MDL, word lines WL, and piling word lines CWL.

In the column direction Y, k × 1 bit lines BL<0> to BL<k1-1> (collectively referred to as bit lines BL) are provided corresponding to the respective memory cells.

In the row direction X, each of the memory blocks BK is provided with m×n sub-bit lines SDL<0> to SDL<mn-1> (collectively referred to as sub-bit lines SDL) corresponding to the respective memory cells. Further, in the k memory blocks BK of the memory array 10_0, m main digit lines MDL<0> to MDL<m-1> (collectively referred to as main digit lines MDL) are arranged in the row direction X in a common manner.

In the first embodiment, the digit line DL is hierarchically grouped by the main digit line MDL and the S digit line DL. In this case, it is conceivable that the m×n sub-digit line SDL belonging to each memory block BK constitutes a line group according to each of the n sub-digit lines SDL adjacent to each other. The number of the row groups of the sub-digit line SDL is m. The main digit line MDL corresponds to m row groups, respectively. For example, the main digit line MDL<0> corresponds to the row group formed by the sub-bit lines SDL<0> to SDL<n-1>. Similarly, the main digit line MDL<m-1> corresponds to the row group formed by the sub-bit lines SDL<mn-n> to SDL<mn-1>.

At the time of data writing, the row selection signal outputted by the row decoder 40 uses the main decoding signal transmitted by the main digit line MDL, and the sub-decoding signals SDW<0> to <n-1> of n bits. (Also known as sub-decoding signals SDW<0:n-1>, collectively referred to as sub-decoding signals SDW). The output node of the row decoder 40 is connected to the signal lines for the m main digital bit lines MDL and the n sub decoding signals SDW. At the time of data writing, one of the above-mentioned row groups is selected by the main decoding signal circulating on the main digit line MDL. Further, one sub-bit line SDL belonging to the selected line group is selected by the sub-decoding signal SDW.

In addition, in the row direction X of the memory array 10_0, each of the memory blocks BK is provided, and m×n word lines WL<0> to WL<mn-1> are set corresponding to the respective memory cells (collectively referred to as Word line WL) (as shown in Figure 6). In addition, in the k memory blocks BK of the memory array 10_0, m×n piling word lines CWL<0> to CWL<mn-1> are set in a common manner corresponding to each memory cell row (collectively referred to as piling characters). Line CWL). The word line WL and the gate of the access transistor ATR are integrated, and thus are formed by polysilicon or polycrystalline germanium. In contrast, the piling word line CWL is formed by a metal material on the upper layer of the word line. . The piling word line CWL is electrically connected to the word line WL disposed in the same memory cell row at a plurality of positions. The piling word line CWL is also referred to as a branch wiring CWL.

The memory array 10_0 additionally includes a word line driver 50, a digit line driver 60<0> to 60<k-1>, a bit line driver 80_0, 80_1, and a bit line selection circuit 90.

The word line driver 50 is commonly arranged in the k memory blocks BK, and is arranged in close proximity to the row decoder 40 in the case of the first embodiment. The output node of the word line driver 50 is connected to the piling word line CWL. The row decoder 40 transmits the row selection signal to the word line driver 50 in accordance with the row address signal RA when the read permission signal RE is set to the active state. The word line driver 50 sets the C word line WL corresponding to the selected row to the H level according to the received row selection signal. As a result, the word line WL electrically connected to the peg word line CWL at a plurality of positions is set to the active state, and the access transistor ATR of the memory cell MC of the selected line is turned on.

The resistance of the peg word line CWL formed of the metal material is smaller than that of the word line WL formed by polycrystalline germanium or polycrystalline germanide. Therefore, the piling word line CWL can transmit a signal at a high speed compared to the word line WL. Therefore, as in the first embodiment, the piling word line CWL and the word line WL are electrically connected at a plurality of positions, whereby the activation signal from the word line driver 50 can be transmitted to the farthest memory cell MC at a high speed.

Further, when the piling word line CWL is used, the word line driver 50 for setting the piling word line CWL to the active state can be disposed in common to the plurality of memory blocks BK. Therefore, when the word line driver 50 is disposed in each of the memory blocks BK and the word line WL is directly set to be in an activated state, the arrangement area of the word line driver 50 can be reduced.

The digit line drivers 60<0> to 60<k-1> (collectively referred to as the digit line drivers 60) are provided corresponding to the memory blocks BK<0> to BK<k-1>, respectively. Signal lines for the m main bit lines MDL and the n sub decoding signals SDW are connected to each of the digit line drivers 60<0> to 60<k-1>. Further, the digital line drivers 60<0> to 60<k-1> are supplied with the corresponding block selection signals BS<0> to BS<k-1> by the column decoder 70_0 (collectively referred to as block selection signals). BS). The column decoder 70_0 sets the block selection signal BS to an active state for the bit line driver 60 corresponding to the memory block BK (hereinafter also referred to as a selection memory block) including the selected memory cell.

The output nodes of the digital line drivers 60<0> to 60<k-1> are connected to the sub-digit line SDL of the corresponding memory block BK. Each of the bit line drivers 60 supplies a data write current to the sub-bit line SDL selected by the main decoding signal of the main digit line MDL and the sub-bit line SDL selected by the sub-decoding signal SDW when the block selection signal BS is supplied in the active state. Therefore, since the data write current is not flown into the unselected memory block BK, the power consumption of the entire MRAM unit 6 can be reduced, and the possibility of erroneous writing can be reduced.

Further, in the memory array 10_0 of the first embodiment, as described above, the sub-digit line SDL for the data write current is divided and set in accordance with each memory block BK. Therefore, the wiring resistance of the digit line can be reduced as compared with the case where the majority of the memory block BK is commonly configured with the bit line. As a result, the digit line driver 60 can supply a sufficiently large current for data writing without increasing the voltage of the power supply node VDD.

The bit line drivers 80_0 and 80_1 are disposed on both sides of the column direction Y across the memory block BK. The output nodes of the bit line drivers 80_0, 80_1 are connected to k × 1 bit lines BL<0> to BL<k1-1>. The bit line drivers 80_0 and 80_1 are based on the column selection signals of the column decoders 70_0 and 70_1, and write data to the data lines corresponding to the bit line BL corresponding to the selected column in the direction corresponding to the data Din.

The bit line selection circuit 90 receives the column selection signal of the column decoder 70_1 as a gate function for connecting the bit line BL corresponding to the selected column and the sense amplifier 20_0.

FIG. 6 is a circuit diagram showing the memory block BK<0> of FIG. 5 and its corresponding digit line driver 60<0>. 6 shows the digital line driver 60 with k memory blocks BK<0> to BK<k-1> and k digit line drivers 60<0> to 60<k-1> respectively represented in FIG. <0> and the composition of the memory block BK<0>.

Referring to FIG. 6, a plurality of memory cells MC provided in the memory block BK<0> are set on one bit line BL<0> to BL<1-1> and m×n piling word lines CWL< 0>~CWL<mn-1> The position of the intersection.

The word line WL to which the gate of the access transistor ATR of each memory cell MC is connected is electrically connected to the corresponding peg word line CWL at a plurality of positions. The source lines SL<0> to SL<mn-1> (collectively referred to as source lines SL) to which the sources of the access transistors ATR of the memory cells MC are connected are arranged in the row direction X. One end of the source line SL is connected to the ground node GND.

The sub-digit line SDL is wired in the row direction X in close proximity to the TMR element of the memory cell MC provided in the corresponding memory cell row. One end of each sub-digit line SDL is connected to the power supply node VDD. The other end of each sub-digit line SDL is connected to the drain of the corresponding driving transistor 66 provided in the bit line driver 60<0>.

The digit line driver 60<0> includes: n AND gates 62<0> to 62<n-1> (collectively referred to as an AND gate ("AND" gate) 62; and m×n AND gates 68<0> ～68<mn-1> (collectively referred to as AND gate 68); and m×n drive transistors 66<0> to 66<mn-1> (collectively referred to as drive transistor 66).

The AND gates 62<0> to 62<n-1> are respectively provided corresponding to the n sub-decoding signals SDW<0> to SDW<n-1>. One of the input terminals of the AND gate 62<0> to 62<n-1> is commonly input to the corresponding block selection signal BS<0>, and the other input terminal is input with the corresponding sub-decoding signal SDW. <0> to SDW<n-1>. The output terminals of the AND gates 62<0> to 62<n-1> are connected to the n signal lines 64<0> to 64<n-1>, respectively. The AND gate 62 activates the corresponding signal line 64 to the H level when the block selection signal BS<0> is activated to the H level and the corresponding sub-decoding signal SDW is activated to the H level.

The AND gates 68<0> to 68<mn-1> are respectively provided corresponding to the m×n sub-bit lines SDL<0> to SDL<mn-1>. Therefore, similarly to the sub-digit line SDL, it is conceivable that one row group is constituted by each of the n AND gates 68 corresponding to each of the main digit lines MDL.

One of the n AND gates 68 belonging to the same row group is commonly connected to the corresponding main digit line MDL. The other input terminals of the n AND gates 68 belonging to the same row group are individually connected with n signal lines 64<0> to 64<n-1>. For example, the other input terminals of the AND gates 68<0> to 68<mn-1> corresponding to the main digit line MDL<0> are connected to the signal lines 64<0> to 64<n-1>, respectively. Similarly, the other input terminal of the AND gate 68<mn-n> to 68<mn-1> corresponding to the main digit line MDL<m-1> is connected to the signal line 64<0> to 64<n-1, respectively. >.

The driving transistor 66 is an N-channel MOS transistor. The gates of the driving transistors 66<0> to 66<mn-1> are respectively connected to the output terminals of the AND gates 68<0> to 68<mn-1>. The output of the AND gate 68 is activated to the H level, and the corresponding drive transistor 66 is turned on. As a result, a data write current flows from the power supply node VDD to the ground node GND via the sub-digit line SDL.

According to the configuration of the above-described digit line driver 60<0>, the AND gate 62 outputs the logical product of the block selection signal BS and the sub-decoding signal SDW. Further, the AND gate 68 is a logical product of the output of the AND gate 62 and the main decoded signal of the main digit line MDL. As a result, corresponding to the output of the AND gate 68, the data write current flows into the corresponding sub-digit line SDL. Thus, in the selected block selected by the column decoder 70, the data write current flows into the sub-digit line SDL corresponding to the selected row selected by the row decoder 40.

The order of writing data and reading data for the selected memory cell will be described below with reference to a specific timing chart.

Fig. 7 is a timing chart showing the data writing operation and the data reading operation of the memory cell MC of the memory array 10_0. In FIG. 7, the horizontal axis represents time, and the vertical axis sequentially represents the clock signal CLK, the read permission signal RE, the write permission signal WE, the voltage waveform of the main digit line MDL<0>, and the block selection signal BS from the top. The voltage waveform, the voltage waveform of the sub-decoding signal SDW, the current waveform I (SDL<0>) of the sub-digit line SDL<0> in the memory block BK<0>, and the current waveform I of the bit line BL<0> (BL<0>), the voltage waveform of the piling word line CWL<0> and the voltage waveform of the word line WL<0> in the memory block BK<0>.

Hereinafter, among the plurality of memory cells MC in which the memory block BK<0> of FIG. 6 is set, the memory cell MC in which the intersection of the near word line WL<0> and the bit line BL<0> is set is selected. The sequence of writing/reading data for the selected memory cell will be described with reference to Figs. 5-7.

Among them, the data writing/data reading is performed in synchronization with the clock signal CLK. The time t0 to t6 at which the write permission signal WE is activated to the H level is a write cycle in which data is written to the selected memory cell. Further, the time t6 to t9 at which the read permission signal KE is activated to the H level is a read cycle in which data is read by the selected memory cell. First, explain the data write cycle.

At time t1, the column decoder 70_0 sets the block selection signal BS<0> to the H level of the active state. At this time, the other block selection signals BS<1> to BS<k-1> are maintained at the L level. In this case, the memory block BK<0> (selection memory block) including the selected memory cell is selected.

At time t2, the row decoder 40 sets the main digit line MDL<0> and the sub-decode signal SDW<0> to the H level of the active state. In this case, the outputs of the AND gate 62<0> and the AND gate 68<0> of the digit line driver 60<0> become the H level, so the driving transistor 66<0> connected to the sub-digit line SDL<0> is Turn on. As a result, a data write current is supplied to the sub-digit line SDL<0>.

At time t3, the bit line drivers 80_0, 80_1 are in response to the column selection signals from the column decoders 70_0, 70_1, and correspond to the bit line BL<0> corresponding to the selected column, and the inflow and write data Din are corresponding. The direction data is written to the current. As a result, both the sub-digit line SDL<0> and the bit line BL<0> are supplied with the data write current, and the selected memory cell provided at the intersection of the two is written into the data.

At time t4, the row decoder 40 sets the main digit line MDL<0> and the sub-decode signal SDW<0> to the L level of the inactive state. Thus, the outputs of the AND gate 62<0> and the AND gate 68<0> of the digit line driver 60<0> return to the L level, and the drive transistor 66<0> becomes non-conductive. As a result, the current I (SDL<0>) of the sub-bit line SDL<0> in the memory block BK<0> is stopped, and the data writing to the selected memory cell is ended.

At time t5, the column decoders 70_0, 70_1 set the block selection signal BS<0> to the L level. Further, the column decoders 70_0 and 70_1 stop the supply of the current (BL<0>) of the bit line driver 80_0, 80_1 to the bit line BL<0>.

The data readout period is explained below. The word line driver 50 that receives the row selection signal from the row decoder 40 sets the piling word line CWL<0> to the H level of the active state at time t7. In this case, the word line WL<0> to which the piling word line CWL<0> is connected is activated to the H level, and the access transistor ATR of the selected row is turned on. Further, the bit line selection circuit 90 that receives the column selection signal from the column decoder 70_1 connects the bit line BL<0> corresponding to the selected column to the sense amplifier 20_0. The sense amplifier 20_0 detects the difference between the data read current flowing into the selected memory cell through the bit line BL<0> and the reference current, and amplifies it.

At the next time t8, the piling character line CWL<0> returns to the L level, and the word line WL<0> also returns to the L level. In this case, the access transistor ATR of the selected row becomes non-conductive. Further, by the bit line selection circuit 90, the connection between the bit line BL<0> and the sense amplifier 20_0 is cut off.

Fig. 8 is a cross-sectional structural view showing a memory cell MC of the first embodiment. Referring to Fig. 8, an access transistor ATR is formed on the main surface of the p-type semiconductor substrate SUB. The access transistor ATR has a source region 110 of an n-type region, and a drain region 112 and a gate. The gate line and the word line WL are integrally formed. On the main surface of the semiconductor substrate SUB, the first to fifth metal wiring layers M1 to M5 are sequentially laminated with each other through the interlayer insulating film from the substrate side.

The source region 110 of the access transistor ATR is electrically connected to the source line SL formed using the first metal wiring layer M1 via the metal film 116 formed in the contact hole. Further, the gate and the word line WL are electrically connected to the peg word line CWL formed using the second metal wiring layer M2 via the metal film 114 formed in the contact hole.

The main digit line MDL is formed using the third metal wiring layer M3 of the upper layer of the piling word line CWL, and the sub-digit line SDL is formed by the fourth metal wiring layer M4 of the upper layer.

The TMR element is disposed above the sub-digit line SDL. The TMR element has a magnetic layer (fixed magnetization layer) PL having a fixed magnetization direction, and a magnetic layer (free magnetization layer) FL which is magnetized in a direction corresponding to a data write magnetic field generated by a data write current. . A tunneling barrier layer ISO formed of an insulator film is disposed between the fixed magnetization layer PL and the free magnetization layer FL.

The TMR element is electrically connected to the drain region 112 of the access transistor ATR via a metal film 118 formed on the contact hole and the barrier metal 120. The barrier metal 120 is a buffer member provided to achieve electrical coupling between the TMR element and the metal film. The bit line BL is electrically coupled to the free magnetization layer FL of the TMR element, and is provided on the fifth metal wiring layer M5 of the upper layer of the TMR element.

As described above, in the memory cell MC of the first embodiment, the source line SL, the piling word line CWL, the main digit line MDL, the sub-digit line SDL, and the bit line BL are formed. Therefore, all five metal wiring layers are required. M1 ~ M5.

According to the MRAM unit 6 of the first embodiment, the piling word line CWL electrically connected to the word line WL at a plurality of positions is commonly disposed in the plurality of memory blocks BK. The word line driver 50 transmits the activation signal of the word line WL using the piling word line CWL having a resistance smaller than the word line WL. Therefore, the transmission of the activation signal to the memory cell MC can be speeded up, and the reading of the data from the memory cell MC can be speeded up.

Further, by using the piling word line CWL, the word line driver 50 can be commonly disposed in the plurality of memory blocks BK. Therefore, compared with the case where the word line driver 50 is set in each memory block BK to directly activate the word line WL, the area required for the arrangement of the word line driver 50 can be reduced.

Further, the sub-digit line SDL for flowing the data write current at the time of data writing is divided and set in each of the memory blocks BK. Therefore, the configuration resistance of the digit line can be reduced as compared with the case where the majority bit block BK is commonly configured with a bit line. As a result, it is possible to supply a sufficiently large current required for data writing.

Further, by using the block selection signal BS corresponding to the row address, the data write current can be flown only in the sub-bit line SDL provided on the memory block including the selected memory cell. As a result, the power consumption of the entire MRAM unit 6 can be reduced, and the possibility of erroneous writing to the unselected memory cell MC can be reduced.

(Modification of the first embodiment)

By changing the shape and arrangement of the constituent elements of the memory array of the first embodiment, the degree of accumulation of the memory array can be further improved. In the present modification, the portion from the semiconductor substrate to the second metal wiring layer M2 is changed from the cross-sectional structural view of FIG. Specifically, (i) the interconnection of the source regions of the memory cells, (ii) the change of the wiring of the source, and (iii) the change of the shape and arrangement of the connection between the word line and the peg character line. .

This will be described in detail below with reference to Figs. Further, the connecting portion is also referred to as a piling portion or a branch portion.

Fig. 9 is a plan view showing the layout of a memory array according to a modification of the first embodiment.

Fig. 10 is a cross-sectional view taken along line X-X of Fig. 9. FIG. 9 and FIG. 10 show the structure of the memory array up to the semiconductor substrate SUB to the second metal wiring layer M2 according to the present modification. In Fig. 9, the area of each memory cell MC is distinguished by a two-dot line.

First, (i) the interconnection of the source regions 110 of the memory cells and (ii) the wiring changes of the source lines SL will be described.

As shown in FIGS. 9 and 10, each of the word lines WL extends in the X direction through the central portion of the memory cell MC of the corresponding row. In each memory cell MC, a drain region 112 of the access transistor ATR is formed on one side of the holding word line WL, and a source region 110 is formed on the other side. Further, the memory cells MC adjacent to each other in the Y direction are arranged such that the source regions 110 are opposed to each other.

In the present modification, the n-type impurity regions extending in the row direction X, that is, the interconnecting regions 110A are formed at the boundary of the memory cells adjacent to each other. The interconnected area 110A is configured for each of the two rows of memory cells. Each of the interconnection regions 110A is formed integrally with the source region 110 of the plurality of memory cells MC adjacent to the interconnection region 110A. As such, a plurality of source regions are electrically connected to each other via the interconnect region 110A.

Moreover, the source line SL formed using the first metal interconnect layer M1 is formed in a boundary between mutually adjacent memory cells, and extends in the column direction Y. In the case of FIG. 9, the source line SL is set in a memory cell array of two columns. The source line SL and the interconnecting region 110A are connected to each other at a point of intersection with each other by a metal film 116 formed in the contact hole. In this manner, the source region 110 of each of the memory cells MC is electrically connected to the ground node GND provided at one end of the source line SL.

As shown in FIG. 8, in the memory array of the first embodiment, the source region 110 of each of the memory cells MC is individually connected to the source line SL via the metal film 116 formed in the contact hole. On the other hand, in the present modification, the source regions 110 of the memory cells MC are connected to each other via the interconnection regions 110A extending in the row direction X. The source line SL is connected to the interconnecting region 110A. Therefore, the number of source lines SL and the number of contact holes necessary for grounding the source regions 110 of the memory cells MC can be reduced.

Further, the drain region 112 of each memory cell MC is connected to the upper TMR element (not shown) by the metal film 118 formed in the contact hole. This point is the same as that of the first embodiment.

Hereinafter, the shape of the connection portion between the word line WL and the piling word line CWL and the change of the wiring will be described.

As shown in FIGS. 9 and 10, the piling word line CWL is formed directly above the word line WL using the second metal wiring layer M2. When viewed in the thickness direction of the substrate SUB, the piling word line CWL is formed to be wider than the word line WL so as to cover the word line WL.

In the case of the first embodiment, as shown in Fig. 8, the piling word line CWL is directly connected to the word line WL directly under the metal film 114 formed in the contact hole. However, in this case, as the line width of the word line WL becomes thinner, it becomes difficult to provide a contact hole on the word line WL.

When a contact hole is to be formed, a plurality of rectangular convex pattern portions 122 protruding in the width direction (column direction Y) of the word line WL are provided in each word line WL of FIG. The convex pattern portion 122 is disposed at a portion other than the boundary between the memory cells in which the source lines SL are disposed, in a boundary between mutually adjacent memory cells. In the present modification, the convex pattern portion 122 of each character line WL is disposed one for each of the four memory cells MC.

The protruding direction of the convex pattern portion 122 is a direction separating from the interconnecting region 110A. When the convex pattern portion 122 is protruded in the direction close to the interconnection region 110A, the gate voltage applied to the word line WL affects the current flowing into the interconnection region 110A. Therefore, in the word line WL adjacent to each other, the protruding direction of the convex pattern portion 122 is reversed, and a specific interval between the word line WL and the interconnected region 110A can be secured.

Further, in the realm of the same memory grid, the convex pattern portions 122 of the adjacent word lines WL are not provided in both directions. The reason for this is that if the convex pattern portions 122 of the mutually adjacent word lines WL are provided on both sides of the same memory grid, the convex pattern portions 122 are opposed to each other and arranged in close proximity. Therefore, the gate voltage applied to the adjacent square word line WL is affected by the other word line WL, which is a cause of malfunction.

As shown in FIGS. 9 and 10, the convex pattern portion 122 is connected to the metal film 124B formed on the first metal wiring layer M1 via the metal film 124A formed in the contact hole. Further, the metal film 124B formed on the first metal wiring layer M1 is connected to the piling word line CWL via the metal film 124C formed in the contact hole. In this manner, the convex pattern portion 122 of the word line WL and the peg word line CWL are connected via the metal films 124A, 124B, and 124C (collectively referred to as the connecting portion 124). In the present modification, as described above, the convex pattern portion 122 is disposed so as to prevent a new area loss due to the arrangement of the convex pattern portion 122.

Fig. 11 is a circuit diagram of a memory block in a modification of the first embodiment. FIG. 11 is a circuit diagram showing a portion corresponding to the memory block BK<0> of FIG. 6, and a connection between each memory cell and each wiring.

Referring to Fig. 11, a plurality of memory cells MC provided in the memory block BK<0> are provided in one (in the case of Fig. 11, 1 is an integer of 4 or more) bit lines BL<0> to <1- 1> The intersection position of the p-character line CWL<0> to CWL<mn-1> with m×n (m, n is an integer of 2 or more). FIG. 11 shows only four piling character lines CWL<0> to CWL<3>.

The word line WL to which the gate of the access transistor ATR of each memory cell MC is connected is connected to the corresponding peg word line CWL by a plurality of connection portions 124. As described above, the connection portion 124 is provided for every four memory cells MC in the realm of the adjacent memory cells MC. Further, the connection portion 124 of the even-numbered word line WL<0>, WL<2>, and the connection portion 124 of the odd-numbered word line WL<1>, WL<3>, ... are arranged differently. Column. Specifically, as shown in FIG. 11, each source line SL is provided between the set column of the connection portion 124 of the even-numbered word line WL and the connection portion 124 of the odd-numbered word line WL.

The interconnected area 110A is set for each of the two rows of memory cells in the realm of mutually adjacent memory cells. For example, in the case of FIG. 11, the interconnection area 110A is set to the 0th memory cell line corresponding to the word line WL<0>, and is set between the first memory cell line corresponding to the word line WL<1>. . Similarly, a mutual connection area 110A is provided between the second and third memory cell lines and between the fourth and fifth memory cell lines. In Fig. 11, as shown by the broken line, the source of the access transistor ATR of the memory cell MC on both sides of the interconnecting region 110A is connected.

The source lines SL<0> to SL<(1-2>/2> are set in the memory grid of each of the two adjacent memory banks. For example, in the case of FIG. 11, the source The line SL<0> is set in the memory cell column No. 0 corresponding to the bit line BL<0>, and is set between the first memory cell column corresponding to the bit line BL<1>. Similarly, in the second The source line SL<1> is set between the number and the third memory cell, and the source line SL<1> is set between the fourth and fifth memory cells. Each source line SL and each The interconnecting regions 110A are connected at intersections with each other. Further, one end of the source line SL is connected to the ground node GND.

The other points are the same as in the first embodiment. That is, the sub-digit line SDL is wired in the row direction X in close proximity to the TMR element provided in the memory cell MC of the corresponding memory cell row. The main digit line MDL is configured for each of the corresponding sub-bit lines SDL. In FIG. 11, the main digit line MDL<0> is set corresponding to the sub-digit lines SDL<0> to SDL<3>.

As described above, according to the memory array according to the modification of the first embodiment, the source regions 110 of the plurality of memory cells MC are connected to each other via the interconnection region 110A extending in the row direction X. The interconnect region 110A is connected to the source line SL via a metal film 116 formed in the contact hole. Therefore, the number of source lines SL and the number of contact holes required to ground the source regions 110 of the respective memory cells MC can be reduced.

Further, in order to connect the word line WL and the piling word line CWL, the word line WL is provided with a convex pattern portion 122 that protrudes in the width direction of the word line WL. At this time, by taking measures against the arrangement of the convex pattern portions 122, it is possible to prevent new area loss due to the arrangement of the convex pattern portions 122.

(Second embodiment)

Fig. 12 is an explanatory diagram showing the configuration of the memory array 10A_0 of the second embodiment. The memory array 10A_0 of Fig. 12 is a modification of the memory array 10A_0 of the first embodiment of Fig. 5.

Referring to Fig. 12, the memory array 10A_0 includes k (k is an integer of 2 or more) memory blocks BK<0> to BK<k-1> arranged in the row direction X, as in the first embodiment. For the memory block BK). However, FIG. 4 is a case where k=4 is shown for simplicity.

Each of the memory blocks BK includes a plurality of memory cells MC arranged in a matrix in the X and Y directions. As shown in FIG. 12, each of the memory blocks BK has m × n rows (m, n is an integer of 2 or more) in the X direction, and 1 column (1 is an integer of 2 or more) in the Y direction. The memory cell MC is configured. Therefore, in the memory array 10_0, memory cells MC are arranged in the x direction as m×n rows and in the Y direction in k×1 columns (4×1 columns in FIG. 12).

Further, the memory array 10_0 includes a plurality of bit lines BL, bit line drivers 80_0 and 80_1, and bit line selection circuits 90, similarly to the first embodiment.

The bit line BL corresponds to each memory cell arrangement. The k×1 bit lines BL<0> to BL<kl_1> which are the same as the memory cell array are arranged in the column direction Y in the entirety of the memory array 10A_0.

The bit line drivers 80_0 and 80_1 are respectively disposed on both sides of the column direction Y of the memory block BK. The output nodes of the bit line drivers 80_0, 80_1 are connected to the bit lines BL<0> to BL<kl-1>. The bit line drivers 80_0, 80_1, when data is written, are based on the column selection signals of the column decoders 70_0, 70_1, and write the data in the direction corresponding to the bit line BL of the selected column, which flows in and writes the data Din. Into the current. Further, the bit line selection circuit 90 receives the column selection signal of the column decoder 70_1 as a gate function for transmitting the data of the bit line BL of the selected column to the sense amplifier 20_0 at the time of data reading.

Similarly to the first embodiment, the memory array 10A_0 includes a plurality of main digit lines MDL, a plurality of sub-digit lines SDL, and a digit line driver 60.

The main digit line MDL is k (in the second embodiment, k=4), and the memory block BK is commonly arranged. m main digit lines MDL<0> to MDL<m-1> are provided in the row direction X for the entire memory array 10_0.

On the other hand, the sub-digit line SDL is provided for each of the memory cell blocks BK. In each memory block BK, m×n sub-bit lines SDL<0> to SDL<mn-1> are respectively set corresponding to m*n lines of memory cells.

The m × n sub-digit line SDL belonging to each memory block BK is constituted by one sub-group of sub-digit lines SDL adjacent to each other. The entire sub-digit line SDL constitutes a group of m rows. The main digit line MDL corresponds to m row groups, respectively.

The digit line drivers 60<0> to 60<k-1> are provided corresponding to the memory blocks BK<0> to BK<k-1>, respectively. In the case of data writing, as in the first embodiment, each of the bit line drivers 60 receives the main decoded signal of the main digit line MDL and the sub-decoded signals SDW<0> to SDW of the n-bit by the row decoder 40A. N-1>.

Each of the bit line drivers 60<0> receives the corresponding block selection signals BS<0> to BS<k-1> by the column decoder 70_0. One of the memory blocks BK is selected by the block selection signal BS. One of the above-described row groups of the selected memory block BK is selected by the main decoding signal flowing through the main digit line MDL. Further, one sub-bit line SDL belonging to the selected line group is selected by the sub-decoding signal SDW. The digit line driver 60 injects a data write current to the selected sub-digit line SDL.

Similarly to the first embodiment, the memory array 10A_0 further includes a main word line MWL, a word line WL, piling word lines CWL0, CWL1, and a word line driver 50A.

The word line WL (shown in Fig. 13) is disposed in each of the memory blocks BK in the same manner as in the first embodiment. In each memory block BK, m×n word line lines WL<0> to WL<mn-1> are set corresponding to the memory cell line. The word line WL is integrated with the gate of the access transistor ATR of the memory cell MC provided in the corresponding memory cell row, and is formed by polysilicon or polycrystalline germanium.

Further, the arrangement of the piling word lines CWL0, CWL1 and the word line driver 50 is different from that of the first embodiment. Further, in the second embodiment, the m main word lines MWL<0> to MWL<m-1> are arranged in the row direction X.

The piling word line includes a plurality of first piling character lines CWL0<0> to CWL0<mn-1> and a plurality of second piling word lines CWL1<0> to CWL1<mn-1>.

The first piling word line CWL0 is among the plurality of memory blocks BK, and a plurality of memory blocks BK disposed on one side (the left side in FIG. 12) of the row direction X of the memory array 10A_0 are commonly arranged. The second piling word line CWL1 is commonly disposed in a plurality of memory blocks BK excluding the memory block BK in which the first piling word line CWL0 is disposed. Preferably, the number of memory blocks BK in which the first piling word line CWL0 is arranged is set to be equal to the number of memory blocks BK in which the second piling word line CWL1 is arranged. The piling character lines CWL0 and CWL1 are respectively corresponding to the memory cell line settings. The piling word lines CWL0 and CWL1 are formed of a metal material and are electrically connected to the word line WL provided in the corresponding memory cell row at a plurality of positions.

The word line driver 50A is provided between the memory block BK in which the first piling word line CWL0 is disposed, and the memory block BK in which the second piling word line CWL1 is placed. For example, as shown in FIG. 12, when the number of memory blocks BK is K=4, it is set between the memory blocks BK<0>, BK<1>, BK<2>, and BK<3>. In this case, the piling word lines CWL0 and CWL1 extend from the row direction X of the word line driver 50A with the word line driver 50A as a starting point.

As described above, by dividing the piling word line by two, the wiring resistance of each of the piling word lines CWL0 and CWL1 can be made lower than that of the first embodiment. As a result, compared with the first embodiment, the signal transmission of the piling word line CWL of the second embodiment becomes high speed. At this time, since the word line driver 50A is disposed at the center of the divided piling word line CWL, the area of the word line driver 50A is almost unchanged as compared with the case of the first embodiment.

Similarly to the case of the sub-digit line SDL, the piling word lines CWL0 and CWL1 also form a line group by n adjacent to each other. On one side (the left side in FIG. 12) of the row direction X of the word line driver 50A, one row group is constituted by each of the n piling word lines CWL0. Further, on the other side (the right side in FIG. 12) of the row direction X of the word line driver 50A, one row group is constituted by each of the n piling word lines CWL1.

The main word line MWL is arranged in the row direction X between the row decoder 40A and the word line driver 50A. Each of the M main character line lines MWL corresponds to a line group formed by the line group formed by the piling word line CWL0 and the piling word line CWL1. For example, the main character line MWL<0> corresponds to the row group and the piling word line CWL1<0> to CWL1<n-1> formed by the piling word line CWL0<0> to CWL0<n-1>. The group of rows that are formed. Similarly, the main character line MWL<m-1> corresponds to the line group formed by the piling character line CWL0<mn-n>~CWL0<mn-1> and the piling word line CWL1<mn-n> A group of lines formed by ~CWL1<mn-1>.

The row selection signal output from the row decoder 40A uses the main decoded signal and the n-bit sub-decoded signals SDR<0> to SDR<n-1> which are distributed on the main word line MWL. At the time of data reading, one of the row groups formed by the above-described piling word lines CWL0 and CWL1 is selected by the main decoding signal flowing through the main word line MWL. Further, by the sub-decoding signal SDR, the peg word lines CWL0, CWL1, 1 corresponding to the selected column among the piling word lines CWL0, CWL1 belonging to the selected line group are selected and activated.

FIG. 13 is a circuit diagram showing the memory block BK<2>, the digit line driver 60<2>, and the word line driver 50A of FIG. The memory block BK<2> and the digit line driver 60<2> of FIG. 13 represent the memory blocks BK<0> to BK<3> of FIG. 12 and the digit line drivers 60<0> to 60<3>, respectively. By. Here, the configuration of the memory block BK<2> and the digit line driver 60<2> in Fig. 13 is the same as that described with reference to Fig. 6 of the first embodiment, and thus the description thereof is omitted. The configuration of the word line driver 50A will be described below.

Referring to FIG. 13, the word line driver 50A includes: m×n inverters 51<0> to 51<mn-1> (collectively referred to as an inverter 51); m×n inverters 52<0 >~52<mn-1> (collectively referred to as inverter 52); and m×n NAND (“NAND”) gates 54<0> to 54<mn-1> (collectively referred to as NAND gates 54).

The inverters 51<0> to 51<mn-1> are provided corresponding to m×n piling word lines CWL0<0> to CWL0<mn-1> on one side of the row direction X, respectively. Similarly, the inverters 52<0> to 52<mn-1> are respectively provided corresponding to m×n piling word lines CWL1<0> to CWL1<mn-1> on the other side of the row direction X. . Further, the NAND gates 54<0> to 54<mn-1> are respectively m×n piling word lines CWL0<0> to CWL0<mn- for one side of the word line driver 50A in the row direction X. 1> corresponds to the same, and corresponds to the m×n piling character lines CWL1<0> to CWL1<mn-1> on the other side.

The inverters 51 and 52 and the NAND gate 54 are similar to the piling word lines CWL0 and CWL1, and can be considered to constitute each n group of rows. Each row group has a corresponding relationship with the main character line MWL.

One of the n NAND gates 54 belonging to the same row group is commonly connected to the corresponding main word line MWL. The other input terminals of the n NAND gates 54 belonging to the same row group are individually connected to the signal lines of the n sub-decoding signals SDR<0> to SDR<n-1>. For example, the other input terminal of the NAND gate 54<0> to 54<n-1> corresponding to the main word line MWL<0> is connected to the signals of the sub-decoding signals SDR<0> to SDR<n-1>, respectively. line. Similarly, the other input terminal of the NAND gate 54<mn-n> to 54<mn-1> corresponding to the main word line MWL<m-1> is connected to the sub-decoding signals SDR<0> to SDR<n, respectively. -1>.

The output of NAND gate 54 is branched and one of the branch outputs is input to inverter 51, which is used to drive the corresponding peg word line CWL0. Further, the other of the branch outputs is input to an inverter 52 for driving the corresponding peg character line CWL1.

According to the configuration of the word line driver 50A, the output of the NAND gate 54 connected to the signal line of the activated main word line MWL and the sub-decoding signal SDR is activated to the L level. As a result, the output of the activated NAND gates 54 connected to the inverters 51, 52 is activated to the H level, and the outputs of the inverters 51, 52 are received to activate the piling word lines CWL0, CWL1 to the H position. quasi. In this manner, the main decoded signal and the sub-decoded signal SDR flowing through the main word line MWL are activated, and the peg line lines CWL0 and CWL1 corresponding to the selected line among the plurality of piling word lines CWL0 and CWL1 are activated.

The order of writing data and reading data for the selected memory cell will be described below with reference to a specific timing chart.

Fig. 14 is a timing chart showing the data writing operation and the data reading operation of the memory cell MC of the memory array 10A_0. In FIG. 14, the horizontal axis represents time, and the vertical axis sequentially represents the clock signal CLK, the read permission signal RE, the write permission signal WE, the voltage waveform of the main word line MWL<0>, and the main digit line MDL. Voltage waveform of <0>, voltage waveform of block selection signal BS, voltage waveform of sub-decoding signal SDW, current waveform I of sub-bit line SDL<0> in memory block BK<2> (SDL<0>) The current waveform I (BL<21>) of the bit line BL<21>, the voltage waveform of the sub-decoding signal SDR, the voltage waveform of the piling word line CWL1<0>, and the character in the memory block BK<2> Voltage waveform of line WL<0>.

Hereinafter, among the plurality of memory cells MC in which the memory block BK<2> of FIG. 13 is set, the memory cell MC in which the intersection of the near-pile word line CWL1<0> and the bit line BL<21> is set is selected. The sequence of writing/reading the data for the selected memory cell will be described with reference to Figs. 12-14.

Among them, the data writing/data reading is performed in synchronization with the clock signal CLK. The time t0 to t6 at which the write permission signal WE is activated to the H level is a write cycle in which data is written to the selected memory cell. Further, the time t6 to t9 at which the read permission signal RE is activated to the H level is a read cycle in which data is read by the selected memory cell. First, explain the data write cycle.

At time t1, the column decoder 70_0 sets the block selection signal BS<2> to the H level of the active state. At this time, the other block selection signals BS<0>, BS<1>, and BS<3> are maintained at the L level. In this case, the memory block BK <select memory block> including the selected memory cell is selected.

At time t2, the row decoder 40 sets the main digit line MDL<0> and the sub-decode signal SDW<0> to the H level of the active state. In this case, the outputs of the AND gates 62<0> and 68<0> of the digit line driver 60<2> become the H level, and thus the driving transistor 66<0> to which the sub-digit line SDL<0> is connected is turned on. As a result, a data write current is supplied to the sub-digit line SDL<0>.

Thereafter, the bit line drivers 80_0, 80_1 receiving the column selection signals caused by the column address signals CA by the column decoders 70_0, 70_1 are at time t3, and the bit lines BL<21> are input and written to the data Din. The direction data is written to the current. As a result, both the sub-digit line SDL<0> and the bit line BL<21> are caused to flow into the data write current, and the selected memory cell provided at the intersection of the two is written into the data.

At time t4, the row decoder 40A sets the main digit line MDL<0> and the sub-decode signal SDW<0> to the L level of the inactive state. In this case, the outputs of the AND gates 62<0> and 68<0> of the digit line driver 60<2> are restored to the L level, and the driving transistor 66<0> becomes non-conductive. As a result, the current I (SDL<0>) of the sub-digit line SDL<0> in the memory block BK<2> is stopped, and the data writing to the selected memory cell is ended.

At time t5, the column decoders 70_0, 70_1 set the block selection signal BS<2> to the L level. Further, the column decoders 70_0 and 70_1 stop the supply of the current (BL<21>) to the bit line BL<21> by the bit line drivers 80_0 and 80_1.

The data readout period is explained below. The word line driver 50A that receives the row selection result from the row decoder 40A sets the main word line MWL<0> and the sub-decode signal SDR<0> to the active state at time t7. In this case, the piling word lines CWL0<0> and CWL1<0> are activated to the H level. As a result, the word line WL<0> to which the piling word line CWL0<0> and CWL1<0> are connected is activated to the H level, and the access transistor ATR of the selected row is turned on. Further, the bit line selection circuit 90 that receives the column selection signal from the column decoder 70_1 connects the bit line BL<21> corresponding to the selected column to the sense amplifier 20_0. The sense amplifier 20_0 detects the difference between the data read current flowing into the selected memory cell via the bit line BL<21> and the reference current, and is amplified.

At the next time t8, the piling character line CWL<0> returns to the L level, and the word line WL<0> also returns to the L level. In this case, the access transistor ATR of the selected row becomes non-conductive. Further, the connection between the bit line BL<21> and the sense amplifier 20_0 is cut off by the bit line selection circuit 90.

Fig. 15 is a cross-sectional structural view showing a memory cell MC of the second embodiment. Fig. 15 is a cross-sectional schematic view showing the memory cell MC disposed between the row decoder 40A and the word line driver 50A in the column direction Y, among the memory array 10A_0 shown in Fig. 12.

Referring to Fig. 15, an access transistor ATR is formed on the main surface of the p-type semiconductor substrate SUB. The access transistor ATR has a source region 110 and a drain region 112 of an n-type region, and a gate. The gate line and the word line WL are integrally formed. On the main surface of the semiconductor substrate SUB, the first to fifth metal wiring layers M1 to M5 are sequentially laminated to each other via the interlayer insulating film from the substrate side.

The source region 110 of the access transistor ATR is electrically connected to the source line SL formed using the first metal wiring layer M1 via the metal film 116 formed in the contact hole. Further, the gate and the word line WL are electrically connected to the peg word line CWL0 formed by using the second metal wiring layer M2 via the metal film 114 formed in the contact hole.

The main digit line MDL and the main word line MWL are formed using the third metal wiring layer M3 of the upper layer of the piling word line CWL0. The memory cell MC with respect to the m × n rows is arranged in the row direction X, and the main digit line MDL and the main word line MWL total 2 × m. Therefore, it is sufficient that the wirings are disposed on the same metal wiring layer.

The sub-digit line SDL is formed using the fourth metal wiring layer M4. Further, the TMR element is disposed above the sub-digit line SDL. The TMR element has a magnetic layer (fixed magnetization layer) PL having a fixed magnetization direction, and a magnetic layer (free magnetization layer) FL which is magnetized in a direction corresponding to a data write magnetic field generated by a data write current. . A tunneling barrier layer ISO formed of an insulator film is disposed between the fixed magnetization layer PL and the free magnetization layer FL.

The TMR element is electrically connected to the drain region 112 of the access transistor ATR via a metal film 118 formed on the contact hole and the barrier metal 120. The barrier metal 120 is a buffer member provided to achieve electrical coupling between the TMR element and the metal film. The bit line BL is electrically coupled to the free magnetization layer FL of the TMR element, and is provided on the fifth metal wiring layer M5 of the upper layer of the TMR element.

As described above, in the memory cell MC of the second embodiment, the source line SL, the piling word line CWL0, the main digit line MDL, the main word line MWL, the sub-digit line SDL, and the bit line BL are formed. As in the first embodiment, all of the five metal wiring layers M1 to M5 are required.

As described above, in the memory cell MC of the second embodiment, the source line SL, the piling word line CWL, the main digit line MDL, the sub-digit line SDL, and the bit line BL are formed, and therefore all five metal wiring layers are required. M1 ~ M5.

According to the MRAM portion of the semiconductor device 1 of the second embodiment, the piling word line is divided into two, and the wiring resistance of each of the piling word lines CWL0 and CWL1 can be reduced as compared with the case of the first embodiment. As a result, in the second embodiment, the signal transmission of the piling word line CWL is high in comparison with the case of the first embodiment. At this time, since the word line driver 50A is disposed at the center of the divided piling word line CWL, the area required for the arrangement of the word line driver 50A is almost unchanged as compared with the case of the first embodiment.

In addition, the sub-digit line SDL for the data write current flows when the data is written, and is divided and set in each of the memory blocks BK as in the first embodiment. Therefore, the configuration resistance of the digit line can be reduced as compared with the case where the majority bit block BK is commonly configured with a bit line. As a result, it is possible to supply a sufficiently large current required for data writing.

Further, similarly to the first embodiment, by using the block selection signal BS corresponding to the column address signal CA, the data write current can be supplied only to the sub-bit line SDL provided on the memory block including the selected memory cell. As a result, the power consumption of the entire MRAM section can be reduced, and the possibility of erroneous writing of the unselected memory cell MC can be reduced.

In addition, the configuration from the semiconductor substrate SUB to the second metal interconnect layer M2 in the cross-sectional structural view of Fig. 15 is the same as the cross-sectional structural view of the first embodiment of Fig. 8. Therefore, similarly to the modification of the first embodiment, (i) the source regions of the memory cells are connected to each other, (ii) the wiring of the source lines is changed, and (iii) the word lines and the piling word lines are performed. The shape and arrangement of the connection portions between the two can further increase the accumulation degree of the memory array.

(Modification of Second Embodiment)

To ensure a sufficient write current, it is possible to set the power supply voltage of the driving circuit of the digit line DL to the power supply voltage of the driving circuit higher than the word line WL. For example, such an internal circuit is required to reduce the power consumption of the entire MRAM unit.

Specifically, the power supply voltage of the connected sub-digit line SDL of FIG. 13 is increased to VDD2. In addition, when the gate driving voltage of the driving transistor 66 of the digit line driver 60 is to be increased, the power supply voltage of the driving AND gate 68 is increased to VDD2, and the voltage level of the input signal of the AND gate 68 is also increased. In the modification of the second embodiment, the voltage of the H level of the main decoded signal is increased by the level shifter 45 provided in the row decoder 40B before the main decoded signal is output to the main digit line MDL. Is VDD2.

Fig. 16 is a block diagram showing a schematic configuration of a row decoder 40B according to a modification of the second embodiment.

Referring to Fig. 16, row decoder 40B includes decoder 41, m inverters 42, m AND gates 43 and 44, and m level shifters (voltage level shift circuits) 45. The operating voltages of the inverter 42 and the AND gates 43, 44 are VDD1, and the operating voltage of the level shifter 45 is VDD2 larger than VDD1.

The decoder 41 outputs the main decoding result generated by the row address signal RA to the m inverters 42. An input terminal of each of the AND gates 43, 44 is supplied with an output signal of the corresponding inverter 42. Further, the other input terminal of the AND gate 43 is supplied with the read permission signal RE in common, and the other input terminal of the AND gate 44 is supplied with the write permission signal WE in common.

At this time, when the output of the inverter 42 is at the H level and the read permission signal RE is activated to the H level, the AND gate 43 outputs the main decoded signal of the H level (voltage VDD1) to the main word line MWL. .

Further, when the output of the inverter 42 is at the H level and the write permission signal WE is activated to the H level, the output of the AND gate 44 becomes the H level (voltage VDD1). At this time, the level shifter 45 receives the output of the AND gate 44 to increase the voltage level to VDD2. The main decoded signal whose voltage level is increased is output to the main digit line MDL.

Fig. 17 is a circuit diagram showing the configuration of the memory block BK<2>, the digit line driver 60A<2>, and the word line driver 50A in the modification of the second embodiment. The digit line drivers 60A<0> to 60A<3> are variants of the digit line drivers 60<0> to 60<3> of the second embodiment. In FIG. 17, the digital line driver 60A<2> is represented by a digit line driver 60A<0> to 60A<3>.

Referring to Fig. 17, the digit line driver 60A<2> differs from the bit line driver 60<2> of Fig. 13 in that it includes n level shifters 63 provided on the output side of the n AND gates 62. The level shifter 63 receives the output of the corresponding AND gate 62, increases the voltage level to VDD2, and outputs it to the AND gate 68.

As described above, in the modification of the second embodiment, it is necessary to increase the voltage level of the input signal of the AND gate 68 to VDD2. Here, by setting the level shifter 63, in addition to the main decoded signal flowing into the main digit line MDL, the other input signal to the AND gate 68 also increases the voltage of the H level to VDD2. In this case, the H-level voltage of the sub-decode signal SDW and the block selection signal BS is VDD1 lower than VDD2. In addition, the driving voltage of the AND gate 62 is also VDD1.

Further, instead of setting the level shifter 63 in the digit line driver 60A<2>, setting the level shifter 63 to the row decoder 40B and the column decoder 70_0, and sub-decoding the signal SDW and the block selection. The H-level voltage of the signal BS is previously increased to VDD2. In this case, the driving voltage of the AND gate 62 also needs to be increased to VDD2.

The other configuration of Fig. 17 is the same as that described with reference to Fig. 13 of the second embodiment, and therefore the description thereof will not be repeated.

As described above, in the modification of the second embodiment, the signal level of the main decoded signal is increased by providing the m-level shifter 45 having the same number as the number of main digit lines MDL in the row decoder 40B. Further, on the output side of the AND gate 62 of each memory block BK, the signal level of the sub-decode signal is increased by providing n level shifters 63. As a result, the gate driving voltage of the driving transistor 66 can be increased, and the data writing current flowing into the sub-digit line can be increased.

Here, by providing a level shifter directly in front of the gate of the driving transistor 66, the gate driving voltage of the driving transistor 66 can be increased. However, in this case, each of the memory blocks BK requires m × n level shifters equal to the number of the driving transistors 66. Therefore, according to the method of the modification of the second embodiment, the number of the level shifters is reduced as compared with the case where the level shifter is provided directly in front of the gate of the driving transistor 66. Further, in the first embodiment, the write current flowing into the sub-digit line SDL can be increased by the same method.

(Third embodiment)

In the MRAM unit 6 of the first embodiment, the high-speed data reading is achieved by providing the piling word line CWL, and the area of the row selection circuit is reduced. However, in the MRAM portion 6 of the first embodiment, the metal wiring layer is increased by the portion of the peg word line CWL, and all of the five metal wiring layers are required.

The MRAM unit 6 of the third embodiment transmits a line selection signal when data is written to the digit line driver 60 by using the piling word line CWL. In this way, the main digit line MDL is not required, and the one-layer metal wiring layer can be reduced as compared with the MRAM unit 6 of the first embodiment. Further, by setting the latch circuit 92 to maintain the activation state of the peg word line CWL, countermeasures are taken to shift the activation timing of the piling word line CWL from the timing of the current flowing into the bit line BL.

Fig. 18 is an explanatory diagram showing the configuration of the memory array 10C_0 of the third embodiment. The memory array 10C_0 of Fig. 18 is a variant of the memory array 10_0 of the first embodiment of Fig. 5.

Referring to Fig. 18, the memory array 10C_0 includes k (k is an integer of 2 or more) memory blocks BK<0> to BK<k-1> arranged in the row direction X, as in the first embodiment. For the memory block BK).

Each of the memory blocks BK includes a plurality of memory cells MC arranged in a matrix in the X and Y directions. As shown in FIG. 18, for each of the memory blocks BK, the memory cell MC is p rows (p is an integer of 2 or more) in the X direction and 1 column (1 is an integer of 2 or more) in the Y direction. Configuration. Therefore, in the memory array 10C_0 as a whole, the memory cell MC is arranged in the x direction in p rows and in the Y direction in k × 1 columns.

The memory array 10C_0 includes a plurality of bit lines BL, bit line drivers 80_0 and 80_1, and bit line selection circuits 90, as in the first embodiment.

The bit line BL corresponds to each memory cell arrangement. In the entire memory array 10C_0, k × 1 bit lines BL<0> to BL<k1-1> of the same number are stored in the column direction Y.

The bit line drivers 80_0 and 80_1 are respectively disposed on both sides of the column direction Y of the memory block BK. The output nodes of the bit line drivers 80_0, 80_1 are connected to the bit lines BL<0> to BL<k1-1>. The bit line drivers 80_0, 80_1, when data is written, are based on the column selection signals of the column decoders 70_0, 70_1, and write the data in the direction corresponding to the bit line BL of the selected column, which flows in and writes the data Din. Into the current. Further, the bit line selection circuit 90 receives the column selection signal of the column decoder 70_1 as a gate function for transmitting the data of the bit line BL of the selected column to the sense amplifier 20_0 at the time of data reading.

The memory array 10C_0 further includes a word line WL, a piling word line CWL1, and a word line driver 50C.

The word line WL (shown in FIG. 19) is disposed in each of the memory blocks BK in the same manner as in the first embodiment. In each memory block BK, p word line lines WL<0> to WL<p-1> are set corresponding to the memory cell line. The word line WL is integrated with the gate of the access transistor ATR of the memory cell MC provided in the corresponding memory cell row, and is formed by polysilicon or polycrystalline germanium.

The piling word line CWL is the same as that of the first embodiment, and is commonly disposed in k memory blocks BK. In the memory array 10C_0, p peg character lines CWL<0> to CWL<p-1> are associated with the memory cell row setting. The piling word line CWL is formed of a metal material and is electrically connected to the word line WL disposed on the corresponding memory cell row at a plurality of positions.

The word line driver 50C is commonly configured in the k memory blocks BK, and is disposed in close proximity to the row decoder 40. The output node of the word line driver 50C is connected to the piling word line CWL. The word line driver 50C receives the line selection signal generated by the row address signal RA from the row decoder 40C in the case of both data reading and data writing, and outputs it to the piling word line CWL. As described above, the third embodiment differs from the first embodiment in that the piling word line CWL not only transmits the line selection signal at the time of data reading but also transmits the line selection signal at the time of data writing.

The memory array 10C_0 further includes a sub-digit line SDL and a digit line driver 60C.

The sub-digit line SDL is provided in each memory block BK as in the first embodiment. In each of the memory blocks BK, p sub-bit lines SDL<0> to SDL<p-1> are provided corresponding to the memory cells of the p-row.

The digit line drivers 60C<0> to 60<k-1> (collectively referred to as the digit line drivers 60) are provided corresponding to the memory blocks BK<0> to BK<k-1>, respectively. Each of the bit line drivers 60C receives the row selection signal by the p-pile word line CWL, and the latch decoder activation signal MDLL is received by the row decoder 40C. The latch activation signal MDLL is a signal for setting the latch circuit described later in each digit line driver 60C to an active state. Further, the bit line driver 60C receives the corresponding block selection signals BS<0> to BS<k-1> by the column decoder 70_0.

When data is written, one of the memory blocks BK is selected by the block selection signal. One of the p sub-bit lines SDL of the selected memory block BK is selected by the row selection signal flowing into the piling word line CWL. The digit line driver 60C causes the material write current to flow into the sub-digit line SDL while the latch activation signal MDLL is activated.

19 is a circuit diagram showing the configuration of the memory block BK<0> of FIG. 18 and its corresponding digit line driver 60C<0>. The digit line driver 60C<0> and the memory block BK<0> of FIG. 19 respectively represent k memory blocks BK<0> to BK<k-1> and k digit line drivers 60C shown in FIG. 0>~60C<k-1>. The configuration of the memory block BK<0> in Fig. 19 is the same as that of Fig. 6 in the first embodiment, and thus the overlapping description will be omitted. The configuration of the digit line driver 60C<0> will be described below.

Referring to FIG. 19, the digit line driver 60C<0> includes: an AND gate 91; and p latch circuits 92<0> to 92<p-1> (collectively referred to as a latch circuit 92); and p The drive transistors 94<0> to 94<p-1> (collectively referred to as drive transistors 94).

The AND gate 91 receives the block selection signal BS<0> corresponding to the latch activation signal MDLL and the memory block BK, and outputs a latch activation signal DLL<0> determined according to each memory block BK. The AND gate 91 sets the latch activation signal DLL<0> to the active state when both the latch activation signal MDLL and the corresponding block selection signal BS<0> are activated.

The latch circuits 92<0> to 92<p-1> are provided corresponding to the sub-digit lines SDL<0> to SDL<p-1>, respectively. A row selection signal, a latch activation signal DLL<0>, and a reference voltage VREFDL flowing through the piling word line CWL are input to the latch circuit 92. The latch circuit 92 maintains the activated state of the peg word line CWL between when the latch activation signal DLL<0> is set to activation. When the activated state of the piling word line CWL is maintained, the latch circuit 92 supplies the reference voltage VREFDL to the gate of the driving transistor 94 that drives the corresponding sub-digit line SDL. The reference voltage VREFDL is supplied from the reference power source 160 of FIG.

The drive transistors 94<0> to 94<p-1> are provided corresponding to the sub-digit lines SDL<0> to SDL<p-1>, respectively. The driving transistor 94 is turned on when the gate is applied with the reference voltage VREFDL, and the data write current flows into the corresponding sub-digit line SDL.

Fig. 20 is a circuit diagram showing the configuration of the latch circuit 92<0> of the bit line driver 60C<0> of Fig. 19. The latch circuit 92<0> of Fig. 20 represents the latch circuit 92 provided in each of the bit line drivers 60C<0>60C<k-1> of Fig. 18. A latch circuit 92 of the same configuration is provided for each of the bit line drivers 60C.

Referring to Fig. 20, the latch circuit 92<0> includes a p-channel MOS transistor Q1 and n-channel MOS transistors Q2, Q3. The source of the MOS transistor Q1 is connected to the power supply node VDD, and the drain is connected to the node N1. The MOS transistors Q2 and Q3 are connected in series between the node N1 and the ground node GND. The gates of the MOS transistors Q1 and Q2 are simultaneously connected to the signal line of the latch activation signal DLL<0>. The gate of the MOS transistor Q3 is connected to the corresponding piling word line CWL<0>.

Further, the latch circuit 92<0> includes two inverters 132a and 132b, a p-channel MOS transistor Q4, and n-channel MOS transistors Q5 and Q6. The input terminal of the inverter 132a and the output terminal of the inverter 132b are connected to the node N1. The input terminal of the inverter 132b and the output terminal of the inverter 132a are connected to the node N2. The inverters 132a and 132b perform a latching operation.

MOS transistors Q4 and Q5 form a CMOS transmission gate. Explain that their connections are as follows. The source of the MOS transistor Q4 and the drain of the MOS transistor Q5 are connected to the power supply line of the reference voltage VREFDL. Further, the drain of the MOS transistor Q4 and the source of the MOS transistor Q5 are connected to the node N3. The gate of MOS transistor Q4 is connected to node N1. The gate of the MOS transistor Q5 is connected to the node N2. By the set value of the reference voltage VREFDL, the magnitude of the data write current flowing into the sub-digit line SDL is adjusted when the driving transistor 94<0> is turned on.

The MOS transistor Q6 is connected between the node N3 and the ground node GND. The gate of the MOS transistor Q6 is connected to the node N1. Node N3 is connected to the gate of drive transistor 94<0>.

The operation of the latch circuit 92<0> will be described below. When both the signal line of the latch activation signal DLL<0> and the peg word line CWL<0> are H-level, the MOS transistor Q1 is turned off, and the MOS transistors Q2 and Q3 are turned on. Therefore, the node N1 becomes the L level, and the node N2 becomes the H level. Hereinafter, the voltage level state of the nodes N1 and N2 is referred to as the first state. In the first state, the MOS transistors Q4 and Q5 are turned on, and the MOS transistor Q6 is turned off. Therefore, the potential of the node N3 is equal to the reference voltage VREFDL, and the driving transistor 94<0> is turned on. As a result, the data write current flows into the sub-digit line SDL.

After that, when the piling word line CWL<0> is at the L level, the MOS transistor Q3 is in a non-conduction state, but the signal line of the latch activation signal DLL<0> can be maintained at the first level as long as it is H level. status.

When the signal line of the latch activation signal DLL<0> is at the L level, the MOS transistor Q1 is turned on, and the MOS transistor Q2 is turned off. Therefore, the node N1 becomes the H level, and the node N2 becomes the L level. Hereinafter, the voltage level state of the nodes N1 and N2 is referred to as the second state. In the second state, the MOS transistors Q4 and Q5 are in a non-conduction state, and the MOS transistor Q6 is turned on. Therefore, the potential of the node N3 is equal to the ground potential GND, and the driving transistor 94<0> becomes a non-conduction state. As a result, the sub-digit line SDL becomes an inactive state.

As described above, when the signal line of the latch activation signal DLL<0> is at the H level, the latch circuit 92<0> maintains the activation state of the piling word line CWL<0>, and the internal state becomes the first state. status. In the first state, the corresponding sub-digit line SDL is set to the active state, and the data write current flows into the sub-digit line SDL. When the signal line of the latch activation signal DLL<0> is at the L level, the internal state of the latch circuit 92<0> is in the second state, and the sub-digit line SDL is in the inactive state.

The sequence of writing and reading the selected memory cells will be described below. Fig. 21 is a timing chart showing the data writing operation and the data reading operation of the memory cell MC of the memory array 10C_0. In FIG. 21, the horizontal axis represents time, and the vertical axis sequentially represents the clock signal CLK, the read permission signal RE, the write permission signal WE, the voltage waveform of the block selection signal BS, and the bit line BL<0>. The current waveform I (BL<0>), the voltage waveform of the piling word line CWL<0>, the voltage waveform of the word line WL<0> in the memory block BK<0>, and the latch activation signal MDLL The voltage waveform, the voltage waveform of the latch activation signal DLL in each memory block BK, and the current waveform I (SDL<0>) of the sub-digit line SDL<0> in the memory block BK<0>.

Hereinafter, among the plurality of memory cells MC in which the memory block BK<0> of FIG. 19 is set, the memory cell MC in which the intersection of the near word word line WL<0> and the bit line BL<0> is set is selected. The order in which the data for the selected memory cell is written will be described with reference to Figs. 18, 19, and 21. Since the data readout period from time t7 to time t10 is the same as that of the first embodiment of Fig. 7, the description thereof will not be repeated.

At time t1, the column decoder 70_0 sets the block selection signal BS<0> to the H level of the active state. At this time, the other block selection signals BS<1> to BS<k-1> are maintained at the L level of the inactive state. In this case, the memory block BK<0> is selected.

At time t2, the digit line driver 60C<0> sets the P-stack line CWL<0> corresponding to the selected row to the H-level of the active state in response to the signal from the row decoder 40C. Thus, the word line WL<0> of the memory block BK<0> is also activated to the H level.

Further, at time t2, the latch activation signal MDLL becomes the H level. Here, the block selection signal BS<0> is maintained in the H level state after the time t1, and therefore, the latch activation signal DLL<0> outputted by the AND gate 91 of FIG. 19 becomes the H level. As a result, the latch circuit 92<0> holds the activated state of the piling word line CWL<0>, and the data write current flows into the sub-bit line SDL<0> of the memory block BK<0>.

At time t3, the piling character line CWL<0> returns to the L level to become an inactive state. Along with this, the word line WL<0> of the memory block BK<0> also returns to the L level level. At this time t3, the latch activation signal MDLL is maintained at the H level, and therefore, the data write current continues to flow into the sub-digit line SDL<0>.

At time t4, the bit line drivers 80_0, 80_1 are in response to the column selection signals from the column decoders 70_0, 70_1, and correspond to the bit line BL<0> corresponding to the selected column, and the inflow and write data Din are corresponding. The direction data is written to the current.

At time t5, the latch activation signal MDLL returns to the L level, and therefore, the latch activation signal DLL<0> outputted by the AND gate 91 of FIG. 19 also returns to the L level. Thus, the voltage supplied from the latch circuit 92<0> to the gate of the driving transistor 94<0> also becomes the L level. As a result, the data write current flowing into the sub-digit line SDL<0> becomes zero. The data is written to the end.

At time t6, while the block selection signal BS<0> becomes the L level, the current flowing into the bit line BL<0> returns to the L level. The data write cycle is ended accordingly.

Wherein, at time t3, the voltage drop timing of the piling word line CWL<0> must be set to be faster than the falling timing of the current of the bit line BL<0>. The reason will be described below with reference to Fig. 22 .

Fig. 22 is a timing chart for explaining the rise of the current flowing into the bit line BL<0> and the timing of the falling of the voltage of the piling word line CWL<0>. In Fig. 22, the horizontal axis represents time, corresponding to time t2 to t6 of Fig. 21. The vertical axis of FIG. 22 sequentially represents the current waveform I (BL<0>) of the bit line BL<0> and the current waveform I of the sub-digit line SDL<0> in the memory block BK<0>. SDL<0>), the voltage waveform of the latch activation signal DLL<0>, and the voltage waveform of the piling word line CWL<0>.

19 and 22, in the time zone A from time t2 to time t3, both the latch activation signal DLL<0> and the voltage of the piling word line CWL<0> are in the H level state. Therefore, the latch circuit 92<0> maintains the activated state of the piling word line CWL<0>. Further, in the time zone A, the piling character line CWL<0> is activated to the H level, so that the access transistor ATR of the memory cell MC connected by the piling word line CWL<0> is turned on.

At time t2 to t5, band B, the latch circuit 92<0> remains activated. Therefore, the driver transistor 94<0> of FIG. 19 corresponding to the latch circuit 92<0> is turned on, and the data write current flows into the sub-bit line SDL<0> of the memory block BK<0>.

At time t4 to time t6, the data write current flows into the bit line BL<0>. Therefore, data writing to the memory cell MC is performed between time t4 and time t5 of the common portion of the time zone B and the time zone D.

Wherein, the peg character line CWL<0> is decreased to the L level at the time t3, and the access transistor is selected based on the selected memory cell when the data writing current starts to flow into the bit line BL<0> at the time t4 is slow. The ATR causes the data write current to flow into the bit line BL<0>. Therefore, an increase in consumption current and a writing error occur. Therefore, it is necessary to set the time t3 before the time t4 and the time zone C between the time t3 and the time t4, and it is necessary to set a certain margin of the estimated amount. In this case, when the line selection signal for data writing is transmitted to the digit line driver 60C using the piling word line CWL, it is necessary to adjust the timing at which the data write current flows into the bit line BL by using the latch circuit 92.

Fig. 23 is a sectional structural view showing a memory cell of the third embodiment; Referring to Fig. 23, an access transistor ATR is formed on the main surface of the p-type semiconductor substrate SUB. The access transistor ATR has a source region 110 of an n-type region, and a drain region 112 and a gate. The gate line and the word line WL are integrally formed. On the main surface of the semiconductor substrate SUB, the first to fourth metal wiring layers M1 to M4 are sequentially laminated to each other via the interlayer insulating film from the substrate side.

The source region 110 of the access transistor ATR is electrically connected to the source line SL formed using the first metal wiring layer M1 via the metal film 116 formed in the contact hole. Further, the gate and the word line WL are electrically connected to the peg word line CWL formed using the second metal wiring layer M2 via the metal film 114 formed in the contact hole.

The sub-digit line SDL is formed using the third metal wiring layer M3. Further, the TMR element is disposed above the sub-digit line SDL. The TMR element has a magnetic layer (fixed magnetization layer) PL having a fixed magnetization direction, and a magnetic layer (free magnetization layer) FL which is magnetized in a direction corresponding to a data write magnetic field generated by a data write current. . A tunneling barrier layer ISO formed of an insulator film is disposed between the fixed magnetization layer PL and the free magnetization layer FL.

The TMR element is electrically connected to the drain region 112 of the access transistor ATR via a metal film 118 formed on the contact hole and the barrier metal 120. The barrier metal 120 is a buffer member provided to achieve electrical coupling between the TMR element and the metal film. The bit line BL is electrically coupled to the free magnetization layer FL of the TMR element, and is provided on the fourth metal wiring layer M4 of the upper layer of the TMR element.

The memory cell MC of the first embodiment of Fig. 8 requires a metal wiring layer for forming the main digit line MDL. Further, the memory cell MC of the third embodiment of Fig. 23 does not require the main digit line MDL. Therefore, compared with the memory cell MC of the first embodiment of Fig. 8, the memory cell MC of the third embodiment of Fig. 23 is reduced by one layer of the main digit line MDL to form four layers.

As described above, according to the MRAM portion of the semiconductor device 1 of the third embodiment, the row selection signal at the time of data writing is transmitted by the piling word line CWL, and the main digit line MDL of the MRAM portion of the first embodiment is not required. Therefore, compared with the MRAM portion of the first embodiment, the MRAM portion of the third embodiment can be reduced by one metal wiring layer.

Further, a latch circuit 92 for maintaining the activated state of the piling word line CWL is provided in the digit line driver 60C. The latch circuit 92 accepts the temporary activation state of the word line WL corresponding to the selected memory cell before the supply of the current to the bit line BL corresponding to the selected memory cell in the write operation to the selected memory cell. Current is caused to flow into the corresponding sub-digit line SDL. The current supply to the sub-digit line SDL is maintained at least until the current is supplied to the corresponding bit line BL after the non-activation of the corresponding word line WL.

Therefore, the data write current flows into the bit line BL, and when data is written to the TMR element, the word line WL can be set to be inactivated. As a result, the data write current flowing into the bit line BL is not circulated through the access transistor ATR, and the increase in the power consumption or the erroneous writing can be prevented.

Further, in the case where the data is written, the sub-digit line SDL for the data write current flows, and is divided and set in each of the memory blocks BK as in the first embodiment. Therefore, the configuration resistance of the digit line can be reduced as compared with the case where the majority bit block BK is commonly configured with a bit line. As a result, it is possible to supply a sufficiently large current required for data writing.

Further, similarly to the first embodiment, by using the block selection signal BS corresponding to the column address signal CA, the data write current can be flown only to the sub-bit line SDL provided on the memory block including the selected memory cell. As a result, the power consumption of the entire MRAM section can be reduced, and the possibility of erroneous writing of the unselected memory cell MC can be reduced.

Further, similarly to the first embodiment, the piling word line CWL electrically connected to the word line WL connected to each of the memory cells MC at a plurality of positions is commonly disposed in the plurality of memory blocks BK. Therefore, the activation signal to the memory cell MC can be transmitted at a higher speed than in the case of using only the word line WL, and the data reading speed can be improved.

Further, by using the piling word line CWL, the word line driver 50C can be commonly disposed in the plurality of memory blocks BK. Therefore, as compared with the case where the word line driver 50C is set in each memory block BK to directly activate the word line WL, the area required for the arrangement of the word line driver 50C can be reduced.

The configuration from the semiconductor substrate SUB to the second metal interconnect layer M2 in the cross-sectional structural view of Fig. 23 is the same as the cross-sectional structural view of the first embodiment of Fig. 8. Therefore, similarly to the modification of the first embodiment, (i) the source regions of the memory cells are connected to each other, (ii) the wiring of the source lines is changed, and (iii) the word lines and the piling word lines are performed. The shape and arrangement of the connection portions between the two can further increase the accumulation degree of the memory array.

The above embodiments are merely examples and are not intended to limit the present invention. The invention also includes and is intended to cover all modifications and equivalents.

(effect of the invention)

According to the present invention, the piling word line and the word line are electrically connected at a plurality of positions, and the conductive layer forming the word line is formed by a conductive layer having a small sheet resistance, so that the piling word line is formed The signal transmission enables high-speed data reading. In addition, the piling word line is commonly set in most of the blocks, so the word line driving circuit for character line activation can be commonly set in most blocks. Therefore, the number of word line drive circuits can be reduced as compared with the case where the word line is independently set in each block to achieve high speed reading of data.

In addition, the digit lines are independently provided in the respective blocks, and the wiring resistance can be suppressed to be smaller, and as a result, a sufficient current amount for data writing can be supplied.

1. . . Semiconductor device

2. . . Microcomputer department

3. . . SRAM

4. . . Analog circuit

5. . . Clock generation department

6. . . MRAM

10, 10A, 10C. . . Memory array

20. . . Sense amplifier

40, 40A, 40B, 40C. . . Row decoder

41. . . decoder

45, 63. . . Level shifter

50, 50A, 50C. . . Word line driver

60, 60C. . . Digital line driver

66, 94. . . Drive transistor

70. . . Column decoder

80. . . Bit line driver

90. . . Bit line selection circuit

91. . . AND gate

92. . . Latch circuit

ADD. . . Address signal

RA. . . Row address signal

CA. . . Column address signal

ATR. . . Access transistor

BK. . . Memory block

MC. . . Memory grid

BL. . . Bit line

WL. . . Word line

CWL, CWL0, CWL1. . . Piling word line

MWL. . . Main character line

SDL. . . Sub-digit line

MDL. . . Main digit line

DL. . . Digital line

SL. . . Source line

SDR. . . Secondary decoding signal

SDW. . . Secondary decoding signal

BS. . . Block selection signal

MDLL, DLL. . . Latch activation signal

M1～M5. . . Metal wiring layer

SUB. . . Substrate

VREFDL. . . Reference voltage

140. . . Control circuit

150. . . Output circuit

151. . . Write data latch circuit

152. . . Reader data latch circuit

153. . . Address signal latch circuit

160. . . Reference power

1 is a schematic plan view showing an example of the configuration of a semiconductor device 1 according to the first embodiment of the present invention.

Fig. 2 is a block diagram showing the overall configuration of the MRAM unit 6 of Fig. 1.

FIG. 3 is a circuit diagram showing a schematic configuration of each of the memory cells MC constituting the memory array 10 of FIG.

Fig. 4 is a plan view showing an example of the arrangement of the respective sections of the MRAM unit 6 of Fig. 2;

Fig. 5 is an explanatory view showing the configuration of the memory array 10_0 of Fig. 4.

FIG. 6 is a circuit diagram showing the memory block BK<0> of FIG. 5 and its corresponding digit line driver 60<0>.

Fig. 7 is a timing chart showing the data writing operation and the data reading operation of the memory cell MC of the memory array 10_0.

Fig. 8 is a cross-sectional structural view showing a memory cell MC of the first embodiment.

Fig. 9 is a plan view showing the layout of a memory array according to a modification of the first embodiment.

Fig. 10 is a cross-sectional view taken along line X-X of Fig. 9.

Fig. 11 is a circuit diagram of a memory block in a modification of the first embodiment.

Fig. 12 is an explanatory diagram showing the configuration of the memory array 10A_0 of the second embodiment.

FIG. 13 is a circuit diagram showing the memory block BK<2>, the digit line driver 60<2>, and the word line driver 50A of FIG.

Fig. 14 is a timing chart showing the data writing operation and the data reading operation of the memory cell MC of the memory array 10A_0.

Fig. 15 is a cross-sectional structural view showing a memory cell MC of the second embodiment.

Fig. 16 is a block diagram showing a schematic configuration of a row decoder 40B according to a modification of the second embodiment.

Fig. 17 is a circuit diagram showing the configuration of the memory block BK<2>, the digit line driver 60A<2>, and the word line driver 50A in the modification of the second embodiment.

Fig. 18 is an explanatory diagram showing the configuration of the memory array 10C_0 of the third embodiment.

19 is a circuit diagram showing the configuration of the memory block BK<0> of FIG. 18 and its corresponding digit line driver 60C<0>.

Fig. 20 is a circuit diagram showing the configuration of the latch circuit 92<0> of the bit line driver 60C<0> of Fig. 19.

Fig. 21 is a timing chart showing the data writing operation and the data reading operation of the memory array 10C_0 for the memory cell MC.

Fig. 22 is a timing chart for explaining the rise of the current flowing into the bit line BL<0> and the timing of the falling of the voltage of the piling word line CWL<0>.

Fig. 23 is a sectional structural view showing a memory cell of the third embodiment;

40C. . . Row decoder

50C. . . Word line driver

60C. . . Digital line driver

70_0. . . Column decoder

80_0: 80_1. . . Bit line driver

90. . . Bit line selection circuit

91. . . AND gate

92. . . Latch circuit

94. . . Drive transistor

ATR. . . Access transistor

BK. . . Memory block

MC. . . Memory grid

BL. . . Bit line

WL. . . Word line

CWL. . . Piling word line

SDL. . . Sub-digit line

DL. . . Digital line

SL. . . Source line

BS. . . Block selection signal

MDLL, DLL. . . Latch activation signal

VREFDL. . . Reference voltage

VDD. . . Power node

GND. . . Ground node

TMR. . . TMR component

Claims (17)

A semiconductor device comprising: a memory array divided into a plurality of blocks in a row direction, comprising a plurality of memory cells arranged in a matrix; each of the memory cells comprising: a magnetoresistive element, the resistance of which corresponds to a magnetic gas data And the switching element is connected in series to the magnetoresistive element and has a control electrode; and further includes: a plurality of bit lines respectively corresponding to the memory array of the memory array, each system for distributing the magnetic gas The first data write current necessary for writing the data; the majority digit line, each digit line is individually set in each of the blocks of the above-mentioned majority block, and is written in the first data Writing a second data write current in a direction in which a current intersects, and writing the magnetic data; and a plurality of digital lines connected to a plurality of the control electrodes included in the memory cell corresponding to the memory array, a conductive layer having a first sheet resistance; and a plurality of piling word lines respectively corresponding to the memory cells of the memory array are commonly disposed in the plurality of blocks, Each of the layers is formed of a conductive layer having a second sheet resistance smaller than the first sheet resistance, and is electrically connected to the word line provided on the corresponding memory cell row at a plurality of positions. The semiconductor device of claim 1, further comprising: a row selection circuit commonly disposed in the plurality of blocks for selecting a memory cell row according to the address signal, the memory cell row being included as a data reading object And the memory of the data writing object; the word line driving circuit is commonly disposed in the plurality of blocks, and when the data is read, the piling word line set on the selected memory cell line of the row selecting circuit is activated; Most digit line driver circuits are respectively arranged corresponding to the majority of the above blocks, At the time of data writing, the second data write current is caused to flow into the digit line set on the selected memory cell row of the row selection circuit. The semiconductor device of claim 2, further comprising: a column selection circuit, which is commonly disposed in the plurality of blocks, and is configured to select a memory grid according to the address signal, wherein the memory cell array is included as a data read The memory of the object and the data write target; each of the plurality of bit line drive circuits causes the second data write current to flow in, and includes a digit line corresponding to the block selected by the column selection circuit. The semiconductor device of claim 1, wherein the semiconductor device further comprises: a row selection circuit, which is commonly disposed in the plurality of blocks, for selecting a memory cell row according to the address signal, the memory cell row comprising the data a memory cell for reading an object and a data writing object; the word line driving circuit is commonly disposed in the plurality of blocks for activating the piling word line set on the selected memory cell row of the row selecting circuit; and The digit line driving circuits are respectively disposed corresponding to the plurality of blocks; each of the plurality of bit line driving circuits includes: a plurality of latch circuits respectively connected to the plurality of piling word lines for maintaining the connected piling An activation state of the word line; the plurality of latch circuits are respectively provided corresponding to the plurality of bit lines; and each of the plurality of bit line drive circuits causes the second data write current to flow in the data writing A digit line corresponding to the latch circuit that remains active. The semiconductor device of claim 4, further comprising: a column selection circuit, which is commonly disposed in the plurality of blocks The memory cell array is selected according to the address signal, and the memory cell array includes a memory cell that becomes a data reading object and a data writing object; each of the plurality of latch circuit circuits is in a corresponding digit line system and includes When the blocks selected by the column selection circuit correspond to the memory cells, the activation state of the connected piling word lines is maintained. The semiconductor device of claim 5, further comprising: a bit line driving circuit for causing the first data write current to flow into a memory cell selected by the column selection circuit during data writing; and a control circuit For controlling the row selection circuit, the word line driver circuit, the plurality of latch circuits, the column selection circuit, and the bit line driving circuit; the control circuit is driven by the word line when the data is written The circuit sets the piling word line set on the selected memory cell row of the row selection circuit to an activation state, so that the latch circuit of the activated piling word line connection is maintained in an activated state, and the word line driving circuit is Setting the piling word line set on the selected memory cell row of the row selection circuit to an inactive state, and then flowing the first data write current by the bit line driving circuit, and selecting the memory by the column selection circuit The bit line set on the grid. The semiconductor device according to any one of claims 4 to 6, further comprising: a semiconductor substrate; and first to fourth metal wiring layers, which are sequentially placed on the main surface of the semiconductor substrate from the substrate side An insulating layer between the layers is laminated; each of the plurality of memory cells is disposed between the third and fourth metal wiring layers, and each of the plurality of memory cells is opened The off device is a field effect transistor formed on a main surface of the semiconductor substrate, the control electrode is a gate of the field effect transistor, and a plurality of wirings for connecting a source of the field effect transistor are In the first metal wiring layer, the plurality of piling word lines are formed by the second metal wiring layer, and the plurality of bit lines are formed by the third metal wiring layer, and the plurality of bit lines are formed by the fourth A metal wiring layer is formed. A semiconductor device comprising: a memory array including a plurality of memory cells arranged in a matrix and divided into a plurality of blocks arranged in a row direction; each of the memory cells comprising: a magnetoresistive element, the resistance of which corresponds to The magnetic component changes; and the switching element is connected in series to the magnetoresistive element and has a control electrode; and further includes: a plurality of bit lines respectively corresponding to the memory array of the memory array, and each system is used for inflow The first data write current necessary for writing the magnetic material data; the majority digit lines, each of the blocks in the majority of the blocks are individually set according to each memory cell row, and the first data is Writing a current to the second data write current in the direction in which the write current intersects, and writing the magnetic data; the plurality of digital lines are connected to a plurality of the switching elements included in the memory cell corresponding to the memory array. Control electrode, formed by a conductive layer having a first sheet resistance; a plurality of first piling word lines respectively corresponding to the memory cells of the memory array, and being commonly set a plurality of blocks disposed on one side of the row direction of the memory array in the plurality of blocks; and a plurality of second piling word lines respectively corresponding to the memory cells of the memory array, and being commonly disposed in the plurality of regions A plurality of blocks other than the block in which the plurality of first piling word lines are arranged are removed from the block; the first plurality and the second part are Each of the piling word lines is formed of a conductive layer having a second sheet resistance smaller than the first sheet resistance, and is electrically connected to the word line disposed on the same memory cell row at a plurality of positions; The selection circuit is commonly disposed in the plurality of blocks, and is configured to select a memory cell row according to the address signal, the memory cell row includes a memory cell that becomes a data reading object and a data writing object; the word line driving circuit is Commonly disposed in the plurality of blocks, when the data is read, the first and second piling word lines set on the selected memory cell row of the row selection circuit are activated; and the plurality of bit line driving circuits respectively correspond to the majority The block is set, and when the data is written, the second data write current is caused to flow into the digit line set on the selected memory cell row of the row selection circuit. A semiconductor device comprising: a plurality of memory blocks, wherein each of the memory blocks includes a plurality of memory cells arranged in a matrix on a substrate, and is disposed in a row direction of the plurality of memory cells; each of the memory cells includes: a magnetoresistive element that uses a magnetoresistance effect to memorize data; and an access transistor that is connected in series to the magnetoresistive element; and a multi-digital line that is associated with each of the plurality of memory blocks The memory cells are arranged to be connected to the control electrodes of the access transistors corresponding to the memory cells; and the plurality of sub-bit lines are arranged in each of the plurality of memory blocks corresponding to the plurality of memory cells. a magnetic resistance element for applying a current-sensing magnetic field to a corresponding memory cell; a plurality of piling word lines are disposed in common to the plurality of memory blocks, wherein the plurality of digital lines are disposed, and a plurality of digital element lines are formed by upper layer wiring layers, and are electrically connected to respective corresponding word lines at a plurality of positions; row selection circuit And is commonly disposed in the plurality of memory blocks for performing row selection of the plurality of memory cells; and the word line driving circuit is configured to receive the first row selection signal from the row selection circuit, so that the majority of the piling words are The piling word line selected by the meta-line is activated; and a plurality of digit line driving circuits, each digit line driving circuit is disposed in each of the plurality of memory blocks for accepting the second row selection signal from the row selecting circuit, The current is caused to flow into the selected sub-digit line. The semiconductor device according to claim 9, wherein the sheet resistance of the wiring layer forming the word line is larger than the sheet resistance of the wiring layer forming the peg line. The semiconductor device of claim 9 or 10, wherein the second row selection signal includes a main decoding signal and a sub decoding signal, wherein the main decoding signal is a wiring different from the plurality of piling word lines, that is, Most of the main digit lines are transmitted. The semiconductor device according to claim 11, wherein the semiconductor device further includes: first to fourth metal wiring layers, which are laminated on the main surface of the substrate from the substrate side through the insulating layers between the layers The magnetoresistive elements of the plurality of memory cells are disposed on the upper layer of the fourth metal wiring layer, and each of the access transistors of the plurality of memory cells is a field effect transistor formed on the main surface of the substrate, The control electrode is a gate of the field effect transistor, and a plurality of wires for connecting the source of the field effect transistor are formed by the first metal wiring layer, and the plurality of peg lines are formed by the second metal Wiring layer formation, the above The number of main digit lines is formed by the third metal wiring layer, and the plurality of sub-digit lines are formed of the fourth metal wiring layer. A semiconductor device according to claim 9 or 10, wherein said second row selection signal is transmitted by said plurality of piling word lines. The semiconductor device according to claim 13, wherein the semiconductor device further includes: first to third metal wiring layers, wherein the insulating layer of each layer is laminated on the main surface of the substrate from the substrate side in sequence The magnetoresistive elements of the plurality of memory cells are disposed on the upper layer of the third metal wiring layer, and each of the access transistors of the plurality of memory cells is a field effect transistor formed on the main surface of the substrate, The control electrode is a gate of the field effect transistor, and a plurality of wires for connecting the source of the field effect transistor are formed by the first metal wiring layer, and the plurality of peg lines are formed by the second metal The wiring layer is formed, and the plurality of sub-digit lines are formed of the third metal wiring layer. The semiconductor device of claim 13, wherein the semiconductor device further comprises: a plurality of bit lines arranged corresponding to the plurality of memory cells for applying a current-induced magnetic field to the magnetic field of the corresponding memory cell; a resisting element; each of the plurality of bit line driving circuits includes a plurality of latch circuits for accepting a write operation to the selected memory cell before starting to supply current to the bit line corresponding to the selected memory cell Selecting a temporary activation state of the word line corresponding to the memory cell to cause a current to flow into the corresponding sub-digit line, and the non-live of the corresponding word line After the state, the current supply of the sub-digit line is maintained at least until the current supply to the corresponding bit line is started. The semiconductor device of claim 15, wherein each of the plurality of bit line driving circuits further includes a plurality of driving transistors, and is provided corresponding to each of a plurality of sub-digit lines in the corresponding block, and receives a reference voltage. And controlling the ON/OFF of the data write current; each of the plurality of latch circuits includes a transfer gate that is turned on during the activation state of the corresponding piling word line; and the individual of the plurality of drive transistors The control electrode is supplied with a reference voltage via the transfer gate. The semiconductor device of claim 9 or 10, wherein the row selection circuit includes a voltage level shift circuit for boosting a signal level in a selected state of the second row selection signal to be higher than the above The signal level in the selected state of the 1-line selection signal is a high voltage.