JP4675362B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Access Memory) device has attracted attention as a storage device that can store nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of an MRAM device will be dramatically improved by using a thin film magnetic material using a magnetic tunnel junction (MTJ) as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000., “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000., and “A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM”, ISSCC Digest of Technical Papers, TA7. 6, Feb. 2000., etc.

  FIG. 26 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereinafter also simply referred to as “MTJ memory cell”).

  Referring to FIG. 26, the MTJ memory cell forms a tunnel magnetoresistive element TMR whose electrical resistance changes in accordance with the stored data level and a path of sense current Is passing through tunnel magnetoresistive element TMR during data reading. Access element ATR. Since access element ATR is typically formed of a field effect transistor, in the following, access element ATR is also referred to as access transistor ATR. Access transistor ATR is coupled between tunneling magneto-resistance element TMR and a fixed voltage (ground voltage Vss).

  Write word line WWL for instructing data write to MTJ memory cell, read word line RWL for executing data read, and data read and data write corresponding to the data level of stored data A bit line BL which is a data line for transmitting an electric signal is arranged.

FIG. 27 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.
Referring to FIG. 27, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. A ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that is magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by the fixed magnetic layer FL, the tunnel barrier TB, and the free magnetic layer VL.

  At the time of data reading, access transistor ATR is turned on in response to activation of read word line RWL. As a result, the sense current Is can flow through the current path of the bit line BL, the tunnel magnetoresistive element TMR, the access transistor ATR, and the ground voltage Vss.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, when the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are the same (parallel), compared to the case where the magnetization directions of both are opposite (anti-parallel) directions. The tunnel magnetoresistive element TMR becomes small.

  Therefore, if the free magnetic layer VL is magnetized in the direction corresponding to the stored data, the voltage change caused in the tunnel magnetoresistive element TMR by the sense current Is differs depending on the stored data level. Therefore, for example, if the sense current Is is supplied to the tunnel magnetoresistive element TMR after precharging the bit line BL to a constant voltage, the data stored in the MTJ memory cell can be read by detecting the voltage of the bit line BL. it can.

FIG. 28 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 28, at the time of data writing, read word line RWL is inactivated and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL in the direction corresponding to the write data is supplied to write word line WWL and bit line BL. The magnetization direction of free magnetic layer VL is determined by data write currents flowing through write word line WWL and bit line BL, respectively.

  FIG. 29 is a conceptual diagram illustrating the relationship between the data write current and the magnetization direction of the tunnel magnetoresistive element at the time of data writing to the MTJ memory cell.

  Referring to FIG. 29, a horizontal axis H (EA) indicates a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and write word line WWL, respectively.

  In the MTJ memory cell, the fixed magnetization direction of the fixed magnetization layer FL is along the easy magnetization axis of the free magnetization layer VL, and the free magnetization layer VL has the stored data level (“1” and “0”). Accordingly, it is magnetized in the parallel (identical) or antiparallel (opposite) direction to the fixed magnetic layer FL along the easy axis direction. Hereinafter, in this specification, the electric resistances of the tunnel magnetoresistive element TMR respectively corresponding to the two types of magnetization directions of the free magnetic layer VL are denoted by R1 and R0 (where R1> R0). The MTJ memory cell can store 1-bit data (“1” and “0”) corresponding to the two types of magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in the figure. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As shown by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold necessary to change the magnetization direction along the easy axis is lowered. be able to.

When the operating point at the time of data writing is designed as in the example of FIG. 29, the strength of the data writing magnetic field in the easy axis direction is H _WR in the MTJ memory cell that is the data writing target. Designed as such. That is, the value of the data write current flowing through the bit line BL or the write word line WWL is designed so that this data write magnetic field _HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

  In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of the tunnel magnetoresistive element TMR, it is necessary to pass a data write current of a predetermined level or more to both the write word line WWL and the bit line BL. Thus, free magnetic layer VL in tunneling magneto-resistance element TMR is parallel to fixed magnetic layer FL or in the opposite (anti-parallel) direction according to the direction of the data write magnetic field along the easy axis (EA). Magnetized. The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed.

Thus, tunnel magnetoresistive element TMR changes its electric resistance in accordance with the direction of magnetization that can be rewritten by the applied data write magnetic field, so that the two magnetizations of free magnetic layer VL in tunnel magnetoresistive element TMR By associating the direction with the level (“1” and “0”) of the stored data, nonvolatile data storage can be executed.
Roy Scheuerlein and six others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Using FET Switches and Magnetic Tunnel Junctions in Each Cell Tunnel Junction and FET Switch in each Cell), (USA), 2000 Annual Meeting of the Institute of Electrical and Electronics Engineers International Solid State Circuits TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129. M. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” (USA), 2000 Electrotechnical Society of Japan Proceedings TA7.3 (2000 IEEE ISSCC Digest of Technical Papers, TA7.3), p. 130-131.

  The above-described technical literature discloses a technique for constructing an MRAM device that is a random access memory by integrating such MTJ memory cells on a semiconductor substrate.

  FIG. 30 is a conceptual diagram showing a configuration of a memory array including MTJ memory cells integrated and arranged in a matrix.

  Referring to FIG. 30, a highly integrated MRAM device can be realized by arranging MTJ memory cells in a matrix. FIG. 30 shows a case where MTJ memory cells are arranged in n rows × m columns (n, m: natural numbers). For n × m MTJ memory cells arranged in a matrix, n write word lines WWL1 to WWLn and read word lines RWL1 to RWLn and m bit lines BL1 to BLm are arranged. Write word lines WWL1 to WWLn and bit lines BL1 to BLm through which a data write current flows during the data write operation are arranged along the row direction and the column direction.

  However, it is desirable that the tunnel magnetoresistive element used as the MTJ memory cell is arranged in an elongated shape having an aspect ratio (aspect ratio) larger than 1 in order to stabilize the magnetization characteristics. Therefore, unless the shape of tunneling magneto-resistance element TMR and the arrangement of wiring groups (write word lines and bit lines) for flowing a data write current are matched, the current density of these wiring groups will be As a result, a factor that hinders operation reliability of the MRAM device, represented by electromigration, is generated.

  Further, when data is written to the MTJ memory cell, that is, when the magnetization direction of the tunnel magnetoresistive element is rewritten, data write magnetic fields in two directions are applied as described with reference to FIG. Therefore, if the temporal change of these data write magnetic fields is not appropriate, there is a problem that the magnetization operation becomes unstable and may cause a malfunction.

  In a so-called “page mode operation” for speeding up the operation of the dynamic random access memory (DRAM), a plurality of column addresses are continuously randomly accessed while the row selection is fixed. Therefore, when the same page mode operation is applied to the MRAM, it is necessary to design in consideration of the data write characteristics to the MTJ memory cell as described above.

  The present invention has been made in order to solve such problems, and an object of the present invention is to match a shape of an MTJ memory cell having a stable magnetization characteristic and to stably operate a thin film magnetic material. It is to provide a body storage device.

  Another object of the present invention is to provide a configuration of a thin film magnetic memory device having a page mode operation capable of stable and high speed operation.

  In the thin film magnetic memory device according to the present invention, the electrical resistance changes in accordance with the rewritable magnetization direction in response to application of a predetermined data write magnetic field generated by the first and second data write currents. A plurality of memory cells having a magnetic storage unit, a first data write wiring arranged along a first direction for flowing a first data write current, and a second data write current And a second data write wiring arranged along the second direction for flowing. The first data write current is larger than the second data write current, and the cross-sectional area of the first data write wiring is larger than the cross-sectional area of the second data write wiring.

  Preferably, the first and second data write wirings are set such that a distance between the first data write wiring and the magnetic storage unit is longer than a distance between the second data write wiring and the magnetic storage unit. Is placed.

  Preferably, the wiring width of the first data write wiring is wider than the wiring width of the second data write wiring.

  Preferably, the wiring thickness of the first data write wiring is larger than the wiring thickness of the second data write wiring.

  With such a configuration, the data write wiring can be arranged so as to generate a data write magnetic field so that the current density of one of the wirings does not increase and the operation reliability is not lowered.

  Preferably, each magnetic storage unit has a shape in which the aspect ratio of the long side and the short side is greater than 1. The first data write wiring has a wiring width in the long side direction, and the second data write wiring has a wiring width narrower than the first data write wiring in the short side direction.

  In this way, a wiring group for passing a data write current can be provided with a magnetic memory unit (tunnel magnetoresistive element) designed in a shape for having stable magnetization characteristics. It can be arranged efficiently without causing a drop and an increase in memory array area.

  More preferably, the second data write wiring is arranged using a metal wiring layer that is higher than the first data write wiring.

  In this way, it can be easily applied to a logic-embedded memory device such as a system LSI.

  A thin-film magnetic memory device according to another configuration of the present invention includes a plurality of memory cells each having a magnetic memory portion whose electrical resistance changes according to a rewritable magnetization direction in response to application of a data write magnetic field. A first data write wiring for flowing a first data write current for generating a data write magnetic field in a direction along the easy magnetization axis, and a data write magnetic field in a direction along the hard magnetization axis And a second data write wiring for allowing a second data write current to flow. At the start of the data write operation for rewriting the magnetization direction of the magnetic memory unit, the rise time constant of the first data write current is larger than the rise time constant of the second data write current.

  Alternatively, preferably, the plurality of memory cells are arranged in a matrix, the first data write wiring is provided for each memory cell column, and the second data write wiring is provided for each memory cell row. . The thin film magnetic memory device is arranged for each memory cell column and a column selection line arranged for each memory cell column. In the selected column, a corresponding column selection line is changed from a first voltage to a second voltage. And a column selection line driving unit for driving with the operating current. The predetermined operating current is set such that the rise time constant of the first data write current is larger than the rise time constant of the second data write current.

  With this configuration, the magnetic field in the hard axis direction applied to the memory cell can be generated more quickly than the magnetic field in the easy axis direction at the start of data writing. Thereby, the magnetic storage part of the memory cell to be written with data can be stably magnetized.

  Preferably, at the end of the data write operation, the supply end timing of the second data write current is earlier than the supply stop timing of the first data write current.

  In this way, at the end of data writing, there is provided a period in which the data writing magnetic field in the hard axis direction decreases while a predetermined level of data writing magnetic field is applied in the easy magnetic axis direction. Can do. As a result, the magnetic memory portion of the memory cell to be written with data can be magnetized more stably.

  More preferably, each magnetic storage unit has a shape in which the aspect ratio of the long side and the short side is larger than 1. The first data write wiring is arranged in the direction along the short side, and the second data write wiring is arranged in the direction along the long side.

  In this way, the shape of the magnetic memory unit can be designed so as to have stable magnetization characteristics, and a wiring group for passing a data write current can be efficiently arranged.

  In particular, in such a configuration, the column selection line driving unit drives the corresponding column selection line with one of the first and second voltages according to the column selection result, and the driving unit. And a drive current switching unit that supplies a first current as a predetermined operating current during a data write operation and supplies a second current larger than the first current as a predetermined operating current during a data read operation. .

  In this way, at the time of data reading, the column selection line of the selected column can be driven at high speed, so that the data reading speed can be further increased.

  A thin film magnetic memory device according to still another configuration of the present invention includes a page mode operation including a row cycle in which a unit operation cycle receives a row address and a plurality of subsequent column cycles each receiving a column address. Is a thin film magnetic memory device that is arranged in a matrix, each rewritable in response to application of a predetermined data write magnetic field generated by the first and second data write currents A plurality of memory cells each having a magnetic memory portion whose electrical resistance changes in accordance with the magnetization direction, and a plurality of second cells for flowing a first data write current in the selected row, corresponding to each memory cell row. A plurality of second data write wirings that are provided corresponding to one data write wiring and a memory cell column, respectively, for flowing a second data write current in the selected column; And a row selecting section for controlling supply of the first data write current to the first data write lines. The row selection unit temporarily stops the supply of the first data write current corresponding to the selected row at the end of each column cycle.

  Preferably, the row selection unit includes a latch circuit for holding a row selection result corresponding to a row address input in the row cycle, a row selection result held in the latch circuit, and data writing and data reading. A drive unit for activating the first data write wiring corresponding to the selected row in order to flow the supply of the first data write current in response to a control signal for selectively instructing including.

  With this configuration, in the page mode operation, the supply of the data write current corresponding to the selected row is temporarily stopped at the end of each column cycle. Therefore, it is possible to execute a page mode operation that can operate stably and at high speed with a low risk of erroneous data writing.

  Preferably, one of the first and second data write currents generates a magnetic field along the easy axis direction in the magnetic memory unit. The other one of the first and second data write currents generates a magnetic field along the hard axis direction in the magnetic memory unit. In each column cycle in which the data write operation is instructed, the rise time constant of one data write current is larger than the rise time constant of the other data write current.

  Alternatively, preferably, one of the first and second data write currents generates a magnetic field along the easy axis direction in the magnetic storage unit, and the first and second data write currents are generated. The other data write current among the currents generates a magnetic field along the hard axis direction in the magnetic memory unit. In each column cycle in which the data write operation is instructed, the supply start timing of one data write current is later than the supply start timing of the other data write current.

  In this way, at the start of data writing, the magnetic field in the hard axis direction applied to the memory cell can be generated more quickly than the magnetic field in the easy axis direction. Therefore, in each column cycle in which data writing is instructed, the magnetic storage portion of the memory cell to be written with data can be stably magnetized.

  Particularly in such a configuration, each magnetic memory unit has a shape in which the aspect ratio of the long side and the short side is larger than 1. One of the first and second data write wirings through which one data write current flows is arranged along the short side direction, and the other data of the first and second data write wirings The other through which the write current flows is arranged along the long side direction.

  In this way, the shape of the magnetic memory unit can be designed so as to have stable magnetization characteristics, and a wiring group for passing a data write current can be efficiently arranged.

  A thin film magnetic memory device according to still another configuration of the present invention includes a page mode in which a unit operation cycle includes a row cycle in which a row address is input and a plurality of subsequent column cycles in each of which a column address is input. A thin film magnetic memory device that performs an operation, and includes a plurality of memory cells arranged in a matrix. Each memory cell includes a magnetic storage unit whose electrical resistance changes according to a rewritable magnetization direction in response to application of a predetermined data write magnetic field generated by the first and second data write currents, and a magnetic storage And an access element that is electrically coupled in series with the portion and selectively turned on to pass the data read current. The thin film magnetic memory device further includes a plurality of data write selection lines provided corresponding to the memory cell rows and selectively activated to pass the first data write current, and the memory cell rows And a plurality of data read select lines which are selectively activated to turn on the access elements, a plurality of data lines respectively provided corresponding to the memory cell columns, and data read instructing In each column cycle, the data read current is supplied to the data line corresponding to the input column address, and the data line corresponding to the input column address is supplied to the data line corresponding to the input column address. A read / write control circuit for supplying a second data write current and a plurality of data write select lines according to a row selection result based on the row address, and Further comprising a row selection section for controlling the activation of the number of data write select line. The row selection unit deactivates the data read selection line corresponding to the selected row and activates the data write selection line corresponding to the selected row for a predetermined period in each column cycle in which the data write operation is instructed. .

  With this configuration, data reading and data writing can be executed in any combination in each column cycle within one page mode operation.

  Preferably, the row selection unit activates the data read selection line corresponding to the selected row in a period other than the predetermined period in each column cycle.

  More preferably, each memory cell is arranged to have a node electrically connected to the corresponding data write selection line, and the row selection unit includes the activation period of each data read selection line and the first data The activation of a plurality of data read selection lines is controlled so as to avoid a time overlap with the supply period of the write current.

  Alternatively, more preferably, each memory cell is arranged electrically isolated from the corresponding data write selection line, and the row selection unit includes the activation period of each data read selection line and the first data write The activation of the plurality of data read selection lines is controlled so that the current supply period has a temporal overlap period.

  As described above, the active state of the data read selection line (read word line) of the selected row is maintained except for a predetermined period of the column cycle in which the data write operation is instructed. Therefore, the operation of each column cycle in which the read operation is instructed can be accelerated.

  A thin film magnetic memory device according to still another configuration of the present invention has a page mode operation including a row cycle in which a unit operation cycle receives a row address and a plurality of subsequent column cycles each receiving a column address. A thin film magnetic memory device to be executed, comprising a plurality of memory cells arranged in a matrix. Each memory cell includes a magnetic storage unit whose electrical resistance changes according to a rewritable magnetization direction in response to application of a predetermined data write magnetic field generated by the first and second data write currents, and a magnetic storage And an access element that is electrically coupled in series with the portion and selectively turned on to pass the data read current. The thin film magnetic memory device further includes a plurality of data write selection lines provided corresponding to the memory cell rows and selectively activated to pass the first data write current, and the memory cell rows And a plurality of data read select lines which are selectively activated to turn on the access elements, a plurality of data lines respectively provided corresponding to the memory cell columns, and a row address. A row selection unit for controlling activation of the plurality of data write selection lines and the plurality of data read selection lines according to the row selection result is further provided. The row selection unit activates the data read selection line corresponding to the selected row in the row cycle, and deactivates each data read selection line in each column cycle. The thin film magnetic memory device further supplies a data read current to each of M (M: an integer of 2 or more) data lines of at least a part of the plurality of data lines in the row cycle, and data A read / write control circuit for supplying a second data write current to the data line corresponding to the input column address in each column cycle in which writing is instructed, and a memory belonging to the selected row in the row cycle A read data holding circuit for holding M pieces of stored data corresponding to M data lines read from a cell, and in each column cycle in which a data read operation is instructed, And a control circuit for instructing one output corresponding to the input column address of the M pieces of stored data.

  With this configuration, the storage data corresponding to the selected row is read in the row cycle and held in the same unit operation cycle. Therefore, the operation of each subsequent column cycle in which the data read operation is instructed can be speeded up.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 according to the first embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 performs random access in response to external control signal CMD and address signal ADD, and executes input of write data DIN and output of read data DOUT. The data read operation and data write operation in the MRAM device 1 are executed, for example, at a timing synchronized with an external clock signal CLK. Alternatively, the operation timing may be determined internally without receiving the clock signal CLK from the outside.

  The MRAM device 1 includes a control circuit 5 that controls the entire operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 having a plurality of MTJ memory cells arranged in a matrix. The configuration of the memory array 10 will be described in detail later. A plurality of write word lines WWL and read word lines RWL are arranged corresponding to MTJ memory cell rows (hereinafter also simply referred to as “memory cell rows”). . Bit lines BL and / BL are arranged corresponding to the MTJ memory cell columns (hereinafter also simply referred to as “memory cell columns”).

  The MRAM device 1 further includes a row decoder 20, a column decoder 25, a word line driver 30, and read / write control circuits 50 and 60.

  Row decoder 20 performs row selection in memory array 10 in accordance with row address RA indicated by address signal ADD. Column decoder 25 performs column selection in memory array 10 in accordance with column address CA indicated by address signal ADD. The word line driver 30 selectively activates the read word line RWL or the write word line WWL based on the row selection result of the row decoder 20. A memory cell (hereinafter also referred to as “selected memory cell”) designated as a data read or data write target is indicated by row address RA and column address CA.

  Write word line WWL is coupled to ground voltage Vss in region 40 on the opposite side of memory array 10 from where word line driver 30 is arranged. Read / write control circuits 50 and 60 apply to bit lines BL and / BL of a selected memory cell column (hereinafter also referred to as “selected column”) corresponding to the selected memory cell during data reading and data writing. This is a general term for a group of circuits arranged in a region adjacent to the memory array 10 in order to flow a data write current and a sense current (data read current).

FIG. 2 is a circuit diagram showing a configuration of the memory array shown in FIG.
Referring to FIG. 2, memory array 10 has MTJ memory cells MC arranged in n rows × m columns (n, m: natural numbers). In memory array 10, read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are arranged corresponding to the memory cell rows, and bit lines BL1 to BLm are provided corresponding to the memory cell columns, respectively.

  In the following, when the write word line, the read word line, and the bit line are collectively expressed, they are expressed using the symbols WWL, RWL, and BL, respectively, and the specific write word line, read word line, When a bit line is indicated, a subscript is added to these symbols to indicate them as WWL1, RWL1, BL1. The high voltage state (power supply voltage Vcc) and low voltage state (ground voltage Vss) of the signal and signal line are also referred to as “H level” and “L level”, respectively.

  Each MTJ memory cell MC includes a tunnel magnetoresistive element TMR that functions as a magnetic memory unit that has an electrical resistance that changes according to the level of stored data, and an access transistor ATR that functions as an access element, connected in series. As already described, a MOS transistor that is a field effect transistor formed on a semiconductor substrate is typically applied to the access transistor ATR.

  Tunneling magneto-resistance element TMR is electrically coupled between access transistor ATR and corresponding write word line WWL. Access transistor ATR is electrically coupled between corresponding bit line BL and tunneling magneto-resistance element TMR.

  Access transistor ATR has its gate coupled to corresponding read word line RWL. Access transistor ATR is turned on when read word line RWL is activated to H level, and electrically couples tunnel magnetoresistive element TMR between corresponding bit line BL and write word line WWL. On the other hand, when read word line RWL is in an inactive state (L level), access transistor ATR is turned off to electrically disconnect bit line BL and tunneling magneto-resistance element TMR.

  With this configuration, tunneling magneto-resistance element TMR and bit line BL are not directly coupled but are coupled via access transistor ATR. Thereby, each bit line BL is not directly coupled to a number of tunnel magnetoresistive elements TMR belonging to the corresponding memory cell column, but is electrically coupled only to the tunnel magnetoresistive elements of the selected memory cell to be read. . Thereby, the capacity of the bit line BL can be suppressed, and the operation at the time of data reading can be speeded up.

  Further, tunnel magnetoresistive element TMR can be pulled down to ground voltage Vss at the time of data reading using write word line WWL. Therefore, it is not necessary to provide a dedicated wiring for supplying the ground voltage Vss, and the MRAM device can be manufactured with a smaller number of metal wiring layers.

  FIG. 3 is an operation waveform diagram for explaining data write and data read operations in the memory array shown in FIG.

  First, the operation at the time of data writing will be described. The word line driver 30 activates the write word line WWL corresponding to the selected row according to the row selection result of the row decoder 20 and connects it to the power supply voltage Vcc. Since one end of each write word line WWL is coupled to the ground voltage Vss in the region 40, the data write current Ip flows in the direction from the word line driver 30 toward the region 40 in the write word line WWL of the selected row. It is.

  On the other hand, in the non-selected row, write word line WWL is maintained in an inactive state (L level: ground voltage Vss), and therefore no data write current flows. Each read word line RWL is maintained in an inactive state (L level) during data writing.

  Read / write control circuits 50 and 60 generate a data write current having a direction according to the data level of the write data by controlling the voltage across bit line BL of the selected column. For example, when writing storage data of “1”, the bit line voltage on the read / write control circuit 60 side is set to a high voltage state (power supply voltage Vcc), and the read / write control circuit 50 on the opposite side is set. The bit line voltage on the side is set to a low voltage state (ground voltage Vss). Thereby, data write current + Iw can be supplied to the bit line of the selected column in the direction from read / write control circuit 60 toward 50.

  On the other hand, when the stored data of “0” is written, the voltage polarity of the bit lines on the read / write control circuit 50 side and the 60 side is switched, and the data in the direction from the read / write control circuit 50 toward 60 A write current -Iw can flow. As a result, the data write magnetic field according to the level of the write data can be applied by supplying both the data write currents Ip and ± Iw to the selected memory cell to be the data write target. .

Next, the data read operation will be described.
At the time of data reading, word line driver 30 activates read word line RWL corresponding to the selected row to H level according to the row selection result of row decoder 20. In a non-selected row, the voltage level of read word line RWL is maintained in an inactive state (L level). On the other hand, since each write word line WWL is maintained at the ground voltage Vss, each MTJ memory cell is pulled down to the ground voltage Vss.

  Bit line BL is precharged to ground voltage Vss before the data read operation. From this state, the bit line of the selected column is pulled up by, for example, power supply voltage Vcc by read / write control circuit 50 and supplied with constant sense current Is.

  When data reading is started and the read word line RWL of the selected row is activated to H level and the corresponding access transistor ATR is turned on, the MTJ memory cell corresponding to the selected row receives the bit through the access transistor ATR. Electrically coupled between the line (pull-up with power supply voltage Vcc) and write word line WWL (ground voltage Vss). As a result, the sense current Is passes through the tunnel magnetoresistive element TMR of the selected memory cell. Therefore, in the selected memory cell selected as the data read target, a voltage change drop (ΔV0 or ΔV1 in FIG. 3) corresponding to the stored data level of the selected memory cell occurs.

  Next, the arrangement of MTJ memory cells in such an MRAM device will be described.

FIG. 4 is a cross-sectional view showing the configuration of the tunnel magnetoresistive element in the MTJ memory cell.
Referring to FIG. 4, tunneling magneto-resistance element TMR corresponding to a magnetic tunnel junction has an antiferromagnetic layer 101 and a fixed magnetization formed on antiferromagnetic layer 101 and having a fixed magnetic field in a fixed direction. A partial region of the layer 102, a free magnetic layer 103 that is magnetized by an applied magnetic field, a tunnel barrier 104 that is an insulator film formed between the fixed magnetic layer 102 and the free magnetic layer 103, and a contact electrode 105 Including.

The antiferromagnetic material layer 101, the fixed magnetic layer 102, and the free magnetic layer 103 are formed of an appropriate magnetic material such as FeMn, NiFe. The tunnel barrier 104 is formed of Al ₂ O ₃ or the like. Tunneling magneto-resistance element TMR is electrically coupled to the upper wiring via a barrier metal (not shown), which is disposed as necessary and is a buffer material for electrically coupling to the metal wiring.

  Contact electrode 105 is electrically coupled to the lower wiring. For example, the upper wiring corresponds to the bit line BL, and the lower wiring corresponds to a metal wiring coupled to the access transistor ATR.

  FIG. 5 is a conceptual diagram illustrating the arrangement of bit line BL and write word line WWL with respect to the tunnel magnetoresistive element according to the first embodiment.

  Referring to FIG. 5, tunnel magnetoresistive element TMR has an elongated shape in which the aspect ratio (a: b in FIG. 5) of the long side and the short side is about 2: 1 to 4: 1. . By adopting such a shape, the easy axis (EA) and the hard axis (HA) of the tunnel magnetoresistive element are along the long side direction and the short side direction, respectively.

  Further, by forming a rectangular shape with the apex of the rectangle cut out, unnecessary magnetization can be prevented from occurring in the direction of the hard axis (HA) in the vicinity of the end. As a result, in each MTJ memory cell, two types of magnetization directions along the easy axis in the free magnetization layer in the tunnel magnetoresistive element are associated with the levels of the write data, respectively, so that highly reliable data storage is possible. Can be performed. At this time, by applying a magnetic field in the hard axis direction, the threshold necessary for the magnetization reversal in the easy axis direction can be lowered. That is, considering these magnetization characteristics, as described with reference to FIG. 29, the operating point at the time of data writing, that is, the applied magnetic field, corresponds to the case where both the data write current in the row direction and the column direction are applied. Set to do.

  In this way, when the shape of the tunnel magnetoresistive element, that is, the shape of the MTJ memory cell is designed in consideration of the stability of the magnetization operation at the time of data writing, a data write magnetic field along the easy axis direction is generated. Therefore, the layout of the bit line BL for this purpose is naturally wider than that of the write word line WWL for generating a magnetic field in the hard axis direction, and the memory array can be reduced in area.

  In other words, since the bit line BL has a wiring width in the long side direction and the write word line WWL has a wiring width in the short side direction, the bit line BL has a wider wiring width than the write word line WWL. Easy to secure.

FIG. 6 is a structural diagram illustrating the arrangement of the tunnel magnetoresistive element according to the first embodiment.
Referring to FIG. 6, access transistor ATR is formed in p type region PAR on semiconductor main substrate SUB. Access transistor ATR has source / drain regions 110 and 120 which are n-type regions, and a gate 130. Source / drain region 110 is coupled to bit line BL formed in first metal interconnection layer M1.

  Read word line RWL is provided to control the gate voltage of access transistor ATR, and it is not necessary to actively flow a current. Therefore, from the viewpoint of increasing the degree of integration, the read word line RWL is formed using a polysilicon layer, a polycide structure, or the like in the same wiring layer as the gate 130 without newly providing an independent metal wiring layer.

  Source / drain region 120 of access transistor ATR is electrically coupled to tunneling magneto-resistance element TMR through metal film 150 formed in the contact hole, first metal interconnection layer M1, and barrier metal 140. Barrier metal 140 is a cushioning material provided to electrically couple tunneling magneto-resistance element TMR and metal wiring.

  Write word line WWL is formed in second metal interconnection layer M2 and is electrically coupled to tunneling magneto-resistance element TMR.

  As described above, the bit line BL and the write word line WWL for allowing the data write current to flow are provided on the semiconductor substrate on which the MRAM device is manufactured, and the bit line BL having a wiring width in the long side direction of the tunnel magnetoresistive element TMR. And the tunnel magnetoresistive element TMR are arranged so as to be larger than the distance between the write word line WWL having a wiring width in the short side direction of the tunnel magnetoresistive element TMR and the tunnel magnetoresistive element TMR.

  That is, a bit line BL that is required to pass a larger current at the time of data writing and that is disposed relatively far from the tunnel magnetoresistive element TMR is a bit line BL that can easily secure a wide wiring width. As a result, the current density of the write word line WWL in which it is relatively difficult to ensure the wiring width can be suppressed. As a result, in the MRAM device including the MTJ memory cell having the stable data writing characteristic, the wiring group for allowing the data writing current to flow can be efficiently arranged so as not to deteriorate the operation reliability. .

  Further, in a system LSI or the like in which a memory and a logic are integrated on the same chip, the upper metal wiring layer is generally designed to have a larger film thickness. Therefore, as shown in FIG. 6, if the structure is such that the write word line WWL is disposed on the upper layer side, the cross-sectional area of the write word line WWL where it is difficult to secure the wiring width from the relationship with the shape of the tunnel magnetoresistive element TMR is Easy to secure. For this reason, the MRAM device according to the first embodiment can be easily applied to a logic-embedded memory device.

  On the other hand, in the configuration shown in FIG. 6, if the wiring thickness of the bit line BL, that is, the thickness of the metal wiring layer M1 is designed to be large, while preventing an increase in the current density of the bit line BL through which a larger data write current flows, The wiring width can be reduced. As a result, the memory cell size can be reduced in consideration of the shape of the tunnel magnetoresistive element TMR.

[Embodiment 2]
As described in the first embodiment, in the data write operation, two types of data write magnetic fields along the hard axis direction and the easy axis direction are applied to the MTJ memory cell. In the second embodiment, a method of supplying a data write current for stably magnetizing the tunnel magnetoresistive element constituting each MTJ memory cell in the data write operation will be described.

  FIG. 7 is a circuit diagram showing a configuration of the memory array and its peripheral circuits according to the second embodiment.

  Referring to FIG. 7, in the configuration according to the second embodiment, read word lines RWL1 to RWLn and write word lines WWL1 to WWLn are arranged corresponding to the memory cell rows as in the memory array shown in FIG. Is done. On the other hand, bit lines BL1, / BL1 to BLm, / BLm that constitute bit line pairs BLP1 to BLPm are provided corresponding to the memory cell columns, respectively. Hereinafter, when the bit lines / BL1 to / BLm are collectively described, they are expressed as the bit line / BL.

  The MTJ memory cell MC is connected to one of the bit lines BL and / BL for each row. For example, the MTJ memory cell belonging to the first memory cell column will be described. The MTJ memory cell in the first row is coupled to the bit line / BL1, and the MTJ memory cell in the second row is connected to the bit line BL1. Combined with. Similarly, each of the MTJ memory cells is connected to one of the bit line pairs / BL1 to / BLm in the odd-numbered row, and is connected to one of the other bit line pairs BL1 to BLm in the even-numbered row.

  In the configuration according to the second embodiment, memory array 10 further includes a plurality of dummy memory cells DMC coupled to bit lines BL1, / BL1 to BLm, / BLm, respectively. The dummy memory cells DMC are arranged in 2 rows × m columns so as to correspond to one of the dummy read word lines DRWL1 and DRWL2. Dummy memory cells corresponding to dummy read word line DRWL1 are coupled to bit lines BL1, BL2-BLm, respectively. On the other hand, the remaining dummy memory cells corresponding to dummy read word line DRWL2 are coupled to bit lines / BL1, / BL2- / BLm, respectively.

  Dummy memory cell DMC has dummy resistance element TMRd and dummy access element ATRd. Electric resistance Rd of dummy resistance element TMRd is set to an intermediate value between electric resistances Rax and Rmin corresponding to storage data levels “1” and “0” of MTJ memory cell MC, that is, Rmax> Rd> Rmin. Dummy access element ATRd is typically formed of a field effect transistor, like the access element of the MTJ memory cell. Therefore, hereinafter, the dummy access element is also referred to as a dummy access transistor ATRd.

  Further, dummy write word lines DWWL1 and DWWL2 are arranged corresponding to the rows of dummy memory cells, respectively. Depending on the structure of the dummy resistance element TMRd, the arrangement of the dummy write word line may be unnecessary. However, in order to ensure the continuity of the shape on the memory array and avoid the complexity of the manufacturing process, the write word line WWL Dummy write word lines DWWL1 and DWWL2 designed in the same manner as in FIG.

  At the time of data reading, if odd-numbered rows are selected according to the row selection result and each of bit lines / BL1- / BLm and MTJ memory cell MC are coupled, dummy read word line DRWL1 is activated. Thus, each of bit lines BL1-BLm and dummy memory cell DMC are coupled. On the other hand, when even-numbered rows are selected and each of bit lines BL1 to BLm is coupled to MTJ memory cell MC, dummy read word line DRWL2 is activated and bit lines / BL1 to / BLm are activated. Are connected to the dummy memory cell DMC.

  The dummy read word lines DRWL1 and DRWL2 are collectively referred to as a dummy read word line DRWL.

  Word line driver 30 couples one end of write word line WWL of the selected row to power supply voltage Vcc2 during data writing. Thereby, similarly to the first embodiment, the data write current Ip in the row direction can be made to flow in the direction from the word line driver 30 toward the region 40 on the write word line WWL of the selected row. On the other hand, the write word line of the non-selected row is coupled to the ground voltage Vss by the word line driver 30.

  At the time of data reading, word line driver 30 selectively activates read word line RWL and dummy read word lines DRWL1, DRWL2 to H level (power supply voltage Vcc1) according to the row selection result. Specifically, when an odd row is selected and the MTJ memory cell group of the selected row is connected to / BL1 to / BLm, the dummy read word line DRWL1 is activated, and the dummy memory cell group is Connected to bit lines BL1 to BLm. Similarly, when an even-numbered row is selected, dummy read word line DRWL2 is activated.

  Corresponding to the memory cell columns, column selection lines CSL1 to CSLm for performing column selection are provided. Column decoder 25 sets one of column selection lines CSL1 to CSLm to a selected state (H level) in each of data writing and data reading in accordance with a decoding result of column address CA, that is, a column selection result. Activate.

  Further, a data bus pair DBP for transmitting read data and write data is arranged. Data bus pair DBP includes complementary data buses DB and / DB.

  Read / write control circuit 50 includes a data write circuit 51W, a data read circuit 51R, and column select gates CSG1 to CSGm provided corresponding to the memory cell columns, respectively.

  Here, since each of column selection gates CSG1 to CSGm has the same configuration, the configuration of column selection gate CSG1 provided corresponding to bit lines BL1 and / BL1 will be representatively described.

  Column select gate CSG1 includes a transistor switch electrically coupled between data bus DB and bit line BL1, and a transistor switch electrically coupled between data bus / DB and bit line / BL1. Have. These transistor switches are turned on / off according to the voltage of the column selection line CSL1. That is, when column select line CSL1 is activated to a selected state (H level), column select gate CSG1 electrically couples data buses DB and / DB to bit lines BL1 and / BL1, respectively.

  In the following, column selection lines CSL1 to CSLm and column selection gates CSG1 to CSGm are collectively referred to as column selection line CSL and column selection gate CSG, respectively.

  Read / write control circuit 60 includes short-circuit switch transistors 62-1 to 62-m and control gates 66-1 to 66-m provided corresponding to the memory cell columns, respectively. Read / write control circuit 60 further includes precharge transistors 64-1a, 64-1b to 64-ma provided between bit lines BL1, / BL1 to bit lines BLm, / BLm and ground voltage Vss, respectively. 64-mb.

  Hereinafter, the short-circuit switch transistors 62-1 to 62-m, the precharge transistors 64-1a, 64-1b to 64-ma, 64-mb, and the control gates 66-1 to 66-m are collectively referred to as a short circuit. Also referred to as switch transistor 62, precharge transistor 64 and control gate 66.

  Each control gate 66 outputs an AND logic operation result of the corresponding column selection line CSL and control signal WE. Therefore, during the data write operation, the output of control gate 66 corresponding to the selected column is selectively activated to H level.

  The short-circuit switch transistor 62 is turned on / off in response to the output of the corresponding control gate 66. Therefore, at the time of data write operation, one ends of bit lines BL and / BL corresponding to the selected column are electrically coupled by short-circuit switch transistor 62.

  Each precharge transistor 64 is turned on in response to activation of the bit line precharge signal BLPR to precharge the bit lines BL1, / BL1 to bit lines BLm, / BLm to the ground voltage Vss. The bit line precharge signal BLPR generated by the control circuit 5 is activated to the H level in the active period of the MRAM device 1 at least in a predetermined period before executing data reading. On the other hand, during the data read operation and data write operation in the active period of MRAM device 1, bit line precharge signal BLPR is inactivated to L level and precharge transistor 64 is turned off.

Next, the configuration of the data read circuit and the data write circuit will be described.
FIG. 8 is a circuit diagram showing a configuration of data read circuit 51R.

  Referring to FIG. 8, data read circuit 51R receives power supply voltage Vcc1 and supplies constant current I (Read) to internal nodes Ns1 and Ns2, respectively, and constant current supply circuits 70 and 71 and internal node Ns1 N channel MOS transistor 73 electrically coupled between data bus DB, N channel MOS transistor 74 electrically coupled between internal node Ns2 and data bus / DB, and internal nodes Ns1 and Ns2 Amplifier 75 for amplifying the voltage level difference between them and outputting read data DOUT, and resistors 76 and 77.

  Reference voltage Vrr is applied to the gates of N channel MOS transistors 73 and 74. Resistors 76 and 77 are provided for pulling down internal nodes Ns1 and Ns2 to ground voltage Vss. With such a configuration, data read circuit 51R can supply sense current Is corresponding to constant current I (Read) to each of data buses DB and / DB during data read.

  At the time of data reading, each of data buses DB and / DB is pulled down to ground voltage Vss through one of bit lines BL and / BL and one of a selected memory cell and one of dummy memory cells. Therefore, data stored in the selected memory cell can be read by amplifying the voltage difference between internal nodes Ns1 and Ns2 by data read circuit 51R.

FIG. 9 is a circuit diagram showing a configuration of data write circuit 51W.
Referring to FIG. 9, data write circuit 51W includes a constant current supply circuit 80 for supplying a constant current I (write), and P channel MOS transistors 81 and 82 constituting a current mirror. Thereby, the supply current to the internal node Nw0 is set according to the constant current I (write).

  Data write circuit 51W further includes inverters 84, 85 and 86 which operate by receiving an operation current supplied through internal node Nw0. Each of inverters 84, 85 and 86 operates by receiving supply of power supply voltage Vcc2 and ground voltage Vss.

  Inverter 84 inverts the voltage level of write data DIN and transmits it to data bus DB. Inverter 85 inverts the voltage level of write data DIN and transmits it to the input node of inverter 86. Inverter 86 inverts the output of inverter 84 and transmits the inverted signal to data bus / DB. Therefore, data write circuit 51W sets the voltage of data buses DB and / DB to one of power supply voltage Vcc2 and ground voltage Vss according to the level of write data DIN.

  Thus, in the selected column, data bus DB (/ DB) to column selection gate CSG to bit line BL (/ BL) to short-circuit switch transistor 62 to bit line / BL (BL) to column selection gate CSG to data bus / DB A data write current ± Iw in a direction corresponding to the level of the write data DIN can be passed through the path (DB).

  Power supply voltage Vcc2 that is the operating voltage of data write circuit 51W is set higher than Vcc1 that is the operating voltage of data read circuit 51R. This is because the data write currents Ip and ± Iw necessary for magnetizing the tunnel magnetoresistive element TMR of the selected memory cell are larger than the sense current Is necessary for data reading at the time of data writing. For example, an external power supply voltage supplied from the outside of the MRAM device 1 is applied as it is to the power supply voltage Vcc2, and the external power supply voltage is dropped by a voltage drop circuit (not shown) to generate the power supply voltage Vcc1. Thus, these power supply voltages Vcc1 and Vcc2 can be supplied efficiently.

Next, the configuration of the column decoder and word line driver will be described.
FIG. 10 is a block diagram showing a configuration of the column decoder 25 shown in FIG.

  Referring to FIG. 10, column decoder 25 includes decode units CDU1 to CDUm and drive units DVU1 to DVUm provided corresponding to the memory cell columns, respectively. Each of decode units CDU1 to CDUm receives an input of column address CA and activates its output to L level when the corresponding memory cell column is selected. Drive units DVU1 to DVUm drive column select lines CSL1 to CSLm in response to outputs of decode units CDU1 to CDUm.

  FIG. 11 is a circuit diagram showing the configuration of the drive unit. Since each of drive units DVU1 to DVUm has the same configuration, FIG. 11 representatively shows the configuration of drive unit DVU1 corresponding to column selection line CSL1.

  Referring to FIG. 11, drive unit DVU1 includes P channel MOS transistors 200 and 201 connected in series between power supply voltage Vcc1 and column select line CSL1, and in series between power supply voltage Vcc1 and select line CSL1. P channel MOS transistors 202 and 203 connected to each other and an N channel MOS transistor 204 connected between column select line CSL1 and ground voltage Vss are provided.

  Drive unit DVU 1 further includes logic gates 206 and 208. Logic gate 206 outputs an AND logic operation result of control signals / RE and / WR1. Control signal / WR1 is activated to L level during a data write operation for a predetermined period in which column selection line CSL of the selected column is desired to be activated. In other periods, control signal / WR1 is inactivated to H level. Control signal / RE is activated to L level for a predetermined period during a data read operation, and deactivated to H level during other periods.

  Logic gate 208 applies an OR logic operation result of the output of logic gate 206 and the output of decode unit CDU 1 to the gates of P channel MOS transistors 201 and 203 and N channel MOS transistor 204. An inverted signal of control signal / WE is input to the gate of P channel MOS transistor 200, and control signal / WE is input to the gate of P channel MOS transistor 202.

  The current driving capability of P channel MOS transistor 202 is designed to be smaller than that of P channel MOS transistor 200. For example, such characteristics can be realized by designing the gate width of the P-channel MOS transistor 202 to be narrower than that of the transistor 200.

  With such a configuration, the data write operation is performed by an inverter composed of a P-channel MOS transistor 203 and an N-channel MOS transistor 204 that receives the operation current I1 from the turned-on P-channel MOS transistor 202. Column select line CSL1 is driven according to the output of logic gate 208.

  Specifically, when the output of the decode unit CDU1 is activated to the L level, that is, when the first memory cell column is selected, the column selection line CSL1 is activated during the activation period of the control signal / WR1 ( In response to (L level), it is driven to H level (power supply voltage Vcc2). The column selection line CSL in the non-selected column is driven to the ground voltage Vss.

  In the data read operation, on the other hand, the operation current I2 (I2> I1) is supplied from the turned-on P-channel MOS transistor 200, and the inverter composed of the P-channel MOS transistor 201 and the N-channel MOS transistor 204 is replaced with the logic gate 208. The column selection line CSL1 is driven according to the output of. Therefore, selected column select line CSL1 is driven to H level (power supply voltage Vcc2) in response to the activation period (L level) of control signal / RE.

  Thus, while the decode result output timing from the decode unit CDU1 is the same at the time of data reading and at the time of data writing, the driving force (supply current amount) of the activated column selection line CSL is the data It differs between writing and reading data. Therefore, the rising speed of the voltage of the activated column selection line CSL at the time of data writing is slow, that is, the rising time constant becomes large. On the other hand, at the time of data reading, the rising speed of the voltage of the activated column selection line CSL is fast, that is, the rising time constant is small.

FIG. 12 is a circuit diagram showing a configuration of the write word line driver.
Referring to FIG. 12, row decoder 20 includes decode units RDU1-RDUn provided corresponding to the memory cell rows, respectively. Each of decode units RDU1-RDUn receives the input of row address RA and activates its output to L level when the corresponding memory cell row is selected.

  The word line driver 30 includes a write word line drive unit 30W that controls activation of the write word lines WWL1 to WWLn, and a read word line drive unit 30R that controls activation of the read word lines RWL1 to RWLn.

  The write word line drive unit 30W includes drive gates 210-1 to 210-n provided corresponding to the write word lines WWL1 to WWLn, respectively. Drive gates 210-1 to 210-n are formed of NOR gates that operate in response to supply of power supply voltage Vcc2 and ground voltage Vss. Drive gates 210-1 to 210-n drive write word lines WWL1 to WWLn according to outputs (decode results) of decode units RDU1 to RDUn and control signal / WR2.

  Control signal / WR2 is activated to an L level so as to correspond to a predetermined period for activating write word line WWL of the selected row during a data write operation. In other periods, control signal / WR2 is inactivated to H level. Control signals / WR1, / WR2, / RE are generated by control circuit 5, for example. At the start of data write operation, the activation timing of control signals / WR1 and / WR2 (H level → L level) is set in common, but at the end of data write operation, control signal / WR2 is inactive After being activated (L level → H level), control signal / WR1 is deactivated.

  Thus, write word line WWL corresponding to the selected row is driven to power supply voltage Vcc2 (H level) in order to flow data write current Ip during a period in which control signal / WR2 is set to L level. In contrast, the write word line WWL of the non-selected row is maintained at the ground voltage Vss (L level). On the other hand, each write word line WWL is inactivated and set to ground voltage Vss in a period other than the data write operation including the data read operation when control signal / WE is set to the H level. .

  Read word line drive unit 30R includes drive gates 220-1 to 220-n provided corresponding to read word lines RWL1 to RWLn, respectively. Drive gates 220-1 to 220-n are formed of NOR gates that operate in response to supply of power supply voltage Vcc1 and ground voltage Vss. Drive gates 220-1 to 220-n drive read word lines RWL1 to RWLn according to outputs (decode results) of decode units RDU1 to RDUn and control signal / RE.

  In a data read operation in which control signal / RE is set to L level, read word line RWL corresponding to the selected row is driven to H level (power supply voltage Vcc1) to turn on access transistor ATR. In contrast, the read word line RWL of the non-selected row is maintained at the ground voltage Vss (L level). On the other hand, each read word line RWL is inactivated and set to ground voltage Vss in a period other than the data read operation including the data write operation when control signal / RE is set to the H level. .

  Although not shown in FIG. 12, the same decode units and drive gates as the read word lines RWL are arranged for the dummy read word lines DRWL1 and DRWL2.

  FIG. 13 is an operation waveform diagram for illustrating a data read operation and a data write operation according to the second embodiment.

  Referring to FIG. 13A, in the data read operation, the data read operation is started in response to the read command input at the activation timing of clock signal CLK.

  When the data read operation is started, the read word line RWL of the selected row and the column select line CSL of the selected column are activated in response to the input row address RA and column address CA. There is no particular restriction on the activation order of the read word line RWL and the column selection line CSL, and both are activated at the fastest timing in order to realize high-speed access.

  In particular, drive units DVU1 to DVUm in column decoder 25 drive column selection line CSL by P channel MOS transistor 200 (FIG. 11) having a large current driving capability. Therefore, when a decoding result is transmitted from the decoding unit at time t0, column selection line CSL of the selected column rises from L level to H level at time t1.

  At the time of data reading, each write word line WWL is maintained at the ground voltage Vss, so that no data write current flows. On the other hand, a constant sense current Is is supplied to the bit lines BL and / BL in the selected column in response to the activation period of the column selection line CSL. The sense current Is passes through the tunnel magnetoresistive element in the selected memory cell via the access transistor turned on in response to the activation of the read word line RWL. As a result, the voltage change described with reference to FIG. 3 occurs in the bit line of the selected column, so that stored data can be read from the selected memory cell.

  At the end of the data read operation, column selection line CSL of the selected column is inactivated at time t4. In response to this, the supply of the sense current Is to the bit lines BL, / BL in the selected column is also terminated.

  Referring to FIG. 13B, at the time of data writing, similarly, a write command is input in response to the activation timing of clock signal CLK, and the data writing operation is started.

  When the data write operation is started, the write word line WWL of the selected row is activated according to the input row address RA, and the data write current Ip is supplied. Data write current Ip reaches a predetermined level at time tw.

  On the other hand, column selection line CSL in the selected column is driven at a moderate speed by P-channel MOS transistor 202 (FIG. 11) having a small current driving capability. Therefore, the rising time constant of column selection line CSL is set larger during data writing than during data reading. That is, when the decoding result is transmitted from the decoding unit at time t0, the column selection line CSL rises from the L level to the H level at time t2, which is later than time t1. In FIG. 13A, for comparison, the operation waveform of the column selection line of the selected column at the time of data reading is indicated by a dotted line.

  Thereby, data write current ± Iw flowing through bit lines BL, / BL of the selected column starts to flow gently according to the drive speed of column select line CSL at the start of data writing. That is, at time t2 later than time tw when data write current Ip reaches a predetermined level, data write current ± Iw flowing through bit lines BL and / BL of the selected column reaches a predetermined level. In other words, the driving force of the column selection line CSL during the data write operation, that is, the operating current I1 shown in FIG. 11 is designed so that the column selection line CSL can be activated at such timing.

  With this configuration, the data write magnetic field in the easy magnetization direction is applied after the data write magnetic field in the hard magnetization direction is first applied to the tunnel magnetoresistive element of the selected memory cell at the start of data writing. A magnetic field can be applied.

  At the end of the data write operation, the column selection line CSL in the selected column is deactivated, that is, a time earlier than the time t4 when the supply of the data write current ± Iw to the bit lines BL and / BL in the selected column is ended. At t3, the write word line WWL of the selected row is deactivated, and the supply of the data write current Ip is completed. That is, the deactivation timing of control signal / WR1 shown in FIG. 11 is set corresponding to time t4, and the deactivation timing of control signal / WR2 shown in FIG. 12 is set corresponding to time t3. Is done. Each activation timing of control signals / WR1 and / WR2 is set in correspondence with time t0.

  Thus, at the end of the data write operation, a period during which the data write magnetic field in the hard axis direction decreases can be provided under the application of a predetermined level of data write magnetic field in the easy axis direction. it can.

  FIG. 14 is a conceptual diagram illustrating the magnetization behavior of the tunnel magnetoresistive element during the data write operation according to the second embodiment.

  Referring to FIG. 14A, before time t0 (t <t0) before the data write operation, the free magnetic layer in the tunnel magnetoresistive element has a certain direction along the easy axis (FIG. 14). (A) is magnetized in the right direction). In the following, a data write operation for rewriting the magnetization direction in FIG.

  Referring to FIG. 14B, between time t0 and time t1 (t = t0 to t1), data along the hard axis (HA) is generated by the data write current Ip flowing through the write word line WWL. A write magnetic field Hh is applied. Thereby, the magnetization direction of the free magnetic layer starts to rotate gradually.

  Further, referring to FIG. 14C, during a period from time t1 to time t2 (t = t1 to t2), the data write magnetic field Hh in the hard axis direction of a predetermined level is applied. A data write magnetic field He in the easy axis direction for reversing the magnetization direction of the free magnetic layer is applied. When the sum of the data write magnetic fields Hh and He reaches a region corresponding to the outside of the asteroid characteristic line shown in FIG. 29, the magnetization direction of the free magnetic layer is changed from the direction indicated by the dotted arrow to the solid arrow. Rewritten to reverse in the direction shown.

  Referring to FIG. 14D, between time t3 and time t4 (t = t3 to t4), the data write magnetic field He along the easy axis direction is applied at a predetermined level. Thus, the data write magnetic field Hh along the hard axis direction decreases. Thereby, at the end of the data write operation, the vector sum of the data write magnetic fields Hh and He changes in the magnetization rotation direction in FIG.

  As shown in FIG. 14E, by changing the data write magnetic fields Hh and He in this order, the magnetization direction of the free magnetic layer is changed to an undesirable intermediate magnetization during the data write operation. It can be stably rewritten in the opposite direction without falling into a state.

  Here, generation of an undesirable intermediate magnetization state at the time of data writing operation in the free magnetic layer will be described with reference to FIG.

  Referring to FIG. 15, end regions 108 and 109 of tunneling magneto-resistance element TMR are not easily magnetized in response to a magnetic field in the easy axis direction, and have a characteristic that the direction and amount of magnetization gradually change. . Therefore, unlike the central region 107 in which the direction and amount of magnetization are set in binary in response to a magnetic field in the easy axis direction, the end region has undesirable characteristics as a memory cell.

  As shown in FIG. 15A or 15B, in the free magnetic layer of the tunnel magnetoresistive element TMR, after the end regions 108 and 109 are magnetized in one direction along the hard axis, the central region Is magnetized in the direction according to the write data level along the easy magnetization axis, so that stable magnetization characteristics can be obtained.

  As described above, the data write magnetic field in the hard axis direction is applied before the data write magnetic field in the easy axis direction by delaying the activation timing of the column selection line CSL from the write word line WWL. The Thus, after the magnetization directions in the end regions 108 and 109 of the tunnel magnetoresistive element TMR are aligned in one direction (upward in FIGS. 15A and 15B), the center region 107 is aligned with the easy magnetization axis. The magnetization reversal in the opposite direction can be performed stably.

  In contrast, when the write word line WWL and the column selection line CSL are activated almost simultaneously, or when the column selection line CSL is activated earlier than the write word line WWL, the free magnetic layer is multistable (Multi- 15 (c), (d), and (e), the magnetization direction becomes an irregular intermediate state other than the desirable stable state.

  As a result, the magnetization direction of the free magnetic layer after data writing is not aligned in a desirable direction as shown in FIG. 15 (a) or (b). Therefore, in a memory cell in which data is written, a desired difference in electrical resistance corresponding to the difference in the stored data level cannot be secured, causing a malfunction and impairing the operational stability of the MRAM device.

  As described above, by supplying the data write current according to the second embodiment, the data write magnetic field in the hard axis direction is changed to the data in the easy axis direction at the start and end of the data write operation. It can be generated or extinguished faster than the write magnetic field. Thereby, data writing can be stably executed in consideration of the magnetization characteristics of the MTJ memory cell.

  Focusing on the column selection line CSL corresponding to the selected column, the driving force of the column selection line CSL is switched between the data read operation and the data write operation, so that the column is displayed at the fastest timing during the data read operation. While the selection line CSL is activated to increase the speed, it is possible to execute stable data writing while avoiding a magnetized unstable intermediate state during the data writing operation. That is, it is possible to achieve both stable data writing and high-speed data reading.

  In FIGS. 14 and 15, the tunnel magnetoresistive element is shown in a rectangular shape, but the magnetization behavior at the time of data writing is the same even when the end is notched as described in the first embodiment. It is.

  Further, the supply of the data write current according to the second embodiment can be executed without being limited to the configuration of the memory array 10 shown in FIG. For example, as shown in FIG. 16, without connecting each write word line WWL to each MTJ memory cell, access transistor ATR and tunnel magnetoresistive element TMR are connected to corresponding bit line BL and ground voltage Vss supply node. The second embodiment can also be applied to a memory array configured to be connected in series with each other.

[Embodiment 3]
In the third embodiment, a configuration for applying a page mode operation used in a general dynamic random access memory to an MRAM device will be described.

  FIG. 17 is an operation waveform diagram for explaining a page mode operation for executing continuous data reading.

  Referring to FIG. 17, one unit operation cycle of page mode operation includes a row cycle in which a row address for executing row selection is input and a plurality of columns while maintaining row selection in the row cycle. And a plurality of column cycles for consecutive access. In each column cycle, a data read operation or a data write operation is instructed, and a column address indicating a data read or data write target is input.

  Each of the row cycle and the column cycle is started in response to the clock signal CLK. In the row cycle, row address RA for row selection is input as address signal ADD. Further, for example, when the memory array 10 is divided into a plurality of banks, and further bank selection is necessary for specifying the selected row, the bank address BA is input together with the row address RA.

  Further, in response to the level of control signal / WE input in the row cycle, it is determined which of data reading and data writing is executed in the subsequent column cycle. In FIG. 17, since the control signal / WE is set to H level at the activation timing of the clock signal CLK in the row cycle, the data read operation is executed in each subsequent column cycle. In each column cycle, column cycle signal / CC is activated to L level for a predetermined period based on clock signal CLK.

  In the operation example shown in FIG. 17, the data read operation is continuously executed in each column cycle. In the row cycle, in response to the input row address RA (and bank address BA), the read word line RWL of the selected row is activated from the L level to the H level. Activation of the read word line RWL of the selected row is maintained within the same unit operation cycle.

  In column cycle 1, control signal / WE is set to H level for a predetermined period. Further, a column address CA1 indicating a data read target is input. In response to the column address CA1, the column selection line CSL of the selected column is activated at the same timing as in FIG. In response to this, a sense current Is for passing the tunnel magnetoresistive element of the selected memory cell flows through the bit line BL of the selected column. Thereby, the storage data of the selected memory cell corresponding to row address RA (and bank address BA) and column address CA1 can be read.

  Similarly, in column cycle 2, data reading from the selected memory cell corresponding to input column address CA2 and row address RA (and bank address BA) is executed.

  FIG. 18 is an operation waveform diagram for explaining a page mode operation in which continuous data writing is executed.

  Referring to FIG. 18, when data write operation is continuously executed in each column cycle, control signal / WE is set to L level in the row cycle. In response to this, each read word line RWL is maintained in an inactive state (L level: ground voltage Vss) in the row cycle and each subsequent column cycle. Further, the row selection result in response to the row address RA (and bank address BA) input in the row cycle is held in the same unit operation cycle.

  In each column cycle in which the data write operation is executed, control signal / WE is set to L level for a predetermined period. Activation of the write word line WWL in the selected row corresponding to the row address RA (and bank address BA) input in the row cycle is controlled for each column cycle.

  For example, by using a column cycle signal / CC and a delay signal of control signal / WE, a write word of a selected row for a predetermined period (time t0 to t4 in FIG. 18) in which a data write operation is executed. Line WWL is activated to pass data write current Ip. In other periods, the write word line WWL of the selected row is deactivated and the supply of the data write current is completed. That is, at the end of the row cycle and each column cycle, each write word line WWL is deactivated and supply of data write current Ip is temporarily stopped.

  As a result, the risk of erroneous data writing can be reduced as compared with the configuration in which the activation of the write word line WWL of the selected row is maintained in the unit operation cycle of the page mode operation. In other words, when the activation of the write word line in the selected row is maintained, a predetermined level magnetic field is continuously applied to each MTJ memory cell in the selected row in the hard axis direction. There is a risk of erroneous data writing even with a small intensity of magnetic noise.

  In column cycle 1, column address CA1 is input as address signal ADD at the activation timing of clock signal CLK, and control signal / WE is set to the L level. Thereby, activation of column selection line CSL corresponding to column address / CA1 and supply of data write current Ip to write word line WWL are executed at the same timing as described in FIG. . Therefore, the data write operation in column cycle 1 is performed in the same manner as in FIG. 13B, and the data write magnetic field in the hard magnetization direction is changed to the easy magnetization axis at the start and end of the data write operation. It can be generated or disappeared more rapidly than the direction data write magnetic field. Thereby, data writing can be stably executed in consideration of the magnetization characteristics of the MTJ memory cell.

FIG. 19 is a circuit diagram showing a configuration of a word line driver according to the third embodiment.
Referring to FIG. 19, word line driver 30 according to the third embodiment includes latch circuits 260-1 to 260-n for latching decode results of decode units RDU1 to RDUn, read word line drive unit 30R, And a write word line drive unit 30W.

  The latch circuits 260-1 to 260-n latch the outputs (decode results) of the decode units RDU1 to RDUn in response to a control signal RC activated at a predetermined timing of the row cycle. As a result, the latch circuits 260-1 to 260-n hold the row selection result corresponding to the row address RA (and bank address BA) input in the row cycle in the same unit operation cycle.

  Read word line drive unit 30R further includes a latch circuit 250 in addition to drive gates 220-1 to 220-n shown in FIG. The latch circuit 250 holds the signal level of the control signal WE (an inverted signal of / WE) input in the low cycle in response to the control signal RC.

  The contents held in each of the latch circuit 250 and the latch circuits 260-1 to 260-n are updated every row cycle of a new unit operation cycle.

  Each of the drive gates 220-1 to 220-n responds to the row selection result held in the latch circuits 260-1 to 260-n and the control signal WE held in the latch circuit 250, and the corresponding read word line Controls activation of RWL. Therefore, as described with reference to FIGS. 17 and 18, when the control signal / WE is set at the L level (WE = “H”) in the row cycle, each read in the row cycle and the subsequent column cycle is performed. Inactive state (L level) of word line RWL is maintained.

  On the other hand, when control signal / WE is set to H level in the row cycle, the active state (H level) of read word line RWL in the selected row is maintained in the row cycle and the subsequent column cycle. The activation control of each read word line RWL is changed every new row cycle in response to the control signal RC. Although not shown in FIG. 19, the same configuration is provided for the dummy read word lines DRWL1 and DRWL2.

  Write word line drive unit 30W according to the third embodiment is different from the configuration of the write word line drive unit shown in FIG. 12 in that switch transistors 212-1 to 212-n and delay circuit 255 are further included.

  Delay circuit 255 delays control signal / WE for a predetermined time and outputs control signal / WEd. Further, each of switch transistors 212-1 to 212-n supplies an operating current to drive gates 210-1 to 210-n in response to column cycle signal / CC shown in FIGS.

  Each of drive gates 210-1 to 210-n receives a row selection result held in latch circuits 260-1 to 260-n shared with read word line drive unit 30R and control signal / WEd from delay circuit 255. In response, the activation of the corresponding write word line WWL is controlled. Delay time in delay circuit 255 is determined in consideration of a preferred supply timing of data write current Ip, that is, time t0 and time t3 shown in FIG.

  With such a configuration, activation of the write word line WWL and the read word line RWL can be controlled at an appropriate timing for executing the page mode operation shown in FIGS. 17 and 18. On the other hand, activation control can be performed on column selection line CSL using a column decoder having the same configuration as that of the second embodiment.

  Thus, according to the configuration according to the third embodiment, high-speed data reading and magnetization of MTJ memory cells are performed in page mode operation for continuously executing either data reading operation or data writing operation. Stable data writing considering characteristics can be performed in a compatible manner.

[Modification 1 of Embodiment 3]
FIG. 20 is an operation waveform diagram illustrating a data write operation in the page mode operation according to the first modification of the third embodiment.

  Referring to FIG. 20, the activation of write word line WWL and read word line RWL is controlled by the word line driver shown in FIG. 19, thereby supplying data write current Ip at the same timing as in FIG. Is set.

  20 is compared with FIG. 18, in the page mode operation according to the first modification of the third embodiment, the activation timing of column selection line CSL in the selected column is delayed in each column cycle instructed to write data. The point is different. That is, the data write current ± Iw for generating the data write magnetic field along the easy axis direction starts to be supplied from time tw and increases to a predetermined level at time t2.

  At the end of the data write operation, the deactivation timing of the column selection line CSL is set to a time t4 that is later than the time t3 corresponding to the deactivation timing of the write word line WWL.

  The data write operation in the subsequent column cycle 2 is also performed for the selected memory cell corresponding to the column address CA2 input in the column cycle and the row address RA (and bank address BA) input in the row cycle. 1 is executed.

  Even in such a data write operation, the supply start and supply end timings of the data write current ± Iw for generating the data write magnetic field in the easy axis direction in the column cycle in which the data write is executed are as follows: It is later than the supply start and supply end timings of the data write current Ip for supplying the data write magnetic field along the hard axis.

  FIG. 21 is a circuit diagram illustrating a configuration of a drive unit of column selection line CSL according to the first modification of the third embodiment. Since the configuration of the drive unit provided for each column selection line CSL is the same as already described, FIG. 21 representatively shows the configuration of the drive unit DVU1 corresponding to the column selection line CSL1.

  Referring to FIG. 21, drive unit DVU1 according to the first modification of the third embodiment is different from the configuration of the drive unit shown in FIG. 11 in that it further includes a delay circuit 265.

  Delay circuit 265 further delays control signal / WEd from delay circuit 255 shown in FIG. 20 by a predetermined time ΔT, and outputs control signal / WEdd. Control gate 206 outputs an AND logic operation result of control signals / RE and / WEdd. Control gate 208 applies the OR operation result of the output from decode unit CDU1 and the output of logic gate 206 to the gates of P channel MOS transistor 201 and N channel MOS transistor 204, as in the configuration of FIG. .

  In the configuration of FIG. 21, the current driving capability of P channel MOS transistor 202 is designed in the same manner as the current driving capability of P channel MOS transistor 200 (operating current I2 in FIG. 11). Therefore, the driving force (supply current amount) of activated column select line CSL at the time of data writing is set in the same manner as at the time of data reading. Therefore, in each of data writing and data reading, the rising speed of the voltage of activated column selection line CSL, that is, the rising time constant is the same.

  In each column cycle in which the data write operation is instructed, the column selection line CSL of the selected column is activated quickly at a timing delayed by ΔT from the write word line WWL of the selected row in response to the control signal / WEdd. (To power supply voltage Vcc2) and inactivated (to ground voltage Vss). By setting predetermined time ΔT in delay circuit 265 in consideration of the difference between times t0 and tw in FIG. 20 and the difference between times t3 and t4, at the timing shown in FIG. Iw can be supplied. If the respective delay times of delay circuits 255 and 265 are appropriately set, both inputs can be made common control signal / WE.

  At the time of data reading, column selection line CSL of the selected column is activated to H level (power supply voltage Vcc1) at the fastest timing at a timing in response to activation of control signal / RE (L level).

  With this configuration, the data write magnetic field in the hard axis direction can be easily magnetized at the start and end of the data write operation in the column cycle in which data write is executed even in the page mode operation. It can be generated or eliminated more quickly than the axial data write magnetic field. Thereby, similarly to the first modification of the second embodiment, the data writing can be stably executed in consideration of the magnetization characteristics of the MTJ memory cell.

[Modification 2 of Embodiment 3]
In the second modification of the third embodiment, a page mode operation that can be continuously executed by mixing a data read operation and a data write operation in a plurality of column cycles in one unit operation cycle will be described.

  FIG. 22 is an operation waveform diagram illustrating a page mode operation according to the second modification of the third embodiment.

  Referring to FIG. 22, in the page mode operation according to the second modification of the third embodiment, as in the page mode operation according to the third embodiment and the first modification, the unit operation cycle includes a row address for row selection. It is started by a row cycle that receives the input of RA (and bank address BA). The row selection result based on the row address RA (and bank address BA) input in the row cycle is held in the same operation cycle. Based on the held row selection result, the read word line RWL of the selected row is activated (H level) except for the column cycle in which the data write operation is instructed.

  In each column cycle, control signal / WE is set to L level for a predetermined period when a data write operation is instructed.

  FIG. 23 is a circuit diagram showing a configuration of read word line drive unit 30R according to the second modification of the third embodiment.

  Referring to FIG. 23, read word line drive unit 30R according to the second modification of the third embodiment includes latch circuit 250 in comparison with the configuration of the read word line drive unit according to the third embodiment shown in FIG. Instead, the difference is that a pulse generation circuit 280 is included. Pulse generation circuit 280 generates control pulse / WCC for defining the activation period of read word line RWL according to the level of control signal / WE at the activation timing of clock signal CLK.

  Referring again to FIG. 22, in the cycle in which control signal / WE is at the H level at the activation timing of clock signal CLK, control pulse / WCC is maintained at the H level. On the other hand, in the column cycle in which data writing is instructed, control signal / WE is set at the L level at the activation timing of clock signal CLK, and accordingly, for a predetermined period (time t0 to time t0 in FIG. 22). t4) The control pulse / WCC is set to L level. The predetermined period is set according to the activation period of the control signal / WE, for example.

  Referring to FIG. 23 again, drive units 220-1 to 220-n respond to the row selection results held in latch circuits 260-1 to 260-n and the corresponding read signal in response to the inverted signal of control signal / WCC. The activation of the word line RWL is controlled. Although not shown in FIG. 23, the same configuration is provided for the dummy read word lines DRWL1 and DRWL2.

  On the other hand, write word line drive unit 30W has the same configuration as that of FIG. 19, and activates write word line WWL in the selected row corresponding to row address RA (and bank address BA) input in the row cycle. Control for each column cycle.

  With this configuration, the read word line RWL of the selected row in which the L level data is held in the corresponding latch circuit is set to the H level except for a predetermined period in the column cycle in which the data write operation is instructed. Activated. This speeds up the operation in each column cycle in which the read operation is instructed.

  In column cycle 1 and column cycle 2 in which the data write operation is instructed, each read word line RWL is deactivated, and the input column address CA1 or CA2 and the row address RA ( The data write operation for the selected memory cell corresponding to the bank address BA) can be executed in the same manner as in the third embodiment or the modification 1 thereof.

  The activation timing of the write word line WWL needs to be set according to the configuration of the memory array 10. As shown in FIG. 16, in the configuration in which each write word line WWL is electrically disconnected from the MTJ memory cell, data is transferred to the write word line WWL while the read word line RWL of the selected row is activated. Even if the write current is supplied, no adverse effect occurs. Therefore, in such a configuration, it is possible to design the activation periods of the read word line RWL and the write word line WWL of the selected row to overlap at the start of the data write operation.

  On the other hand, in a configuration in which a current path including both tunneling magneto-resistance element TMR and write word line WWL is formed in response to turn-on of access transistor ATR as in the memory array shown in FIG. If the activation periods of the read word line RWL and the write word line WWL overlap with each other in time, erroneous data writing needs to occur. Therefore, in such a memory array configuration, it is necessary to set the activation period of the read word line RWL and the write word line WWL so as not to overlap in time in the selected row.

  As described above, in the configuration according to the second modification of the third embodiment, in the page mode operation in which the data read operation and the data write operation can be mixed, high-speed data read and the magnetization characteristics of the MTJ memory cell are It is possible to carry out the stable data writing in consideration of both.

[Modification 3 of Embodiment 3]
In the third modification of the third embodiment, a configuration for further speeding up the data read operation in the page mode operation in which the data read operation and the data write operation are mixed will be described.

  FIG. 24 is an overall block diagram showing a configuration of the MRAM device 2 according to the third modification of the third embodiment.

  24, MRAM device 2 according to the third modification of the third embodiment is different from MRAM device 1 shown in FIG. 1 in that read data latch circuit 300 is further provided.

  Read data latch circuit 300 latches at least a part of the m-bit data read by read / write control circuit 50 in response to control signal LS generated by control circuit 5. Further, read data latch circuit 300 outputs at least one of a plurality of stored data latched therein as read data DOUT in accordance with control signal RO from the control circuit and the column selection result of column decoder 25. .

  Since the configuration for writing write data DIN into a selected memory cell in memory array 10 is similar to that of the third embodiment and its modification 1 or 2, detailed description thereof will not be repeated.

  FIG. 25 is an operation waveform diagram illustrating a page mode operation of MRAM device 2 according to the third modification of the third embodiment.

  Referring to FIG. 25, in the configuration according to the third modification of the third embodiment, one row of data corresponding to the selected row indicated by input row address RA (and bank address BA) in the row cycle is read. Is executed. That is, in the row cycle, in response to control signal / RC activated to L level for a predetermined period, read word line drive unit 30R activates read word line RWL of the selected row.

  Further, in the row cycle, M (M: integer of 2 to m) column selection lines CSL corresponding to at least a part of all memory cell columns are activated in parallel, and a plurality of memories are selected in the selected row. Data reading from the cells is performed in parallel. In general, data reading from all memory cell columns or data reading from either one of the odd / even columns is executed.

  Read / write control circuit 50 is designed so that supply of sense current Is and reading of stored data can be executed in parallel for M memory cell columns selected simultaneously. For example, it is necessary to provide a configuration corresponding to the data read circuit 51R shown in FIG. 8 for the number of memory cell columns (M) to be activated simultaneously. Hereinafter, in the present embodiment, the description will be made assuming that one row of data is read in parallel, that is, “M = m”.

  At the timing when m read data corresponding to the selected row is generated by the read / write control circuit 50, the control circuit 5 activates the control signal LS for a predetermined period. In response to this, read data latch circuit 300 latches the read m pieces of stored data.

  Next, in column cycle 1 in which the data write operation is instructed, control signal / WE is set to L level for a predetermined period including the activation timing of clock signal CLK. A column address CA1 for indicating a data write target is input.

  In response to this, the selected memory cell corresponding to row address RA (and bank address BA) and column address CA1 is stabilized according to the level of the write data, as in the third embodiment or its modifications 1 and 2. Data write currents ± Iw and Ip are supplied to be magnetized selectively.

  In column cycle 2 where a data read operation is instructed, control signal / WE is set to the H level at the activation timing of clock signal CLK. A column address CA2 for indicating a data read target is input.

  In column cycle 2, control circuit 5 activates control signal RO to H level for a predetermined period. In response to this, the read data latch circuit 300 selects one of the m stored data latched in the row cycle based on the column selection result in the column decoder 25 and corresponds to the input column address CA2. The stored data is selected and output as read data DOUT.

  With such a configuration, the data read operation in each column cycle is speeded up because it is not necessary to detect a change in the voltage of the bit line accompanying the sense current Is passing through the selected memory cell.

  Further, in each column cycle, all read word lines RWL are inactivated to L level, so that the write word line WWL is activated at the fastest timing even in the column cycle in which the data write operation is instructed. Data writing operation can be started at high speed.

  As described above, in the configuration according to the third modification of the third embodiment, the page mode operation described in the third embodiment and the first and second modifications is mixed with the data read operation and the data write operation. It can be executed at high speed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic block diagram which shows the whole structure of the MRAM device 1 according to Embodiment 1 of this invention. FIG. 2 is a circuit diagram showing a configuration of a memory array shown in FIG. 1. FIG. 3 is an operation waveform diagram illustrating data write and data read operations in the memory array shown in FIG. 2. It is sectional drawing which shows the structure of the tunnel magnetoresistive element in an MTJ memory cell. FIG. 6 is a conceptual diagram illustrating an arrangement of bit lines BL and write word lines WWL with respect to a tunnel magnetoresistive element according to the first embodiment. FIG. 6 is a structural diagram illustrating the arrangement of tunneling magneto-resistance elements according to the first embodiment. FIG. 7 is a circuit diagram showing a configuration of a memory array and its peripheral circuits according to a second embodiment. FIG. 8 is a circuit diagram showing a configuration of a data read circuit shown in FIG. 7. FIG. 8 is a circuit diagram showing a configuration of a data write circuit shown in FIG. 7. FIG. 8 is a block diagram illustrating a configuration of the column decoder illustrated in FIG. 7. It is a circuit diagram which shows the structure of the drive unit shown in FIG. It is a circuit diagram showing a configuration of a write word line driver. FIG. 11 is an operation waveform diagram for illustrating a data read operation and a data write operation according to the second embodiment. FIG. 12 is a conceptual diagram illustrating the magnetization behavior of a tunnel magnetoresistive element during a data write operation according to the second embodiment. It is a conceptual diagram explaining generation | occurrence | production of the undesirable intermediate | middle magnetization state at the time of the data write operation in a free magnetic layer. It is a circuit diagram which shows the other structural example of a memory array. FIG. 11 is an operation waveform diagram illustrating a page mode operation for executing continuous data reading. FIG. 11 is an operation waveform diagram for explaining a page mode operation for executing continuous data writing. FIG. 11 is a circuit diagram showing a configuration of a word line driver according to a third embodiment. FIG. 16 is an operation waveform diagram illustrating a data write operation in a page mode operation according to the first modification of the third embodiment. FIG. 11 is a circuit diagram illustrating a configuration of a drive unit of column selection line CSL according to a first modification of the third embodiment. FIG. 11 is an operation waveform diagram illustrating a page mode operation according to the second modification of the third embodiment. FIG. 22 is a circuit diagram showing a configuration of a read word line driver unit 30R according to a second modification of the third embodiment. FIG. 16 is an overall block diagram showing a configuration of an MRAM device 2 according to a third modification of the third embodiment. FIG. 16 is an operation waveform diagram illustrating a page mode operation of MRAM device 2 according to the third modification of the third embodiment. It is the schematic which shows the structure of an MTJ memory cell. It is a conceptual diagram explaining the data read-out operation | movement from an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram explaining the relationship between the data write current at the time of data writing to the MTJ memory cell and the magnetization direction of the tunnel magnetoresistive element. It is a conceptual diagram which shows the structure of the memory array comprised by the MTJ memory cell integratedly arranged by the matrix form.

Explanation of symbols

  1, 2 MRAM device, 5 control circuit, 10 memory array, 20 row decoder, 25 column decoder, 30 word line driver, 30W write word line drive unit, 30R read word line drive unit, 51W data write circuit, 51R data read Circuit, 101 Antiferromagnetic layer, 102 Fixed magnetic layer, 103 Free magnetic layer, 104 Tunnel barrier, 250, 260-1 to 260-n Latch circuit, 255, 265 Delay circuit, 280 Pulse generation circuit, 300 Read data latch Circuit, ADD address signal, ATR access transistor, BL, / BL bit line, CA, CA1, CA2 column address, CDU1 to CDUm, RDU1 to RDUn decode unit, CLK clock signal, CSG column selection gate, CSL RAM selection line, DB, / DB data bus, DIN write data, DMC dummy memory cell, DOUT read data, He, Hh data write magnetic field, Ip, ± Iw data write current, Is sense current (data read current) MC MTJ memory cell, RWL read word line, TMR tunnel magnetoresistive element, Vss ground voltage, Vcc, Vcc1, Vcc2 power supply voltage, WWL write word line.

Claims (9)

A semiconductor device that executes a page mode operation in which a unit operation cycle includes a row cycle that receives a row address and a plurality of subsequent column cycles that each receive a column address.
Responding to application of a predetermined data write magnetic field generated by first and second data write currents, each including a thin film magnetic body formed in a semiconductor integrated circuit, arranged in a matrix A plurality of memory cells having a magnetic memory portion whose electrical resistance changes according to the rewritable magnetization direction;
Provided corresponding to memory cell rows in the selected row, a plurality of first wiring for supplying the first data write current,
Provided corresponding to memory cell columns in the selected row, and a plurality of second wiring for flowing the second data write current,
And a row selecting section for controlling supply of the first data write current to the plurality of first wiring,
The row selection unit
A row decoder for executing row selection according to the row address input in the row cycle;
In response to a row selection result by the row decoder and a control signal for selectively instructing data writing and data reading in the subsequent plurality of column cycles, a first wiring corresponding to the selected row is provided. A drive unit for activating to pass the first data write current;
The drive unit, the supply of the first data write current corresponding to the selected row is temporarily stopped for each end of each co-ram cycle of said subsequent plurality of column cycles, the semiconductor device. The row selection unit further includes:
A latch circuit for holding the row selection result in the row decoder;
The drive unit is activated to flow the first data write current through the first wiring corresponding to the selected row in accordance with the row selection result and the control signal held in the latch circuit. The semiconductor device according to claim 1, wherein One of the first and second data write currents generates a magnetic field along the easy axis direction in the magnetic storage unit,
The other data write current of the first and second data write currents generates a magnetic field along the hard axis direction in the magnetic storage unit,
2. The semiconductor device according to claim 1, wherein a rising time constant of one data write current is larger than a rising time constant of the other data write current in each column cycle in which a data write operation is instructed. . One of the first and second data write currents generates a magnetic field along the easy axis direction in the magnetic storage unit,
The other data write current of the first and second data write currents generates a magnetic field along the hard axis direction in the magnetic storage unit,
2. The semiconductor device according to claim 1, wherein the supply start timing of the one data write current is later than the supply start timing of the other data write current in each column cycle in which a data write operation is instructed. . Each of the magnetic storage units has a shape in which the aspect ratio of the long side and the short side is greater than 1,
One wire of each of said first wiring and the second wiring, the one of the data write current is applied is disposed along the direction of the short side,
Of each of said first wiring and the second wiring, the other wirings other data write current is applied are arranged along the direction of the long side, claim 3 or claim Item 5. The semiconductor device according to Item 4. Each of the plurality of memory cells includes
Wherein is electrically coupled to the magnetic storage unit and in series, further includes an access element that is selectively turned on to pass the data read current,
The semiconductor device includes:
A plurality of third wirings provided corresponding to the memory cell rows and selectively activated to turn on the access element;
In each column cycle instructed to read data, the data read current is supplied to the second wiring corresponding to the input column address, and input in each column cycle instructed to write data. further comprising a read write control circuit for supplying the second data write current to the data line corresponding to the column address,
The row selection unit further controls activation of the plurality of third wirings;
The drive unit deactivates the third wiring corresponding to the selected row in each column cycle in which a data write operation is instructed according to the row selection result by the row decoder and the control signal . The semiconductor device according to claim 1 , wherein the first wiring corresponding to the selected row is activated for a predetermined period. The semiconductor device according to claim 6, wherein the drive unit activates a third wiring corresponding to the selected row in a period other than the predetermined period in each column cycle. Each of the memory cells is configured to have a node electrically connected to the corresponding first wiring,
The drive unit, the activation of the supply period of each of the third activation period of the wire and the second data write current so as to avoid overlap in time, the plurality of third wirings The semiconductor device according to claim 7, wherein the semiconductor device is controlled. Each of the memory cells is disposed electrically separated from the corresponding first wiring,
The row selecting section includes a supply period of each of the third activation period of the wire and the second data write current so as to have a temporal overlapping period, the activation of the third wirings The semiconductor device according to claim 7, which is controlled.

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