TW200943291A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- TW200943291A TW200943291A TW097141757A TW97141757A TW200943291A TW 200943291 A TW200943291 A TW 200943291A TW 097141757 A TW097141757 A TW 097141757A TW 97141757 A TW97141757 A TW 97141757A TW 200943291 A TW200943291 A TW 200943291A
- Authority
- TW
- Taiwan
- Prior art keywords
- word line
- common
- memory blocks
- semiconductor device
- common word
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1693—Timing circuits or methods
Abstract
There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007339854 | 2007-12-28 | ||
JP2008140921A JP5150936B2 (en) | 2007-12-28 | 2008-05-29 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200943291A true TW200943291A (en) | 2009-10-16 |
TWI480870B TWI480870B (en) | 2015-04-11 |
Family
ID=41031319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097141757A TWI480870B (en) | 2007-12-28 | 2008-10-30 | Semiconductor device |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP5150936B2 (en) |
CN (1) | CN101593551A (en) |
TW (1) | TWI480870B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI628664B (en) * | 2015-09-18 | 2018-07-01 | 台灣積體電路製造股份有限公司 | Dual rail memory, memory macro and assiociated hybrid power supply method |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8050109B2 (en) * | 2009-08-10 | 2011-11-01 | Sandisk 3D Llc | Semiconductor memory with improved memory block switching |
JP5149414B2 (en) * | 2010-07-16 | 2013-02-20 | シャープ株式会社 | Semiconductor memory device and driving method thereof |
JP5684081B2 (en) * | 2011-09-22 | 2015-03-11 | 株式会社東芝 | Analog / digital converter |
JP2013131521A (en) * | 2011-12-20 | 2013-07-04 | Fujitsu Ltd | Magnetic resistance element, semiconductor memory, and system |
CN103456350A (en) * | 2012-05-30 | 2013-12-18 | 辉达公司 | Semiconductor memory device and word line decoding wiring method |
CN105097036B (en) * | 2015-07-10 | 2019-11-12 | 北京兆易创新科技股份有限公司 | Read operation control method and device in data storage type flash memory |
KR102395724B1 (en) * | 2015-10-07 | 2022-05-10 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
US10950294B2 (en) * | 2019-04-24 | 2021-03-16 | Micron Technology, Inc. | Apparatuses and methods for controlling driving signals in semiconductor devices including word and subword driver circuits |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5946227A (en) * | 1998-07-20 | 1999-08-31 | Motorola, Inc. | Magnetoresistive random access memory with shared word and digit lines |
JP2002170377A (en) * | 2000-09-22 | 2002-06-14 | Mitsubishi Electric Corp | Thin film magnetic storage device |
JP4726290B2 (en) * | 2000-10-17 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit |
JP4726292B2 (en) * | 2000-11-14 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | Thin film magnetic memory device |
JP4731041B2 (en) * | 2001-05-16 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | Thin film magnetic memory device |
US6490217B1 (en) * | 2001-05-23 | 2002-12-03 | International Business Machines Corporation | Select line architecture for magnetic random access memories |
JP4780878B2 (en) * | 2001-08-02 | 2011-09-28 | ルネサスエレクトロニクス株式会社 | Thin film magnetic memory device |
JP4771631B2 (en) * | 2001-09-21 | 2011-09-14 | ルネサスエレクトロニクス株式会社 | Thin film magnetic memory device |
KR100505104B1 (en) * | 2002-04-30 | 2005-07-29 | 삼성전자주식회사 | Magnetic random access memory cells, structures thereof and operation methods thereof |
JP4190238B2 (en) * | 2002-09-13 | 2008-12-03 | 株式会社ルネサステクノロジ | Nonvolatile semiconductor memory device |
JP2004185755A (en) * | 2002-12-05 | 2004-07-02 | Sharp Corp | Nonvolatile semiconductor storage device |
JP2005064050A (en) * | 2003-08-14 | 2005-03-10 | Toshiba Corp | Semiconductor memory device and method of writing data therein |
KR100597636B1 (en) * | 2004-06-08 | 2006-07-05 | 삼성전자주식회사 | Phase change Random Access Memory device |
US7345912B2 (en) * | 2006-06-01 | 2008-03-18 | Grandis, Inc. | Method and system for providing a magnetic memory structure utilizing spin transfer |
-
2008
- 2008-05-29 JP JP2008140921A patent/JP5150936B2/en not_active Expired - Fee Related
- 2008-10-30 TW TW097141757A patent/TWI480870B/en not_active IP Right Cessation
- 2008-11-27 CN CNA2008101816100A patent/CN101593551A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI628664B (en) * | 2015-09-18 | 2018-07-01 | 台灣積體電路製造股份有限公司 | Dual rail memory, memory macro and assiociated hybrid power supply method |
Also Published As
Publication number | Publication date |
---|---|
CN101593551A (en) | 2009-12-02 |
JP5150936B2 (en) | 2013-02-27 |
TWI480870B (en) | 2015-04-11 |
JP2009176396A (en) | 2009-08-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TW200943291A (en) | Semiconductor device | |
CN102576565B (en) | Utilize the system and method for the distributed byte buffer in memory module | |
WO2008022094A3 (en) | Data storage device | |
KR102390917B1 (en) | Clean data strobe signal generating circuit in read interface device | |
JP2012533793A5 (en) | ||
CA2729505A1 (en) | Dual function data register | |
WO2007134319A3 (en) | Multi-chip package for a flash memory | |
TW200943315A (en) | Semiconductor signal processing device | |
WO2013184139A1 (en) | Accessing memory | |
EP2782100A3 (en) | Memory to read and write data at a magnetic tunnel junction element | |
WO2008076790A3 (en) | Multi-die memory device | |
WO2007133646A3 (en) | Adaptive storage system including hard disk drive with flash interface | |
TW200629549A (en) | Semiconductor device | |
DE602007002484D1 (en) | MEMORY DEVICE WITH MODE-SELECTABLE PRELOAD AND CLOCK-TO-CORE CLOCK | |
MX2010006978A (en) | Mram device with shared source line. | |
EP1710804A3 (en) | Line layout structure, semiconductor memory device, and layout method | |
WO2014146012A3 (en) | Data bus inversion including data signals grouped into 10 bits | |
TW200634843A (en) | Page buffer circuit of flash memory device | |
WO2011019487A3 (en) | On-die logic analyzer for semiconductor die | |
KR20080042435A (en) | Semiconductor memory device and method for layout of the same | |
JP2015111486A5 (en) | Information processing device | |
TW201207854A (en) | Semiconductor device and method for driving the same | |
WO2012173750A3 (en) | Magnetic memory system and methods in various modes of operation | |
TW200643724A (en) | System for improving bandwidth among a plurality of memory controllers and method thereof | |
WO2007008324A3 (en) | High-speed interface for high-density flash with two levels of pipelined cache |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |