TWI476958B - 發光二極體封裝結構及其封裝方法 - Google Patents

發光二極體封裝結構及其封裝方法 Download PDF

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TWI476958B
TWI476958B TW098144349A TW98144349A TWI476958B TW I476958 B TWI476958 B TW I476958B TW 098144349 A TW098144349 A TW 098144349A TW 98144349 A TW98144349 A TW 98144349A TW I476958 B TWI476958 B TW I476958B
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emitting diode
carbon nanotube
nanotube film
substrate
light
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TW201123545A (en
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Tai Cherng Yu
Han Lung Lee
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Hon Hai Prec Ind Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H—ELECTRICITY
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    • H01L2924/11—Device type
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    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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    • H01L33/641—Heat extraction or cooling elements characterized by the materials
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/70—Nanostructure
    • Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
    • Y10S977/742—Carbon nanotubes, CNTs

Description

發光二極體封裝結構及其封裝方法
本發明涉及一種發光二極體封裝結構及其封裝方法。
發光二極體作為發光源由於具有高效益之特性，而於汽車、交通訊號燈指示、螢幕顯示，甚至照明等領域得到廣泛應用。發光二極體工作時，會產生大量熱。如果不及時散熱，就會影響發光二極體之性能，甚至會使發光二極體因過熱而損壞。故，發光二極體需要採用不同封裝結構，以提高其散熱效果。
一種發光二極體封裝結構，其包括一基板、一導電層、一封裝膠層、一發光二極體晶片、二金線、一金屬底座及一玻璃透鏡。該基板之反面印製有線路及焊盤。該導電層藉由電鍍銅或銀之方法形成於該基板之正面。該發光二極體晶片黏結於該導電層上。藉由金線將該發光二極體晶片與導電層電性連接。該金屬底座圍繞該發光二極體晶片設置，且該金屬底座全表面電鍍有銀層。該玻璃透鏡蓋於金屬底座上。
上述發光二極體封裝結構之導電層藉由電鍍銅或銀之方法形成於該基板之正面，惟，銅或銀之導熱率約為380瓦/米·開爾文，其散熱性能不佳。並且，上述發光二極體封裝結構之金屬基座圍繞該發光二極體晶片，不利於發光二極體晶片散熱。
鑒於上述狀況，有必要提供一種散熱性能較好之發光二極體封裝結構及其封裝方法。
一種發光二極體封裝結構，其包括一基板、至少一發光二極體晶片、設置於該基板上之奈米碳管薄膜及覆蓋於該奈米碳管薄膜及該至少一發光二極體晶片上之封裝膠層，該奈米碳管薄膜上形成有相互間隔之至少二導電區域，該至少一發光二極體晶片之電極分別對應電連接於該至少二導電區域。
一種發光二極體之封裝方法，其包括如下步驟：提供一種基板；於該基板上設置一奈米碳管薄膜；於該奈米碳管薄膜上形成有相互間隔之複數導電區域；將複數發光二極體晶片之電極對應電連接於該複數導電區域；於該奈米碳管薄膜及複數發光二極體晶片上塗覆一層封裝膠層。
一種發光二極體之封裝方法，其包括如下步驟：提供一種基板；於該基板上設置一層奈米碳管薄膜；於該奈米碳管薄膜上形成有相互間隔之二導電區域；將一發光二極體晶片之電極對應電連接於該二導電區域上；於該奈米碳管薄膜及發光二極體晶片上塗覆一層封裝膠層。
上述發光二極體發光二極體封裝結構採用奈米碳管薄膜作為導電層，奈米碳管之軸向導熱率大於6600瓦/米•開爾文，其較大提高發光二極體封裝結構之散熱性能。同時，在製備奈米碳管薄膜的過程中,可根據預先設計直接形成相互間隔之導電區域，無需於基板電鍍或印刷導電層，故，上述發光二極體發光二極體封裝結構製造較方便。封裝膠層可填充於該複數導電區域之間，以增加該導電區域之間之絕緣性，同時，使發光二極體晶片及奈米碳管薄膜緊密地黏附於基板上。
下面結合附圖及實施方式對本發明之發光二極體封裝結構及其封裝方法作進一步詳細說明。
請參閱圖1，本發明實施方式一之發光二極體封裝結構100，其用於多顆發光二極體組成陣列一起使用。該封裝發光二極體封裝結構100包括一基板10、一奈米碳管薄膜20、複數發光二極體晶片30及一封裝膠層40。奈米碳管薄膜20平鋪於基板10上。奈米碳管薄膜20上開設有複數通槽21，以形成相互間隔之複數導電區域23。複數發光二極體晶片30之電極31、32分別對應電連接奈米碳管薄膜20之複數不同之導電區域23。封裝膠層40含有螢光粉，其塗覆於奈米碳管薄膜20上，且完全覆蓋發光二極體晶片30。封裝膠層40填充於該複數通槽21。本實施方式中，基板10為陶瓷基板。
上述發光二極體封裝結構100亦用於單顆發光二極體單獨使用，此時，需要將該發光二極體封裝結構100切割成複數單一發光二極體封裝結構。
請參閱圖2，本發明實施方式二之發光二極體封裝結構101僅封裝一發光二極體晶片30。奈米碳管薄膜20上形成一通槽21，從而形成相互間隔之二導電區域23。該發光二極體晶片30之電極31、32對應電連接於二導電區域23上。
上述發光二極體封裝結構100及發光二極體封裝結構101採用奈米碳管薄膜20作為導電層，CNT管之軸向導熱率大於6600瓦/米·開爾文，其較大提高發光二極體封裝結構100及發光二極體封裝結構101之散熱性能。並且，在製備奈米碳管薄膜20的過程中,可根據預先設計直接形成相互間隔之導電區域23，無需於基板電鍍或印刷導電層，無需在基板10電鍍或印刷導電層，故，上述發光二極體封裝結構100及發光二極體封裝結構101之製造較方便。另，封裝膠層40填充於該複數通槽21內，以增加該導電區域23之間之絕緣性，同時，使發光二極體晶片30及奈米碳管薄膜20緊密地黏附於基板10上。
請參閱圖3，本發明提供一種發光二極體封裝方法，該封裝方法用於同時封裝複數發光二極體晶片30，其包括如下步驟：
步驟S201，提供一種基板10。本實施方式中，基板10為陶瓷基板或經過陽極氧化處理之鋁基板。
步驟S202，基板10上設置上一層奈米碳管薄膜20。
步驟S203，於奈米碳管薄膜20上，形成相互間隔之複數導電區域23。可藉由雷射打孔或選擇性加熱之方法，於奈米碳管薄膜20上形成複數通槽21，以形成該複數導電區域23。
步驟S204，將複數發光二極體晶片30之電極31、32對應電連接該複數導電區域23上。
步驟S205，於奈米碳管薄膜20及該複數發光二極體晶片30上塗覆一封裝膠層40。封裝膠層40含有螢光粉，且封裝膠層40之外表面較平坦。
步驟S206，切割基板10形成複數單一發光二極體封裝結構101。
如果用於形成發光二極體封裝結構100，則步驟S206可省略。上述封裝方法可同時批量形成複數單一發光二極體封裝結構101，其製造效率較高。並且，封裝方法無需於基板10上電鍍金屬層，其製造方法較簡單。
請參閱圖4，本發明提供另一種發光二極體封裝方法，該封裝方法用於封裝單一發光二極體晶片30，其包括如下步驟：
步驟S301，提供一種基板10。本實施方式中，基板10為陶瓷基板或經過陽極氧化處理之鋁基板。
步驟S302，基板10上設置一層奈米碳管薄膜20。
步驟S303，於奈米碳管薄膜20上，形成二相互間隔之導電區域23。可藉由雷射打孔或選擇性加熱之方法，於奈米碳管薄膜20上形成一通槽21，以形成該二導電區域23。
步驟S204，將一發光二極體晶片30之電極31、32對應電連接該二導電區域23。
步驟S205，於奈米碳管薄膜20及該發光二極體晶片30上塗覆一封裝膠層40。
綜上所述，本發明確已符合發明專利之要件，遂依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。
10‧‧‧基板
20‧‧‧奈米碳管薄膜
21‧‧‧通槽
23‧‧‧導電區域
30‧‧‧發光二極體晶片
31、32‧‧‧電極
40‧‧‧封裝膠層
100、101‧‧‧發光二極體封裝結構
圖1係本發明實施方式一之發光二極體封裝結構剖面示意圖。
圖2係本發明實施方式二之發光二極體封裝結構剖面示意圖。
圖3係本發明發光二極體之封裝方法之流程圖。
圖4係本發明發光二極體之另一封裝方法之流程圖。
10‧‧‧基板
20‧‧‧奈米碳管薄膜
21‧‧‧通槽
23‧‧‧導電區域
30‧‧‧發光二極體晶片
31、32‧‧‧電極
40‧‧‧封裝膠層
100‧‧‧發光二極體封裝結構

Claims (10)

  1. 一種發光二極體封裝結構，包括一基板、至少一發光二極體晶片，其改良在於：該封裝結構還包括一封裝膠層及設置於該基板上之一奈米碳管薄膜，該奈米碳管薄膜上形成有相互間隔之至少二導電區域，該至少一發光二極體晶片之電極分別對應電連接於該至少二導電區域，該封裝膠層覆蓋該奈米碳管薄膜及該至少一發光二極體晶片。
  2. 如申請專利範圍第1項所述之發光二極體封裝結構，其中該奈米碳管薄膜上開設有至少一通槽，以形成該至少二導電區域。
  3. 如申請專利範圍第1項所述之發光二極體封裝結構，其中該封裝膠層含有螢光粉。
  4. 如申請專利範圍第1項所述之發光二極體封裝結構，其中該基板為陶瓷基板。
  5. 一種發光二極體之封裝方法，其包括如下步驟：
    提供一種基板；
    於該基板上設置一層奈米碳管薄膜；
    於該奈米碳管薄膜上形成有複數相互間隔之導電區域；
    將複數發光二極體晶片之電極對應電連接於該複數導電區域；
    於該奈米碳管薄膜及複數發光二極體晶片上塗覆一封裝膠層。
  6. 如申請專利範圍第5項所述之發光二極體之封裝方法，其中該奈米碳管薄膜藉由雷射或加熱之方法形成該複數導電區域。
  7. 如申請專利範圍第5項所述之發光二極體之封裝方法，其中該封裝膠層含有螢光粉。
  8. 如申請專利範圍第5項所述之發光二極體之封裝方法，其中該封裝方法還包括切割塗覆有該封裝膠層之基板，以形成複數單一發光二極體之步驟。
  9. 一種發光二極體之封裝方法，其包括如下步驟：
    提供一種基板；
    於該基板上設置一層奈米碳管薄膜；
    於該奈米碳管薄膜上形成有二相互間隔之導電區域；
    將一發光二極體晶片之電極對應電連接於該二導電區域；
    於該奈米碳管薄膜及發光二極體晶片上塗覆一封裝膠層。
  10. 如申請專利範圍第9項所述之發光二極體之封裝方法，其中該奈米碳管薄膜藉由雷射或加熱之方法形成該二導電區域。
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