TWI474407B - A method for manufacturing a transistor, a transistor, and a sputtering target - Google Patents

Description

Method for manufacturing transistor, transistor and sputtering target

The present invention relates to a method for producing a transistor having an active layer composed of an oxide semiconductor, a transistor, and a sputtering target.

In recent years, active matrix type liquid crystal displays have been widely used. The active matrix type liquid crystal display has a field effect type thin film transistor (TFT) for each pixel as a switching element.

As the thin film transistor, a polycrystalline germanium type thin film transistor in which an active layer is composed of polycrystalline germanium is known; and an active layer is an amorphous germanium type thin film transistor composed of amorphous germanium.

Compared with the polycrystalline germanium type thin film transistor, since the active layer of the amorphous germanium type thin film transistor is easy to manufacture, it has the advantage of being able to form a film uniformly on a relatively large area of the substrate.

On the other hand, a transparent amorphous oxide film is being developed as an active layer material capable of achieving a higher mobility of a carrier (electron or hole) than amorphous germanium. For example, Patent Document 1 describes an electric field effect type transistor using a homologous compound InGaO ₃ (ZnO) _m (a natural number of m system less than 6) as an active layer, which is borrowed in an oxygen environment. It is formed by pulsed laser evaporation. Further, Patent Document 2 describes a method of forming a conductive oxide thin film by sputtering a target made of a sintered body of In:Ga:Zn=1:1:1 in an oxygen atmosphere.

The conductive properties of the active layer composed of an oxide semiconductor are affected by the amount of oxygen contained therein. Therefore, it is conventional to form an oxide semiconductor film having a target conductivity by adjusting the oxygen partial pressure at the time of film formation.

Prior technical literature

Patent literature

Patent Document 1: Japanese Laid-Open Patent Publication No. 2006-165529 (paragraph [0057])

Patent Document 2: Japanese Laid-Open Patent Publication No. 2000-44236 (paragraphs [0030], [0034])

However, in the method of controlling the oxygen content of the film by the partial pressure of oxygen at the time of film formation, the oxygen concentration in the surface of the substrate must be uniform. Therefore, as the substrate is increased in area, it is difficult to supply uniform oxygen to the surface of the substrate. Therefore, it is difficult to uniformize the film quality, and there is a problem that the substrate cannot be enlarged.

In view of the above circumstances, an object of the present invention is to provide a method for producing a transistor, a transistor, and a sputtering target which can obtain the conductive characteristics of a target active layer without introducing oxygen at the time of film formation.

In order to achieve the above object, a method for producing a transistor according to the present invention includes forming an oxide semiconductor layer having the following composition range by sputtering a target made of an oxide semiconductor in a non-oxidizing atmosphere. The oxide semiconductor is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , and has a ratio z/y of 0 or more and less than 0.9, and the ratio x/y is 0 or more. A composition range of less than 6.5. The oxide semiconductor layer is heat-treated at a temperature of 200 ° C or more and 400 ° C or less.

The transistor of the present invention includes a gate electrode, an active layer, a gate insulating film, a source electrode, and a drain electrode.

The foregoing active layer is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , and the foregoing active layer has a ratio z/y of 0 or more and less than 0.9 and a ratio x/y of 0. The above is composed of an oxide semiconductor having a composition range of less than 6.5.

The gate insulating film is formed between the gate electrode and the active layer.

The source electrode and the drain electrode are electrically connected to the active layer.

The sputtering target of the present invention is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , and the sputtering target has a ratio z/y of 0 or more and less than 0.9, and An oxide semiconductor having a ratio x/y of 0 or more and less than 6.5.

A method for producing a transistor according to an embodiment of the present invention includes forming an oxide semiconductor layer having the above composition range by sputtering a target made of an oxide semiconductor in a non-oxidizing atmosphere. The oxide semiconductor is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} (x, y, and z are integers), and has a ratio z/y of 0 or more and less than 0.9. And the ratio x/y is 0 or more and less than 6.5 (when x, y, and z are positive numbers, a composition range of 0<(z/y)<0.9 and 0<(x/y)<6.5). The oxide semiconductor layer is heat-treated at a temperature of 200 ° C or more and 400 ° C or less.

The non-oxidizing environment means a vacuum environment in which an oxidizing gas such as oxygen is not intentionally introduced into the processing chamber as a reaction gas, and does not mean to exclude oxygen remaining in the processing chamber during depressurization. According to the above method, it is not possible to uniformize the oxygen concentration on the surface of the substrate, and it is possible to form an oxide semiconductor layer having a uniform in-plane, and it is also possible to easily cope with an increase in size of the substrate.

Further, the sputter film formed in the above environment has a composition which is the same as or substantially the same as the composition of the target. As described above, by sputtering a target semiconductor material having a predetermined composition ratio to form an oxide semiconductor layer of a film, it is impossible to directly obtain predetermined transistor characteristics. Therefore, the oxide semiconductor semiconductor is promoted by annealing (heat treatment) the film-formed oxide semiconductor layer in the above temperature range. The structure of the bulk layer is relaxed, enabling it to exhibit the desired transistor properties.

Regarding the composition range of the target, in the above formula, the ratio z/y is 0 or more and less than 0.9, and the ratio x/y is 0 or more and less than 6.5 (when x, y, and z are positive numbers, 0<(z) /y)<0.9 and 0<(x/y)<6.5). Thereby, by the heat treatment at 400 ° C after film formation, it is possible to obtain a transistor having an on/off current ratio (ratio between the on current value and the off current value) of 5 digits or more.

Here, even when the In content (z=0) and the Zn content (x=0), an on/off current ratio of 5 or more digits can be obtained. When the ratio z/y is 0.9 or more, the Ga ₂ O ₃ component is insufficient, and it is difficult to obtain an on/off current ratio which is operable as a transistor. Further, when the ratio x/y is 6.5 or more, the ZnO component is excessive, and it is difficult to obtain an on/off current ratio which is operable as a transistor.

The heat treatment temperature is set to 200 ° C or more and 400 ° C or less. When the heat treatment temperature is less than 200 ° C, the structure relaxation effect of the oxide semiconductor layer cannot be promoted, and it is difficult to ensure an on/off current ratio of 5 digits or more. Further, when the heat treatment temperature is more than 400 ° C, the substrate on which the oxide semiconductor layer is formed or the various functional films formed on the substrate may be limited in material.

The ratio z/y may be 0 or more and less than 0.5, and the ratio x/y is larger than 0 and smaller than 6.5 (when x, y, and z are positive numbers, 0<(z/y)<0.5) And 0 < (x / y) < 6.5).

Thereby, a transistor having an on/off current ratio of 5 digits or more can be manufactured by heat treatment at 300 ° C after film formation.

The ratio z/y may be 0 or more and less than 0.5, and the ratio x/y is larger than 0.3 and smaller than 2.6 (when x, y, and z are positive numbers, 0<(z/y)<0.5) And 0.3 < (x / y) < 2.6).

Thereby, it is possible to manufacture a transistor having an on/off current ratio of 5 digits or more and a mobility of 1.0 cm ² /Vs or more by heat treatment at 300 ° C after film formation.

The ratio z/y may be 0 or more and less than 0.9, and the ratio x/y is larger than 0, smaller than 2.6, and the ratio y (x+y+z) is less than 0.8 (x, y, and z). When it is a positive number, 0 < (z / y) < 0.9, 0 < (x / y) < 2.6 and (y / x + y + z) < 0.8).

Thereby, it is possible to manufacture a transistor having an on/off current ratio of 5 digits or more and a mobility of 1.0 cm ² /Vs or more by heat treatment at 400 ° C after film formation.

A transistor according to an embodiment of the present invention includes a gate electrode, an active layer, a gate insulating film, a source electrode, and a drain electrode.

The foregoing active layer is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , and the aforementioned active layer has a ratio z/y of 0 or more and less than 0.9, and the ratio x/y A composition range of 0 or more and less than 6.5 (when x, y, and z are positive numbers, an oxide semiconductor having 0 < (z/y) < 0.9 and 0 < (x/y) < 6.5) is used.

The gate insulating film is formed between the gate electrode and the active layer. The source electrode and the drain electrode are electrically connected to the active layer.

According to the above transistor, an on/off current ratio of 5 digits or more can be obtained.

The ratio z/y may be 0 or more and less than 0.5, and the ratio x/y is larger than 0 and smaller than 6.5 (when x, y, and z are positive numbers, 0<(z/y)<0.5) And 0 < (x / y) < 6.5).

Thereby, it is possible to obtain an on/off current ratio of 5 digits or more without requiring high temperature processing of more than 300 °C.

The ratio z/y may be 0 or more and less than 0.5, and the ratio x/y is larger than 0.3 and smaller than 2.6 (when x, y, and z are positive numbers, 0<(z/y)<0.5) And 0.3 < (x / y) < 2.6).

Thereby, high-temperature processing of more than 300 ° C is not required, and an on/off current ratio of 5 digits or more can be obtained, and the mobility is 1.0 cm ² /Vs or more.

The ratio z/y may be 0 or more and less than 0.9, and the ratio x/y is 0 or more and less than 2.6, and the ratio y(x+y+z) is a range of less than 0.8 (x, y, and z are positive numbers) When, 0 < (z / y) < 0.9, 0 < (x / y) < 2.6 and (y / x + y + z) < 0.8).

Thereby, it is possible to obtain a degree of mobility in which the on/off current ratio is 5 digits or more and 1.0 cm ² /Vs or more without requiring high temperature processing of more than 400 °C.

The sputtering target according to an embodiment of the present invention is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , and the sputtering target has a ratio z/y 0 or more, less than 0.9, and the ratio x/y is 0 or more and less than 6.5 (when x, y, and z are positive numbers, the composition range of 0<(z/y)<0.9, 0<(x/y)<6.5) The oxide semiconductor is composed of.

According to the sputtering target described above, an active layer for a thin film transistor having an on/off current ratio of 5 digits or more can be formed.

The ratio z/y may be 0 or more and less than 0.5, and the ratio x/y is larger than 0 and smaller than 6.5 (when x, y, and z are positive numbers, 0<(z/y)<0.5) And 0 < (x / y) < 6.5).

Thereby, an active layer for a thin film transistor having an on/off current ratio of 5 digits or more can be formed without requiring a high temperature treatment of more than 300 °C.

The ratio z/y may be 0 or more and less than 0.5, and the ratio x/y is larger than 0.3 and smaller than 2.6 (when x, y, and z are positive numbers, 0<(z/y)<0.5) And 0.3 < (x / y) < 2.6).

Thereby, it is not necessary to perform high-temperature processing of more than 300 ° C, and it is possible to form an active layer for a thin film transistor having an opening/closing current ratio of 5 digits or more and a mobility of 1.0 cm ² /Vs or more.

The ratio z/y may be 0 or more and less than 0.9, and the ratio x/y is 0 or more and less than 2.6, and the ratio y (x+y+z) is less than 0.8. (When x, y, and z are positive numbers, 0 < (z / y) < 0.9, 0 < (x / y) < 2.6 and (y / x + y + z) < 0.8).

Thereby, it is possible to form an active layer for a thin film transistor having an opening/closing current ratio of 5 digits or more and a mobility of 1.0 cm ² /Vs or more by not requiring high temperature treatment of more than 400 ° C.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Fig. 1 is a schematic cross-sectional view showing the configuration of a transistor according to an embodiment of the present invention. In the present embodiment, a so-called bottom gate type electric field effect type transistor will be described as an example.

The transistor 1 of the present embodiment has a gate electrode 11, an active layer 15, a gate insulating film 14, a source electrode 17S, and a drain electrode 17D.

The gate electrode 11 is composed of a conductive film formed on the surface of the substrate 10. Typically, substrate 10 is a transparent glass substrate. Typically, the gate electrode 11 is composed of a metal single layer film of a molybdenum (Mo), chromium (Cr), aluminum (Al), copper (Cu) or the like, or a metal multilayer film, and is formed, for example, by a sputtering method. In the present embodiment, the gate electrode 11 is made of copper. The thickness of the gate electrode 11 is not particularly limited, for example, 300 nm.

The active layer 15 functions as a channel layer of the transistor 1. The film thickness of the active layer 15 is, for example, 50 nm to 200 nm. The active layer 15 is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , and has a ratio z/y of 0 or more and less than 9, and the ratio x/y is 0 or more and less than The composition of 6.5.

The active layer 15 can be formed by forming a film using a sputtering target having the above composition range and then heat-treating (annealing) at a predetermined temperature, as will be described later. By sputtering the target in a non-oxidizing environment, it is possible to form a target and a target An oxide semiconductor layer constituting the same or substantially the same composition. By annealing the semiconductor layer, the structure of the semiconductor layer can be relaxed, and for example, an active layer exhibiting an on/off current ratio of 5 digits or more can be formed.

A gate insulating film 14 is formed between the gate electrode 11 and the active layer 15. The gate insulating film 14 is made of a tantalum oxide film (SiOx) or a tantalum nitride film (SiNx). However, the gate insulating film 14 is not limited thereto, and can be formed using various electrical insulating films such as a metal oxide film. The film formation method is not particularly limited, and may be a CVD method, a sputtering method, a vapor deposition method, or the like. The film thickness of the gate insulating film 14 is not particularly limited, and may be, for example, 200 nm to 400 nm.

The source electrode 17S and the drain electrode 17D are formed apart from each other on the active layer 15. The source electrode 17S and the drain electrode 17D are made of, for example, a metal single film of aluminum, molybdenum, copper, titanium, or the like, or a multilayer film of the metals. As will be described later, the source electrode 17S and the drain electrode 17D can be simultaneously formed by patterning a metal film. The thickness of the metal film is, for example, 100 nm to 500 nm.

On the active layer 15, a stop layer 16 is formed. The stop layer 16 is provided to protect the active layer 15 from being affected by the etchant when the source electrode 17S and the drain electrode 17D are patterned. The stop layer 16 may be composed of, for example, a tantalum oxide film, a tantalum nitride film, or the like.

The source electrode 17S and the drain electrode 17D are covered by the protective film 19. The protective film 19 is made of, for example, an electrically insulating material such as a tantalum nitride film. The protective film 19 is provided to isolate the element portion including the active layer 15 from the outside air. The protective film 19 is provided with an interlayer connection hole at an appropriate position for connecting the source electrode 17S and the drain electrode 17D to the wiring layer 21. The wiring layer 21 connects the transistor 1 to a peripheral circuit not shown in the drawing, and is composed of a metal film of aluminum, copper or the like.

Next, a method of manufacturing the transistor 1 of the present embodiment configured as above will be described. 2 and 3 are cross-sectional views showing important parts of respective steps of the method of manufacturing the transistor 1.

First, as shown in FIG. 2(A), a gate electrode 11 is formed on one surface of the substrate 10. The gate electrode 11 is formed by patterning a gate electrode film formed on the surface of the substrate 10 into a predetermined shape.

Subsequently, as shown in FIG. 2(B), a gate insulating film 14 is formed on the surface of the substrate 10 so as to cover the gate electrode 11. The thickness of the gate insulating film 14 is, for example, 200 nm to 500 nm.

Then, as shown in FIG. 2(C), a film having an In-Ga-Zn-O composition (hereinafter simply referred to as "IGZO film") 15F is formed on the gate insulating film 14.

The IGZO film 15F is formed by a sputtering method. As a sputtering target, it can be represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} (x, y, and z are integers), and the ratio z/y is 0 or more. A sintered body of an oxide semiconductor having a composition ratio of less than 0.9 and a ratio x/y of 0 or more and less than 6.5. The IGZO film 15F is formed by sputtering a target in a non-oxidizing environment.

The sputtering target may be composed of a sintered body obtained by mixing raw material powders of the respective components of In ₂ O ₃ , Ga ₂ O ₃ and ZnO at the above composition ratio. Alternatively, a sintered body of each of the above components may be used. At this time, an In-Ga-Zn-O-based oxide semiconductor film can be formed by sputtering the three-dimensional target simultaneously in the sputtering chamber. At this time, the composition ratio of the oxide semiconductor film can be adjusted by changing the sputtering conditions or the discharge conditions of the respective targets.

The oxide semiconductor has a significant change in electrical conductivity depending on the amount of oxygen contained. Conventionally, when an oxide semiconductor film is formed by a sputtering method, a reactive sputtering method is used while using a target of In:Ga:Zn=1:1:1. This reactive sputtering method uses oxygen as a reactive gas. In this method, the degree of oxidation of the formed film can be controlled by adjusting the flow rate of oxygen introduced into the sputtering process chamber. However, in this method, it is necessary to uniformly introduce oxygen into the inner surface of the substrate, and it is difficult to achieve uniformization of the film quality as the substrate is enlarged.

Therefore, in the present embodiment, the target material can be sputtered without introducing oxygen into the sputtering processing chamber, whereby an oxide semiconductor film having high film uniformity can be formed. Further, by setting the composition range of the target as described above, it is possible to form a sufficient active layer without causing oxygen deficiency in the formed oxide semiconductor film, and to visualize the target transistor characteristics.

Further, the sputtering method of the present embodiment means that the oxygen is not actively introduced into the sputtering processing chamber, that is, the sputtering film is formed. Therefore, the film formation treatment in the coexistence of oxygen which is inevitably left in the treatment chamber is included in the sputtering method.

According to the present embodiment, it is possible to form an oxide semiconductor layer having a uniform in-plane, and it is also possible to easily respond to an increase in size of the substrate (substrate 10). Further, the sputter film formed in the above environment has a composition which is the same as or substantially the same as the composition of the target. As described above, by sputtering an oxide semiconductor layer formed by sputtering a target having a predetermined composition ratio, it is impossible to directly obtain predetermined transistor characteristics. Therefore, by annealing (heat treatment) the film-formed oxide semiconductor layer in the above temperature range, the structure of the oxide semiconductor layer is relaxed, and the desired transistor characteristics can be exhibited.

The discharge method of the sputtering may be any of DC discharge, AC discharge, and RF discharge. Further, a magnetron discharge method in which a permanent magnet is disposed on the back side of the target may be employed. The IGZO film 15F can be formed by heating the substrate 10 to a predetermined temperature, or can be formed in a non-heated state.

Subsequently, as shown in FIG. 2(D), a stop layer is formed on the IGZO film 15F. 16. The stop layer 16 functions as an etching protective layer, and the step of patterning the metal film constituting the source electrode and the drain electrode, which will be described later, and the unnecessary region of etching and removing the IGZO film 15F, protect the channel region of the IGZO film from being avoided. It is affected by the etchant.

The stop layer 16 is composed of, for example, a tantalum nitride film. The stop layer 16 is formed by patterning a tantalum nitride film formed on the IGZO film 15F into a predetermined shape. The film thickness of the stop layer 16 is not particularly limited, and is, for example, 30 nm to 300 nm.

Subsequently, as shown in FIG. 2(E), the metal film 17F is formed to cover the IGZO film 15F and the stop layer 16. Typically, the metal film 17F is composed of a metal single layer film of molybdenum or chromium, aluminum, copper, or the like, or a metal multilayer film, and is formed, for example, by a sputtering method. The thickness of the metal film 17F is not particularly limited, and is, for example, 100 nm to 500 nm.

Subsequently, as shown in FIGS. 3(A) and (B), the metal film 17F is patterned. The patterning step of the metal film 17F has a step of forming the photoresist mask 18 (Fig. 3(A)) and an etching step of the metal film 17F (Fig. 3(B)). The photoresist mask 18 has a mask pattern that opens the region directly above the stop layer 16 and the peripheral region of the respective transistors. After the photoresist mask 18 is formed, the metal film 17F is etched by a wet etching method. Thereby, the metal film 17F is separated into the source electrode 17S and the drain electrode 17D which are electrically connected to the active layer 15, respectively.

In the step of forming the source electrode 17S and the drain electrode 17D, the stop layer 16 functions as an etch stop layer of the metal film 17F. That is, the stop layer 16 has a function of protecting the IGZO film 15F from being affected by an etchant (for example, phosphoric acid) to the metal film 17F. The stop layer 16 is formed to cover a region (hereinafter referred to as a "channel region") between the source electrode 17S and the drain electrode 17D of the IGZO film 15F. Therefore, IGZO film 15F The channel region is not affected by the etching step of the metal film 17F.

Subsequently, as shown in FIG. 3(B), the IGZO film 15F is etched by using the photoresist mask 18 as a mask. The etching method is not particularly limited, and may be a wet etching method or a dry etching method. By the etching step of the IGZO film 15F, the IGZO film 15F is isolated in the element unit, and the active layer 15 composed of the IGZO film 15F is formed.

At this time, the function of the stop layer 16 serves as an etching protection film of the IGZO film 15F located at the position of the channel region. That is, the stop layer 16 has a channel region directly under the protective stop layer 16 from being affected by an etchant (for example, oxalic acid) from the IGZO film 15F. Thereby, the channel region of the active layer 15 is not affected by the etching step of the IGZO film 15F.

After patterning of the IGZO film 15F, the photoresist mask 18 is removed from the source electrode 17S and the drain electrode 17D by ashing.

Subsequently, as shown in FIG. 3(C), a protective film is formed on the surface of the substrate 10 so as to cover the source electrode 17S, the drain electrode 17D, the stop layer 16, the active layer 15, and the gate insulating film 14 (Passivation). Membrane) 19.

The protective layer 19 isolates the transistor element containing the active layer 15 from external gases to ensure specified electrical and material properties. The protective film 19 is typically composed of an oxide film or a nitride film of a tantalum oxide film (SiO ₂ ), a tantalum nitride film (SiNx), or the like, and is formed, for example, by a CVD method or a sputtering method. The thickness of the protective film 19 is not particularly limited, and is, for example, 200 nm to 500 nm.

Subsequently, as shown in FIG. 3(C), a contact hole 19a that connects the source/drain electrodes is formed in the protective film 19. This step has a step of forming a photoresist mask on the protective film 19, an etching step of etching the protective film 19 exposed from the opening of the photoresist mask, and a step of removing the photoresist mask.

The contact hole 19a is formed by a dry etching method, but a wet etching method may also be employed. Further, although not shown, a contact hole connected to the source electrode 17S can be formed in the same position at any position.

Subsequently, as shown in FIG. 3(D), the wiring layer 21 contacting the source/drain electrodes is formed through the contact hole 19a. This step has the steps of: forming the wiring layer 21; forming a photoresist mask on the wiring layer 21; etching the wiring layer 21 not covered by the photoresist mask; and removing the photoresist mask.

Typically, the wiring layer 21 is formed of an ITO film or an IZO film, and is formed, for example, by a sputtering method or a CVD method. The etching of the wiring layer 21 is performed by a wet etching method, but is not limited thereto, and a dry etching method may also be employed.

The transistor 1 after forming the wiring layer 21 shown in FIG. 3(D) is followed by an annealing step (heat treatment) for the purpose of structural relaxation of the active layer 15. Thereby, the transistor characteristics of the active layer 15 can be improved. Further, the annealing step may be performed immediately after the active layer 15 is formed (for example, before the formation of the stop layer 16).

The annealing step is carried out in the atmosphere at a temperature of 200 ° C or higher and 400 ° C or lower. Thereby, the transistor 1 having an on/off current ratio of 5 digits or more can be manufactured. When the annealing temperature is less than 200 ° C, the structural relaxation effect of the active layer 15 cannot be promoted, and it is difficult to ensure an on/off current ratio of 5 digits or more. Further, when the annealing temperature is more than 400 ° C, there are cases where material limitations are imposed on the substrate 10 or various functional films formed on the substrate 10 from the viewpoint of heat resistance.

The transistor 1 of the present embodiment configured as described above is applied with a constant forward voltage (source-drain voltage: Vds) between the source electrode 17S and the drain electrode 17D. In this state, a gate voltage (Vgs) of a threshold voltage (Vth) or more is applied between the gate electrode 11 and the source electrode 17S in the active layer. In 15, a carrier (electrons, holes) is generated, and a current (source-drain current: Ids) is generated between the source and the drain by the forward voltage between the source and the drain. The larger the gate voltage, the larger the source-drain current becomes.

The source-drain current at this time is also referred to as an on-state current, and the higher the mobility of the active layer 15, the larger the current value can be obtained. In the present embodiment, since the active layer 15 is composed of an oxide semiconductor, the mobility is higher than that of the active layer composed of amorphous germanium. Therefore, according to the present embodiment, the field effect transistor 1 having a high on current can be obtained.

On the other hand, when the voltage applied to the gate electrode 11 is OFF (0), the current generated between the source and the drain is almost zero. The source-drain current at this time is also referred to as an off-state current, which is determined by the resistance value of the active layer 15 and the source-drain voltage. The smaller the off current value is, the larger the ratio of the on current to the off current value (on-off current ratio) is, and good characteristics as a transistor can be obtained.

In the transistor structure shown in Fig. 1, the inventors measured the transistor characteristics (on/off current ratio characteristics) of various samples produced by different compositions of the active layers.

4(A) and (B) show an IGZO film obtained by sputtering a film having a composition ratio of In:Ga:Zn=1:1:1 to an In-Ga-Zn-O-based target. One of the experimental results of the transistor characteristics. 4(A) shows the transistor characteristics of the IGZO film immediately after film formation, and FIG. 4(B) shows the transistor characteristics of the IGZO film after annealing at 400 ° C after film formation. The sputtering conditions were a discharge power (RF) of 80 W, an argon partial pressure of 0.8 Pa, and an argon flow rate of 100 sccm. In the figure, the results of the experiment show that the IGZO film (sample 1) formed by the film having a partial pressure of oxygen of 0.00 Pa is formed, and the film is formed under the condition of an oxygen partial pressure of 0.15 Pa. The experimental results of the IGZO film (sample 2).

As shown in FIG. 4(A), the value of the source-drain current (Ids) of the sample 1 was larger than that of the sample 2 immediately after the film formation. This is because the sample 1 is formed in a non-oxidizing environment, and the oxidation degree is low and the conductivity of the active layer is higher than that of the sample 2. Further, each sample could not exhibit on/off current characteristics and could not be directly used as a transistor.

Therefore, it was found that the on/off current characteristics as shown in Fig. 4(B) can be exhibited by annealing the samples 1 and 2 as shown in Fig. 4(A) at 400 °C. The structure relaxation of the IGZO film can be promoted by the annealing treatment. Further, compared with the sample 1, it was confirmed that the test 様 2 system showed a high on/off current ratio. As is clear from the results of FIG. 4(B), when an IGZO target having a composition ratio of 1:1:1 is used, it is possible to manufacture a transistor excellent in on/off current ratio characteristics by sputtering in the coexistence of oxygen. .

On the other hand, an example of the change in characteristics caused by the difference in the composition ratio of the IGZO film formed in a non-oxidizing environment is shown in Figs. 5(A) and (B). In this example, when an In ₂ O ₃ target, a Ga ₂ O ₃ target, and a ZnO target are each placed in a sputtering chamber and these are simultaneously sputtered, an IGZO film having a predetermined composition ratio can be obtained. To control the discharge power of each target.

Fig. 5(A) shows the transistor characteristics of the IGZO film immediately after film formation. Fig. 5(B) shows the crystal characteristics of the IGZO film after annealing at 400 °C after film formation. In the figure, ◆ shows the experimental results of an IGZO film (sample 3) of In/Ga/Zn=35/33/32 at% (discharge power: 120/120/120 W), and the system shows In/Ga/Zn=28. Experimental results of IGZO film (sample 4) at /57/15 at% (discharge power: 60/120/40 W). The sputtering environment was an argon partial pressure of 0.8 Pa (flow rate: 100 sccm) and an oxygen partial pressure of 0.00 Pa.

As shown in Fig. 5(A), it was impossible to determine effective transistor characteristics in any of the samples immediately after film formation. On the other hand, as shown in Fig. 5(B), after annealing at 400 °C, any sample shows a clear difference between the on-current value and the off-current value, but the difference in the characteristics of sample 3 and sample 4 is particularly remarkable. . Regarding sample 4, the on/off current ratio was 5 digits or more, the mobility was 3.76 cm ² /V‧s, and the threshold voltage (Vth) was 1.66V.

Compared with Sample 3 in which the composition ratio of In/Ga/Zn is approximately 1:1:1, Sample 4 has a high content of Ga. That is, it was confirmed that by adding Ga more than other components, effective transistor characteristics can be exhibited even in a non-oxidizing environment.

Therefore, the inventors of the present invention produced a transistor of the structure shown in FIG. 1 based on a plurality of types of IGZO films in which the composition ratio (component ratio) of the target was different and which was sputter-deposited in a non-oxidizing environment, and evaluated. These transistor characteristics. In the evaluation, the on/off current ratio (Ion/Ioff) and the mobility were measured for the samples obtained by annealing the IGZO film at 300 ° C and 400 ° C.

As a result of the measurement, the composition range in which the on/off current ratio of five or more digits can be obtained at the annealing temperature of 400 ° C is indicated by hatching in the state diagram of FIG. 6 . Fig. 6 is a three-dimensional state diagram of InO _1.5 -GaO _1.5 -ZnO. In Fig. 6, when the boundary line of the area indicated by the hatching is a solid line, the boundary line is included in the above composition range, and when the boundary line is a broken line, the boundary line is not included in the above composition range. The meaning of the line type of the boundary line is the same in Figures 7-9.

When the composition of the IGZO film is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , the hatched region R1 of FIG. 6 shows that the ratio z/y is 0 or more and less than 0.9, and The ratio x/y is a range of 0 or more and less than 6.5. The IGZO film having the composition range of the region R1 can be formed into a transistor having an on/off current ratio of 5 digits or more by applying an annealing treatment at 400 °C.

Here, even when the In content is 0 (z = 0) and the Zn content is 0 (x = 0), an on/off current ratio of 5 or more digits can be obtained. Test included in area R1 An example of the composition (C1 to C5) is as follows.

Sample C1=In:Ga:Zn(z:y:x)=0:100:0

Sample C2 = In: Ga: Zn = 25.5: 34.7: 39.8

Sample C3 = In: Ga: Zn = 8.8: 29.2: 62.0

Sample C4 = In: Ga: Zn = 13.1: 70.3: 16.6

Sample C5=In:Ga:Zn=0:80:20

When the ratio z/y is 0.9 or more, the Ga ₂ O ₃ component is insufficient, and it is difficult to obtain an on/off current ratio which is operable as a transistor. Further, when the ratio x/y is 6.5 or more, the ZnO component is excessive, and it is difficult to obtain an on/off current ratio which is operable as a transistor.

Fig. 7 is a three-dimensional state diagram showing InO _1.5 -GaO _1.5 -ZnO having a composition range R2 of an on/off current ratio of 5 or more digits at an annealing temperature of 300 °C. When the composition of the IGZO film is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , the hatched region region R2 of FIG. 7 shows that the ratio z/y is 0 or more and less than 0.5. And the ratio x/y is a range greater than 0 and less than 6.5. The IGZO film having the composition range of the region R2 can be formed into a transistor having an on/off current ratio of 5 digits or more by performing annealing treatment at 300 °C. Examples of the samples corresponding to the region R2 include the samples C1, C3, C4, and C5 among the above C1 to C5.

Moreover, regarding the sample C5, it was confirmed that the on/off current ratio of five or more digits can be obtained by the annealing treatment at 200 °C.

Fig. 8 is a three-dimensional state diagram showing InO _1.5 -GaO _1.5 -ZnO in a composition range R3 in which an on/off current ratio of 5 digits or more and a mobility of 1 cm ² /V ‧ s or more are obtained at an annealing temperature of 300 °C. When the composition of the IGZO film is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , the hatching region R3 of FIG. 8 shows that the ratio z/y is 0 or more and less than 0.5, and The ratio x/y is in the range of more than 0.3 and less than 2.6. The IGZO film having the composition range of the region R3 can be formed into a transistor having an on/off current ratio of 5 digits or more and a mobility of 1 cm ² /V‧s or more by performing annealing treatment at 300 °C. As a sample corresponding to the region R3, a sample C3 is mentioned among the above C1 to C5.

Fig. 9 is a three-dimensional state diagram showing InO _1.5 -GaO _1.5 -ZnO in a composition range R4 in which an on/off current ratio of 5 digits or more and an mobility of 1 cm ² /V ‧ s or more are obtained at an annealing temperature of 400 °C. When the composition of the IGZO film is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , the hatched region R4 of FIG. 9 shows that the ratio z/y is 0 or more and less than 0.9, and The ratio x/y is 0 or more, less than 2.6, and the ratio y/(x+y+z) is a range of less than 0.8. The IGZO film having the composition range of the region R4 can be formed into a transistor having an on/off current ratio of 5 digits or more and a mobility of 1 cm ² /V‧s or more by performing annealing treatment at 400 °C. Examples of the samples corresponding to the region R4 include samples C2, C3, and C4 among the above C1 to C5.

As described above, according to the present embodiment, by setting the composition range of the target as described above, it is possible to manufacture a thin film transistor having an on/off current ratio of 5 digits or more without introducing oxygen into the sputtering chamber.

Further, since it is not necessary to introduce oxygen into the sputtering chamber, a transistor having predetermined crystal characteristics can be produced. Therefore, the film quality uniformity in the surface of the substrate can be improved, and the substrate can be easily increased in size.

The embodiment of the present invention has been described above, but the present invention is not limited thereto, and various modifications can be made based on the technical idea of the present invention.

For example, in the above embodiment, a so-called bottom gate type (reverse stack type) transistor is described as an example, but the present invention can also be applied to a top gate type (stack type) transistor.

Moreover, the above transistor 1 can be used as a liquid crystal display or organic A TFT for an active matrix display panel such as an EL display. Further, the above-described transistor 1 can use a transistor element as various semiconductor devices or electronic devices.

1‧‧‧Optoelectronics

10‧‧‧Substrate

11‧‧‧ gate electrode

14‧‧‧Gate insulation film

15‧‧‧Active layer

15F‧‧‧IGZO film

16‧‧‧stop layer

17S‧‧‧ source electrode

17D‧‧‧汲electrode

17F‧‧‧Metal film

18‧‧‧Light-shielding mask

19‧‧‧Protective film

19a‧‧‧Contact hole

21‧‧‧Wiring layer

R1, R2, R3‧‧‧ composition range

Fig. 1 is a schematic cross-sectional view showing the configuration of a transistor according to an embodiment of the present invention.

Fig. 2 is a cross-sectional view showing the steps of the method for manufacturing the above transistor.

Fig. 3 is a cross-sectional view showing the steps of the method for manufacturing the above transistor.

4 is an experimental result showing the electrical characteristics of an IGZO film formed by sputtering in an oxidizing environment and an IGZO film formed by sputtering in a non-oxidizing environment, and shows (A) immediately after film formation. (B) Data after annealing treatment.

Fig. 5 is a graph showing experimental results of electrical characteristics of an IGZO film obtained by sputtering a target having a different composition ratio, and shows (A) data after annealing (B) immediately after film formation.

Fig. 6 is a three-dimensional state diagram showing InO _1.5 -GaO _1.5 -ZnO having a composition range of an IGZO film (or a target) having an on/off current ratio of 5 or more digits at 400 °C.

Fig. 7 is a three-dimensional state diagram showing InO _1.5 -GaO _1.5 -ZnO in a composition range in which an IGZO film (or a target) having an on/off current ratio of 5 or more digits is obtained by annealing at 300 °C.

FIG 8 lines showed at 300 deg.] C anneal can be obtained more than 5 digits of the on / off current ratio and 1cm ² / V‧s IGZO film in mobility (or target) of the composition range of the InO _{1.5 -GaO 1.5} - Three-dimensional system state diagram of ZnO.

Shown in FIG. 9 based annealing above 400 deg.] C or more can be obtained 5-digit on / off current ratio and 1cm ² / V‧s IGZO film in mobility (or target) of the composition range of the InO _{1.5 -GaO 1.5} - Three-dimensional system state diagram of ZnO.

1‧‧‧Optoelectronics

10‧‧‧Substrate

11‧‧‧ gate electrode

14‧‧‧Gate insulation film

15‧‧‧Active layer

16‧‧‧stop layer

17S‧‧‧ source electrode

17D‧‧‧汲electrode

19‧‧‧Protective film

21‧‧‧Wiring layer

Claims (3)

A method for manufacturing a transistor, wherein the on/off current ratio of the transistor is 5 digits or more and the mobility is 1 cm ² /V ‧ s or more, and the transistor is manufactured by sputtering in a non-oxidizing environment An oxide semiconductor layer having a composition range of Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} is formed by a target made of an oxide semiconductor. Further, the ratio z/y is 0 or more and less than 0.9, and the ratio x/y is 0 or more and less than 2.6, and the ratio y/(x+y+z) is a composition range of less than 0.8; at 200 ° C or higher, 400 ° C The oxide semiconductor layer is heat-treated at the following temperature. A transistor having an on/off current ratio of 5 or more digits and a mobility of 1 cm ² /V ‧ s or more, the electro-crystalline system comprising: a gate electrode; an active layer composed of an oxide semiconductor; The oxide semiconductor is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} and has a ratio z/y of 0 or more and less than 0.9, and the ratio x/y is 0 or more. a composition range of less than 2.6, and a ratio y / (x + y + z) of less than 0.8; a gate insulating film formed between the gate electrode and the active layer; and a source electrode and a drain electrode, and the foregoing The active layer is electrically connected. A sputtering target, which is represented by the general formula Zn _x Ga _y In _z O _{(x+3y/2+3z/2)} , and the sputtering target has a ratio z/y of 0 or more and less than 0.9, a ratio An oxide semiconductor in which x/y is 0 or more and less than 2.6 and the ratio y/(x+y+z) is a composition range of less than 0.8.