TW201036073A - Method for manufacturing transistor, transistor, and sputtering target - Google Patents

Abstract

Disclosed is a method for manufacturing a transistor, which is capable of achieving desired electrical conduction characteristics of an active layer without introducing oxygen during the film formation. In a method for manufacturing a transistor according to one embodiment of the present invention, an oxide semiconductor layer (an active layer (15)) having the above-mentioned composition range is formed by sputtering a target, which is formed from an oxide semiconductor, in a non-oxidizing atmosphere. The oxide semiconductor has a composition range represented by the following general formula: ZnxGaylnzO(x+3y/2+3z/2) with the ratio z/y being O or greater but less than 0.9 and the ratio x/y being 0 or greater but less than 6.5. The oxide semiconductor layer is subjected to a heat treatment at a temperature of not less than 200 DEG C but not more than 400 DEG C. Consequently, a transistor having an on/off current ratio characteristic of not less than 5 digits can be manufactured.

Description

201036073 VI. Description of the Invention: [Technical Field] The present invention relates to a method for producing a transistor having an oxide layer, a transistor, and a frequency conversion. [Prior Art] 近年来 近年来 In recent years, Active matrix type liquid crystal display The dynamic matrix type liquid crystal display has a pixel for each pixel. The main field effect type thin film transistor (TFT). As the switching element, as the thin film transistor, an active layer polycrystalline silicon-type thin film transistor is known; and an active layer is a tantalum-type thin germanium crystal composed of a non-曰 = vermiculite. The amorphous yttrium formed by the impotence and the 薄膜 曰曰 夕 薄膜 薄膜 薄膜 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为 因为The advantage of uniform film formation. The substrate of the product is amorphous. The 1:: layer is: the actual [: body (electron, hole) mobility ratio film. For example, in the patent 0 document, the development of a transparent amorphous oxide thin electric field effect transistor Γ, a number) as the active layer of the lasing laser environment cap from the pulse in the oxygen ring splash shovel by Ιη1 The sintered body of the conductive oxide thin film 1 is formed of a dry material to form a conductive property of the =::r:rr layer, and a partial pressure of the material is formed to form oxygen having a target conductivity of ===film 3 [Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-165529 (paragraph [〇〇57]) Patent Document 2: JP-A-2000-44236 (paragraph [0034]) However, by film formation The method of controlling the oxygen content of the film by the partial pressure of oxygen 'the oxygen concentration in the substrate © must be uniformized. Therefore, as the substrate is made larger in area, it is difficult to supply uniform oxygen to the surface of the substrate, so that the film quality becomes difficult, and there is a problem that the substrate cannot be enlarged. SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a method for producing a transistor, a transistor, and a material for which a conductive property of a target active layer can be obtained without introducing oxygen at the time of film formation. In order to achieve the above object, the method for producing a transistor of the present invention comprises forming an oxide semiconductor layer having the following composition range by a material of a non-oxidizing Wei towel mixed with an oxide semiconductor. The front material + conductor-like znxGayInAx+3y/2(10)) shirt has a ratio z/y of 0 or more and less than 〇.9, and the ratio x/y is 〇 or more and less than the composition range. The above-mentioned oxide semiconductor layer is used. c or more "

The following Wen Tangzhen is imaginary. L Gate Insulation The transistor of the present invention includes a gate electrode, an active layer film, a source electrode, and a electrodeless electrode. The 乂Wei active layer is represented by the general formula ZnxGayInz〇(4), and the active layer has an oxide semiconductor having a ratio z/y of 0 or more and less than 〇9, and a composition range of 〇 or more and less than 6.5. Composition. The gate insulation between 4/24 and 201036073 is difficult to form on the gate electrode and the active layer. The source electrode and the drain electrode are electrically connected to the active layer. The sputtering target of the present invention is of the formula ZnxGa In. In the above, the above-described oxide semiconductor having a ratio z/y of G and a composition of 0 or more and less than 6.5 is a method of manufacturing a transistor of the present embodiment. An oxide semiconductor layer having the above composition range is formed by a surface of an oxide semiconductor in a non-oxidizing environment. The oxide semiconducting ^^^ΖηχΟΜη2〇(^ Π: 匕 rate z/y is 〇 or more and less than 〇.9 ' and the ratio x/y is smaller than 〇, 6.5 (x, y, and Z are positive numbers, 〇 &lt;(z/y)&lt;0.9 and the composition range. The oxide semiconductor layer is heat-treated at a temperature equal to or higher than the above.) _ The above non-oxidizing environment means that it is not intentionally deliberately in the processing chamber. The emulsified gas of the second oxidizing gas is used as the vacuum gas in the reaction gas (IV), and the noise is not excluded from the oxygen remaining in the processing chamber. According to the upper = inner = the oxygen concentration on the surface of the silk plate is integrated, the surface can be formed. The emulsified semiconductor layer of the buckle can also easily respond to the splash formed by the large-scale fine Hi substrate in the above-described environment, and has a composition similar to that of the transfer 5 or the like. The film-forming oxide semiconductor layer cannot directly obtain a layer and thus promotes structural relaxation of the oxide semiconducting 5/24 201036073 bulk layer by annealing (heat treatment) the formed oxide semiconductor lump X target. A transistor that can be used to make the composition of the target I Above, less than 0.9, and ratio 1 in the above formula b ratio y is 0 ί ^ γγ) &lt;0·9 x 〇y&lt;(^ ° ^6'5^^ fine value and power off to 4 5 = On/off current ratio that can be obtained even if In contains (2 = 〇) and Zn content (X = 〇). When the ratio is 9 or more, '(10) is obtained as an operable opening of the transistor / When the off current is 'x/ya 65 or more, the Zn0 component is excessive, and it is difficult to obtain an on/off current ratio which can be operated as a body. The heat treatment temperature is set to · C or more, 働. (10). Heat treatment temperature X at 200 C When the structure relaxation of the oxide semiconductor layer is not promoted, it is difficult to ensure an on/off current ratio of 5 or more digits. Further, when the heat treatment temperature is longer than the timing, the substrate on which the oxide semiconductor layer is formed or on the substrate is The formation of various mesas may cause a material limitation. The ratio z/y may be 〇 or more and less than 〇5, and the ratio χ/y is larger than 0 and smaller than 6.5 (X). When y and z are positive numbers, 〇&lt;(z/y)&lt;0.5 and 〇&lt;(x/y)&lt;6 5). Thereby, by heat treatment at 300 ° C after film formation, Ability to manufacture open / The transistor having a current-to-current ratio of 5 or more digits may have a ratio Z/y of 〇 or more and less than G 5 , and the ratio x/y is larger than 0.3 and smaller than 2.6 (X, y, and z). When it is a positive number, 〇&lt;(z/y)&lt;0,5 and 〇.3&lt;(x/y)&lt;2 6). Thereby, it can be manufactured by heat treatment at 300 〇C after film formation. The on/off current ratio is 5 digits or more and the mobility is 1〇cm2/Vs or more. The solar cell body is 0 6/24 201036073. The ratio z/y is 0 or more and less than 〇9, and the ratio is _ Larger than 2.6, smaller than 2.6, and the ratio coffee (4) is less than 〇8 (when X, y, and Z are positive numbers, 〇&lt;_&lt;〇.9, 〇&lt;(x/y)&lt;2.6 And (y/x+y+z) &lt;0.8). Thereby, by the heat treatment at 400 t: after film formation, it is possible to manufacture a transistor having an on/off current ratio of 5 or more digits and a mobility of 1 〇 cm 2 /Vs or more. A transistor according to an embodiment of the present invention includes a gate electrode, an active layer, a gate insulating film, a source electrode, and a electrodeless electrode. The active layer is represented by the general formula ZnxGayInz〇(4) pure (7), and the active layer has a ratio z/y of 〇 or more and less than 〇9, and the ratio X/y is 〇 or more and less than 6.5. The composition range (when X, y, and z are positive numbers, 〇&lt;(ζ/^)&lt;0.9 and 〇&lt;(x/y)&lt;6.5) is composed of an oxide semiconductor. The seven-way gate is extremely formed between the aforementioned impurity electrode and the aforementioned active layer. The source electrode and the electrodeless electrode are electrically connected to the active layer.依照 According to the above transistor, an on/off current ratio of 5 digits or more can be obtained. ❹ The ratio z/y may be 〇 or more and less than 〇5, and the ratio X/y is larger than 0 and smaller than 6.5 (when X, y, and z are positive numbers, 〇&lt;(z/ y) &lt;〇.5 and 〇&lt;(x/y)&lt;6 5). Thereby, it is possible to obtain an on/off current ratio of 5 or more digits without requiring a high temperature treatment of more than 300. The ratio Z/y may be 〇 or more and less than 〇5, and the ratio x/y is larger than 〇.3 and smaller than 2.6 (when x, y, and z are positive numbers, 〇&lt;(z/ y) &lt; 0.5 and 〇, 3 &lt; (x / y;) &lt; 2.6). Thereby, high-temperature processing of more than 300 °C is not required, and an on/off current ratio of 5 or more digits can be obtained, and the mobility is 1.0 cm 2 /Vs or more. 7/24 201036073 It is also possible to recite that the ratio z/y is 0 or more and less than 〇9, the ratio x/y is 0 or more, less than 2.6, and the ratio y(x+y+z) is smaller than 〇8 ( When x, y, and z are positive numbers, 〇 &lt;(z/y)&lt;〇.9, 〇&lt;(x/y)&lt;2 6 and (y/x+y+z)&lt;0.8). By this, no more than 400 is required. The high-temperature treatment of (:, the on/off current ratio is 5 digits or more and the mobility of i.〇cm2/Vs or more. The sputtering target according to an embodiment of the present invention is composed of the general formula ZnxGayInzO ( x+3y/2+3z/2) indicates that the aforementioned splashing dry material has a ratio z/y of 0 or more and less than 0.9, and the ratio x/y is 〇 or more and less than 6.5 (x, y, and z are positive numbers) When '&lt;(z/y)&lt;〇.9, 〇&lt;(x/y)&lt;6.5) is composed of an oxide semiconductor having a composition range. According to the sputtering target described above, it is possible to form 5 The opening/closing current of the number of digits or more is thinner than the active layer for the transistor. The ratio z/y may be 0 or more and less than 〇.5, and the ratio x/y is larger than 0 and smaller than 6.5. The range (x, y, and z are positive numbers, 〇 &lt;(z/y) &lt;0.5 and 0 &lt;(χ/}〇&lt;6.5). By this, 'high temperature processing of more than 300 〇C is not required, and An active layer for a thin film transistor having an on/off current ratio of 5 or more digits can be formed. The ratio z/y is 0 or more and less than 0.5, and the ratio x/y is larger than 〇.3. a range smaller than 2.6 (when X, y, and z are positive, 〇&lt ;(z/[)&lt;〇.5 and 0.3&lt;(x/y)<2.6). By this, 'high-temperature processing of more than 300 ° C is not required, and an off current ratio of 5 or more digits can be formed and An active layer for a thin film transistor having a mobility of 1.0 cm 2 /V or more. The ratio z/y may be 0 or more and less than 〇.9, and the ratio X/y is 〇 or more, less than 2.6, and a ratio y ( x+y+z) is a range less than 〇8. 8/24 201036073 (When X, y, and Z are positive numbers, 0 &lt;(z/y)&lt;0 9 , 〇&lt;(x/y)&lt;2 6 and (y/x+y+z) &lt;0.8). Thereby, by requiring no high temperature treatment of more than 4 〇〇〇C, it is possible to form an on/off current ratio of 5 digits or more and i 〇 cm 2 Active layer for thin film transistors with mobility above ^ys.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing the structure of a transistor according to an embodiment of the present invention. In the present embodiment, a so-called bottom-type electric field effect type transistor is described as an example. The transistor i of the present embodiment has a gate electrode η, an active layer 15, a gate insulating film 14, a source electrode 17S, and a drain electrode 17D. The gate electrode 11 is composed of a conductive film formed on the surface of the substrate 10. Typically, substrate 10 is a transparent glass substrate. Typically, the closed pole electrode 11 is formed of a metal single layer film of indium (application), chromium (Cr), slag (A1), copper (Cu), or the like, and is formed, for example, by a lining method. In the present embodiment, the gate electrode 11 is composed of a retort. The thick production of the f-dimensional electrode 11 is not particularly limited, and is, for example, 300 nm. In addition, the living layer 15 functions as a channel layer of the transistor. The thickness of the active layer μ scoop is, for example, 5 Q nm to m nm. Active layer 15

ZnxGayInz〇(x+3_/2) represents a composition range in which the ratio z/y is 〇 or more, two or more, and the ratio x/y is 0 or more and less than 6.5. The sturdy layer 15 of the door can be formed by heat treatment (annealing) at a predetermined temperature after forming the film using the above-mentioned composition = recording material: in the non-auditory environment - (4), Qingcheng has an oxide semiconductor layer of the same or substantially the same composition as the leather material 9/24 201036073. By annealing the semiconductor layer, the structure of the semiconductor layer can be promoted, and an active layer exhibiting an on/off current ratio of 5 digits or more can be formed. The gate insulating film 14 is formed by the gate electrode u and the insulating layer of the active layer '5, which is composed of a Weihua film (10) 、), and is not limited thereto, and can also be used for metal oxidation.

An electrically insulating film is formed. The film formation method is not particularly limited, and may be CVD ί Ϊ Ϊ may be a reduced ore method, a steaming method, or the like. The film thickness of the interlayer insulating film 14 is particularly limited, and may be, for example, 2 nm to 4 (nine), and the electrode (7) and the electrode (5) are separated from each other on the active layer 15. The source electrode 17S and the drain electrode can be formed, for example, by a metal single film such as copper, titanium, or the like, or a multilayer film of the metal, and the source electrode 17S and the drain electrode 17 are formed at the same time. The thickness of the metal film is in the form of a metal film, and the thickness of the metal group is, for example, 100 nm to the inner layer of the active layer I5, and the patterning of the stop layer 16 electrode 17S and the electrodeless electrode 17D is formed.曰6 series in the source to avoid the 刻 刻 刻 ' ' 叫 活性 活性 活性 活性 活性 活性 活性 活性 活性 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕The protective film 19 is provided in a suitable roll: the crotch portion is separated from the outside air, and the transistor is connected to the solid two, and the wire layer 21 is connected. The wiring layer 21 is a metallurgy m of copper or the like (four), Further, the method of manufacturing the transistor 1 of the present embodiment, which is composed of the above-mentioned structure, is shown in Fig. 2 and Fig. 3 is a cross-sectional view showing an important part of the potential of the transistor. The ιϋ2=2(A) of each step of the method of the Japanese body 1 is a gate electrode formed on the surface of the substrate 1G... Jade 11 The gate electrode film formed on the substrate 10 is formed into a predetermined shape. The gate electrode 2 (8) is formed on the surface of the substrate 1G to form a gate insulating film by covering the interlayer ❹ 〇°.闸 The gate insulating film 14 is, for example, 2 nanometers to 5 nanometers. The degree of the scales 14 is subsequently 'as shown in Fig. 2(c), Ιη·η·〇 on the gate insulating film A film composed of (hereinafter referred to as "de-zero film"). There is a use of storage formed by Gu. For those who make money, they can work as a sintered body of an oxide semiconductor having a composition range of less than 0.9 and a ratio of x/y = less than 6.5. The IGZO film 15F is formed by sputtering a remaining material in a chemical environment. The above-mentioned splashing material can be composed of a sintered body obtained by mixing raw material powders of the respective components of the above-mentioned sag and ΖηΟ in the above composition ratio. A sintered body of each component. At this time, an oxide semiconductor film can be formed by treating the ternary (four) at the same time as the inside of the treatment. At this time, the condition or discharge condition of each dry material is made. In contrast, the oxide semiconductor film of the oxide semiconductor film can be adjusted in accordance with the amount of oxygen contained, and the conductive property is greatly affected. When the oxide semiconductor film is formed by the money method, In. Ga. Zn 1 is used. · 1 . Reactive sputtering method while using the target of '丨 ' ' 11 / 24 201036073 This reactive sputtering method uses oxygen as a reactive gas. In this method, by adjusting the oxygen flow introduced into the sputtering processing chamber , can control the degree of oxidation of the formed film. ^ Yes In the case of the financial method, it is necessary to introduce oxygen in the base_surface, and it is difficult to achieve uniformity of the film quality as the substrate is enlarged. Therefore, in the present embodiment, the ore is dried by introducing oxygen into the clock processing chamber. The material can be finely formed into an oxide semiconductor film having a high film quality. Further, as described above, the filament s of the tree can prevent the oxygen-deficient film from forming an oxide thin film and form a sufficient active layer. It is revealed by the characteristics of the target transistor. The method of reducing the plating in the present embodiment means that the oxygen is not actively introduced into the sputtering treatment chamber to carry out the impurity. Therefore, the oxygen remaining in the processing chamber does not remain. The film formation process in the coexistence is also included in the enamel, the shame, the smear of the oxide layer, and the size of the substrate (substrate 1 〇) can be easily increased. The fine coating film has the same or substantially the same composition as (4). As described above, by setting a pure ratio of the predetermined composition ratio, the ruthenium layer cannot directly obtain a predetermined transistor characteristic L. Hunting is performed by annealing the oxide semiconductor layer after film formation in the above temperature range (heat Treatment) to promote the oxidation: relaxation, can make it appear the required crystal characteristics. The structure of the bovine conductor layer is loose: = discharge fC discharge, AC discharge, magnetic of the liver release magnet = two = with the back of the wire The side configuration is permanently twisted to the couch-film 15F system. The substrate can be 忉,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The layer 6 is used as the electrode of the etched electrode and the electrode of the ruthenium, and the channel of the film is protected by the step of constituting the source Γ°.

Domains are protected from the effects of money. D, the stop layer 16 is, for example, a ridge nitride film (4). On the membrane 15F, it is a cockroach: hunting,. The film thickness of the stop layer is not particularly limited = 3 m to 300 nm. (7) Ruchuan

After the tunneling, as shown in Fig. 2 (6), the metal film 17F is formed so as to cover the untwisting film and the stop layer 6. Typically, the metal film ‘ ^, _ metal monolayer film or gold ❹ phase is formed, and ^ is formed by splashing. The thickness of gold _ 17F is not limited, for example, 1 〇〇 nanometer ~ 500 nm. Subsequently, as shown in FIGS. 3(A) and (8), the metal film 17F is patterned. The patterning step of the metal film 17F has a step of forming a photoresist mask 图 (Fig. 3(A)) and a step of forming a metal iridium 17F (Fig. 3(B)). The photoresist mask 18 has a mask pattern in which the region immediately above the stop layer 16 and the peripheral region of the respective transistors are opened. After the photoresist scale 18 is formed, the metal film 17F is etched by the wet method. Thereby, the metal film 17F is separated into the source electrode 17S and the drain electrode 17D which are electrically connected to the active layer. / In the step of forming the source electrode 17S and the drain electrode 17D, the stop layer 16 functions as an etch stop layer of the metal film HF. That is, the stop layer 16 has a function of protecting the IGZ0 film 15F from being affected by an etchant (e.g., phosphoric acid) to the metal film ΐ7p. The stop layer 16 is formed so as to cover a region between the source electrode 17S of the IGZO film 15F and the electrodeless electrode UD (hereinafter referred to as "channel region"). Therefore, the channel region of the IGz ruthenium film isf 13/24 201036073 is not affected by the etching step of the metal film 17F. Subsequently, as shown in Fig. 3 (8), the IGZO film 15F is left with the photoresist mask | (1) 乍 as a mask. The fine j method has no restriction limit ^, which can be a wet type engraving method or a dry remnant method. The IGZO film 15F is isolated in the element unit by the remaining step of the IGz ruthenium film 15F, and an active layer 丨5 composed of the 1Gz ruthenium film 15F is formed. At this time, the function of the stop layer 16 serves as a rotten protective film of the IGZO film 15F located at the position of the channel region. The stop layer 16 has a function of protecting the channel region directly below the stop layer 16 from the influence of the smear agent (e.g., oxalic acid) from the heavy film. Thereby, the channel region of the active layer 丨5 does not affect the etching step of the IGZO film 15F. After patterning of the IGZO film 1SF, the photoresist mask 18 is removed from the source electrode 17S and the drain electrode 17D by ashing. Subsequently, as shown in FIG. 3(C), on the surface of the substrate 1 ,, the source (7), the electrodeless electrode 17D, the stop layer 16, the active layer 15, the immersion film, and the ruthenium film 14 are formed to protect. Membrane (Passivation Membrane) 19. The protective layer 19 is a transistor element containing the active layer 15 to avoid the influence of the == body to ensure the specified electrical and material properties. For example, the "type" is composed of a Weihua film (Si〇2), a Weihua film (5) Nx), a film or a nitride film, and is deposited by a CVD method, for example, by a CVD method. The thickness is not particularly limited. For example, 200 to 500 electrodes are as shown in FIG. 3(C), and a step of forming a source dirty mask is formed in the protective film 19. "Shen" is formed on the protective film 19. β 'step from the protective film 19 of the opening of the photoresist mask to the step ' and the step of removing the contact. 14/24 201036073 The contact hole 19a is formed by dry etching, but a wet residual method can also be used. Further, although not shown, a contact hole connected to the source electrode 7S can be formed at an arbitrary position. As shown in Fig. 3(D), the wiring layer 21 contacting the source electrode is formed by contacting the hole group. This step has the steps of: forming a wiring layer 21, forming a photoresist on the squeaking layer 21; etching the wiring layer 21 not covered by the photoresist mask; and removing the silk mask. ❹ 〇 Typically, the wiring layer 21 is composed of a ITO film or an IZO film, and is formed, for example, by a money reduction method or a CVD method. Wiring layer = wet side method 'but not limited to this, dry = engraving can also be used. The electric crystal crucible 1 after forming the wiring layer 21 shown in Fig. 3 (9) is followed by an annealing step (heat treatment) for the purpose of relaxation of the living structure. The crystal characteristics of the active layer 15 are raised. Moreover, the annealing step is also carried out immediately before the active layer 15 is formed (e.g., before the formation of the stop layer 16). ^The social steps are in the atmosphere, winning more than €, 働. The temperature below c is applied. Hunting this, it is possible to manufacture an open annealing temperature of 5 or more digits. At C, it is not possible to promote the active layer 15 = acting 'difficult to be mixed with 5 or more digits of on/off current ratio. Further, when the beauty is reduced to more than 400 C, from the viewpoint of heat resistance, there are material limitations on various functional films formed on the substrate =: The transistor i of the present embodiment having the above configuration is based on the source 17S. Between the electrode and the electrodeless electrode 17D, a certain randomness is applied, in the active layer 15/24 201036073 by the indirect electricity _s between the gate electrode u and the source ==% pure limit voltage _ The carrier generated in 15 (electronic, thunder, and 卩 卩 丄 丄 丄 丄 丄 丄 丄 丄 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 越大 源 源 源 源 源 源 源 源 源 源 源 源 源 源Polar current current), the current of the active layer 15 and the current of the 〇n·state (in this embodiment, the current value is compared with the active layer composed of amorphous germanium) When the voltage applied to the gate of the gate and the gate of the gate is OFF (〇), the current generated between the four poles _^ pole is almost zero. At this time, the source i5^^ is determined. The smaller the off current value, because The ratio of the open current to the off =: ratio (on-off current ratio) is larger. As a transistor, the structure of the private crystal in Fig. 1 is lost. The crystal characteristics (on/off characteristics) of various samples manufactured differently. Fig. 4(A) and (8) show that the composition will have a fast: Ga: Zn = n 1 :: [ ratio h-Ga- Zn-O-based target, one of the experimental results of the electrical aa body of the IGz yttrium film formed by sputtering. Figure 4 (A) shows the transistor characteristics of the IGZO film immediately after film formation, Figure 4 (b) shows the film formation after 4(8). [The crystal characteristics of the IGZO film after annealing. The sputtering conditions are the discharge power (RF) of 80 W. The argon partial pressure is 〇.8pa, and the argon flow rate is i〇〇sccm. Further, in the figure, ♦ shows an experimental result of an IGZ ruthenium film (sample 1) formed by a film having an oxygen partial pressure of 0.0000 Pa, which is shown to form a film under an oxygen partial pressure of 015 Pa. The experimental result of the IGZO film (sample 2) was obtained. 16/24 201036073, as shown in Fig. 4(A), the value of the _ current is larger than that of the sample 2 after the film formation. Because sample 1 is formed in a non-oxygen-formed film, the degree of oxidation is lower than that of sample 2 and the conductivity of the active layer is different. X, each sample cannot show the on/off current characteristics, directly Used as a transistor. ',, ,in

Oh. Therefore, it has been found that the on/off current characteristic shown in Fig. 2 can be expressed by performing the annealing treatment in the sample C as shown in Fig. 4(A). The IGZ〇_structural age can be promoted by annealing treatment. Moreover, the phase #乂4*1 can confirm that the test 2 shows a high on/off current ratio. As is clear from the results of Fig. 4(B), when the IGZO dry material having a fraction ratio of 丨: 丨:i is produced, 'the sputtering with the oxygen can coexist, and the electric current with excellent on/off current ratio characteristics can be manufactured. Crystal. On the other hand, the IGZO film formed in a non-oxidizing environment has a characteristic change in the composition ratio, and the sub-system is as shown in Figs. 5(A) and (9). In this example, each of the target is controlled such that an In2〇3 target, a GkO] target, and a Zn〇 target are placed in a miscellaneous treatment chamber, and the scale is simultaneously mixed, so that an IGZO film having a predetermined composition ratio can be obtained. Discharge power. Fig. 5(A) shows the transistor characteristics of the IGZ ruthenium film immediately after film formation. Fig. 5(B) shows the transistor characteristics of the IGZ ruthenium film after annealing at 4 Å after film formation. In the figure, ♦ is an experimental result showing an IGZO film (sample 3) of In/Ga/Zn=35/33/32 at% (discharge power: 120/120/120 W), which shows In/Ga/Zn=28/ Experimental results of an IGZ diaphragm (sample 4) of 57/15 at% (discharge power: 6 〇 / 12 〇 / 4 〇 w). The sputtering environment is argon partial pressure of 〇 8pa (flow rate is lOOsccm) and oxygen partial pressure of 〇.OOPa. As shown in Fig. 5(A), the effective transistor characteristics could not be confirmed for any of the samples immediately after the film formation. On the other hand, as shown in Fig. 5(B), 4〇〇. 〇 Annealing 17/24 201036073 After treatment, any sample showed a clear difference between the on current value and the off current value. However, the difference in the characteristics of sample 3 and sample 4 was particularly remarkable. There is only water 4, the on/off current ratio is more than 5 digits, and the mobility is 3 76cm2/v·^ The threshold voltage (Vth) is 1.66V. &gt; Compared with the composition ratio of In/Ga/Zn, the ratio of 试样:1:1 is 3, and the pattern of Form 5 = Ga is high. That is, it was confirmed that by adding Ga more than other tools, it is possible to exhibit effective transistor characteristics even in a non-oxidizing environment. In the meantime, the inventors of the present invention manufactured a plurality of IGZ ruthenium films which are formed by sputtering a non-oxidizing environment in a non-oxidizing environment by a composition ratio (component ratio) of dry materials, thereby producing a transistor having the structure shown in FIG. And evaluate these transistor characteristics'. In the evaluation, the on/off current ratio (Ion/Ioff) and the mobility of the IGZO film at 300 ° C and 40 (TC annealed samples were measured. The measurement results were 4 退火 at the annealing temperature. The ratio of the opening/closing current ratio of 5 &lt; or more is shown by hatching in Fig. 6. Fig. 6 is a three-dimensional state diagram of InC^-GaOu-ZnO. In Fig. 6, the hatching When the boundary line of the display area is a solid line, the boundary line is included in the above composition range, and when the boundary line is a dotted line, the boundary line is not included in the above-mentioned package range. The meaning of the line type of the boundary line, The same applies to Fig. 7 to 9. When the composition of the 1GZ tantalum film is represented by the general formula ZnxGayInzO (x+3y/2, the hatching area R1 of Fig. 6 shows a ratio of 〇 or more, less than 0.9, and the ratio x/y. It is a range of 0 or more and less than 6 5. The IGZO film having a composition range of the region ri can be formed into a transistor having an on/off current ratio of 5 digits or more by annealing the coating chamber c. This 'when the In content is 0 (2 = 〇) and the Zn content is 〇 (χ = 〇), the on/off current ratio of 5 or more digits can be obtained. In the region R1 An example (C1 to C5) containing the components of the test 18/24 201036073 is as follows. Sample Cl = In : Ga : Zn (z : y : χ) = 〇: (10): 〇 sample C2 = 1n : Ga : Ζη = 25.5 : 34.7 : 39 8 Sample C3 = In : Ga : Ζ η = 8.8 : 29.2 : 62.0 Sample C4 = in : Ga : Ζη = 13.1 : 70.3 : 16 6 Sample C5 = In : Ga : Ζη=0 : 80 : 20 When the ratio z/y is 0.9 or more, the gamma 3 component is insufficient, and it is difficult to obtain an on/off current ratio which is operable as a transistor. Further, when the ratio x/y is 6° or more, Zn If the bismuth component is excessive, it is difficult to obtain the on/off current ratio which can function as the transistor 5. &gt; ® 7 series age at 3 GG t annealing temperature can be _ 5 digits or more of on/off current ratio composition range R2 In A three-dimensional state diagram of 〇15_Ga〇i 5_Zn〇. When the composition of the IGZO film is expressed by the general formula ZnxGa + _), the hatched region region R2 of Fig. 7 shows that the ratio z/y is 〇 or more and less than 〇. , 5 ' and the ratio x / y is greater than 〇, less than 65. The IGZO film having the composition range of the region R2 is subjected to annealing treatment of 3 ,, which is sufficient to have 5 or more digits. switch For the sample corresponding to the region R2, samples ci, C3, C4, and C5 are listed among the above ci to C5. Further, the sample C5 was confirmed to be 2 Å. The annealing treatment of 匸 can obtain an on/off current ratio of 5 digits or more. Fig. 8 is a three-dimensional state diagram showing hOwGaO^ZnO which is capable of obtaining an on/off current ratio of 5 digits or more and a composition range R3 of mobility of 1 cm 2 /V.s or more at an annealing temperature of 300 °C. When the composition of the IGZ ruthenium film is represented by the general formula ZnxGayInzO (x+3y/2+3z/2), the hatched region R3 of FIG. 8 shows that the ratio z/y is 0 or more and less than 0.5, and the ratio x/y is Greater than 〇3, less than 19/24 201036073 2.6 range. The release film having the composition range of the region R3 can be formed into a transistor having a switching current ratio of 5 digits or more and a mobility of W/V.S or more by performing an annealing treatment of 300 t. As a sample corresponding to the region R3, among the above C1 to C5, the ridge sample C3: and Fig. 9 are shown at 4 (the Xrc annealing temperature can obtain an on/off current ratio of 5 digits or more and lcm2/Vs). The composition range of the above mobility is similar to the three-dimensional state diagram of InOu-GaUnO. When the composition of the release film is expressed by the general formula ZnxGayInz〇(x+3y/2+3z/2), the hatched area R4 of Fig. 9 The ratio z/y is 0 or more and less than 〇.9, and the ratio x/y is 〇 or more ', less than 2·6' and the ratio y/(x+y+z) is smaller than 〇8. The IGZO film of the composition range can be formed into a transistor having an on/off current ratio of 5 or more and a mobility on lem2/Vnx by performing annealing treatment of 40 Å. As a sample corresponding to the suspension region R4, In the above, 'samples C2, C3, and C4 can be cited. The above is only a matter of sorrow, and the composition of the dry material is as described above, so that it is not necessary to introduce oxygen in the miscellaneous treatment chamber. A thin film transistor having an on/off current ratio of more than $ digits. - Again, it is possible to manufacture a crystal having a prescribed transistor characteristic without introducing oxygen into the sputtering chamber. In addition, the film quality uniformity in the surface of the substrate can be increased, and the size of the substrate can be easily increased. The embodiment of the present invention has been described above. However, the present invention is not limited to the technical idea based on the present invention. For example, in the above embodiment, a crystal of a so-called bottom gate type (reverse type) is described as an example, but the present invention can also be applied to a transistor of a gate type (stack type). Further, the above-described transistor 1 can be used as an active matrix type display panel such as a liquid crystal display or an organic 20/24 201036073 EL display. This:: 1 can be used as electricity for various semiconductor devices or electronic devices: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a configuration of a transistor according to an embodiment of the present invention. Fig. 2 is a cross-sectional view showing a step of a method for manufacturing the transistor. Fig. 3 is a view showing a method of manufacturing the above transistor. Fig. 4 shows the electrical characteristics of the IGZ0 film formed by sputtering and forming a film in an oxidizing environment and IGZ0 film formed by sputtering in a non-oxidizing environment. One of the experimental results shows (A) the data after annealing (B) after the film formation. Fig. 5 shows one of the electrical characteristics of the IGZ ruthenium film formed by sputtering a target with different composition ratios. The experimental results show (A) data after annealing (B) after annealing, and Fig. 6 shows that IGZO film can be obtained by annealing at 400 °C to obtain an on/off Q current ratio of 5 or more digits (or Target range

Three-dimensional system state diagram of InOu-GaOu-ZnO. Fig. 7 is a three-dimensional diagram showing the composition range of InO.5_Ga〇i.5-ZnO which is obtained by annealing at 300 ° C to obtain an on/off current ratio of 5 or more digits. Fig. 8 is a view showing the InOu-GaOu-ZnO of an IGZO film (or a target) having an opening/closing current ratio of 5 or more digits and a mobility of 1 cm 2 /V · s or more at 300 ° C. The 3D system state diagram. Figure 9 shows the InO of the IGZO臈 (or the material) of the IGZO臈 (or the material) that is capable of obtaining an on/off current ratio of 5 digits or more and a mobility of 1 cm2/V·s or more at 400 °C. A three-dimensional state diagram of ^-GaO^-ZnO. [Description of main components] I Transistor 10 Substrate II Gate electrode 14 Gate insulating film 15 Active layer 15F IGZO film 0 16 Stop layer 17S Source electrode 17D Dip electrode 17F Metal film 18 Photoresist mask 19 Protective film 19a Contact hole 21 Wiring layer "IU, R2, R3 composition range 22/24

Claims (1)

201036073 VII. The scope of application for patents: L. The manufacturing method of two kinds of transistors is formed on the oxidation/t*r» of the following composition range by building a clock in a measurable environment. Law one" </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The ratio z/y is 〇 or more and less than 〇5, and the ratio x/y is larger than 0 and smaller than 6.5. 3. The method for manufacturing a transistor according to the second aspect of the invention, wherein the ratio z /y is 〇 or more and less than 〇.5, &quot; The aforementioned ratio x/y is larger than 0.3 and smaller than 2.6. 4. ^ Patent application method for manufacturing a transistor according to item i, wherein the ratio z/ y is 〇 or more and less than 〇.9, 八❹ The ratio x/y is 0 or more and less than 2.6, and the ratio y/(x+y+z) is less than 〇8. 5. A transistor having: a pole electrode; and a ratio x/y is a composition range of 〇 or more and less than 6 5; an active layer composed of an object semiconductor, which is obtained by "&+xyYay3z/" 2) indicates that the ratio z/y is 0 or more: an insulating film between the inter-electrode electrode and the active layer; and /, shovel The source electrode and the drain electrode electrically connected to the twin layer. 23/24 201036073. The transistor according to claim 5, wherein the ratio z/y is 0 or more and less than 0.5, the ratio x/ y is larger than 0 and smaller than 6.5. 7. The transistor according to claim 6, wherein the ratio z/y is 0 or more and less than 0.5, and the ratio x/y is larger than 0.3 and larger than 2.6. 8. The transistor according to claim 5, wherein the ratio z/y is 0 or more and less than 0.9, and the ratio x/y is 0 or more and less than 2.6 ' ratio y/(x+y+ z) is less than 0.8. 9. A sputtering target, which is represented by the general formula ZnxGayInzO (x+3y/2+3z/2), and the aforementioned sputtering target has a ratio z/y of 0 or more and less than 0.9. And a sputtering target according to the ninth aspect of the invention, wherein the ratio z/y is 0 or more and less than 0.5 ' The aforementioned ratio x/y is larger than 0 and smaller than 6.5. 11. The sputtering target according to claim 10, wherein the ratio z/y is 0 or more and small. The above-mentioned ratio x/y is larger than 〇·3 and smaller than 2.6. 12. The sputtering target according to claim 9, wherein the ratio z/y is 0 or more and less than 0.9, the foregoing The ratio x/y is 0 or more and less than 2. 6 ' The ratio y / (x + y + z) is less than 0.8.