TWI471915B - Gate structure and method of making the same - Google Patents

Description

Gate structure and manufacturing method thereof

The present invention relates to a gate structure and a method of fabricating the same, and more particularly to a gate structure of a complementary MOS transistor image sensor and a method of fabricating the same.

Charge-coupled devices (CCDs) are optical circuit components commonly used to convert light into electronic signals. They are used in a wide range of applications, including displays, transcription machines, cameras, etc. The CCD has a wide range of functions, but it is still limited by its higher price and size. Therefore, a complementary CMOS image sensor (CIS) has been developed, in which a photodiode and a CCD have similar functions, and are also used to convert light into an electronic signal. Since CIS is fabricated in a conventional semiconductor process, existing semiconductor devices and technologies can be utilized, so production continues to increase.

A typical CIS can be divided into a light sensing area and an element area according to its function, wherein the light sensing area is usually provided with at least one photodiode and a transfer transistor located in the element region. A MOS transistor such as a reset transistor, a source follower transistor, or a select transistor is combined to form a CIS for receiving external light and sensing the intensity of illumination. And transmit the signal to the external connection line.

Traditionally, in the fabrication of the gate sidewalls of the transistor of the image sensor, a sidewall material layer must first be formed. The sidewall material layer not only covers the gate of each transistor, but also covers each photosensitive layer. Polar body. A dry etch, such as plasma etching, is then performed to remove portions of the sidewall sub-material layers to form sidewalls on each of the gate sidewalls. When the sidewall material layer is etched, the sidewall material layer on the upper surface of each gate and the upper surface of each of the photosensitive diodes is almost completely removed by the plasma, so that the exposed surface of the photosensitive diode is bombarded by the plasma, and further The germanium lattice on the surface of the photodiode is destroyed. As a result, the dark current in the photodiode will be unstable and noise will be generated.

In order to prevent the plasma from damaging the photosensitive diode, a photoresist pattern is formed to protect the surface of each photosensitive diode before dry etching the sidewall material layer. However, this method not only requires the preparation of an additional mask but also increases the process steps and reduces the productivity. After the sidewall is completed, the surface of the photodiode remains in the sidewall material layer, leaving the sidewall material layer. It affects the amount of current generated by the photodiode and reduces the sensitivity.

Therefore, the main object of the present invention is to provide a method for fabricating a gate structure, which can effectively avoid damage to the surface of the photodiode when forming the sidewall.

According to a preferred embodiment of the present invention, a method for fabricating a gate structure is provided. First, a gate is formed, and then a first tantalum oxide layer and a tantalum nitride layer are formed. a second ruthenium oxide layer sequentially covers the gate from bottom to top, and then, a dry etch is performed to etch the second ruthenium oxide layer, and finally, a wet etch is performed to etch the tantalum nitride layer and the first ruthenium oxide layer Floor. According to a preferred embodiment of the present invention, the etching liquid used in the wet etching is an RCA cleaning liquid. According to another preferred embodiment of the present invention, the tantalum nitride layer is formed by SINGEN, and the formed tantalum nitride layer is not substantially etched by phosphoric acid.

According to another preferred embodiment of the present invention, another gate structure is provided, including: a gate; and a gate sidewall disposed on a vertical sidewall of the gate, and the gate The pole sidewall includes an ONO stack layer composed of a first tantalum oxide layer, a tantalum nitride layer and a second tantalum oxide layer, and the tantalum nitride layer is formed by using SINGEN, and the formed nitride is formed. The tantalum layer is not substantially etched by phosphoric acid.

The invention is characterized in that a tantalum nitride layer in a tantalum oxide-yttria-yttria (ONO) stacked layer is formed by means of SINGEN, and the focus is that the tantalum nitride layer formed by the method of SINGEN is substantially not phosphated. Etched, but can be etched by the RCA cleaning solution. After the yttria-tantalum nitride-yttria stack layer is formed, a portion of the second ruthenium oxide layer is removed by dry etching, and then wet etching is performed with the RCA cleaning solution while etching the first ruthenium oxide layer and the tantalum nitride layer. The layer and the second layer of tantalum oxide form a gate sidewall.

Please refer to FIGS. 1 to 4, and FIGS. 1 to 4 are schematic views showing a method of fabricating the gate structure of the present invention. Figure 5 is a schematic diagram of a gate structure with defects. Figure 6 is a schematic diagram showing the method of manufacturing the CIS.

Taking a single CIS unit as an example, as shown in FIG. 1, first, a substrate 10 such as a germanium substrate or a semiconductor substrate such as a silicon-on-insulator (SOI), which contains at least one P-type doping, is provided. A well 12 and a shallow trench isolation (STI) structure 14 are formed in the substrate 10. The P-type doping well 12 can be divided into at least one photo sensing area A and at least one element area B. This is well known to those skilled in the art and those of ordinary skill, and will not be described here.

Then, a gate 16 is formed on the element region B. The gate 16 may be formed by forming a dielectric layer (not shown) on the surface of the substrate 10. The dielectric layer may be formed by thermal oxidation. Oxide compounds, or various dielectric materials formed by other deposition processes. A conductive layer (not shown) is then formed on the dielectric layer, and the conductive layer may comprise a polysilicon layer, a metal halide, a metal, an alloy, or various conductive materials formed by other deposition processes. Then, a yellow light etch process is performed on the conductive layer and the dielectric layer to form a gate 16 on the substrate 10. Then, as shown in FIG. 1, a sidewall sub-material layer 18 is formed on the surface of the substrate 10 and the gate 16. The sidewall material layer 18 of the present invention is a tantalum oxide-tantalum nitride-yttria (ONO) stacked layer formed by, for example, forming a first tantalum oxide layer 20 on the surface of the substrate 10 and the gate 16. A tantalum nitride layer 22 and a second tantalum oxide layer 24 sequentially cover the surface of the substrate 10 and the gate 16 from bottom to top. Wherein, the first ruthenium oxide layer 20 can be formed by deposition and has a thickness of about 100 angstroms. The second hafnium oxide layer 24 can also be formed using deposition. It is to be noted that the tantalum nitride layer 22 of the present invention is formed by the SINGEN method. For example, the formed tantalum nitride layer 22 is formed using an Applied Centura SiNgenPlus LPCVD machine provided by Applied Materials. The tantalum nitride layer 22 thus formed is relatively loose and is not substantially etched by phosphoric acid. The above Applied Centura SiNgenPlus LPCVD machine is a monolithic low pressure chemical vapor deposition (LPCVD) tantalum nitride reactor characterized by being capable of depositing at low temperatures, operating at temperatures of about 600 to 800 ° C, and providing better The quality of yttrium oxide.

Then, as shown in FIG. 2, the dry tantalum layer 22 is used as a stop layer by dry etching, such as plasma etching, and is dedicated to etching the second hafnium oxide layer 24 such that the second hafnium oxide layer 24 is on the sidewall of the gate 16. On the tantalum nitride layer 22, a sidewall 26 is formed. At this time, the second ruthenium oxide layer 24 on the substrate 10 above the top of the gate 16 and not covered by the gate 16 is completely removed by plasma etching, exposing the underlying tantalum nitride layer 22, leaving the gate The second ruthenium oxide layer 24 on the side wall of the pole 16 forms the sidewall spacer 26; or, as shown in Fig. 3, the second ruthenium oxide layer 24 on the top of the gate 16 and the substrate 10 may have some residual. The subsequent processes of the present invention are applicable to the case.

Thereafter, as shown in FIG. 4, the tantalum nitride layer 22 and the first hafnium oxide layer 20 are mainly etched by wet etching, and the second hafnium oxide layer 24 is also simultaneously etched to be on the sidewall of the gate 16. A sidewall 28 is formed by the first tantalum oxide layer 20, the tantalum nitride layer 22, and the second tantalum oxide layer 24. So far, the gate structure 38 of the present invention has been completed, and the gate structure of the present invention can be used as a transfer transistor, a reset transistor, a source follower transistor in a CMOS image sensor. (source follower transistor) or select the gate structure of the select transistor.

It should be noted that in the wet etching of the tantalum nitride layer 22, the first hafnium oxide layer 20 and the second hafnium oxide layer 24, the etching solution used is an RCA cleaning solution, generally containing ammonium hydroxide. RCA blankets of (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ) are used to remove the native oxide formed on the semiconductor wafer, or as a wet after the various etching steps in the semiconductor process. Cleaning process. Conventionally, a tantalum nitride layer formed by chemical vapor deposition can be etched using phosphoric acid because phosphoric acid has a high selectivity to tantalum nitride and tantalum oxide, so phosphoric acid etches only tantalum nitride without etching tantalum oxide. . However, as shown in Fig. 5, if the phosphoric acid is used to carry out the wet etching step of the tantalum nitride layer 22 of the ONO stack layer of the present invention, the tantalum nitride layer 22 is caused to have defects 30, in other words, An undercut of the tantalum nitride layer 22 under the second hafnium oxide layer 24 occurs.

However, since the tantalum nitride layer 22 of the present invention is deliberately formed by the SINGEN method, the structure is looser, so the present invention can be wet-etched using the RCA cleaning solution because the RCA cleaning solution can simultaneously etch the tantalum oxide and utilize it. The tantalum nitride produced by the SINGEN method, that is, in the step of wet etching, the first tantalum oxide layer 20, the tantalum nitride layer 22 and the second tantalum oxide layer 24 can be etched by the RCA cleaning solution, but Obtaining the structure shown in Fig. 4 does not cause defects as shown in Fig. 5.

The present invention differs from the conventional process in that the present invention successively etches the ONO stacked layer by dry and wet etching, that is, first uses a dry etching to treat the second layer of tantalum oxide with the tantalum nitride layer 22 as a stop layer. Layer 24, and then using a wet etch, such as RCA cleaning solution as an etchant, primarily etches tantalum nitride layer 22 and first hafnium oxide layer 20 and also etches second hafnium oxide layer 24 to form sidewall spacers 28 . Conventional techniques typically use dry etching or wet etching throughout the process to etch sidewall material layers, such as ONO stacked layers. Further, the tantalum nitride layer 22 in the ONO stacked layer of the present invention is formed by using SINGEN, and therefore, the tantalum nitride layer 22, the first tantalum oxide layer 20, and the second tantalum oxide layer 24 of the present invention can utilize the RCA cleaning liquid. Also etched. Therefore, the structurally complete sidewall spacer 28 as shown in FIG. 4 can be formed, and since the first ruthenium oxide layer 20 is removed by wet etching, it is not removed by plasma etching, and therefore, the light sensing region A The surface of the substrate 10 does not cause the germanium lattice to be destroyed due to plasma bombardment, resulting in unstable dark current. In addition, it is not necessary to add a process step of forming a photoresist to protect the photo sensing region A and removing the photoresist, as in the prior art.

After the gate structure 38 is completed, the desired photodiode or corresponding drain/source is then formed. For example, as shown in FIG. 6, a first patterned photoresist layer (not shown) covers the substrate 10, the STI structure 14, and the gate structure 38, exposing the photosensitive diode region A, and then ion implantation. An N-type dopant (e.g., phosphorus or arsenic, etc.) is doped into the substrate 10 of the photodiode region A to form an N-type doping region 32. The first patterned photoresist layer is subsequently stripped to complete the process of the photodiode. Then, a second patterned photoresist (not shown) is used as a mask, and an N-type doping region 36 is doped on one side of the gate structure 38. Thus, the CIS process is completed.

Finally, as shown in FIG. 4, the gate structure 38 provided by the present invention can be applied to a transfer transistor, a reset transistor, and a source follower in a CIS wafer. Transistor) Select a MOS transistor such as a select transistor or a CMOS transistor in other general peripheral regions. The gate structure 38 provided by the present invention is disposed on a substrate 10, and the gate structure 38 includes a gate 16 and a gate sidewall 28 is disposed on a vertical sidewall of the gate 16, and the gate sidewall 28 includes An ONO stacked layer composed of a first hafnium oxide layer 20, a tantalum nitride layer 22, and a second hafnium oxide layer 24. It is worth noting that the tantalum nitride layer 22 of the present invention is substantially not etched by phosphoric acid. In addition, the gate 16 further includes a dielectric layer 15 disposed on the substrate 10. In accordance with a preferred embodiment of the present invention, the first yttria layer 20 has a thickness of about 100 angstroms and is formed by means of heat oxidation. The second hafnium oxide layer 24 can be formed using deposition.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Base

12. . . P-type doping well

14. . . STI structure

15. . . Dielectric layer

16. . . Gate

18. . . Side wall material layer

20. . . First ruthenium oxide layer

twenty two. . . Tantalum nitride layer

twenty four. . . Second ruthenium oxide layer

26. . . Side wall

28. . . Side wall

30. . . defect

32. . . N-doped region

36. . . N-doped region

38. . . Gate structure

1 to 4 are schematic views showing a method of fabricating the gate structure of the present invention.

Figure 5 is a schematic diagram of a gate structure with defects.

Figure 6 is a schematic diagram showing the method of manufacturing the CIS.

10. . . Base

12. . . P-type doping well

14. . . STI structure

15. . . Dielectric layer

16. . . Gate

20. . . First ruthenium oxide layer

twenty two. . . Tantalum nitride layer

twenty four. . . Second ruthenium oxide layer

28. . . Side wall

Claims (8)

A method for fabricating a gate structure includes: forming a gate; forming a first tantalum oxide layer, a tantalum nitride layer, and a second tantalum oxide layer sequentially covering the gate from bottom to top; performing a dry etching, Partially etching the second ruthenium oxide layer; and performing a wet etch to etch the tantalum nitride layer and the first ruthenium oxide layer. The method for fabricating a gate structure according to claim 1, wherein the first hafnium oxide layer, the tantalum nitride layer, and the second hafnium oxide layer are collectively grouped with hafnium oxide-tantalum nitride-yttria ( ONO) stacked layers. The method for fabricating a gate structure according to claim 1, wherein the tantalum nitride layer is substantially not etched by phosphoric acid. The method for fabricating a gate structure according to claim 1, wherein the etching solution used for the wet etching is an RCA cleaning solution. The method for fabricating a gate structure according to claim 4, wherein the RCA cleaning solution comprises ammonia water and hydrogen peroxide. The method for fabricating a gate structure according to claim 1, wherein the method is In the dry etching, the second ruthenium oxide layer is etched until the exposure of the tantalum nitride layer begins. The method for fabricating a gate structure according to claim 1, wherein the second etching layer, the tantalum nitride layer and the first tantalum oxide layer are simultaneously etched until the complete etching is performed. Removing the tantalum nitride layer at the top of the gate and at least a portion of the first tantalum oxide layer, such that the second tantalum oxide layer, the tantalum nitride layer and the first tantalum oxide layer after etching are applied to the gate The pole vertical sidewalls together form a gate sidewall. The method for fabricating a gate structure according to claim 1, wherein the gate structure is applicable to a transfer transistor, a reset transistor, and a source in a CMOS image sensor. A source follower transistor or a select transistor.