CN115911062A

CN115911062A - Shallow trench isolation structure and forming method thereof

Info

Publication number: CN115911062A
Application number: CN202110957771.XA
Authority: CN
Inventors: 徐涛
Original assignee: Galaxycore Shanghai Ltd Corp
Current assignee: Galaxycore Shanghai Ltd Corp
Priority date: 2021-08-20
Filing date: 2021-08-20
Publication date: 2023-04-04

Abstract

The invention discloses a method for forming a shallow trench isolation structure, a shallow trench isolation structure and a method for forming a semiconductor device. The method for forming the shallow trench isolation structure comprises the following steps: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first oxidation layer on the surface of the groove; performing nitridation treatment on the first oxide layer to form a nitrided-oxide layer; and filling the groove through a second oxide layer to form the shallow groove isolation structure. The invention forms a novel STI by carrying out oxidation treatment, nitridation treatment and reoxidation treatment on the shallow trench, thereby improving the imaging performance of the CIS.

Description

Shallow trench isolation structure and forming method thereof

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a shallow trench isolation structure and a forming method thereof.

Background

A CMOS Image Sensor (CIS) records image information by converting a light image on a photosensitive surface into an electrical signal in a proportional relationship with the light image using a photoelectric conversion function of an optoelectronic device in a pixel array, and processing and storing the electrical signal by a peripheral circuit.

In general, a Shallow Trench Isolation (STI) is used to separate and isolate active regions on a semiconductor wafer from each other. In the manufacturing process of the CIS, after the STI process is formed, a plurality of processes such as ion implantation, high-temperature and low-temperature heat treatment, and plasma etching may be performed, and the above processes may affect an interface state and a fixed charge density of the image sensor, thereby affecting a dark current (dark current) or a white pixel (white pixel) of the CIS. Based on the above problems, the present invention provides a method for forming a shallow trench isolation structure.

Disclosure of Invention

Based on the above problems, the present invention forms a novel STI by performing oxidation, nitridation, and reoxidation on a shallow trench, thereby improving the imaging performance of a CIS. Specifically, the invention provides a method for forming a shallow trench isolation structure, which comprises the following steps: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first oxidation layer on the surface of the groove; performing nitridation treatment on the first oxide layer to form a nitrided-oxide layer; and filling the groove through a second oxide layer to form the shallow groove isolation structure.

Optionally, the forming a trench in the semiconductor substrate includes: forming a mask layer on the surface of the semiconductor substrate; and etching the mask layer and the semiconductor substrate to form the groove.

Optionally, the filling the trench with the second oxide layer further includes, before forming the shallow trench isolation structure: and carrying out reoxidation treatment on the nitridation-oxidation layer to form a reoxidation-nitridation-oxidation layer.

Optionally, the filling the trench with the second oxide layer to form the shallow trench isolation structure includes: depositing the second oxide layer to fill the trench; and flattening the semiconductor substrate.

Optionally, after the planarizing the semiconductor substrate, the method further includes: removing the first oxide layer, the nitridation-oxide layer and the reoxidation-nitridation-oxide layer outside the trench; etching the groove area to adjust the height of the shallow groove isolation structure; and removing the mask layer to form the shallow trench isolation structure.

Optionally, the second oxide layer is deposited by high-density plasma deposition or high-aspect-ratio plasma deposition.

Optionally, the first oxide layer is formed by oxidation in a furnace tube or in-situ water vapor generation; the forming temperature is 800-1200 deg.C, and the thickness is 50-200 angstroms.

Optionally, the temperature of the nitriding treatment is 800 ℃ to 1200 ℃, the time is 20s to 3600s, and the gas is NH ₃ 、NO、N ₂ O、N ₂ At least one of (1).

Optionally, the temperature of the reoxidation treatment is 1000 to 1200 ℃, the time is 20 to 3600 seconds, and the gas is O ₂ 。

The invention also provides a method for forming the semiconductor device, which comprises the following steps: forming a plurality of shallow trench isolation structures by the method; and forming a gate structure, a source region and a drain region of the transistor among the plurality of shallow trench isolation structures.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

according to the invention, the shallow trench is subjected to oxidation treatment, nitridation treatment and reoxidation treatment, and a silicon-nitrogen bond is introduced into the oxide layer in the trench and the interface of the oxide layer and the silicon to form a novel STI, so that the influence of subsequent processes such as ion implantation, high-temperature and low-temperature heat treatment, plasma etching and the like on the interface state and the fixed charge density of the image sensor is reduced, and further the dark current or the white pixel of the CIS is reduced.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 illustrates an exemplary method for forming a shallow trench isolation structure according to an embodiment of the present invention;

fig. 2-12 are cross-sectional views of a shallow trench isolation structure at various stages of fabrication, in accordance with various embodiments of the present invention.

Detailed Description

The following detailed description is exemplary and is intended to provide further explanation of the invention as claimed. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when used in this specification the singular forms "a", "an", and/or "the" include "specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

Fig. 1 illustrates an exemplary method 100 for forming a shallow trench isolation structure according to an embodiment of the present invention; the forming method 100 includes the steps of:

step S1: providing a semiconductor substrate;

step S2: forming a groove in the semiconductor substrate;

and step S3: forming a first oxidation layer on the surface of the groove;

and step S4: performing nitridation treatment on the first oxide layer to form a nitrided-oxide layer;

step S5: and filling the groove through a second oxide layer to form the shallow groove isolation structure.

The above steps will be described with reference to fig. 2 to 7.

Referring to fig. 2, a semiconductor substrate 10 is provided. In particular, the semiconductor substrate 10 may be a doped or undoped semiconductor material such as silicon, germanium, silicon Germanium On Insulator (SGOI) or a combination thereof. The semiconductor substrate 10 may include a substrate of a multi-layered epitaxial layer.

Referring to fig. 3 and 4, a trench 30 is formed in the semiconductor substrate 10. Specifically, referring to fig. 3, a mask layer 21 and a mask layer 22 may be formed on the surface of the semiconductor substrate 10; a patterned photoresist is formed by forming a photoresist (not shown) on the mask layer 21, and by exposure and development. Mask layer 22 may be silicon oxide; mask layer 21 may be silicon nitride.

Further, referring to fig. 4, the mask layer 21 and the mask layer 22 and the semiconductor substrate 10 are etched by an etching process to form the trench 30.

Referring to fig. 5, a first oxide layer 41 is formed on the surface of the trench 30. Specifically, the first oxidation layer 41 may be formed by oxidation in a furnace tube or in-situ steam generation; the forming temperature is 800-1200 deg.C, and the thickness is 50-200 angstroms.

Referring to FIG. 6, for the firstThe oxide layer 41 is subjected to a nitridation process to form a nitrided-oxide layer 42. Specifically, the temperature of the nitriding treatment is 800 ℃ to 1200 ℃, the time is 20s to 3600s, and the gas is NH ₃ 、NO、N ₂ O、N ₂ At least one of (1).

In some embodiments, referring to fig. 7, a reoxidation process may be performed on the nitride-oxide layer 42 to form a reoxidation-nitride-oxide layer 43. The temperature of the reoxidation treatment is 1000 ℃ to 1200 ℃, the time is 20 seconds to 3600 seconds, and the gas is O ₂ 。

Referring to fig. 8 to 12, the trench 30 is filled with the second oxide layer 44 to form a shallow trench isolation structure 50.

Referring to fig. 8, the trench 30 is filled by depositing a second oxide layer 44; the second oxide layer 44 may be deposited by high density plasma deposition or high aspect ratio plasma deposition.

Referring to fig. 9, the semiconductor substrate 10 is planarized.

Referring to fig. 10, the first oxide layer 41, the nitride-oxide layer 42, and the reoxidation-nitride-oxide layer 43 outside the trench 30 are removed.

Referring to fig. 11, the trench 30 region is etched to adjust the height of the shallow trench isolation structure 50.

Referring to fig. 12, the mask layer 21 and the mask layer 22 are removed, thereby forming a shallow trench isolation structure 50.

The present invention also provides a method of forming a semiconductor device, comprising forming a plurality of shallow trench isolation structures by the method 100 of forming shallow trench isolation structures of fig. 1; and forming a gate structure, a source region and a drain region of the transistor among the plurality of shallow trench isolation structures.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for forming a shallow trench isolation structure is characterized by comprising the following steps:

providing a semiconductor substrate;

forming a groove in the semiconductor substrate;

forming a first oxidation layer on the surface of the groove;

performing nitridation treatment on the first oxide layer to form a nitrided-oxide layer;

and filling the groove through a second oxide layer to form the shallow groove isolation structure.

2. The method of claim 1, wherein the forming the trench in the semiconductor substrate comprises:

forming a mask layer on the surface of the semiconductor substrate;

and etching the mask layer and the semiconductor substrate to form the groove.

3. The method of claim 1, wherein the filling the trench with the second oxide layer further comprises, prior to forming the shallow trench isolation structure:

and carrying out reoxidation treatment on the nitridation-oxidation layer to form a reoxidation-nitridation-oxidation layer.

4. The method of claim 1, in which the filling the trench with the second oxide layer to form the shallow trench isolation structure comprises:

depositing the second oxide layer to fill the trench;

and flattening the semiconductor substrate.

5. The method of claim 4, further comprising, after planarizing the semiconductor substrate:

removing the first oxide layer, the nitridation-oxide layer and the reoxidation-nitridation-oxide layer outside the trench;

etching the groove region to adjust the height of the shallow groove isolation structure;

and removing the mask layer to form the shallow trench isolation structure.

6. The method of claim 1, wherein the second oxide layer is deposited by high density plasma deposition or high aspect ratio plasma deposition.

7. The method of claim 1,

the first oxide layer is formed by oxidation in a furnace tube or in-situ water vapor generation;

the forming temperature is 800-1200 deg.c and the thickness is 50-200 angstrom.

8. The method of claim 1, wherein the temperature of the nitridation process is 800 ℃ to 1200 ℃, the time is 20s to 3600s, and the gas is NH ₃ 、NO、N ₂ O、N ₂ At least one of (1).

9. The method of claim 3, wherein the reoxidation process is performed at a temperature of 1000 to 1200 degrees Celsius for 20 to 3600 seconds and with a gas of O ₂ 。

10. A shallow trench isolation structure formed by the method of any of claims 1 to 9.

11. A method of forming a semiconductor device, wherein a plurality of shallow trench isolation structures are formed by the method of any one of claims 1 to 9;

and forming a gate structure, a source region and a drain region of the transistor among the plurality of shallow trench isolation structures.