KR20110075946A - Method for manufacturing of image sensor - Google Patents

Method for manufacturing of image sensor Download PDF

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Publication number
KR20110075946A
KR20110075946A KR1020090132521A KR20090132521A KR20110075946A KR 20110075946 A KR20110075946 A KR 20110075946A KR 1020090132521 A KR1020090132521 A KR 1020090132521A KR 20090132521 A KR20090132521 A KR 20090132521A KR 20110075946 A KR20110075946 A KR 20110075946A
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South Korea
Prior art keywords
gate
etching process
forming
pattern
semiconductor substrate
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KR1020090132521A
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Korean (ko)
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정충경
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주식회사 동부하이텍
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Priority to KR1020090132521A priority Critical patent/KR20110075946A/en
Publication of KR20110075946A publication Critical patent/KR20110075946A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

In another embodiment, a method of manufacturing an image sensor includes: defining a logic region and a pixel region on a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And performing a third wet etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates.

Description

Manufacturing Method of Image Sensor {METHOD FOR MANUFACTURING OF IMAGE SENSOR}

An embodiment relates to a method of manufacturing an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon sensor (CIS). Are distinguished.

CMOS image sensor uses CMOS technology that uses control and signal processing circuits as peripheral circuits to make MOS transistors as many as the number of pixels and uses them to detect the output in turn. A device employing a switching system.

CMOS image sensors are generally divided into an active pixel sensor (APS) array area that detects light to generate an electrical signal, and a logic area (a peripheral circuit area) that processes electrical signals generated in the APS array area. have.

Here, each unit pixel of the APS array region includes a transfer gate electrode, a photodiode and a floating diffusion region positioned at both sides of the transfer gate electrode.

The logic region includes CMOS transistors for processing the electrical signal.

In the image sensor manufacturing process, the pixel region forms a contact that does not employ a silicide film to reduce diode leakage, and the logic region that processes an electrical signal forms a contact employing silicide for high speed signal processing.

That is, when the gate characteristics of the pixel region and the logic region are implemented on one wafer, in the case of the logic transistor, the silicide is formed after the gate spacer process, and in the case of the pixel transistor, the non-silicide is formed. -salicide).

Therefore, gate spacer patterning for the pixel region and the logic region is performed by different processes.

1 to 4, a gate spacer patterning process of a general pixel region and a logic region will be described.

Referring to FIG. 1, a logic gate 20 and a pixel gate 30 are formed on a substrate 10 including a logic region L and a pixel region P. Referring to FIG.

A first oxide film 40, a nitride film 50, and a second oxide film 60 are deposited on the semiconductor substrate 10 including the logic gate 20 and the pixel gate 30 to form a spacer having an ONO structure. Can be.

Referring to FIG. 2, a first photoresist pattern 11 is formed on the semiconductor substrate 10 corresponding to the pixel region L, and an etching process of the logic region L is performed.

Spacers 71 having an ONO structure may be formed on both sidewalls of the logic gate 20.

In this case, the semiconductor substrate 10 corresponding to the logic region L may be removed to a predetermined thickness to form silicide. For example, the loss region T1 of the semiconductor substrate 10 may have a thickness of 100 ± 50 μs.

Referring to FIG. 3, a second photoresist pattern 12 is formed on the semiconductor substrate 10 corresponding to the logic region L, and an etching process is performed on the pixel region P. Referring to FIG.

Spacers 72 having an ONO structure may be formed on both sidewalls of the pixel gate 30.

In this case, an oxide layer may remain on the semiconductor substrate 10 corresponding to the pixel region P to have a predetermined thickness to form the non-silicide. For example, the oxide layer pattern 43 remaining on the semiconductor substrate 10 may be 150 ± 100 μs.

When the logic gate 20 and the pixel gate 30 are formed, the first and second photoresist patterns 11 and 12 are formed by respective photo masks, and the respective patterning processes are performed. As a result, since the number of photo masks increases, there is a problem that price competitiveness and productivity decrease.

In addition, the gate 20 of the logic region L performs a dry etch process until the loss region T1 of the semiconductor substrate 10 is generated using the first photoresist pattern 11, and the pixel region ( The gate 30 of P) employs a process of leaving the oxide film pattern 43 using another second photoresist pattern 12.

In this process, since the logic region is processed only by the dry etching method (P), it is difficult to control the thickness of the loss region T1 of the semiconductor substrate 10, and the characteristics of the logic region L may be changed.

The embodiment provides a method of manufacturing an image sensor that can simplify the gate forming process of the logic region and the pixel region and improve the efficiency of the image sensor.

A method of manufacturing an image sensor according to a first embodiment includes: defining a logic region and a pixel region in a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And performing a third wet etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates.

A method of manufacturing an image sensor according to a second embodiment includes: defining a logic region and a pixel region in a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the nitride film and the second oxide film and forming a nitride film pattern and a second oxide film pattern on sidewalls of the first and second gates; And performing a second wet etching process on the first oxide film, and forming a first oxide film pattern under the nitride film pattern corresponding to sidewalls of the first and second gates.

A method of manufacturing an image sensor according to a third embodiment includes: defining a logic region and a pixel region in a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And performing a third dry etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates.

In example embodiments, gate spacers may be simultaneously formed in a logic region and a pixel region.

That is, a spacer forming process may be simultaneously performed on sidewalls of the first gate of the logic region and the second gate of the pixel region, and respective ONO spacers may be formed.

The spacer forming process may simultaneously apply a dry etching process and a wet etching process to an ONO layer to form a first spacer on the first gate and a second spacer on the second gate.

Accordingly, the mask and the photo process for forming the spacers of the logic region and the pixel region can be omitted, thereby reducing cost and improving productivity.

In addition, since the spacer process of the logic region and the pixel region is performed at the same time, it is possible to improve the characteristics of the logic circuit by preventing silicon loss of the semiconductor substrate.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

<First Embodiment>

5 to 8 and 16, the manufacturing method of the image sensor according to the first embodiment will be described in detail.

Referring to FIG. 5, a first gate 110 and a second gate 120 are formed on the semiconductor substrate 100.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with P-type impurities or N-type impurities.

An isolation layer 105 defining an active region and a field region is formed in the semiconductor substrate 100.

The device isolation layer 105 may be formed by a shallow trench isolation (STI) method.

The active region defined by the device isolation layer 105 may be divided into a logic region L for signal processing and a pixel region P in which a unit pixel is formed.

Although not shown, logic elements such as NMOS and PMOS transistors, capacitors, and resistors may be disposed in the logic region L to configure a logic circuit.

Although not shown, a photodiode for receiving light to generate photocharges and a transistor circuit (not shown) connected to the photodiode to convert the received photocharges into an electric signal are shown for each pixel. Can be formed.

The transistor circuit is addressed by a transfer transistor for transporting photocharges generated in the photodiode to a floating sensing node, a reset transistor for discharging charge stored in the floating sensing node, a drive transistor serving as a source follower, and a switching role. It can be composed of a select transistor to enable.

The first gate 110 may be formed in the logic region L, and the second gate 120 may be formed in the pixel region P. FIG.

The first gate 110 may be an NMOS or PMOS transistor, and the second gate 120 may be any one of the transistors forming the unit pixel.

The first gate 110 and the second gate 120 may have a structure in which a gate insulating layer and a gate electrode are stacked.

For example, the gate insulating layer may be formed of an insulating film including an oxide film or a nitride film. The gate electrode may be a polysilicon, a metal, or a laminated film of polysilicon and a metal.

The first gate 110 of the logic region L may need to be converted to a metal gate for high integration operation.

Referring to FIG. 5 again, a spacer layer 160 is formed on the semiconductor substrate 100 including the first gate 110 and the second gate 120.

The spacer layer 160 may be formed by sequentially depositing a first oxide layer 130, a nitride layer 140, and a second oxide layer 150 on the semiconductor substrate 100. have.

For example, the first oxide layer 130 is formed to have a thickness of 200 ± 50 GPa TEOS, the nitride layer 140 is formed to have a thickness of 200 ± 50 GPa SiN, and the second oxide film 150 may be formed of TEOS It can be formed to a thickness of 800 ± 50 kPa.

Referring to FIG. 6, a first dry etching process may be performed on the second oxide layer 150 positioned on the top of the spacer layer 160.

Second oxide layer patterns 151 and 152 are formed on sidewalls of the first and second gates 110 and 120 through the first dry etching process.

The first dry etching process may be a front surface etching process using plasma.

Therefore, a second oxide layer pattern 151 is formed on the sidewall of the first gate 110, and a second oxide layer pattern 152 is formed on the sidewall of the second gate 120.

The second oxide layer patterns 151 and 152 of the first gate 110 and the second gate 120 may be formed at the same time.

The second oxide layer patterns 151 and 152 may be selectively formed only on the sidewalls of the first gate 110 and the second gate 120, and the nitride layers may be formed on the first gate 110 and the second gate 120. 140 may be exposed

At the same time, the nitride layer 140 corresponding to the upper portion of the semiconductor substrate 100 corresponding to the logic region L and the pixel region P may be exposed.

Referring to FIG. 7, a second wet etching process is performed on the nitride layer 140 exposed by the second oxide layer patterns 151 and 152.

The second oxide layer patterns 151 and 152 may be used as an etching mask through the second wet etching process, and the exposed nitride layer 140 may be selectively removed.

Accordingly, the nitride layer patterns 141 and 142 may be selectively formed only under the second oxide layer patterns 151 and 152.

The nitride layer pattern 141 and the second oxide layer pattern 151 may be formed on sidewalls of the first gate 110. The nitride layer pattern 142 and the second oxide layer pattern 152 may be formed on sidewalls of the second gate 120.

The second wet etching process may be a wet etching process using H 3 PO 4 chemicals.

Based on the thickness of the nitride film 140 being 200 μs, the second wet etching process is selective for the nitride film 140 using H 3 PO 4 chemical at a temperature of 160 ± 30 ° C. for 10-30 minutes. The patterning process can proceed.

The nitride layer 140 corresponding to the upper portions of the first and second gates 110 and 120 exposed by the second oxide layer patterns 151 and 152 may be removed. At the same time, the nitride layer 140 corresponding to the logic region L and the pixel region P exposed by the second oxide layer patterns 151 and 152 may be removed.

Accordingly, the nitride layer patterns 141 and 142 may be formed only under the second oxide layer patterns 151 and 152 formed in the first and second gates 110 and 120, respectively.

Referring to FIG. 8, a third wet etching process may be performed on the first oxide layer 130 exposed by the second oxide layer patterns 151 and 152 and the nitride layer patterns 141 and 142.

Through the third wet etching process, the second oxide layer patterns 151 and 152 and the nitride layer patterns 141 and 142 may be used as etching masks, and the exposed first oxide layer 130 may be selectively removed.

Accordingly, the first oxide layer patterns 131 and 132 may be selectively formed only under the second oxide layer patterns 151 and 152 and the nitride layer patterns 141 and 142.

An ONO structure first spacer 161 having a first oxide layer pattern 131, a nitride layer pattern 141, and a second oxide layer pattern 151 may be formed on sidewalls of the first gate 110.

A second spacer 162 having an ONO structure having a first oxide layer pattern 131, a nitride layer pattern 142, and a second oxide layer pattern 152 may be formed on a sidewall of the second gate 120.

The third wet etching process may be a wet etching process using diluted HF (DHF) and buffered HF (BHF).

When the thickness of the first oxide layer 130 is 200 μs, the third wet etching process may be performed using a selective patterning process for the first oxide layer 130 using DHF or BHF chemical for 10-30 minutes. You can proceed.

The first oxide layer 130 corresponding to the upper portions of the first and second gates 110 and 120 exposed by the second oxide layer patterns 151 and 152 and the nitride layer patterns 141 and 142 may be removed. At the same time, the first oxide pattern 131 corresponding to the semiconductor substrate 100 of the logic region L and the pixel region P exposed by the second oxide pattern 151 and 152 and the nitride pattern 141 and 142 may be formed. Can be removed.

The first oxide layer pattern 131 is formed only under the second oxide layer patterns 151 and 152 and the nitride layer patterns 141 and 142, and a first spacer 161 is formed in the first gate 110. The second spacer 162 may be formed in the gate 120.

When the first oxide layer pattern 131 is formed by the third wet etching process, a main layer 135 having a second thickness D2 may be formed on the surface of the semiconductor substrate 100.

The main pattern 135 may be selectively formed only on an upper surface of the semiconductor substrate 100 by controlling the third wet etching process.

That is, the main pattern 135 may remain only on the surface of the semiconductor substrate 100 of the logic region L and the surface of the semiconductor substrate 100 of the pixel region P. FIG.

When the first oxide layer 130 is of the first thickness D1, the remain pattern 135 may be formed to have a second thickness D2 smaller than the first thickness. For example, the second thickness of the main pattern 135 may be 100 ± 50 μs.

Since the main pattern 135 remains on the pixel region P and the logic region L, the surface of the semiconductor substrate 100 may be prevented from being damaged by the post-curve implant process.

Referring to FIG. 16, an implant process may be performed on the semiconductor substrate 100 of the logic region L to be aligned with both sides of the first gate 110, and an ion implantation region 171 may be formed.

An implantation process may be performed on the semiconductor substrate 100 of the pixel region P so as to be aligned at both sides of the second gate 120, and an ion implantation region 172 may be formed.

For example, the ion implantation regions 171 and 172 may be made of n-type impurities or p-type impurities.

After removing the main pattern 135 of the semiconductor substrate 100 corresponding to the logic region L, the silicide layer 180 is formed on the surface of the semiconductor substrate 100 and the surface of the first gate 110. Is formed.

The silicide layer 180 masks the pixel region P of the semiconductor substrate 100, and then deposits a metal layer on the semiconductor substrate 100 corresponding to the logic region L of the semiconductor substrate 100. It may be selectively formed only on the surface of the semiconductor substrate 100 and the surface of the first gate 110 through a heat treatment process.

In example embodiments, gate spacers may be simultaneously formed in a logic region and a pixel region.

That is, a spacer forming process may be simultaneously performed on sidewalls of the first gate of the logic region and the second gate of the pixel region, and respective ONO spacers may be formed.

The spacer forming process may simultaneously apply a dry etching process and a wet etching process to an ONO layer to form a first spacer on the first gate and a second spacer on the second gate.

Accordingly, the mask and the photo process for forming the spacers of the logic region and the pixel region can be omitted, thereby reducing cost and improving productivity.

In addition, since the spacer process of the logic region and the pixel region is performed at the same time, it is possible to improve the characteristics of the logic circuit by preventing silicon loss of the semiconductor substrate.

Second Embodiment

9 to 11, a method of manufacturing the image sensor according to the second embodiment will be described. In the description of the second embodiment, detailed description of the same configuration as that of the first embodiment can be omitted.

9, a first gate 210 and a second gate 220 are formed on a semiconductor substrate 200.

The first gate 210 may be formed in the logic region L, and the second gate 220 may be formed in the pixel region P. FIG.

The first gate 210 may be an NMOS or PMOS transistor, and the second gate 220 may be any one of the transistors forming the unit pixel.

The first gate 210 and the second gate 220 may have a structure in which a gate insulating layer and a gate electrode are stacked.

Referring to FIG. 9 again, a spacer layer 260 is formed on the semiconductor substrate 200 including the first gate 210 and the second gate 220.

The spacer layer 260 may be formed by sequentially depositing a first oxide layer 230, a nitride layer 240, and a second oxide layer 250 on the semiconductor substrate 200. have.

For example, the first oxide film 230 is formed with a thickness of 200 ± 50 GPa TEOS, the nitride film 240 is formed with a thickness of 200 ± 50 GPa SiN, and the second oxide film 250 is formed of TEOS It can be formed to a thickness of 800 ± 50 kPa.

Referring to FIG. 10, a first dry etching process may be performed on the second oxide layer 250 and the nitride layer 240 of the spacer layer 260.

The nitride pattern 241 and the second oxide pattern 251 are formed on sidewalls of the first gate 210 through the first dry etching process, and the nitride layer pattern 242 is formed on the sidewalls of the second gate 220. ) And a second oxide film pattern 252 are formed.

The first dry etching process may be a front surface etching process using plasma.

An etching parameter of the first dry etching process may be controlled, and only patterning of the second oxide layer 250 and the nitride layer 240 may be selectively performed.

The nitride layer patterns 241 and 242 and the second oxide layer patterns 251 and 252 may be simultaneously formed in the first gate 210 and the second gate 220.

The nitride layer pattern 241 and the second oxide layer pattern 251 may be formed on sidewalls of the first gate 210, and the lower first oxide layer 230 may be exposed.

The nitride layer pattern 242 and the second oxide layer pattern 252 may be formed on sidewalls of the second gate 220, and the lower first oxide layer 230 may be exposed.

Referring to FIG. 11, a second wet etching process is performed on the first oxide layer 230 exposed by the second oxide layer patterns 251 and 252 and the nitride layer patterns 241 and 242.

Through the second wet etching process, the second oxide layer patterns 251 and 252 and the nitride layer patterns 241 and 242 may be used as etching masks, and the exposed first oxide layer 230 may be selectively removed.

Accordingly, the first oxide layer patterns 231 and 232 may be selectively formed only under the second oxide layer patterns 251 and 252 and the nitride layer patterns 241 and 242.

An ONO structure first spacer 261 having a first oxide layer pattern 231, a nitride layer pattern 241, and a second oxide layer pattern 251 may be formed on sidewalls of the first gate 210.

A second spacer 262 having an ONO structure having a first oxide layer pattern 232, a nitride layer pattern 242, and a second oxide layer pattern 252 may be formed on a sidewall of the second gate 220.

The second wet etching process may be a wet etching process using diluted HF (DHF) and buffered HF (BHF).

Based on the thickness of the first oxide layer 230 being 200 μs, the second wet etching process may be performed by a selective patterning process for the second oxide layer using DHF or BHF chemical for 10 to 30 minutes. have.

The first oxide layer 230 corresponding to the upper portions of the first and second gates 210 and 220 exposed by the second oxide layer patterns 251 and 252 and the nitride layer patterns 241 and 242 may be removed. At the same time, the first oxide layer 230 corresponding to the logic region L and the pixel region P exposed by the second oxide layer patterns 251 and 252 and the nitride layer patterns 241 and 242 may be removed.

The first oxide layer patterns 231 and 232 are formed only below the second oxide layer patterns 251 and 252 and the nitride layer patterns 241 and 242, and a first spacer 261 is formed on the first gate 210. The second spacer 262 may be formed in the gate 220.

When the first oxide layer patterns 231 and 232 are formed by the second wet etching process, a main layer pattern 235 having a second thickness D2 may be formed on the surface of the semiconductor substrate 200.

The main pattern 235 may be selectively formed only on an upper surface of the semiconductor substrate 200 by the control of the secondary wet etching process.

That is, the main pattern 235 may remain only on the surface of the semiconductor substrate 200 in the logic region L and the surface of the semiconductor substrate 200 in the pixel region P. FIG.

When the first oxide layer 230 is of the first thickness D1, the main pattern 235 may be formed to have a second thickness D2 smaller than the first thickness. For example, the second thickness of the main pattern 235 may be 100 ± 50 μs.

Since the main pattern 235 remains on the pixel region P and the logic region L, the surface of the semiconductor substrate 200 may be prevented from being damaged by the post-curve implant process.

Thereafter, as shown in FIG. 16, an ion implantation process and a silicide process may be performed.

Third Embodiment

12 to 15, a manufacturing method of the image sensor according to the third embodiment will be described. In the description of the third embodiment, detailed description of the same configuration as that of the first embodiment can be omitted.

12, a first gate 310 and a second gate 320 are formed on the semiconductor substrate 300.

The first gate 310 may be formed in the logic region L, and the second gate 320 may be formed in the pixel region P. FIG.

The first gate 310 may be an NMOS or PMOS transistor, and the second gate 320 may be any one of the transistors forming the unit pixel.

The first gate 310 and the second gate 320 may have a structure in which a gate insulating layer and a gate electrode are stacked.

Referring to FIG. 12 again, a spacer layer 360 is formed on the semiconductor substrate 300 including the first gate 310 and the second gate 320.

The spacer layer 360 may be formed by sequentially depositing a first oxide 330, a nitride 340, and a second oxide 350 on the semiconductor substrate 300. have.

For example, the first oxide film 330 has a thickness of 200 ± 50 GPa TEOS, the nitride film 340 has a thickness of 200 ± 50 GPa SiN, and the second oxide film 350 has a TEOS It can be formed to a thickness of 800 ± 50 kPa.

Referring to FIG. 13, a first dry etching process may be performed on the second oxide layer 350 positioned on the top of the spacer layer 360.

Second oxide layer patterns 351 and 352 are formed on sidewalls of the first and second gates 310 and 320 through the first dry etching process.

The first dry etching process may be a front surface etching process using plasma.

Accordingly, a second oxide pattern 351 is formed on sidewalls of the first gate 310, and a second oxide pattern 352 is formed on sidewalls of the second gate 320.

The second oxide layer patterns 351 and 352 of the first gate 310 and the second gate 320 may be formed at the same time.

The second oxide layer patterns 351 and 352 may be selectively formed only on the sidewalls of the first gate 310 and the second gate 320, and the nitride layers may be formed on the first gate 310 and the second gate 320. The 340 may be exposed. The nitride layer 340 corresponding to the upper portion of the semiconductor substrate 100 corresponding to the logic region L and the pixel region P may also be exposed.

Referring to FIG. 14, a second wet etching process is performed on the nitride layer 340 exposed by the second oxide layer patterns 351 and 352.

The second oxide layer patterns 351 and 352 may be used as an etching mask through the second wet etching process, and the exposed nitride layer 340 may be selectively removed.

Therefore, nitride layer patterns 341 and 342 may be selectively formed only under the second oxide layer patterns 351 and 352.

A nitride film pattern 341 and a second oxide film pattern 351 may be formed on sidewalls of the first gate 310. A nitride layer pattern 342 and a second oxide layer pattern 352 may be formed on sidewalls of the second gate 320.

The second wet etching process may be a wet etching process using H 3 PO 4 chemicals.

When the thickness of the nitride film 340 is 200 μs, the second wet etching process may be performed at 160 ± 30 ° C. for 10 to 30 minutes using H 3 PO 4 chemical to the nitride film 340. An optional patterning process can be performed.

The nitride layer 340 corresponding to the upper portions of the first and second gates 310 and 320 exposed by the second oxide layer patterns 351 and 352 may be removed. At the same time, the nitride layer 340 corresponding to the logic region L and the pixel region P exposed by the second oxide layer patterns 351 and 352 may be removed.

Accordingly, the nitride layer patterns 341 and 342 may be formed only under the second oxide layer patterns 351 and 352 formed on the first and second gates 310 and 320, respectively.

Referring to FIG. 8, a third dry etching process may be performed on the first oxide layer 330 exposed by the second oxide layer patterns 351 and 352 and the nitride layer patterns 341 and 342.

Through the third dry etching process, the second oxide layer patterns 351 and 352 and the nitride layer patterns 341 and 342 may be used as an etching mask, and the exposed first oxide layer 330 may be selectively removed.

Accordingly, the first oxide layer patterns 331 and 332 may be selectively formed only under the second oxide layer patterns 351 and 352 and the nitride layer patterns 341 and 342.

An ONO structure first spacer 361 having a first oxide layer pattern 331, a nitride layer pattern 341, and a second oxide layer pattern 351 may be formed on sidewalls of the first gate 310.

A second spacer 362 having an ONO structure having a first oxide pattern 332, a nitride layer pattern 342, and a second oxide layer pattern 352 may be formed on sidewalls of the second gate 320.

The third dry etching process may be a reactive ion etching process using plasma.

Therefore, a selective patterning process for the second oxide film 350 may be performed.

The first oxide layer 330 corresponding to the upper portions of the first and second gates 310 and 320 exposed by the second oxide layer patterns 351 and 352 and the nitride layer patterns 341 and 342 may be removed. At the same time, the first oxide layer 330 corresponding to the logic region L and the pixel region P exposed by the second oxide layer patterns 351 and 352 and the nitride layer patterns 341 and 342 may be removed.

The first oxide layer patterns 331 and 332 are formed only below the second oxide layer patterns 351 and 352 and the nitride layer patterns 341 and 342, and the first spacer 361 is formed on the first gate 310, and the second layer is formed on the second gate pattern 310. The second spacer 362 may be formed in the gate 320.

When the first oxide layer patterns 331 and 332 are formed by the tertiary dry etching process, a main pattern 335 having a second thickness D2 may be formed on the surface of the semiconductor substrate 100.

The main pattern 335 may be selectively formed only on the upper surface of the semiconductor substrate 100 by the control of the third dry etching process.

That is, the main pattern 335 may remain only on the surface of the semiconductor substrate 100 in the logic region L and the surface of the semiconductor substrate 100 in the pixel region P. FIG.

When the first oxide layer 330 is of the first thickness D1, the re main pattern 335 may be formed to have a second thickness D2 smaller than the first thickness. For example, the second thickness of the main pattern 335 may be 100 ± 50 μs.

Since the main pattern 335 remains on the pixel region P and the logic region L, the surface of the semiconductor substrate 100 may be prevented from being damaged by the post-curve implant process.

Thereafter, as shown in FIG. 16, an ion implantation process and a silicide process may be performed.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 to 4 are cross-sectional views illustrating a manufacturing process of a general image sensor.

5 to 8 are sectional views showing the manufacturing process of the image sensor according to the first embodiment.

9 to 11 are cross-sectional views illustrating a manufacturing process of the image sensor according to the second embodiment.

12 to 16 are sectional views showing the manufacturing process of the image sensor according to the third embodiment.

Claims (11)

Defining a logic region and a pixel region in the semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming a spacer layer on which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And And performing a third wet etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates. The method of claim 1, The first dry etching process is a front etching process using a plasma, the second wet etching process is a wet etching process using H 3 PO 4 chemical, the third etching process is a wet etching process using DHF and BHF chemicals. Method for manufacturing an image sensor, characterized in that. The method of claim 1, When the first oxide film pattern is formed by the third wet etching process, a main pattern of a first thickness is formed on a surface of the semiconductor substrate. The method of claim 3, Removing the main domain pattern corresponding to the logic region, and forming a silicide layer on a surface of the semiconductor substrate and a surface of the first gate corresponding to the logic region. Defining a logic region and a pixel region in the semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming a spacer layer on which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the nitride film and the second oxide film and forming a nitride film pattern and a second oxide film pattern on sidewalls of the first and second gates; And Performing a second wet etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates. . The method of claim 5, The secondary wet etching process is a method of manufacturing an image sensor, characterized in that the wet etching process using the DHF and BHF chemicals. The method of claim 5, When the first oxide film pattern is formed by the second wet etching process, a main pattern of a first thickness is formed on a surface of the semiconductor substrate. The method of claim 7, wherein Removing the main domain pattern corresponding to the logic region, and forming a silicide layer on a surface of the semiconductor substrate and a surface of the first gate corresponding to the logic region. Defining a logic region and a pixel region in the semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming a spacer layer on which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And And performing a third dry etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates. 10. The method of claim 9, When the first oxide film pattern is formed by the tertiary dry etching process, a method of manufacturing an image sensor, characterized in that a remain pattern having a first thickness is formed on a surface of the semiconductor substrate. The method of claim 10, Removing the main domain pattern corresponding to the logic region, and forming a silicide layer on a surface of the semiconductor substrate and a surface of the first gate corresponding to the logic region.
KR1020090132521A 2009-12-29 2009-12-29 Method for manufacturing of image sensor KR20110075946A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108063146A (en) * 2017-12-15 2018-05-22 上海华力微电子有限公司 The manufacturing method of cmos image sensor
CN110010452A (en) * 2017-11-30 2019-07-12 台湾积体电路制造股份有限公司 Circuit devcie with grid sealing element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010452A (en) * 2017-11-30 2019-07-12 台湾积体电路制造股份有限公司 Circuit devcie with grid sealing element
CN108063146A (en) * 2017-12-15 2018-05-22 上海华力微电子有限公司 The manufacturing method of cmos image sensor

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