KR20110075946A - Method for manufacturing of image sensor - Google Patents
Method for manufacturing of image sensor Download PDFInfo
- Publication number
- KR20110075946A KR20110075946A KR1020090132521A KR20090132521A KR20110075946A KR 20110075946 A KR20110075946 A KR 20110075946A KR 1020090132521 A KR1020090132521 A KR 1020090132521A KR 20090132521 A KR20090132521 A KR 20090132521A KR 20110075946 A KR20110075946 A KR 20110075946A
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- South Korea
- Prior art keywords
- gate
- etching process
- forming
- pattern
- semiconductor substrate
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- 238000000034 method Methods 0.000 title claims abstract description 125
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000004065 semiconductor Substances 0.000 claims abstract description 69
- 238000001039 wet etching Methods 0.000 claims abstract description 43
- 238000001312 dry etching Methods 0.000 claims abstract description 29
- 125000006850 spacer group Chemical group 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 13
- 239000000126 substance Substances 0.000 claims description 9
- 238000000059 patterning Methods 0.000 description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000007943 implant Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
In another embodiment, a method of manufacturing an image sensor includes: defining a logic region and a pixel region on a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And performing a third wet etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates.
Description
An embodiment relates to a method of manufacturing an image sensor.
An image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon sensor (CIS). Are distinguished.
CMOS image sensor uses CMOS technology that uses control and signal processing circuits as peripheral circuits to make MOS transistors as many as the number of pixels and uses them to detect the output in turn. A device employing a switching system.
CMOS image sensors are generally divided into an active pixel sensor (APS) array area that detects light to generate an electrical signal, and a logic area (a peripheral circuit area) that processes electrical signals generated in the APS array area. have.
Here, each unit pixel of the APS array region includes a transfer gate electrode, a photodiode and a floating diffusion region positioned at both sides of the transfer gate electrode.
The logic region includes CMOS transistors for processing the electrical signal.
In the image sensor manufacturing process, the pixel region forms a contact that does not employ a silicide film to reduce diode leakage, and the logic region that processes an electrical signal forms a contact employing silicide for high speed signal processing.
That is, when the gate characteristics of the pixel region and the logic region are implemented on one wafer, in the case of the logic transistor, the silicide is formed after the gate spacer process, and in the case of the pixel transistor, the non-silicide is formed. -salicide).
Therefore, gate spacer patterning for the pixel region and the logic region is performed by different processes.
1 to 4, a gate spacer patterning process of a general pixel region and a logic region will be described.
Referring to FIG. 1, a
A
Referring to FIG. 2, a first
In this case, the
Referring to FIG. 3, a second
In this case, an oxide layer may remain on the
When the
In addition, the
In this process, since the logic region is processed only by the dry etching method (P), it is difficult to control the thickness of the loss region T1 of the
The embodiment provides a method of manufacturing an image sensor that can simplify the gate forming process of the logic region and the pixel region and improve the efficiency of the image sensor.
A method of manufacturing an image sensor according to a first embodiment includes: defining a logic region and a pixel region in a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And performing a third wet etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates.
A method of manufacturing an image sensor according to a second embodiment includes: defining a logic region and a pixel region in a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the nitride film and the second oxide film and forming a nitride film pattern and a second oxide film pattern on sidewalls of the first and second gates; And performing a second wet etching process on the first oxide film, and forming a first oxide film pattern under the nitride film pattern corresponding to sidewalls of the first and second gates.
A method of manufacturing an image sensor according to a third embodiment includes: defining a logic region and a pixel region in a semiconductor substrate; Forming a first gate in the logic region and forming a second gate in the pixel region; Forming an ONO layer in which a first oxide film-nitride film-second oxide film is stacked on the semiconductor substrate including the first gate and the second gate; Performing a first dry etching process on the second oxide layer and forming a second oxide pattern on sidewalls of the first and second gates; Performing a second wet etching process on the nitride film and forming a nitride film pattern under the second oxide film pattern corresponding to sidewalls of the first and second gates; And performing a third dry etching process on the first oxide layer, and forming a first oxide layer pattern under the nitride layer pattern corresponding to sidewalls of the first and second gates.
In example embodiments, gate spacers may be simultaneously formed in a logic region and a pixel region.
That is, a spacer forming process may be simultaneously performed on sidewalls of the first gate of the logic region and the second gate of the pixel region, and respective ONO spacers may be formed.
The spacer forming process may simultaneously apply a dry etching process and a wet etching process to an ONO layer to form a first spacer on the first gate and a second spacer on the second gate.
Accordingly, the mask and the photo process for forming the spacers of the logic region and the pixel region can be omitted, thereby reducing cost and improving productivity.
In addition, since the spacer process of the logic region and the pixel region is performed at the same time, it is possible to improve the characteristics of the logic circuit by preventing silicon loss of the semiconductor substrate.
Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.
In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.
<First Embodiment>
5 to 8 and 16, the manufacturing method of the image sensor according to the first embodiment will be described in detail.
Referring to FIG. 5, a
The
An
The
The active region defined by the
Although not shown, logic elements such as NMOS and PMOS transistors, capacitors, and resistors may be disposed in the logic region L to configure a logic circuit.
Although not shown, a photodiode for receiving light to generate photocharges and a transistor circuit (not shown) connected to the photodiode to convert the received photocharges into an electric signal are shown for each pixel. Can be formed.
The transistor circuit is addressed by a transfer transistor for transporting photocharges generated in the photodiode to a floating sensing node, a reset transistor for discharging charge stored in the floating sensing node, a drive transistor serving as a source follower, and a switching role. It can be composed of a select transistor to enable.
The
The
The
For example, the gate insulating layer may be formed of an insulating film including an oxide film or a nitride film. The gate electrode may be a polysilicon, a metal, or a laminated film of polysilicon and a metal.
The
Referring to FIG. 5 again, a
The
For example, the
Referring to FIG. 6, a first dry etching process may be performed on the
Second
The first dry etching process may be a front surface etching process using plasma.
Therefore, a second
The second
The second
At the same time, the
Referring to FIG. 7, a second wet etching process is performed on the
The second
Accordingly, the
The
The second wet etching process may be a wet etching process using H 3 PO 4 chemicals.
Based on the thickness of the
The
Accordingly, the
Referring to FIG. 8, a third wet etching process may be performed on the
Through the third wet etching process, the second
Accordingly, the first
An ONO structure
A
The third wet etching process may be a wet etching process using diluted HF (DHF) and buffered HF (BHF).
When the thickness of the
The
The first
When the first
The
That is, the
When the
Since the
Referring to FIG. 16, an implant process may be performed on the
An implantation process may be performed on the
For example, the
After removing the
The
In example embodiments, gate spacers may be simultaneously formed in a logic region and a pixel region.
That is, a spacer forming process may be simultaneously performed on sidewalls of the first gate of the logic region and the second gate of the pixel region, and respective ONO spacers may be formed.
The spacer forming process may simultaneously apply a dry etching process and a wet etching process to an ONO layer to form a first spacer on the first gate and a second spacer on the second gate.
Accordingly, the mask and the photo process for forming the spacers of the logic region and the pixel region can be omitted, thereby reducing cost and improving productivity.
In addition, since the spacer process of the logic region and the pixel region is performed at the same time, it is possible to improve the characteristics of the logic circuit by preventing silicon loss of the semiconductor substrate.
Second Embodiment
9 to 11, a method of manufacturing the image sensor according to the second embodiment will be described. In the description of the second embodiment, detailed description of the same configuration as that of the first embodiment can be omitted.
9, a
The
The
The
Referring to FIG. 9 again, a
The
For example, the
Referring to FIG. 10, a first dry etching process may be performed on the
The
The first dry etching process may be a front surface etching process using plasma.
An etching parameter of the first dry etching process may be controlled, and only patterning of the
The
The
The
Referring to FIG. 11, a second wet etching process is performed on the
Through the second wet etching process, the second
Accordingly, the first
An ONO structure
A second spacer 262 having an ONO structure having a first
The second wet etching process may be a wet etching process using diluted HF (DHF) and buffered HF (BHF).
Based on the thickness of the
The
The first
When the first
The
That is, the
When the
Since the
Thereafter, as shown in FIG. 16, an ion implantation process and a silicide process may be performed.
Third Embodiment
12 to 15, a manufacturing method of the image sensor according to the third embodiment will be described. In the description of the third embodiment, detailed description of the same configuration as that of the first embodiment can be omitted.
12, a
The
The
The
Referring to FIG. 12 again, a
The
For example, the
Referring to FIG. 13, a first dry etching process may be performed on the
Second
The first dry etching process may be a front surface etching process using plasma.
Accordingly, a
The second
The second
Referring to FIG. 14, a second wet etching process is performed on the
The second
Therefore,
A
The second wet etching process may be a wet etching process using H 3 PO 4 chemicals.
When the thickness of the
The
Accordingly, the
Referring to FIG. 8, a third dry etching process may be performed on the
Through the third dry etching process, the second
Accordingly, the first
An ONO structure
A second spacer 362 having an ONO structure having a
The third dry etching process may be a reactive ion etching process using plasma.
Therefore, a selective patterning process for the
The
The first
When the first
The
That is, the
When the
Since the
Thereafter, as shown in FIG. 16, an ion implantation process and a silicide process may be performed.
The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.
1 to 4 are cross-sectional views illustrating a manufacturing process of a general image sensor.
5 to 8 are sectional views showing the manufacturing process of the image sensor according to the first embodiment.
9 to 11 are cross-sectional views illustrating a manufacturing process of the image sensor according to the second embodiment.
12 to 16 are sectional views showing the manufacturing process of the image sensor according to the third embodiment.
Claims (11)
Priority Applications (1)
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KR1020090132521A KR20110075946A (en) | 2009-12-29 | 2009-12-29 | Method for manufacturing of image sensor |
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KR1020090132521A KR20110075946A (en) | 2009-12-29 | 2009-12-29 | Method for manufacturing of image sensor |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108063146A (en) * | 2017-12-15 | 2018-05-22 | 上海华力微电子有限公司 | The manufacturing method of cmos image sensor |
CN110010452A (en) * | 2017-11-30 | 2019-07-12 | 台湾积体电路制造股份有限公司 | Circuit devcie with grid sealing element |
-
2009
- 2009-12-29 KR KR1020090132521A patent/KR20110075946A/en not_active Application Discontinuation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110010452A (en) * | 2017-11-30 | 2019-07-12 | 台湾积体电路制造股份有限公司 | Circuit devcie with grid sealing element |
CN108063146A (en) * | 2017-12-15 | 2018-05-22 | 上海华力微电子有限公司 | The manufacturing method of cmos image sensor |
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