JP2012019085A - Solid-state imaging device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device and a manufacturing method of the same which enable microfabrication of a peripheral logic circuit region and prevent deterioration in pixel characteristics.SOLUTION: The manufacturing method of the solid-state imaging device including an imaging region having a plurality of unit pixel regions and a peripheral logic circuit region provided on the periphery of the imaging region comprises the steps of forming an electrode film of a first film thickness and a block film on a semiconductor substrate, removing the block film by using a first resist pattern corresponding to a gate electrode of a transistor in the unit pixel region as a mask to reduce the thickness of the electrode film, and removing the electrode film by using a second resist pattern corresponding to a gate electrode of a transistor in the peripheral logic circuit region and the block film as masks.

Description

  Embodiments described herein relate generally to a solid-state imaging device and a method for manufacturing the same.

  The CMOS image sensor includes an imaging area in which a plurality of unit pixel areas are arranged, and a peripheral logic circuit area provided around the imaging area. Each unit pixel area has a color filter that transmits light of a specific wavelength, a photodiode that receives light that has passed through the color filter, generates a signal charge according to the amount of incident light, and reads out the signal charge of the photodiode. And a MOS transistor for performing. The peripheral logic circuit area has circuits for performing AD conversion and image processing, and MOS transistors that constitute these circuits are provided. Hereinafter, the MOS transistor provided in the unit pixel region is referred to as a pixel transistor, and the MOS transistor provided in the peripheral logic circuit region is referred to as a logic transistor. The gate electrode film of the pixel transistor is called a pixel gate electrode film, and the gate electrode film of the logic transistor is called a logic gate electrode film.

  With the miniaturization of the peripheral logic circuit region, the logic gate electrode film is thinned. When the pixel gate electrode film is thinned in the same manner as the logic gate electrode film, in order to prevent implanted ions at the time of forming the diffusion layer of the pixel transistor from reaching the channel region through the pixel gate electrode film, It is necessary to increase the thickness of the block film (block film during ion implantation) formed on the pixel gate electrode film.

  However, when the block film is made thicker, when a resist pattern for ion implantation is processed, a resist residue is generated in the space portion having a high aspect ratio due to a decrease in resist opening property, and a diffusion layer of the pixel transistor is formed. There was a problem that the pixel characteristics were deteriorated without being formed.

JP 2009-283552 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device and a manufacturing method thereof for miniaturizing a peripheral logic circuit region and preventing deterioration of pixel characteristics.

  According to the present embodiment, a method for manufacturing a solid-state imaging device includes: an imaging region in which a plurality of unit pixel regions are arranged; and a peripheral logic circuit region provided around the imaging region. It is. The method includes the steps of forming an electrode film having a first thickness on a semiconductor substrate, forming a block film on the electrode film, and forming a gate electrode of a transistor in the unit pixel region on the block film. Forming a first resist pattern in the region; removing the block film using the first resist pattern as a mask; and forming a second electrode film having a thickness smaller than the first film thickness using the first resist pattern as a mask. Forming a second resist pattern in a gate electrode formation region of the transistor in the peripheral logic circuit region on the block film having the second thickness; and a step of removing the first resist pattern; And a step of removing the electrode film using the block film and the second resist pattern as a mask.

It is process sectional drawing explaining the manufacturing method of the solid-state imaging device which concerns on embodiment of this invention. It is process sectional drawing following FIG. FIG. 3 is a process cross-sectional view subsequent to FIG. 2. FIG. 4 is a process cross-sectional view subsequent to FIG. 3. FIG. 5 is a process cross-sectional view subsequent to FIG. 4. FIG. 6 is a process cross-sectional view subsequent to FIG. 5. FIG. 7 is a process cross-sectional view subsequent to FIG. 6. It is a schematic block diagram of the solid-state imaging device concerning the embodiment. It is process sectional drawing explaining the manufacturing method of the solid-state imaging device by a modification.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 to 7 are process cross-sectional views illustrating a method for manufacturing a solid-state imaging device according to this embodiment.

  As shown in FIG. 1, an element isolation region 101 having an STI (Shallow Trench Isolation) structure is formed on a surface portion of a silicon substrate (semiconductor substrate) 100. For example, a mask material (not shown) made of a silicon nitride film or the like in which a region for forming the element isolation region 101 is opened is formed on the silicon substrate 100, and reactive ion etching (RIE) or the like is performed using this mask material. Grooves are formed in the silicon substrate 100 by anisotropic etching. Then, an element isolation insulating film made of a silicon oxide film or the like is deposited in this groove by a chemical vapor deposition (CVD) method or the like. Then, etch back is performed by a chemical mechanical polishing (CMP) method or the like using the mask material as a stopper. After the etch back, the mask material is removed. In this way, the element isolation region 101 can be formed. Note that the upper surface of the element isolation region 101 is higher than the surface of the silicon substrate 100 by the thickness of the mask material.

  Note that the element isolation region 101 is formed in each of an imaging region A in which a plurality of unit pixel regions are arranged and a peripheral logic circuit region B provided around the imaging region in the solid-state imaging device. Here, the unit pixel region of the solid-state imaging device includes a color filter that transmits light of a specific wavelength, a photodiode that receives light that has passed through the color filter, generates a signal charge according to the amount of incident light, and a photodiode A region in which a MOS transistor for reading signal charges and the like is provided. In addition, the peripheral logic circuit region B of the solid-state imaging device is a region where a MOS transistor constituting a circuit that performs AD conversion and image processing is provided.

  In the following description, a MOS transistor provided in the imaging region A (unit pixel region) is referred to as a pixel transistor, and a MOS transistor provided in the peripheral logic circuit region B is referred to as a logic transistor. In addition, the gate electrode of the pixel transistor is referred to as a pixel gate electrode, and the gate electrode of the logic transistor is referred to as a logic gate electrode.

  As shown in FIG. 2, an insulating film 102 that becomes a gate insulating film of a transistor is formed on a silicon substrate 100. The insulating film 102 is a silicon oxynitride (SiON) film, for example. Then, an electrode film 103 to be a pixel gate electrode and a logic gate electrode is formed over the insulating film 102 and the element isolation region 101. The electrode film 103 is a polysilicon film having a thickness of about 185 nm deposited by, for example, a low pressure CVD (LPCVD) method.

  Next, the block film 104 is formed on the electrode film 103. The block film 104 is a film for preventing ions from passing through the pixel gate electrode and reaching the silicon substrate 100 in an ion implantation step for forming a diffusion layer of the pixel transistor to be performed later. The block film 104 is a silicon nitride film having a thickness of about 150 nm deposited by, for example, the LPCVD method.

  Subsequently, a photoresist is applied on the block film 104, and the photoresist is patterned so that a region where the pixel gate electrode in the imaging region A is provided remains to form a resist pattern 110.

  As shown in FIG. 3, using the resist pattern 110 as a mask, the block film 104 is etched away by the RIE method or the like. After detecting the end of the etching of the block film 104 using the waveform monitor, the etching conditions are switched, the electrode film 103 is etched using the resist pattern 110 as a mask, and the electrode film 103 is processed to a predetermined film thickness. Here, the predetermined film thickness is a film thickness required for the logic gate electrode, and is, for example, about 150 nm.

  As shown in FIG. 4, the resist pattern 110 is removed by wet etching. Next, a photoresist is applied on the electrode film 103, and the photoresist is patterned so that a region where the logic gate electrode in the peripheral logic circuit region B is provided remains, thereby forming a resist pattern 120.

  As shown in FIG. 5, the electrode film 103 is removed by the RIE method or the like using the block film 104 and the resist pattern 120 as a mask. Thus, the pixel gate electrode 103a and the logic gate electrode 103b having a smaller size (thin film thickness and shorter gate length) than the pixel gate electrode 103a can be formed.

  As shown in FIG. 6, the resist pattern 120 is removed by wet etching. Next, a photoresist is applied on the silicon substrate 100, and the photoresist is patterned so that a region where the pixel transistor in the imaging region A is provided is formed, thereby forming a resist pattern 130. Subsequently, ions are implanted into the surface portion of the silicon substrate 100 by ion implantation to form a diffusion layer (ion implantation layer) 105. The ion to be implanted is, for example, boron or phosphorus.

  Here, since the pixel gate electrode 103a is not thinned like the logic gate electrode 103b and has a large film thickness, even if the block film 104 is not thickened, ions penetrate the pixel gate electrode 103a. Reaching the silicon substrate 100 (the channel region of the pixel transistor) can be prevented. Accordingly, it is possible to prevent deterioration of the characteristics of the pixel transistor.

  As shown in FIG. 7, the resist pattern 130 is removed by wet etching. Next, a protective film 106 is formed on the surfaces of the silicon substrate 100, the pixel gate electrode 103a, and the logic gate electrode 103b. The protective film 106 is a silicon oxide film, for example. Then, the block film 104 is selectively wet etched with respect to the protective film 106 to remove the block film 104.

  Thereafter, as shown in FIG. 8, a stacked structure is formed by repeating deposition of the interlayer insulating film 141, formation of the contact 142, and formation of the wiring 143 by a known method. Then, the interlayer insulating film 141 in the imaging region A is etched to a thickness just above the wiring 143 to form a color filter 144 and a microlens 145. The color filter 144 transmits light of a specific wavelength. For example, three colors of R (red), G (green), and B (blue) form a set.

  A photodiode 146 is provided on the surface of the silicon substrate 100 below the color filter 144. The formation of the photodiode 146 has not been described in the above-described steps shown in FIGS. 1 to 7, but a resist pattern that opens only the photodiode 146 portion after the pixel gate electrode 103a is formed and before the block film 104 is removed. Then, ion implantation is performed on the silicon substrate 100, whereby an impurity layer to be the photodiode 146 can be formed. The impurity layer that becomes the photodiode 146 is configured by a pn junction including an n-type region and a p-type region.

  FIG. 8 is a schematic diagram and does not limit the structures of the imaging region A and the peripheral logic circuit region B. FIG.

  Thus, according to the present embodiment, it is possible to manufacture a solid-state imaging device in which the logic gate electrode 103b having a reduced thickness is formed, the peripheral logic circuit region B is miniaturized, and the characteristic deterioration of the pixel transistor is prevented. .

  (Comparative Example) A method of manufacturing a solid-state imaging device according to a comparative example will be described with reference to FIG. In addition, in the comparative example shown in FIG. 9, the same code | symbol is attached | subjected to the same part as embodiment shown in FIGS. 1-8, and description is abbreviate | omitted.

  The pixel gate electrode 203a in the comparative example is smaller in film thickness than the pixel gate electrode 103a in the above embodiment, and is about the same as the film thickness of the logic gate electrode 103b. In the comparative example, since the film thickness of the pixel gate electrode 103a is small, the block film 204 is thicker than the block film 104 in the above embodiment. Polysilicon constituting the logic gate electrode 203 a has higher ion permeation preventive properties than the block film 204. Therefore, in order to prevent ions from reaching the silicon substrate 100 to the same extent as in the above embodiment, the thickness of the block film 204 is increased more than the thickness of the logic gate electrode 203a. There is a need to. Therefore, the total thickness of the pixel gate electrode 203a and the block film 204 according to the comparative example is larger than the total thickness of the gate electrode 103a and the block film 104 in the above embodiment.

  As shown in FIG. 9, when forming a resist pattern 230 in which an area where the pixel transistor of the imaging region A is provided is formed in order to form the diffusion layer 205 of the pixel transistor by ion implantation, the pixel gate electrode 203a and the block Resist residue 231 is generated in a space portion having a high aspect ratio due to the large total film thickness of the film 204.

  When the resist residue 231 is generated, even if ion implantation is performed, only a part of the diffusion layer 205 of the pixel transistor is formed, and the pixel characteristics may be deteriorated.

  When the block film 204 is formed of a nitride film, the mask material (the protective film 106 in the above embodiment) formed when removing the block film 204 is an oxide film. Since the block film 204 is thickened, it is necessary to thicken the oxide film of the mask material. In general, a process for forming an oxide film is a high-temperature treatment, and forming a thick oxide film mask material leaves the transistor under a high temperature for a long time, which may deteriorate the characteristics of the transistor.

  In the case where the block film 204 is formed using an oxide film, even if the mask material is formed, the oxide film constituting the element isolation region 101 is also removed when the thickened block film 204 is removed. May deteriorate.

  Although it is conceivable that the block film 204 is not removed, in that case, the distance between the color filter provided in the imaging region A and the photodiode is increased, and the sensitivity characteristic of the photodiode is deteriorated.

  As described above, when the pixel gate electrode 203a is thinned in accordance with the logic gate electrode 103b and the block film 204 is thickened, the performance of the solid-state imaging device may be deteriorated.

  On the other hand, according to the above embodiment, the pixel gate electrode 103a is not thinned while the logic gate electrode 103b is thinned. Therefore, it is not necessary to thicken the block film 104. Therefore, it is possible to prevent deterioration of pixel characteristics and to make the peripheral logic circuit area fine.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

100 Silicon substrate 101 Element isolation region 102 Insulating film 103 Electrode film 103a Pixel gate electrode 103b Logic gate electrode 104 Block film 105 Diffusion layers 110, 120, 130 Resist pattern

Claims (5)

A solid-state imaging device manufacturing method comprising an imaging area in which a plurality of unit pixel areas are arranged, and a peripheral logic circuit area provided around the imaging area,
Forming an electrode film having a first thickness on a semiconductor substrate;
Forming a block film on the electrode film;
Forming a first resist pattern on a gate electrode formation region of the transistor in the unit pixel region on the block film;
Removing the block film using the first resist pattern as a mask;
Processing the electrode film into a second film thickness smaller than the first film thickness using the first resist pattern as a mask;
Removing the first resist pattern;
Forming a second resist pattern on a gate electrode formation region of a transistor in the peripheral logic circuit region on the block film having the second film thickness;
Removing the electrode film using the block film and the second resist pattern as a mask;
A method for manufacturing a solid-state imaging device. After the step of removing the electrode film,
Removing the second resist pattern;
Forming a third resist pattern in which a transistor formation region in the unit pixel region is opened on the semiconductor substrate;
Implanting ions into the semiconductor substrate in the transistor formation region using the first film thickness electrode film and the block film formed on the electrode film as a mask;
The method of manufacturing a solid-state imaging device according to claim 1, further comprising: After the step of implanting the ions,
Removing the third resist pattern;
Removing the block film;
Forming an insulating film on the semiconductor substrate;
Forming a color filter on the insulating film above the photodiode in the unit pixel region;
The method of manufacturing a solid-state imaging device according to claim 3, further comprising:   The method for manufacturing a solid-state imaging device according to claim 1, wherein the block film is a silicon nitride film or a silicon oxide film. A solid-state imaging device comprising: an imaging region in which a plurality of unit pixel regions are arranged; and a peripheral logic circuit region provided around the imaging region,
The unit pixel region is
A photodiode provided on the surface of the semiconductor substrate;
A color filter provided above the photodiode;
A first transistor in which a signal charge of the photodiode is taken out and a gate electrode has a first film thickness;
Have
The peripheral logic circuit region includes a second transistor in which a gate electrode has a second film thickness that is smaller than the first film thickness.

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