TWI464856B - 已單離晶粒堆疊封裝件之逆取放定位方法 - Google Patents

已單離晶粒堆疊封裝件之逆取放定位方法 Download PDF

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TWI464856B
TWI464856B TW101123781A TW101123781A TWI464856B TW I464856 B TWI464856 B TW I464856B TW 101123781 A TW101123781 A TW 101123781A TW 101123781 A TW101123781 A TW 101123781A TW I464856 B TWI464856 B TW I464856B
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Kai Jun Chang
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Powertech Technology Inc
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    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Description

已單離晶粒堆疊封裝件之逆取放定位方法
本發明係有關於半導體裝置之製造，特別係有關於一種已單離晶粒堆疊封裝件之逆取放定位方法。
多晶片堆疊封裝係為一種新的高密度封裝技術，即在一封裝構件內封裝有多顆相互堆疊之晶片。目前作法係將晶片逐一堆疊在一基板上再予以封裝與測試，然而基板的存在會增加封裝結構的表面接合面積與厚度。
為了減少多晶片堆疊封裝構造之尺寸，有人嘗試省略基板的方式製作，在晶圓等級進行多片晶圓貼合，經晶圓切割之後製成無基板晶粒堆疊體(或稱晶粒立方體，dice cube)，如美國公開專利第2011/0074017號所揭示之技術者。然而，一晶圓內會有不良晶片的產生並且位置不固定，以晶圓對準晶圓的方式會使得無基板晶粒堆疊體的不良率大幅提高。此外，當基板省略時，多晶片堆疊封裝構造之對外導接電極與測試電極的間距將明顯縮小，由原本的數百微米間距縮小到一百微米間距以下，將無法使用原有的封裝測試機台內的測試針(pogo pin)進行測試。目前的作法有二，一為先不測試待上板之後，再進行模組測試，故無法預先確定堆疊晶片之間的接點是否良好；二為先將無基板晶粒堆疊體在單離後結合在一設有扇出電路與扇出端子之轉接基板(通常材質為矽)，再裝載至封裝測試機台內，以進行測試，不但 製程複雜並且測試成本提高。目前對於已單離晶粒堆疊封裝件缺乏在上板前之測試方法。
為了解決上述之問題，本發明之主要目的係在於一種已單離晶粒堆疊封裝件之逆取放定位方法，能符合對已單離晶粒堆疊封裝件進行微間隙探觸測試之要求，且不需要特殊的載具與治具變更。
本發明之次一目的係在於一種已單離晶粒堆疊封裝件之逆取放定位方法，能在上板之前先行晶圓級測試已單離晶粒堆疊封裝件的優劣，達到以低成本方式防止已單離晶粒堆疊封裝件的誤用。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種已單離晶粒堆疊封裝件之逆取放定位方法。首先，提供複數個晶粒堆疊封裝件，每一晶粒堆疊封裝件係包含複數個上下堆疊之晶粒並具有一正面、一背面以及複數個位在該正面上之測試電極；之後，在一晶粒取放裝置內提供一晶圓載具以及一在該晶圓載具下方之定位參考晶圓，該定位參考晶圓係設有至少一X軸標線與至少一Y軸標線；最後，依據該X軸標線與該Y軸標線，逆向取出並放置該些晶粒堆疊封裝件，使其固定於該晶圓載具上，使得該些晶粒堆疊封裝件可進行微間隙探觸之晶圓等級測試。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述之逆取放定位方法中，該X軸標線與該Y軸標線係可為不貫穿該定位參考晶圓之晶圓切割線。
在前述之逆取放定位方法中，該定位參考晶圓之本體相對於該X軸標線與該Y軸標線係可更具有透光性。
在前述之逆取放定位方法中，該定位參考晶圓之本體相對於該X軸標線與該Y軸標線係可更具有光反射性。
在前述之逆取放定位方法中，該晶圓載具係可由一O形晶圓支撐環與一貼附於該O形晶圓支撐環之晶圓固定膠帶所構成。
在前述之逆取放定位方法中，在上述提供該些晶粒堆疊封裝件之步驟中，該些晶粒堆疊封裝件係可貼附於一黏著膠帶上，而該黏著膠帶係預先設置於一長條形膠帶載具之一開口中，而模擬為一基板條。
在前述之逆取放定位方法中，上述提供該些晶粒堆疊封裝件之步驟係可包含以下步驟：設置複數個無基板晶粒堆疊體於該黏著膠帶上，每一無基板晶粒堆疊體係由該些晶粒堆疊所組成，並在兩兩上下相鄰晶粒之間係各形成有一晶粒堆疊間隙，其中該些測試電極係相對遠離該黏著膠帶；以及形成一填充膠體於該黏著膠帶上，以填滿該些晶粒堆疊間隙。
在前述之逆取放定位方法中，上述提供該些晶粒堆疊封裝件之步驟係可更包含：在形成該填充膠體之後之一 去溢膠步驟，以移除該填充膠體超出該些無基板晶粒堆疊體之溢膠部位。
在前述之逆取放定位方法中，每一晶粒內係可設有複數個矽穿孔，並且該些晶粒堆疊封裝件於該些晶粒堆疊間隙內係可設有複數個互連凸塊，其係電性導通該些矽穿孔。
在前述之逆取放定位方法中，在上述逆向取出並放置該些晶粒堆疊封裝件之步驟中，該些晶粒堆疊封裝件係可不遮蓋該X軸標線與該Y軸標線。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之一較佳實施例，一種已單離晶粒堆疊封裝件之逆取放定位方法舉例說明於第1A至1E圖各步驟之元件截面示意圖。依該取放定位方法，首先提供複數個晶粒堆疊封裝件100，第2圖係為所提供之複數個晶粒堆疊封裝件100之正面示意圖，而第3A至3D圖係關於提供複數個晶粒堆疊封裝件100之細部次步驟之元件 截面示意圖。
如第1A及2圖所示，提供複數個晶粒堆疊封裝件100，其係已切割成單體化，較佳為無基板型態。每一晶粒堆疊封裝件100係包含複數個上下堆疊之晶粒110，該些晶粒110係可由同一晶圓切單後所構成，通常該些晶粒110之本體係為半導體材質，該些晶粒110之主動表面係已製作好所需要的積體電路元件，其功能例如可為記載體、邏輯電路或微處理器電路，一般係為非揮發性記載體。並且，每一晶粒堆疊封裝件100係具有一正面102、一背面103以及複數個位在該正面102上之測試電極130，該正面102係為對外之表面接合面，該背面103係為該正面102之相對表面。在本實施例中，該正面102係可由其中一晶粒之主動表面所構成，而該背面103係可由其中一晶粒之非主動表面所構成。該些測試電極130係為連接至該些晶粒110內部積體電路元件之測試用電極。在本實施例中，該些測試電極130係為晶片銲墊，或可為凸塊狀。更具體地，每一晶粒110內係可設有複數個矽穿孔111(Through Silicon Via,TSV)，並且該些上下堆疊之晶粒110之間的晶粒堆疊間隙120內係可設有複數個互連凸塊140，其係電性導通該些矽穿孔111。在本實施例中，每一晶粒堆疊封裝件100係可更具有複數個位在該正面102上之外接凸塊141，例如銅柱、銲球或金屬凸塊，可與該些互連凸塊140在晶粒上位置、材質與尺寸上為實質相同，並由利用重配置 線路層(圖中未繪出)電性連接該些外接凸塊141至該些測試電極130。此外，該些測試電極130之間距係介於60~100微米，本發明之逆取放定位方法特別應用於該些測試電極130之間距不大於100微米之場合，而該些外接凸塊141之間距係可等於或大於該些測試電極130之間距。在一變化實施例中，該些外接凸塊141係可省略，直接以該些測試電極130作為該晶粒堆疊封裝件100之對外電極。該些晶粒堆疊封裝件100之製造係可利用既有的半導體封裝設備。在本步驟中，該些晶粒堆疊封裝件100係可貼附於一黏著膠帶310上，而該黏著膠帶310係預先設置於一長條形膠帶載具311之一開口312中，而模擬為一基板條，可進行無基板之半導體封裝作業。
之後，如第1B圖所示，在一晶粒取放裝置210內提供一晶圓載具220以及一在該晶圓載具220下方之定位參考晶圓230，該定位參考晶圓230係設有至少一X軸標線231與至少一Y軸標線232。該晶粒取放裝置210係具有一在特定軌道212上移動之抓取器211，傳統的取放方式為將一晶圓中晶粒取出並放置於一基板、一晶片包裝帶或一晶片盒，本發明則是逆向將該些晶粒堆疊封裝件100抓取並放置到該晶圓載具220上。如第4圖所示，該晶圓載具220為傳統的晶圓治具，在本實施例中，該晶圓載具220係可由一O形晶圓支撐環221與一貼附於該O形晶圓支撐環221之晶圓固定膠帶222所構成。其中，該晶圓固定膠帶222之表面係具有一感光性 黏著層，用以黏著該些晶粒堆疊封裝件100之背面103，該感光性黏著層之特性為未照光前具有黏著力，在照射特定波長之光線後該感光性黏著層將失去黏著力。如第5圖所示，該定位參考晶圓230則為僅供定位參考並能重覆使用之治具。該定位參考晶圓230係垂直向位於該晶圓載具220之下方，可產生類似複寫謄抄的對位參考效果，且不會在該晶圓載具220上造成對位痕跡。該定位參考晶圓230在尺寸外形上係模擬成一晶圓，例如8吋、12吋或16吋晶圓。在本實施例中，該X軸標線231與該Y軸標線232係可為不貫穿該定位參考晶圓230之晶圓切割線，即延伸至該定位參考晶圓230之周邊，以模擬晶圓切割線，可輕易地被該晶粒取放裝置210定義為該晶圓載具220上的晶圓切割線，而具有高度準確的定位效果。該X軸標線231與該Y軸標線232較佳地係可為半蝕刻之直線凹槽，可供光線照射之；或者，該X軸標線231與該Y軸標線232亦可為直線狀墨線。較佳地，該定位參考晶圓230之本體相對於該X軸標線231與該Y軸標線232係可更具有透光性，例如一玻璃圓盤，可利用由下往上的光線使該X軸標線231與該Y軸標線232投射在該晶圓載具220，以在該晶圓載具220規劃出虛擬之元件設置區。或者，該定位參考晶圓230之本體相對於該X軸標線231與該Y軸標線232係可更具有光反射性，例如一半導體圓盤，以使該X軸標線231與該Y軸標線232由上往下觀視時更為明顯易辨。在不 同實施例中，該定位參考晶圓230之本體係可為可撓性(flexible)，例如，軟性電路板之可撓性層或是紙類，可輕易被吸附固定於該晶粒取放裝置210內。
如第1C圖所示，該些晶粒堆疊封裝件100裝載在該晶粒取放裝置210內。最後，如第1D與1E圖所示，依據該X軸標線231與該Y軸標線232，利用該抓取器211逐一抓取該些晶粒堆疊封裝件100並由該模擬為基板條之膠帶載具311往該晶圓載具220移動，逆向取出並放置該些晶粒堆疊封裝件100，使其固定於該晶圓載具220上。如第6圖所示，該些晶粒堆疊封裝件100排列於該晶圓載具220的方式宛如在同一晶圓中的晶粒位置。故該些晶粒堆疊封裝件100可進行微間隙探觸之晶圓等級測試。在本步驟中，固定於該晶圓載具220上之該些晶粒堆疊封裝件100係可不遮蓋該X軸標線231與該Y軸標線232，可作為固定後再次定位檢查。
此外，關於該定位參考晶圓230之製作係可參閱第7A至7C圖。首先如第7A圖所示，該定位參考晶圓230之主體係為一尺寸可如12吋晶圓之空白玻璃圓盤，上下表面皆為乾淨平滑；如第7B圖所示，利用一定位光罩360對準在該定位參考晶圓230上，以蝕刻或是沉積方式在該定位參考晶圓230之上表面製作出該X軸標線231與該Y軸標線232(如第7C圖所示)，該X軸標線231與該Y軸標線232之形成係亦可利用不同於該定位參考晶圓230本體材料之它物質的鑲嵌或是凹穴填埋所形 成。更具體地，該定位參考晶圓230在該些元件設置區213之外之上表面或下表面之邊緣係可建置有一晶圓辨識碼233，以供條碼系統(bar code system)辨識。此外，本發明之該X軸標線231與該Y軸標線232雖以成為晶圓切割線為較佳，亦可構成不同之定位圖樣(alignment pattern)，例如中央定位標記、角隅定位標記或周邊定位標記218。
如第8圖所示，裝載已搭載該些晶粒堆疊封裝件100之晶圓載具220於一晶圓測試機350內。該些晶粒堆疊封裝件100係完全模擬出由一晶圓切割出且固定在晶圓切割膠帶之晶粒位置，便可無障礙地沿用晶圓測試機之既有裝載機構而裝載進入至該晶圓測試機350內並進行準確定位。利用該晶圓測試機350之複數個晶圓測試探針351探觸該些測試電極130，以電性測試該些晶粒堆疊封裝件100。其中該些晶圓測試探針351係安裝於一探針卡352(probe card)中。該些晶粒堆疊封裝件100不需要搭載在設有扇出電路與扇出端子之轉接基板而能進行晶圓等級測試，以確認該些晶粒110之間的電性導通(即該些互連凸塊140之接合)是否良好。因此，本發明之已單離晶粒堆疊封裝件之逆取放定位方法亦能符合對已單離晶粒堆疊封裝件進行微間隙探觸測試之要求，且不需要特殊的載具與治具變更，藉以在上板前預先挑出或剃除不良的晶粒堆疊封裝件。
本發明之逆取放定位方法參閱第3A至3D圖進一步 說明上述提供該些晶粒堆疊封裝件100之步驟之細部次步驟。
如第3A圖所示，在切割之時與切割之後，複數個晶粒110係黏貼於一晶圓切割膠帶320上，而該晶圓切割膠帶320係黏貼在一晶圓支撐環中(圖中未繪出)。該些晶粒110係可形成於同一晶圓，在切割過程利用一晶圓切割刀具321切割該晶圓之切割道以形成該些晶粒110。在經過晶圓級測試之後，已知良好的晶粒110會被分類與收集。
如第3B圖所示，設置複數個無基板晶粒堆疊體101於該黏著膠帶310上，每一無基板晶粒堆疊體101係由該些晶粒110堆疊所組成，並在兩兩上下相鄰晶粒110之間係各形成有一晶粒堆疊間隙120，其中該些測試電極130係相對遠離該黏著膠帶310，而該些互連凸塊140係位於該些晶粒堆疊間隙120內，以電性導通該些矽穿孔111。
如第3C圖所示，形成一填充膠體150於該黏著膠帶310上，以填滿該些晶粒堆疊間隙120，進而密封該些互連凸塊140。可由一塗膠針頭330提供該填充膠體150，該填充膠體150係形成於該黏著膠帶310上，並在適當的溫度與時間能產生毛細作用之條件下，使該填充膠體150填滿該些晶粒堆疊間隙120，接著，以加熱的預烘烤(pre-curing)方式使該填充膠體150略為固化成形。此外，該填充膠體150除了可以是底部填充膠，亦可為黏 晶材料、非導電性膠(NCP)或是異方性導電膠(ACP)。上述次步驟之晶粒堆疊與塗膠之具體實施技術可參考美國公開第2011/0057327號中第8A與8B圖之相關說明，故可以利用既有的半導體封裝設備之覆晶接合機與點膠機(或模封機)據以實施。此外，該膠帶載具311亦可作為傳送該些無基板晶粒堆疊體101進入烘烤爐之搭載治具
此外，如第3D與1A圖所示，上述提供該些晶粒堆疊封裝件100之步驟係可更包含：在形成該填充膠體150之後之一去溢膠步驟，以移除該填充膠體150超出該些無基板晶粒堆疊體101之溢膠部位151。較佳地，在上述去溢膠步驟之後，該填充膠體150仍可包覆該些晶粒110之複數個側面112。達成此一結構之具體技術手段之一為，該填充膠體150係可為正光阻型，而該去溢膠步驟係為對該填充膠體150之溢膠部位151進行曝光顯影。如第2D圖所示，可利用一曝光光罩340對該填充膠體150之溢膠部位151進行曝光顯影，該曝光光罩340之遮蓋區圖案略大於該些晶粒110尺寸，該填充膠體150之溢膠部位151將會被光照射而產生反應，顯影液可溶解移除該填充膠體150之溢膠部位151，同時，該些晶粒110之側面112仍被該填充膠體150所包覆。當該填充膠體150以加熱烘烤的方式後固化(post curing)之後，即可構成上述之該些晶粒堆疊封裝件100。或者，達成該些晶粒110之側面112被該填充膠體150所包覆之結構之另一具體技術手段為，可利用雷射切割工具切 除該溢膠部位151。
因此，本發明之已單離晶粒堆疊封裝件之逆取放定位方法係使用目前的晶圓測試機而能達成對無基板或晶片尺寸之已單離晶粒堆疊封裝件進行微間隙探觸測試而不需要電性轉接基板，以提供測試出良好的已單離晶粒堆疊封裝件，以低成本方式防止不良已單離晶粒堆疊封裝件的誤用。
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。
100‧‧‧晶粒堆疊封裝件
101‧‧‧無基板晶粒堆疊體
102‧‧‧正面
103‧‧‧背面
110‧‧‧晶粒
111‧‧‧矽穿孔
112‧‧‧側面
120‧‧‧晶粒堆疊間隙
130‧‧‧測試電極
140‧‧‧互連凸塊
141‧‧‧外接凸塊
150‧‧‧填充膠體
151‧‧‧溢膠部位
210‧‧‧晶粒取放裝置
211‧‧‧抓取器
212‧‧‧軌道
220‧‧‧晶圓載具
221‧‧‧O形晶圓支撐環
222‧‧‧晶圓固定膠帶
230‧‧‧定位參考晶圓
231‧‧‧X軸標線
232‧‧‧Y軸標線
233‧‧‧晶圓辨識碼
310‧‧‧黏著膠帶
311‧‧‧膠帶載具
312‧‧‧開口
320‧‧‧晶圓切割膠帶
321‧‧‧晶圓切割刀具
330‧‧‧塗膠針頭
340‧‧‧曝光光罩
350‧‧‧晶圓測試機
351‧‧‧晶圓測試探針
352‧‧‧探針卡
360‧‧‧定位光罩
第1A至1E圖：依據本發明之一較佳實施例，繪示在一種已單離晶粒堆疊封裝件之逆取放定位方法中各主要步驟之元件截面示意圖。
第2圖：依據本發明之一較佳實施例，繪示在一種已單離晶粒堆疊封裝件之逆取放定位方法中所提供之複數個晶粒堆疊封裝件之正面示意圖。
第3A至3D圖：依據本發明之一較佳實施例，繪示在一種已單離晶粒堆疊封裝件之逆取放定位方法中用以提供複數個晶粒堆疊封裝件之細部次步驟之元件截面示意圖。
第4圖：依據本發明之一較佳實施例，繪示在一種已單離晶粒堆疊封裝件之逆取放定位方法中所提供之晶圓載具之正面示意圖。
第5圖：依據本發明之一較佳實施例，繪示在一種已單離晶粒堆疊封裝件之逆取放定位方法中所提供之定位參考晶圓之正面示意圖。
第6圖：繪示在一種已單離晶粒堆疊封裝件之逆取放定位方法中逆向取出並放置該些晶粒堆疊封裝件之正面示意圖。
第7A至7C圖：依據本發明之一較佳實施例，繪示該取放定位方法中所使用之定位參考晶圓在製造過程中之正面示意圖。
第8圖：依據本發明之一較佳實施例，以固定於該晶圓載具上晶粒堆疊封裝件進行晶圓級測試之截片面示意圖。
100‧‧‧晶粒堆疊封裝件
210‧‧‧晶粒取放裝置
211‧‧‧抓取器
212‧‧‧軌道
220‧‧‧晶圓載具
221‧‧‧O形晶圓支撐環
222‧‧‧晶圓固定膠帶
230‧‧‧定位參考晶圓
232‧‧‧Y軸標線
310‧‧‧黏著膠帶
311‧‧‧膠帶載具

Claims (10)

  1. 一種已單離晶粒堆疊封裝件之逆取放定位方法，包含：提供複數個晶粒堆疊封裝件，每一晶粒堆疊封裝件係包含複數個上下堆疊之晶粒並具有一正面、一背面以及複數個位在該正面上之測試電極；在一晶粒取放裝置內提供一晶圓載具以及一在該晶圓載具下方之定位參考晶圓，該定位參考晶圓係設有至少一X軸標線與至少一Y軸標線；以及依據該X軸標線與該Y軸標線，逆向取出並放置該些晶粒堆疊封裝件，使其固定於該晶圓載具上。
  2. 依據申請專利範圍第1項之已單離晶粒堆疊封裝件之逆取放定位方法，其中該X軸標線與該Y軸標線係為不貫穿該定位參考晶圓之晶圓切割線。
  3. 依據申請專利範圍第1項之已單離晶粒堆疊封裝件之逆取放定位方法，其中該定位參考晶圓之本體相對於該X軸標線與該Y軸標線係更具有透光性。
  4. 依據申請專利範圍第1項之已單離晶粒堆疊封裝件之逆取放定位方法，其中該定位參考晶圓之本體相對於該X軸標線與該Y軸標線係更具有光反射性。
  5. 依據申請專利範圍第1項之已單離晶粒堆疊封裝件之逆取放定位方法，其中該晶圓載具係由一O形晶圓支撐環與一貼附於該O形晶圓支撐環之晶圓固定膠帶所構成。
  6. 依據申請專利範圍第1項之已單離晶粒堆疊封裝件之逆取放定位方法，其中在上述提供該些晶粒堆疊封裝件之步驟中，該些晶粒堆疊封裝件係貼附於一黏著膠帶上，而該黏著膠帶係預先設置於一長條形膠帶載具之一開口中，而模擬為一基板條。
  7. 依據申請專利範圍第6項之已單離晶粒堆疊封裝件之逆取放定位方法，其中上述提供該些晶粒堆疊封裝件之步驟係包含以下步驟：設置複數個無基板晶粒堆疊體於該黏著膠帶上，每一無基板晶粒堆疊體係由該些晶粒堆疊所組成，並在兩兩上下相鄰晶粒之間係各形成有一晶粒堆疊間隙，其中該些測試電極係相對遠離該黏著膠帶；以及形成一填充膠體於該黏著膠帶上，以填滿該些晶粒堆疊間隙。
  8. 依據申請專利範圍第7項之已單離晶粒堆疊封裝件之逆取放定位方法，其中上述提供該些晶粒堆疊封裝件之步驟係更包含：在形成該填充膠體之後之一去溢膠步驟，以移除該填充膠體超出該些無基板晶粒堆疊體之溢膠部位。
  9. 依據申請專利範圍第1項之已單離晶粒堆疊封裝件之逆取放定位方法，其中每一晶粒內係設有複數個矽穿孔，並且該些晶粒堆疊封裝件於該些晶粒堆疊間隙內係設有複數個互連凸塊，其係電性導通該些 矽穿孔。
  10. 依據申請專利範圍第1項之已單離晶粒堆疊封裝件之逆取放定位方法，其中在上述逆向取出並放置該些晶粒堆疊封裝件之步驟中，該些晶粒堆疊封裝件係不遮蓋該X軸標線與該Y軸標線。
TW101123781A 2012-07-02 2012-07-02 已單離晶粒堆疊封裝件之逆取放定位方法 TWI464856B (zh)

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Citations (3)

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Publication number Priority date Publication date Assignee Title
US20070037320A1 (en) * 2003-03-17 2007-02-15 National Semiconductor Corporation Multichip packages with exposed dice
US20110147911A1 (en) * 2009-12-22 2011-06-23 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US20110300647A1 (en) * 2010-06-08 2011-12-08 Stmicroelectronics (Tours) Sas Method for manufacturing semiconductor chips from a semiconductor wafer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037320A1 (en) * 2003-03-17 2007-02-15 National Semiconductor Corporation Multichip packages with exposed dice
US20110147911A1 (en) * 2009-12-22 2011-06-23 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US20110300647A1 (en) * 2010-06-08 2011-12-08 Stmicroelectronics (Tours) Sas Method for manufacturing semiconductor chips from a semiconductor wafer

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