TWI455247B - Active device and manufacturing method thereof - Google Patents

Active device and manufacturing method thereof Download PDF

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TWI455247B
TWI455247B TW099137493A TW99137493A TWI455247B TW I455247 B TWI455247 B TW I455247B TW 099137493 A TW099137493 A TW 099137493A TW 99137493 A TW99137493 A TW 99137493A TW I455247 B TWI455247 B TW I455247B
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electrode
layer
channel layer
ohmic contact
forming
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TW099137493A
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TW201220432A (en
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Isaac Wing-Tak Chan
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Ind Tech Res Inst
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Description

主動元件及其製造方法Active component and method of manufacturing same

本發明是有關於一種主動元件及其製造方法,且特別是有關於一種可應用於主動元件面板(active-matrix panel)之主動元件及其製造方法。The present invention relates to an active component and a method of fabricating the same, and more particularly to an active component that can be applied to an active-matrix panel and a method of fabricating the same.

近年來,由於半導體製程技術的進步,主動元件的製造越趨容易、快速。主動元件的應用廣泛,例如電腦晶片、手機晶片或是主動元件顯示器等。以主動元件顯示器為例,主動元件可作為充電或放電的開關。In recent years, due to advances in semiconductor process technology, the manufacture of active components has become easier and faster. Active components are used in a wide range of applications, such as computer chips, cell phone chips, or active component displays. Taking an active component display as an example, the active component can be used as a charge or discharge switch.

傳統主動元件包括底電極、覆蓋底電極之絕緣層、位於絕緣層上之非晶矽層以及摻雜非晶矽層以及位於摻雜非晶矽層上之第一電極以及第二電極。當主動元件的底電極施加一正底電極電壓時,非晶矽層中會形成電子通道。另一方面,施加於第一電極的資料電壓,將以電流的方式由電子通道流到第二電極,且此電流會隨著底電極電壓上升而增加。當停止施加電壓於底電極時,非晶矽層中之電子通道便會消失。換言之,第一電極與第二電極之間即為斷路。The conventional active device includes a bottom electrode, an insulating layer covering the bottom electrode, an amorphous germanium layer on the insulating layer, and a doped amorphous germanium layer and a first electrode and a second electrode on the doped amorphous germanium layer. When a bottom electrode voltage is applied to the bottom electrode of the active device, an electron channel is formed in the amorphous germanium layer. On the other hand, the data voltage applied to the first electrode will flow from the electron channel to the second electrode in a current manner, and this current will increase as the voltage of the bottom electrode rises. When the application of voltage to the bottom electrode is stopped, the electron channel in the amorphous germanium layer disappears. In other words, there is an open circuit between the first electrode and the second electrode.

值得注意的是,為了使主動元件顯示器具有高可靠度以及高顯示品質,所述主動元件在開啟狀態需具有高通過電流且於主動元件之開啟狀態需具有低漏電流。然而,上述傳統主動元件已經無法滿足目前顯示器對於高電流以及低漏電之需求。It is worth noting that in order for the active device display to have high reliability and high display quality, the active device needs to have a high through current in the on state and a low leakage current in the on state of the active device. However, the above conventional active components have been unable to meet the current display requirements for high current and low leakage.

本發明提供一種主動元件及其製造方法,其於主動元件之開啟狀態時具有高通過電流,且於主動元件之開啟狀態時具有低漏電流。The present invention provides an active device and a method of fabricating the same that have a high pass current when the active device is in an open state and a low leakage current when the active device is in an open state.

本發明提出一種主動元件的製造方法,其包括在一基板上形成一第一底電極以及一第二底電極。形成一第一絕緣層以覆蓋第一底電極與該第二底電極。在第一底電極上方之第一絕緣層上形成一第一通道層且於第二底電極上方之第一絕緣層上形成第二通道層。在第一通道層及第二通道層上形成第二絕緣層,其中第二絕緣層暴露出一部分的第一通道層以及一部分的第二通道層。在第一通道層上方形成一第一導電圖案,第一導電圖案包括一第一電極、一第一頂電極以及一第二電極,其中第一電極及第二電極與暴露出的第一通道層電性連接。在第二通道層上方形成一第二導電圖案,第二導電圖案包括一第三電極、一第二頂電極以及一第四電極,其中第三電極及第四電極與暴露出的第二通道層電性連接,且第三電極與第二電極電性連接。The invention provides a method for manufacturing an active device, which comprises forming a first bottom electrode and a second bottom electrode on a substrate. A first insulating layer is formed to cover the first bottom electrode and the second bottom electrode. A first channel layer is formed on the first insulating layer above the first bottom electrode and a second channel layer is formed on the first insulating layer above the second bottom electrode. A second insulating layer is formed on the first channel layer and the second channel layer, wherein the second insulating layer exposes a portion of the first channel layer and a portion of the second channel layer. Forming a first conductive pattern over the first channel layer, the first conductive pattern includes a first electrode, a first top electrode, and a second electrode, wherein the first electrode and the second electrode and the exposed first channel layer Electrical connection. Forming a second conductive pattern over the second channel layer, the second conductive pattern includes a third electrode, a second top electrode, and a fourth electrode, wherein the third electrode and the fourth electrode and the exposed second channel layer The electrical connection is electrically connected, and the third electrode is electrically connected to the second electrode.

本發明另提出一種主動元件的製造方法,包括在一基板上形成一底電極。形成一第一絕緣層以覆蓋底電極。在第一底電極上方之第一絕緣層上形成一通道層。在通道層上形成一第二絕緣層,其中第二絕緣層暴露出一部分的通道層。在通道層上方形成一導電圖案,導電圖案包括一第一電極、一頂電極以及一第二電極,其中第一電極及第二電極與暴露出的通道層電性連接。The invention further provides a method of manufacturing an active device, comprising forming a bottom electrode on a substrate. A first insulating layer is formed to cover the bottom electrode. A channel layer is formed on the first insulating layer above the first bottom electrode. A second insulating layer is formed on the channel layer, wherein the second insulating layer exposes a portion of the channel layer. A conductive pattern is formed over the channel layer, the conductive pattern includes a first electrode, a top electrode, and a second electrode, wherein the first electrode and the second electrode are electrically connected to the exposed channel layer.

本發明提出一種主動元件,其包括一第一底電極以及一第二底電極,位於一基板上;一第一絕緣層,覆蓋第一底電極以及第二底電極;一第一通道層以及一第二通道層,分別位於第一底電極以及第二底電極上方之第一絕緣層上;一第二絕緣層,位於第一通道層以及第二通道層上,且暴露出一部分的第一通道層以及一部分的第二通道層;一第一導電圖案,位於第一通道層上,其中第一導電圖案包括一第一電極、一第一頂電極以及一第二電極,其中第一電極及第二電極與暴露出的第一通道層電性連接;以及一第二導電圖案,位於第二通道層上,其中第二導電圖案包括一第三電極、一第二頂電極以及一第四電極,其中第三電極與第四電極與暴露出的第二通道層電性連接,且第三電極與第二電極電性連接。The present invention provides an active device comprising a first bottom electrode and a second bottom electrode on a substrate; a first insulating layer covering the first bottom electrode and the second bottom electrode; a first channel layer and a a second channel layer respectively located on the first insulating layer above the first bottom electrode and the second bottom electrode; a second insulating layer on the first channel layer and the second channel layer, and exposing a portion of the first channel a layer and a portion of the second channel layer; a first conductive pattern on the first channel layer, wherein the first conductive pattern includes a first electrode, a first top electrode, and a second electrode, wherein the first electrode and the first The second electrode is electrically connected to the exposed first channel layer; and a second conductive pattern is disposed on the second channel layer, wherein the second conductive pattern comprises a third electrode, a second top electrode and a fourth electrode. The third electrode and the fourth electrode are electrically connected to the exposed second channel layer, and the third electrode is electrically connected to the second electrode.

本發明另提出一種主動元件,其包括一底電極,位於一基板上;一第一絕緣層,覆蓋底電極;一通道層,位於第一底電極上方之第一絕緣層上;一第二絕緣層,位於通道層上,其中第二絕緣層暴露出一部分的通道層;以及一導電圖案,其包括一第一電極、一頂電極以及一第二電極,其中第一電極及第二電極與暴露出的通道層電性連接。The invention further provides an active device comprising a bottom electrode on a substrate; a first insulating layer covering the bottom electrode; a channel layer on the first insulating layer above the first bottom electrode; and a second insulating layer a layer on the channel layer, wherein the second insulating layer exposes a portion of the channel layer; and a conductive pattern including a first electrode, a top electrode, and a second electrode, wherein the first electrode and the second electrode are exposed The channel layer is electrically connected.

基於上述,由於本發明之主動元件具有底電極以及頂電極,因此可使底電極與通道層之間以及在頂電極與通道層之間形成兩道電子通道。因而,本發明之主動元件相較於傳統主動元件具有高電流以及低漏電之功效。Based on the above, since the active device of the present invention has a bottom electrode and a top electrode, two electron paths can be formed between the bottom electrode and the channel layer and between the top electrode and the channel layer. Thus, the active device of the present invention has high current and low leakage effects compared to conventional active components.

為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖1至圖7是根據本發明一實施例之具有主動元件之畫素結構的製造流程剖面示意圖。1 to 7 are schematic cross-sectional views showing a manufacturing process of a pixel structure having an active device according to an embodiment of the present invention.

請參照圖1,首先提供一基板100,基板100具有主動元件區T、電容器區C以及畫素電極區P。基板100可為硬質基板、軟性基板、透明基板或是不透明基板。根據本發明之一實施例,基板100之表面上可進一步形成緩衝層102,其材質例如是氧化矽或是氮化矽,但本發明不限於上述材料。之後,在畫素電極區P中的緩衝層102上形成畫素電極104。畫素電極104可為透明電極層、反射電極層或是半穿透半反射式電極層。Referring to FIG. 1, first, a substrate 100 having an active device region T, a capacitor region C, and a pixel electrode region P is provided. The substrate 100 can be a rigid substrate, a flexible substrate, a transparent substrate, or an opaque substrate. According to an embodiment of the present invention, the buffer layer 102 may be further formed on the surface of the substrate 100, and the material thereof is, for example, tantalum oxide or tantalum nitride, but the present invention is not limited to the above materials. Thereafter, the pixel electrode 104 is formed on the buffer layer 102 in the pixel electrode region P. The pixel electrode 104 can be a transparent electrode layer, a reflective electrode layer or a transflective electrode layer.

請參照圖2,在基板100之主動元件區T中形成底電極106a以及底電極106c。根據本發明之一實施例,在形成底電極106a以及底電極106c時,更包括同時在基板100上形成連接層106b。此外,此時更包括在電容器區C中形成電容下電極106d。形成上述底電極106a、底電極106bc、連接層106b以及電容下電極106d之方法例如是採用沈積程序以及微影與蝕刻程序來達成。Referring to FIG. 2, a bottom electrode 106a and a bottom electrode 106c are formed in the active device region T of the substrate 100. According to an embodiment of the present invention, when the bottom electrode 106a and the bottom electrode 106c are formed, it is further included to form the connection layer 106b on the substrate 100 at the same time. Further, at this time, it is further included that the capacitor lower electrode 106d is formed in the capacitor region C. The method of forming the bottom electrode 106a, the bottom electrode 106bc, the connection layer 106b, and the capacitor lower electrode 106d is achieved, for example, by a deposition process and a lithography and etching process.

請參照圖3,在基板100上形成絕緣層108,以覆蓋底電極106a、底電極106c、連接層106b以及電容下電極106d。絕緣層108之材質可為氧化矽或是氮化矽,但本發明不限於上述材料。接著,在底電極106a上方之絕緣層108上形成通道層110以及絕緣層111,並且於底電極106c上方之絕緣層108上形成通道層112以及絕緣層113。形成通道層110與絕緣層111以及形成通道層112與絕緣層113之方法例如是採用沈積程序以及微影與蝕刻程序來達成。根據本實施例,通道層110以及通道層112之材質包括非晶矽或是微晶矽,但本發明不限於上述材料。絕緣層111,113之材質可為氧化矽或是氮化矽,但本發明不限於上述材料。Referring to FIG. 3, an insulating layer 108 is formed on the substrate 100 to cover the bottom electrode 106a, the bottom electrode 106c, the connection layer 106b, and the capacitor lower electrode 106d. The material of the insulating layer 108 may be tantalum oxide or tantalum nitride, but the invention is not limited to the above materials. Next, a channel layer 110 and an insulating layer 111 are formed on the insulating layer 108 over the bottom electrode 106a, and a channel layer 112 and an insulating layer 113 are formed on the insulating layer 108 over the bottom electrode 106c. The method of forming the channel layer 110 and the insulating layer 111 and forming the channel layer 112 and the insulating layer 113 is achieved, for example, by a deposition process and a lithography and etching process. According to the present embodiment, the material of the channel layer 110 and the channel layer 112 includes amorphous germanium or microcrystalline germanium, but the invention is not limited to the above materials. The material of the insulating layers 111, 113 may be tantalum oxide or tantalum nitride, but the invention is not limited to the above materials.

之後,圖案化絕緣層111以及113,以於絕緣層111中形成開口111a,其暴露出一部分的通道層110,並且在絕緣層113中形成開口113a,其暴露出一部分的通道層112,如圖4所示。更詳細來說,圖案化後的絕緣層111覆蓋住位於底電極106a上方之通道層110且暴露出位於底電極106a兩側上方之通道層110。類似地,圖案化後的絕緣層113覆蓋住位於底電極106c上方之通道層112且暴露出位於底電極106c兩側上方之通道層112。上述之圖案化程序例如是採用微影與蝕刻程序。Thereafter, the insulating layers 111 and 113 are patterned to form an opening 111a in the insulating layer 111, which exposes a portion of the channel layer 110, and an opening 113a is formed in the insulating layer 113, which exposes a portion of the channel layer 112, as shown in FIG. 4 is shown. In more detail, the patterned insulating layer 111 covers the channel layer 110 above the bottom electrode 106a and exposes the channel layer 110 above both sides of the bottom electrode 106a. Similarly, the patterned insulating layer 113 covers the channel layer 112 above the bottom electrode 106c and exposes the channel layer 112 above both sides of the bottom electrode 106c. The above-described patterning program is, for example, a lithography and etching process.

根據本實施例,在圖案化絕緣層111,113之過程之中,可進一步圖案化絕緣層108,以於絕緣層108中形成接觸窗開開口C1以及接觸窗開口C2,接觸窗開開口C1以及接觸窗開口C2暴露出連接層106b。另外,在所述圖案化程序之中,亦可進一步圖案化畫素電極區P中的絕緣層105以及絕緣層108,以形成開口O,其暴露出畫素電極104。According to the present embodiment, during the process of patterning the insulating layers 111, 113, the insulating layer 108 may be further patterned to form the contact opening opening C1 and the contact opening C2 in the insulating layer 108, the contact opening opening C1 and the contact window. The opening C2 exposes the connection layer 106b. In addition, in the patterning process, the insulating layer 105 and the insulating layer 108 in the pixel electrode region P may be further patterned to form an opening O that exposes the pixel electrode 104.

請參照圖5,在基板100上形成歐姆接觸層116以及導電圖案(包括第一頂電極118a、第一電極118b、第二電極118c以及上電極圖案118d)。特別是,位於第一電極118b與第二電極118c下方之歐姆接觸層116與被暴露出的通道層112電性連接。另外,第一電極118b更進一步透過接觸窗開口C2而與連接層106b電性連接。此外,在電容器區C中,上電極圖案118d、電容下電極106d以及位於上電極圖案118d與電容下電極106d之間之絕緣層108即構成儲存電容器,而上電極圖案118d之底下也具有歐姆接觸層116。Referring to FIG. 5, an ohmic contact layer 116 and a conductive pattern (including a first top electrode 118a, a first electrode 118b, a second electrode 118c, and an upper electrode pattern 118d) are formed on the substrate 100. In particular, the ohmic contact layer 116 underlying the first electrode 118b and the second electrode 118c is electrically connected to the exposed channel layer 112. In addition, the first electrode 118b is further electrically connected to the connection layer 106b through the contact window opening C2. Further, in the capacitor region C, the upper electrode pattern 118d, the capacitor lower electrode 106d, and the insulating layer 108 between the upper electrode pattern 118d and the capacitor lower electrode 106d constitute a storage capacitor, and the upper electrode pattern 118d also has an ohmic contact underneath. Layer 116.

根據本實施例,歐姆接觸材料116例如是摻雜有N型摻質,其可為摻雜有N型摻質之非晶矽、微晶矽、矽化鉬(MoSi)、矽化鉻(CrSi)或是矽化鈦(TiSi),但本發明不限於上述材料。導電圖案(包括第一頂電極118a、第一電極118b、第二電極118c以及電容上電極118d)之材質包括金屬,例如是鈦、鋁、鉬或鉻,但本發明不限於上述材料。According to the embodiment, the ohmic contact material 116 is doped, for example, with an N-type dopant, which may be an amorphous germanium doped with an N-type dopant, a microcrystalline germanium, a molybdenum molybdenum (MoSi), a chromium telluride (CrSi) or It is titanium telluride (TiSi), but the present invention is not limited to the above materials. The material of the conductive pattern (including the first top electrode 118a, the first electrode 118b, the second electrode 118c, and the capacitor upper electrode 118d) includes a metal such as titanium, aluminum, molybdenum or chromium, but the present invention is not limited to the above materials.

根據本實施例,形成歐姆接觸層116以及導電圖案(包括第一頂電極118a、第一電極118b、第二電極118c以及上電極圖案118d)之方法例如是先依序形成一層導電材料以及一層歐姆接觸材料(未繪示),之後同時圖案化此導電材料以及此歐姆接觸材料。According to the embodiment, the method of forming the ohmic contact layer 116 and the conductive pattern (including the first top electrode 118a, the first electrode 118b, the second electrode 118c, and the upper electrode pattern 118d) is, for example, sequentially forming a layer of conductive material and a layer of ohms. A contact material (not shown) is then patterned simultaneously with the conductive material and the ohmic contact material.

請參照圖6,在基板100上形成歐姆接觸層120以及導電圖案(包括第二頂電極122a、第三電極122b以及第四電極122c)。特別是,位於第三電極122b以及第四電極122c下方的歐姆接觸層120與被暴露出的通道層110電性連接。另外,第四電極122c更進一步透過接觸窗開口C1而與連接層106b電性連接。根據本實施例,歐姆接觸層120例如是摻雜有P型摻質,其可為摻雜有P型摻質之非晶矽、微晶矽、矽化鉬(MoSi)、矽化鉻(CrSi)或是矽化鈦(TiSi),但本發明不限於上述材料。導電圖案(包括第二頂電極122a、第三電極122b以及第四電極122c)之材質包括金屬,例如是鈦、鋁、鉬或鉻,但本發明不限於上述材料。Referring to FIG. 6, an ohmic contact layer 120 and a conductive pattern (including a second top electrode 122a, a third electrode 122b, and a fourth electrode 122c) are formed on the substrate 100. In particular, the ohmic contact layer 120 under the third electrode 122b and the fourth electrode 122c is electrically connected to the exposed channel layer 110. In addition, the fourth electrode 122c is further electrically connected to the connection layer 106b through the contact opening C1. According to the embodiment, the ohmic contact layer 120 is doped with a P-type dopant, for example, an amorphous germanium doped with a P-type dopant, a microcrystalline germanium, a molybdenum molybdenum (MoSi), a chromium telluride (CrSi) or It is titanium telluride (TiSi), but the present invention is not limited to the above materials. The material of the conductive pattern (including the second top electrode 122a, the third electrode 122b, and the fourth electrode 122c) includes a metal such as titanium, aluminum, molybdenum or chromium, but the present invention is not limited to the above materials.

根據本實施例,形成歐姆接觸層120以及導電圖案(包括第二頂電極122a、第三電極122b以及第四電極122c)之方法例如是先依序形成一層導電材料以及一層歐姆接觸材料(未繪示),之後同時圖案化此導電材料以及此歐姆接觸材料。According to the embodiment, the method of forming the ohmic contact layer 120 and the conductive pattern (including the second top electrode 122a, the third electrode 122b, and the fourth electrode 122c) is, for example, sequentially forming a layer of conductive material and an ohmic contact material (not drawn). Show), then simultaneously pattern the conductive material and the ohmic contact material.

在上述圖6之主動元件區T中,頂電極122a、第三電極122b、第四電極122c、通道層110以及底電極106a構成第一主動元件(例如是P型主動元件)。頂電極118a、第一電極118b、第二電極118c、通道層112以及底電極106c構成第二主動元件(例如是N型主動元件)。特別是,第一主動元件(例如是P型主動元件)之第四電極122c與第二主動元件(例如是N型主動元件)之第一電極118b透過連接層106b而電性連接,因而構成一個互補式主動元件。特別是,上述互補式主動元件之第一主動元件(例如是P型主動元件)與第二主動元件(例如是N型主動元件)分別為一雙電極主動元件。In the active device region T of FIG. 6 described above, the top electrode 122a, the third electrode 122b, the fourth electrode 122c, the channel layer 110, and the bottom electrode 106a constitute a first active device (for example, a P-type active device). The top electrode 118a, the first electrode 118b, the second electrode 118c, the channel layer 112, and the bottom electrode 106c constitute a second active device (for example, an N-type active device). In particular, the first electrode 118c of the first active component (for example, a P-type active component) and the first electrode 118b of the second active component (for example, an N-type active component) are electrically connected through the connection layer 106b, thereby forming a Complementary active components. In particular, the first active component (eg, a P-type active component) and the second active component (eg, an N-type active component) of the complementary active device are respectively a two-electrode active component.

在完成上述圖6之步驟之後,可進一步在圖6之結構上形成一保護層124,如圖7所示,以覆蓋主動元件區T中之第一主動元件(例如是P型主動元件)與第二主動元件(例如是N型主動元件)以及電容器區C中的電容器。而在畫素電極區P中,保護層124是暴露出畫素電極104。After the step of FIG. 6 is completed, a protective layer 124 may be further formed on the structure of FIG. 6, as shown in FIG. 7, to cover the first active component (for example, a P-type active component) in the active device region T. The second active component (eg, an N-type active component) and the capacitor in capacitor region C. In the pixel electrode region P, the protective layer 124 exposes the pixel electrode 104.

依照上述之製造方法所得到的主動元件結構如圖7所示。主動元件包括底電極106a、底電極106c、絕緣層108、通道層110、通道層112、絕緣層111,113、歐姆接觸層110以及歐姆接觸層112、導電圖案(第一電極118b、頂電極118a以及第二電極118c)以及導電圖案(第三電極122b、頂電極122a以及第四電極122c)。The structure of the active device obtained according to the above manufacturing method is as shown in FIG. The active device includes a bottom electrode 106a, a bottom electrode 106c, an insulating layer 108, a channel layer 110, a channel layer 112, an insulating layer 111, 113, an ohmic contact layer 110 and an ohmic contact layer 112, and a conductive pattern (first electrode 118b, top electrode 118a, and The two electrodes 118c) and the conductive patterns (the third electrode 122b, the top electrode 122a, and the fourth electrode 122c).

在本實施例中,位於主動元件區T中主動元件例如是薄膜電晶體。當主動元件為電晶體時,底電極106a,106c的功能相當於底閘極,第一電極118b與第二電極118c的功能分別相當於源極與汲極或是汲極與源極,第三電極122b與第四電極122c的功能分別相當於源極與汲極或是汲極與源極,而頂電極118a,122a的功能相當於頂閘極。In the present embodiment, the active element in the active device region T is, for example, a thin film transistor. When the active device is a transistor, the functions of the bottom electrodes 106a, 106c are equivalent to the bottom gate, and the functions of the first electrode 118b and the second electrode 118c are respectively equivalent to the source and the drain or the drain and the source, respectively. The functions of the electrode 122b and the fourth electrode 122c correspond to the source and the drain or the drain and the source, respectively, and the functions of the top electrodes 118a, 122a correspond to the top gate.

底電極106a以及底電極106c位於基板100上。絕緣層108覆蓋底電極106a以及底電極106c。通道層110以及通道層112分別位於底電極106a以及底電極106c上方之絕緣層108上。歐姆接觸層116以及歐姆接觸層120位於通道層110,112上。導電圖案(第一電極118b、頂電極118a以及第二電極118c)位於歐姆接觸層116上,其中位於第一電極118b以及第二電極118c下方之歐姆接觸層116與暴露出的通道層112電性連接。導電圖案(第三電極122b、頂電極122a以及第四電極122c)位於歐姆接觸層120上,其中位於第三電極122b以及第四電極122c下方之歐姆接觸層120與暴露出的通道層110電性連接。此外,第一電極118b與第四電極122c電性連接。The bottom electrode 106a and the bottom electrode 106c are located on the substrate 100. The insulating layer 108 covers the bottom electrode 106a and the bottom electrode 106c. The channel layer 110 and the channel layer 112 are respectively located on the insulating layer 108 above the bottom electrode 106a and the bottom electrode 106c. The ohmic contact layer 116 and the ohmic contact layer 120 are located on the channel layers 110, 112. The conductive patterns (the first electrode 118b, the top electrode 118a, and the second electrode 118c) are located on the ohmic contact layer 116, wherein the ohmic contact layer 116 under the first electrode 118b and the second electrode 118c and the exposed channel layer 112 are electrically connection. The conductive patterns (the third electrode 122b, the top electrode 122a, and the fourth electrode 122c) are located on the ohmic contact layer 120, wherein the ohmic contact layer 120 under the third electrode 122b and the fourth electrode 122c and the exposed channel layer 110 are electrically connection. In addition, the first electrode 118b is electrically connected to the fourth electrode 122c.

根據本發明之一實施例,上述之主動元件更包括連接層106b。第一電極118b與連接層106b電性連接,且第四電極122c與連接層106b電性連接。換言之,第一電極118b與第四電極122c是透過連接層106b而電性連接。在此,連接層106b是與底電極106a以及底電極106c屬於同一膜層。然,本發明不限於此。According to an embodiment of the invention, the active element further includes a connection layer 106b. The first electrode 118b is electrically connected to the connection layer 106b, and the fourth electrode 122c is electrically connected to the connection layer 106b. In other words, the first electrode 118b and the fourth electrode 122c are electrically connected to each other through the connection layer 106b. Here, the connection layer 106b belongs to the same film layer as the bottom electrode 106a and the bottom electrode 106c. However, the invention is not limited thereto.

另外,歐姆接觸層116與導電圖案(第一電極118b、頂電極118a以及第二電極118c)具有相同的圖案。歐姆接觸層120與導電圖案(第三電極122b、頂電極122a以及第四電極122c)具有相同的圖案。在本實施例中,歐姆接觸層116摻雜有N型摻質,且歐姆接觸層120摻雜有P型摻質;或者是歐姆接觸層116摻雜有P型摻質,且歐姆接觸層120摻雜有N型摻質。In addition, the ohmic contact layer 116 has the same pattern as the conductive patterns (the first electrode 118b, the top electrode 118a, and the second electrode 118c). The ohmic contact layer 120 has the same pattern as the conductive patterns (the third electrode 122b, the top electrode 122a, and the fourth electrode 122c). In the present embodiment, the ohmic contact layer 116 is doped with an N-type dopant, and the ohmic contact layer 120 is doped with a P-type dopant; or the ohmic contact layer 116 is doped with a P-type dopant, and the ohmic contact layer 120 It is doped with an N-type dopant.

此外,在電容器區C中,儲存電容器包括電容下電極106d、上電極圖案118d以及位於上電極圖案118d與電容下電極106d之間之絕緣層108。在畫素電極區P中,畫素電極104位於基板100上,且絕緣層108、114暴露出畫素電極104。Further, in the capacitor region C, the storage capacitor includes a capacitor lower electrode 106d, an upper electrode pattern 118d, and an insulating layer 108 between the upper electrode pattern 118d and the capacitor lower electrode 106d. In the pixel electrode region P, the pixel electrode 104 is located on the substrate 100, and the insulating layers 108, 114 expose the pixel electrode 104.

圖8是根據本發明另一實施例之具有主動元件之畫素結構的剖面示意圖。圖8之結構與圖7相似,因此在此與圖7相同的元件以相同的符號表示,且不再重複贅述。圖8之實施例與圖7之實施例不同之處在於在畫素電極區P中,畫素電極118e是形成在絕緣層108上。在本實施例中,畫素電極118e是與導電圖案(第一電極118b、頂電極118a以及第二電極118c)所同時定義出,因此畫素電極118e之下方也有歐姆接觸層116。Figure 8 is a cross-sectional view showing a pixel structure having an active element in accordance with another embodiment of the present invention. The structure of FIG. 8 is similar to that of FIG. 7, and therefore the same components as those of FIG. 7 are denoted by the same reference numerals and will not be described again. The embodiment of FIG. 8 is different from the embodiment of FIG. 7 in that in the pixel electrode region P, the pixel electrode 118e is formed on the insulating layer 108. In the present embodiment, the pixel electrode 118e is defined simultaneously with the conductive pattern (the first electrode 118b, the top electrode 118a, and the second electrode 118c), and thus the ohmic contact layer 116 is also disposed under the pixel electrode 118e.

綜上所述,由於本發明之主動元件具有底電極以及頂電極,因此可使底電極與通道層之間以及在頂電極與通道層之間形成兩道電子通道。因而,本發明之主動元件相較於傳統主動元件具有高電流以及低漏電之功效。In summary, since the active device of the present invention has a bottom electrode and a top electrode, two electron channels can be formed between the bottom electrode and the channel layer and between the top electrode and the channel layer. Thus, the active device of the present invention has high current and low leakage effects compared to conventional active components.

另外,因本發明之頂電極、第一電極以及第二電極是同時定義出,且頂電極、第一電極以及第二電極與位於頂電極、第一電極以及第二電極下方的歐姆接觸層是以同一道光罩定義出。因此,本發明之方法可以節省光罩製程的數目,以降低製造成本。In addition, since the top electrode, the first electrode, and the second electrode of the present invention are simultaneously defined, and the top electrode, the first electrode, and the second electrode and the ohmic contact layer under the top electrode, the first electrode, and the second electrode are Defined by the same mask. Therefore, the method of the present invention can save the number of mask processes to reduce manufacturing costs.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100...基板100. . . Substrate

T...主動元件區T. . . Active component area

C...電容器區C. . . Capacitor zone

P...畫素電極區P. . . Pixel electrode area

102...緩衝層102. . . The buffer layer

104...畫素電極104. . . Pixel electrode

106a、106c...底電極106a, 106c. . . Bottom electrode

106b...連接層106b. . . Connection layer

106d...電容下電極106d. . . Capacitor lower electrode

108、111、113...絕緣層108, 111, 113. . . Insulation

111a,113a...開口111a, 113a. . . Opening

110、112...通道層110, 112. . . Channel layer

116、120...歐姆接觸層116, 120. . . Ohmic contact layer

118b...第一電極118b. . . First electrode

122b...第三電極122b. . . Third electrode

118a、122a...頂電極118a, 122a. . . Top electrode

118c...第二電極118c. . . Second electrode

122c‧‧‧第四電極122c‧‧‧fourth electrode

118d‧‧‧上電極圖案118d‧‧‧Upper electrode pattern

118e‧‧‧畫素電極118e‧‧‧ pixel electrodes

124‧‧‧保護層124‧‧‧Protective layer

C1、C2‧‧‧接觸窗開口C1, C2‧‧‧ contact window opening

O‧‧‧開口O‧‧‧ openings

圖1至圖7是根據本發明一實施例之具有主動元件之畫素結構的製造流程剖面示意圖。1 to 7 are schematic cross-sectional views showing a manufacturing process of a pixel structure having an active device according to an embodiment of the present invention.

圖8是根據本發明另一實施例之具有主動元件之畫素結構的剖面示意圖。Figure 8 is a cross-sectional view showing a pixel structure having an active element in accordance with another embodiment of the present invention.

100...基板100. . . Substrate

102...緩衝層102. . . The buffer layer

104...畫素電極104. . . Pixel electrode

106a、106c...底電極106a, 106c. . . Bottom electrode

106b...連接層106b. . . Connection layer

106d...電容下電極106d. . . Capacitor lower electrode

108、111、113...絕緣層108, 111, 113. . . Insulation

110、112...通道層110, 112. . . Channel layer

116、120...歐姆接觸層116, 120. . . Ohmic contact layer

118b...第一電極118b. . . First electrode

122b...第三電極122b. . . Third electrode

118a、122a...頂電極118a, 122a. . . Top electrode

118c...第二電極118c. . . Second electrode

122c...第四電極122c. . . Fourth electrode

118d...上電極圖案118d. . . Upper electrode pattern

124...保護層124. . . The protective layer

C1、C2...接觸窗開口C1, C2. . . Contact window opening

O...開口O. . . Opening

Claims (16)

一種主動元件的製造方法,包括:在一基板上形成一第一底電極以及一第二底電極;形成一第一絕緣層,覆蓋該第一底電極與該第二底電極;在該第一底電極上方之該第一絕緣層上形成一第一通道層且於該第二底電極上方之該第一絕緣層上形成一第二通道層;在該第一通道層及該第二通道層上形成一第二絕緣層,其中該第二絕緣層暴露出一部分的該第一通道層以及一部分的該第二通道層;在該第一通道層上方形成一第一導電圖案,該第一導電圖案包括一第一電極、一第一頂電極以及一第二電極,其中該第一電極及該第二電極與暴露出的該第一通道層電性連接;以及在該第二通道層上方形成一第二導電圖案,該第二導電圖案包括一第三電極、一第二頂電極以及一第四電極,其中該第三電極與該第四電極與暴露出的該第二通道層電性連接,且該第一電極與該第四電極電性連接;以及在該基板上形成一連接層,其中該第一電極與該連接層電性連接,且該第四電極與該連接層電性連接。 A method for manufacturing an active device, comprising: forming a first bottom electrode and a second bottom electrode on a substrate; forming a first insulating layer covering the first bottom electrode and the second bottom electrode; Forming a first channel layer on the first insulating layer above the bottom electrode and forming a second channel layer on the first insulating layer above the second bottom electrode; at the first channel layer and the second channel layer Forming a second insulating layer, wherein the second insulating layer exposes a portion of the first channel layer and a portion of the second channel layer; forming a first conductive pattern over the first channel layer, the first conductive layer The pattern includes a first electrode, a first top electrode, and a second electrode, wherein the first electrode and the second electrode are electrically connected to the exposed first channel layer; and formed over the second channel layer a second conductive pattern, the second conductive pattern includes a third electrode, a second top electrode, and a fourth electrode, wherein the third electrode and the fourth electrode are electrically connected to the exposed second channel layer And the first electricity And the fourth connection electrode electrically; and forming a connecting layer on the substrate, wherein the first electrode is connected electrically to the connection layer, and the fourth electrode connected electrically to the connection layer. 如申請專利範圍第1項所述之主動元件的製造方法,其中該連接層是與該第一底電極以及該第二底電極同時形成。 The method of manufacturing an active device according to claim 1, wherein the connecting layer is formed simultaneously with the first bottom electrode and the second bottom electrode. 如申請專利範圍第1項所述之主動元件的製造方法,其中在該第一通道層上方形成該第一導電圖案時更包括同時形成一第一歐姆接觸層。 The method of manufacturing an active device according to claim 1, wherein the forming the first conductive pattern over the first channel layer further comprises simultaneously forming a first ohmic contact layer. 如申請專利範圍第3項所述之主動元件的製造方法,其中在該第一通道層上方同時形成該第一歐姆接觸層以及該第一導電圖案之方法包括:依序形成一第一歐姆接觸材料以及一第一導電材料,其中該第一歐姆接觸材料與暴露出的該第一通道層電性連接;以及同時圖案化該第一導電材料以及該第一歐姆接觸材料。 The method for manufacturing an active device according to claim 3, wherein the method of simultaneously forming the first ohmic contact layer and the first conductive pattern over the first channel layer comprises: sequentially forming a first ohmic contact a material and a first conductive material, wherein the first ohmic contact material is electrically connected to the exposed first channel layer; and the first conductive material and the first ohmic contact material are simultaneously patterned. 如申請專利範圍第1項所述之主動元件的製造方法,其中在該第二通道層上方形成該第二導電圖案時更包括同時形成一第二歐姆接觸層。 The method for manufacturing an active device according to claim 1, wherein the forming the second conductive pattern over the second channel layer further comprises simultaneously forming a second ohmic contact layer. 如申請專利範圍第5項所述之主動元件的製造方法,其中在該第二通道層上方同時形成該第二歐姆接觸層以及該第二導電圖案之方法包括:依序形成一第二歐姆接觸材料以及一第二導電材料,其中該第二歐姆接觸材料與暴露出的該第二通道層電性連接;以及同時圖案化該第二導電材料以及該第二歐姆接觸材料。 The method of manufacturing an active device according to claim 5, wherein the method of simultaneously forming the second ohmic contact layer and the second conductive pattern over the second channel layer comprises: sequentially forming a second ohmic contact a material and a second conductive material, wherein the second ohmic contact material is electrically connected to the exposed second channel layer; and simultaneously patterning the second conductive material and the second ohmic contact material. 一種主動元件的製造方法,包括:在一基板上形成一底電極; 形成一第一絕緣層,覆蓋該底電極;在該底電極上方之該第一絕緣層上形成一通道層;在該通道層上形成一第二絕緣層,其中該第二絕緣層暴露出一部分的該通道層;以及在該通道層上方形成一導電圖案,該導電圖案包括一第一電極、一頂電極以及一第二電極,其中該第一電極與該第二電極與暴露出的該通道層電性連接,其中,在該底電極與該通道層之間以及在該頂電極與該通道層之間分別形成一電子通道。 A method of manufacturing an active device, comprising: forming a bottom electrode on a substrate; Forming a first insulating layer covering the bottom electrode; forming a channel layer on the first insulating layer above the bottom electrode; forming a second insulating layer on the channel layer, wherein the second insulating layer exposes a portion And forming a conductive pattern over the channel layer, the conductive pattern comprising a first electrode, a top electrode and a second electrode, wherein the first electrode and the second electrode and the exposed channel The layer is electrically connected, wherein an electron channel is formed between the bottom electrode and the channel layer and between the top electrode and the channel layer. 如申請專利範圍第7項所述之主動元件的製造方法,其中在該通道層上方形成該導電圖案時更包括同時形成一歐姆接觸層。 The method of manufacturing an active device according to claim 7, wherein the forming the conductive pattern over the channel layer further comprises simultaneously forming an ohmic contact layer. 如申請專利範圍第8項所述之主動元件的製造方法,其中在該通道層上方同時形成該歐姆接觸層以及該導電圖案之方法包括:依序形成一歐姆接觸材料以及一導電材料,其中該歐姆接觸材料與暴露出的該通道層電性連接;以及同時圖案化該導電材料以及該歐姆接觸材料。 The method of manufacturing an active device according to claim 8, wherein the method of simultaneously forming the ohmic contact layer and the conductive pattern over the channel layer comprises: sequentially forming an ohmic contact material and a conductive material, wherein An ohmic contact material is electrically connected to the exposed channel layer; and the conductive material and the ohmic contact material are simultaneously patterned. 如申請專利範圍第7項所述之主動元件的製造方法,其中該歐姆接觸層摻雜有N型摻質或是P型摻質。 The method of manufacturing an active device according to claim 7, wherein the ohmic contact layer is doped with an N-type dopant or a P-type dopant. 一種主動元件,包括:一第一底電極以及一第二底電極,位於一基板上;一第一絕緣層,覆蓋該第一底電極以及該第二底電極; 一第一通道層以及一第二通道層,分別位於該第一底電極以及該第二底電極上方之該第一絕緣層上;一第二絕緣層,位於該第一通道層以及該第二通道層上,且暴露出一部分的該第一通道層以及一部分的該第二通道層;一第一導電圖案,位於該第一通道層上,其中該第一導電圖案包括一第一電極、一第一頂電極以及一第二電極,其中該第一電極及該第二電極與暴露出的該第二通道層電性連接;一第二導電圖案,位於該第二通道層上,其中該第二導電圖案包括一第三電極、一第二頂電極以及一第四電極,其中該第三電極及該第四電極與暴露出的該第二通道層電性連接,且該第一電極與該第四電極電性連接;以及一連接層,其中該第一電極與該連接層電性連接,且該第四電極與該連接層電性連接。 An active component includes: a first bottom electrode and a second bottom electrode on a substrate; a first insulating layer covering the first bottom electrode and the second bottom electrode; a first channel layer and a second channel layer are respectively disposed on the first insulating layer above the first bottom electrode and the second bottom electrode; a second insulating layer is located in the first channel layer and the second layer a first channel layer and a portion of the second channel layer are exposed on the channel layer; a first conductive pattern is located on the first channel layer, wherein the first conductive pattern comprises a first electrode, a first top electrode and a second electrode, wherein the first electrode and the second electrode are electrically connected to the exposed second channel layer; and a second conductive pattern is located on the second channel layer, wherein the first electrode The second conductive pattern includes a third electrode, a second top electrode, and a fourth electrode, wherein the third electrode and the fourth electrode are electrically connected to the exposed second channel layer, and the first electrode and the first electrode The fourth electrode is electrically connected; and a connecting layer, wherein the first electrode is electrically connected to the connecting layer, and the fourth electrode is electrically connected to the connecting layer. 如申請專利範圍第11項所述之主動元件,其中該連接層是與該第一底電極以及該第二底電極屬於同一膜層。 The active device of claim 11, wherein the connecting layer is the same film layer as the first bottom electrode and the second bottom electrode. 如申請專利範圍第11項所述之主動元件,更包括一第一歐姆接觸層,位於該第一通道層上,其中該第一歐姆接觸層與該第一導電圖案具有相同的圖案。 The active device of claim 11, further comprising a first ohmic contact layer on the first channel layer, wherein the first ohmic contact layer has the same pattern as the first conductive pattern. 如申請專利範圍第11項所述之主動元件,更包括一第二歐姆接觸層,位於該第二通道層上,其中該第二歐姆接觸層與該第二導電圖案具有相同的圖案。 The active device of claim 11, further comprising a second ohmic contact layer on the second channel layer, wherein the second ohmic contact layer and the second conductive pattern have the same pattern. 一種主動元件,包括:一底電極,位於一基板上;一第一絕緣層,覆蓋該底電極;一通道層,位於該底電極上方之該第一絕緣層上;一第二絕緣層,位於該通道層上,其中該第二絕緣層暴露出一部分的該通道層;以及一導電圖案,其包括一第一電極、一頂電極以及一第二電極,其中該第一電極及該第二電極與暴露出的該通道層電性連接,其中,在該底電極與該通道層之間以及在該頂電極與該通道層之間分別形成一電子通道。 An active component includes: a bottom electrode on a substrate; a first insulating layer covering the bottom electrode; a channel layer on the first insulating layer above the bottom electrode; and a second insulating layer located at a channel layer, wherein the second insulating layer exposes a portion of the channel layer; and a conductive pattern including a first electrode, a top electrode, and a second electrode, wherein the first electrode and the second electrode Electrically connected to the exposed channel layer, wherein an electron channel is formed between the bottom electrode and the channel layer and between the top electrode and the channel layer. 如申請專利範圍第15項所述之主動元件,更包括一歐姆接觸層,位於該通道層上,其中該歐姆接觸層與該導電圖案具有相同的圖案。The active device of claim 15, further comprising an ohmic contact layer on the channel layer, wherein the ohmic contact layer has the same pattern as the conductive pattern.
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