CN110729313B - Display panel, display panel manufacturing method and display device - Google Patents
Display panel, display panel manufacturing method and display device Download PDFInfo
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- CN110729313B CN110729313B CN201911207381.XA CN201911207381A CN110729313B CN 110729313 B CN110729313 B CN 110729313B CN 201911207381 A CN201911207381 A CN 201911207381A CN 110729313 B CN110729313 B CN 110729313B
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 235
- 239000010409 thin film Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000011229 interlayer Substances 0.000 claims abstract description 30
- 238000000151 deposition Methods 0.000 claims description 44
- 238000000059 patterning Methods 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 21
- 238000001312 dry etching Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 13
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910001257 Nb alloy Inorganic materials 0.000 claims description 6
- -1 aluminum molybdenum niobium Chemical compound 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 238000004380 ashing Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 238000005121 nitriding Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000006355 external stress Effects 0.000 description 3
- 239000002346 layers by function Substances 0.000 description 3
- 229910021645 metal ion Inorganic materials 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000003313 weakening effect Effects 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The application discloses a display panel, a display device and a preparation method of the display panel. The light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned at one side of the thin film transistor, which is close to the direction of the substrate; the light shielding unit comprises a first light shielding area and a second light shielding area, and the second light shielding area is arranged to surround the first light shielding area; according to the technical scheme provided by the application, due to the existence of the first shading area of the shading unit, the shading function of the shading layer can not be influenced on one hand, so that the active layer is protected; meanwhile, on the other hand, even if the interlayer insulating layer via hole extends to the shading layer due to the technical problem, the short circuit caused by the conductive path between the source and the drain and the first electrode is not formed, so that poor bright point can not be caused when the voltage is applied to the drain, and the display effect and the product quality can be effectively improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a display panel preparation method and a display device.
Background
The thin film transistor (Thin Film Transistor, TFT) is a field effect transistor with a plurality of functional thin film layers made of transparent glass as a base material, and has an important function on the working performance of the display device. The TFT type display screen is an active matrix liquid crystal display device, and each liquid crystal pixel point is driven by a thin film transistor array integrated behind the pixel point, and the technology of the thin film transistor array is often used to improve the picture quality, so that the TFT type display screen is widely applied to electronic display devices such as mobile phones, flat panel, computer displays, televisions and the like.
The top gate type TFT is one of TFT types, has the characteristic of a short channel, and can effectively promote on-state current when the TFT works. In addition, the overlapping area of the grid electrode and the source electrode and the drain electrode of the top grid type TFT is small, so that the parasitic capacitance is small, the display effect can be remarkably improved, and the power consumption can be effectively reduced. Since the top gate type TFT has the above significant advantages, it is receiving increasing attention. Currently, top gate TFTs mostly use IGZO (indium gallium zinc oxide) semiconductors with high carrier mobility as active layers.
Disclosure of Invention
The invention provides a display panel, a display panel manufacturing method and a display device.
The technical scheme adopted is a display panel, comprising:
a substrate base, and
A shading layer and a plurality of thin film transistors arranged in an array on the substrate;
the light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned at one side of the thin film transistor, which is close to the direction of the substrate base plate;
A buffer layer is arranged on the substrate base plate in the direction away from the shading layer;
The thin film transistor comprises an active layer, a gate insulating layer, a gate, an interlayer insulating layer and a source drain layer which are sequentially arranged in the direction away from the buffer layer;
The active layer comprises a conductive region which is not overlapped with the projection of the active layer and the gate insulating layer on the substrate, and a channel region which is overlapped with the projection of the active layer and the gate insulating layer on the substrate;
The source-drain electrode layer comprises a first electrode and a second electrode;
the light shielding unit comprises a first light shielding area and a second light shielding area, and the second light shielding area is arranged surrounding the first light shielding area;
The projection of the channel region on the substrate is positioned in the projection of the second shading region on the substrate;
the thin film transistor is sequentially provided with a passivation layer and an anode in a direction away from the substrate.
Optionally, the interlayer insulating layer includes a first via hole and a second via hole;
at least part of the projection area of the first shading area and the first via hole on the shading layer has an overlapping area;
and at least part of the projection area of the second shading area and the second through hole on the shading layer has an overlapping area.
Optionally, wherein at least a portion of the first electrode is located within the first via; the first shading area is completely overlapped with the projection area of the first via hole on the shading layer, and is contacted with the first electrode through the first via hole.
Optionally, wherein at least a portion of the second electrode is located within the second via; the second shading area is positioned outside the projection area of the first via hole on the shading layer and is contacted with the second electrode through the second via hole.
Optionally, in the light shielding unit, the first light shielding area and the second light shielding area are isolated from each other by a gap and are not connected with each other.
Optionally, the projection of the slit on the substrate falls completely outside the projection area of the channel region on the substrate.
Optionally, the first light shielding region and the second light shielding region comprise metal conductive materials such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, and the thickness is 0.20-0.25 um.
Optionally, the first light shielding area and the second light shielding area may be integrally and seamlessly connected.
Optionally, the first light shielding region is an insulating material, and the second light shielding region is configured as a conductive material.
Optionally, the insulating material of the first light shielding region is metal oxide or metal nitride, the conductive material of the second light shielding region is a metal material such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, and the thickness is 0.20-0.25 um.
The invention provides a display device which is characterized by comprising any technical characteristics of the display panel.
The invention provides a preparation method of a display panel, which comprises the following steps:
providing a substrate base plate, and
Patterning and depositing a plurality of light shielding units forming a light shielding layer, forming a first light shielding region and a second light shielding region on the light shielding units, the second light shielding region being configured to surround the first light shielding region;
depositing a buffer layer, patterning and depositing to form an active layer, depositing a gate insulating layer, patterning and depositing to form a gate, depositing an interlayer insulating layer, patterning and depositing to form a source drain;
preferably, when forming a plurality of the light shielding units, preparing gaps by coating photoresist, exposing, developing and dry etching processes, so that the first light shielding region is surrounded by the second light shielding region and is isolated from the second light shielding region through the gaps;
The first light shielding region and the second light shielding region are both made of metal conductive materials.
Preferably, a buffer layer is deposited on the light shielding unit, an active layer pattern is formed on the buffer layer by patterning through photoresist, a gate insulating layer pattern is formed on the active layer by patterning, and a metal gate is formed on the gate insulating layer by patterning;
etching the gate insulating layer by adopting a self-alignment process without stripping photoresist used for patterning above the gate, and conducting a conductive process on the exposed edge of the active layer;
depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole through plasma dry etching;
preferably, when forming a plurality of the light shielding units, the method includes:
Performing exposure development process by using a half-tone mask, completely reserving photoresist of an opaque region corresponding to the second shading region, partially reserving photoresist of a semi-transparent region corresponding to the first shading region, developing to remove photoresist of the completely transparent region, and performing etching process to form a first shading layer pattern;
Ashing the residual photoresist on the light shielding layer pattern to remove the photoresist in the semi-transparent area;
oxidizing or nitriding the exposed part of the first shading area corresponding to the semi-transparent area to form an insulator;
stripping all photoresist to form the light shielding layer
Wherein the light shielding units are configured as an integral structure, and the first light shielding area and the second light shielding area are configured as seamless connection;
The first light shielding region is configured as a metal oxide or metal nitride material, and the second light shielding region is configured as a metal material;
depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole through plasma dry etching;
The display panel and the display device comprise a substrate base plate, a shading layer on the substrate base plate and a plurality of thin film transistors arranged in an array. The light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned at one side of the thin film transistor, which is close to the direction of the substrate; the shading unit comprises a first shading area and a second shading area, and the second shading area is arranged to surround the first shading area. According to the technical scheme provided by the application, due to the existence of the first shading area of the shading unit, the shading function of the shading layer can not be influenced on one hand, so that the active layer is protected; meanwhile, on the other hand, even if the interlayer insulating layer via hole extends to the shading layer due to the technical problem, the short circuit caused by the conductive path between the source and the drain and the first electrode is not formed, so that poor bright point can not be caused when the voltage is applied to the drain, and the display effect and the product quality can be effectively improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel with a TFT;
FIG. 2 is a schematic diagram of a sub-pixel circuit connection in an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view of a display panel;
FIG. 4 is a schematic view of a light shielding unit;
FIG. 5 is a schematic cross-sectional view of another display panel;
FIG. 6 is a schematic view of another light shielding unit;
FIG. 7 is a schematic diagram of a process flow for manufacturing a display panel;
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be noted that, for convenience of description, only the portions related to the application are schematically shown in the drawings.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel with a TFT;
As shown, there is provided a display panel including a substrate base plate 10, and a plurality of thin film transistors including an active layer 40, a gate electrode 60, and a source and drain electrode layer 80 prepared thereon; the projection area of the active layer 40 on the substrate has an overlapping and non-overlapping portion with the projection area of the gate electrode on the substrate. The active layer is made of amorphous silicon, polysilicon, metal oxide and other semiconductor materials.
Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping portion may be used for making electrical connection by doping metal ions into the conductor region 401; and the overlap constitutes an active region in the thin film transistor, i.e., channel region 402.
A metal shading layer 20 deposited on the substrate 10 is also included between the substrate 10 and the thin film transistor; the light shielding unit 20 is a light shielding metal layer, and is composed of a plurality of light shielding units corresponding to the plurality of thin film transistors one by one, and the projection of each light shielding unit on the substrate is at least overlapped with the projection of each thin film transistor on the substrate, so as to protect the active layer structure in the thin film transistor thereon from being directly irradiated by light, and avoid the functional failure or weakening of the transistor.
The display panel also comprises a plurality of functional layers, wherein: a buffer layer 30 disposed between the light shielding layer 20 and the active layer 40 for relieving the influence of external stress on the inside of the display panel; a gate insulating layer 50 disposed between the active layer 40 and the gate electrode 60 for avoiding electrical connection between the active layer and the gate electrode; an interlayer insulating layer 70 disposed inside the thin film transistor for preventing the source and drain electrodes from being electrically connected to other connection lines in the display panel, and a passivation layer 90 disposed in a direction away from the substrate to cover the thin film transistor; wherein, the source and drain electrodes of the thin film transistor on the display panel are connected with the conductive region 401 of the active layer 40 through the first via 701 arranged in the interlayer insulating layer 70; the source/drain electrodes of the thin film transistor on the display panel are connected to the light shielding layer 40 through the second via holes 702 penetrating the interlayer insulating layer 70 and the buffer layer 30; source/drain electrodes in the thin film transistors on the display panel are electrically connected to the anode layer 100 through the passivation layer, and the anode layer is made of transparent electrode ITO.
In the design of the AMOLED product circuit, fig. 2 is a schematic diagram illustrating the connection of sub-pixel circuits according to an embodiment of the present invention: the basic structure of a sub-pixel circuit is illustrated with an N-type transistor as an example, and specifically, the sub-pixel circuit includes a driving transistor T3, a first switching transistor T1, a second switching transistor T2, and a light emitting element.
The first electrode of the first switching transistor T1 is connected to the DATA line DATA, the second electrode of the first switching transistor T2 is connected to the gate of the driving transistor T3, and the gate of the first switching transistor T1 is connected to the first scan line G1. The first electrode of the driving transistor T3 is connected to the first power supply terminal VDD, the second electrode of the driving transistor T3 is connected to the anode of the light emitting element, the cathode of the light emitting element is connected to the second power supply terminal VSS, the first electrode of the second switching transistor T2 is connected to the second electrode of the driving transistor T3, the second electrode of the second switching transistor T2 is connected to the sensing line Sense, and the gate of the second switching transistor T2 is connected to the second scanning line G2.
In this embodiment mode, an IGZO semiconductor is used as an active layer. The process flow comprises the following steps: the method comprises the steps of forming a shading layer on a substrate by adopting a chemical vapor deposition process (hereinafter referred to as deposition), utilizing an optical mask plate through the procedures of gluing (photoresist PR), exposing, developing and the like (hereinafter referred to as patterning), further depositing a buffer layer, further patterning and depositing to form an active layer, further depositing a grid insulating layer, further patterning and depositing to form a grid, further not stripping PR glue above a pattern, further adopting a self-alignment process to carry out a high-energy gas dry etching process on the grid insulating layer below, further carrying out a conductor process of the active layer, further depositing an interlayer insulating layer, patterning and continuing dry etching to form a first via hole and a second via hole, further patterning and depositing to form a source/drain electrode, and finally depositing a passivation layer and an anode. Wherein, the signal line connected to the source 801 is a first power supply VDD signal; the drain electrode 802 overlaps the anode 100; the drain electrode 802 is electrically connected with the shielding layer 20 through the second via hole 702, and the access of the electric signal is realized through the source-drain electrode layer;
optionally, the conductor region 401 of the non-channel portion in the active layer 20 forms a storage capacitor together with the shielding element. The storage capacitor formed by the light shielding layer 20 and the conductor region 401 in the active layer 40 as two plates is excellent in operation performance because the buffer layer 30 is only separated from the middle, and more charge can be stored.
In the actual process of preparing the thin film transistor, the non-uniformity of large-area dry etching can cause non-uniform etching of the grid insulating layer of the pixel region, and some positions can be etched to the buffer layer below, so that the light emitting efficiency of the display device is non-uniform; secondly, as the etching degree of the buffer layers at different positions is different, the process is not well controlled when the interlayer insulating layer is etched later, and the lower grating shielding layer pattern layer is easily damaged by etching; in addition, the etching amount is not easy to control when the via hole is prepared, and the situation of short circuit is often caused by over etching, so that certain pixel points of the display equipment cannot be normally lightened, and bad points are caused. Based on the defects and shortcomings of the prior art, a brand new display panel structural design and display panel preparation method are required to be provided during actual process operation, so that the display quality of a product is improved.
In the actual process, the dry etching strength in the process is not easy to control when the first via hole is formed, so that the situation of large excessive etching amount is easy to occur; in addition, the active layer is generally thin in film formation in an actual process, and certain parts are easy to be lost or dry etched, so that the first via hole is always punched on a light shielding unit of the light shielding layer below, the subsequent drain electrode is short-circuited with the light shielding unit in the light shielding layer, a path from the source electrode to the light shielding unit to the drain electrode to the anode ITO is formed, and bright spot defects are caused when the drain electrode is electrified.
The following examples illustrate a plurality of embodiments, which can effectively solve the problem of high brightness of bright spots caused by short circuit between the drain electrode and the light shielding unit, thereby remarkably improving the display quality of the product.
Example 1:
FIG. 3 is a schematic cross-sectional view of a display panel;
The display panel includes a substrate base 10, and a plurality of thin film transistors prepared thereon, including an active layer 40, a gate electrode 60, and a source-drain electrode layer 80; the projection area of the active layer 40 on the substrate has an overlapping and non-overlapping portion with the projection area of the gate electrode on the substrate. Generally, the active layer is made of amorphous silicon, polysilicon, metal oxide, or other semiconductor materials. Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping portion may be used for making electrical connection by doping metal ions into the conductor region 401; and the overlap constitutes an active region 402 in the thin film transistor.
A metal shading layer 20 deposited on the substrate 10 is also included between the substrate 10 and the thin film transistor; the light shielding unit 20 is a light shielding metal layer, and is composed of a plurality of light shielding units corresponding to the plurality of thin film transistors one by one, and the projection of each light shielding unit on the substrate is at least overlapped with the projection of each thin film transistor on the substrate, so as to protect the active layer structure in the thin film transistor thereon from being directly irradiated by light, and avoid the functional failure or weakening of the transistor.
The display panel also comprises a plurality of functional layers, wherein: a buffer layer 30 disposed between the light shielding layer 20 and the active layer 40 for relieving the influence of external stress on the inside of the display panel; a gate insulating layer 50 disposed between the active layer 40 and the gate electrode 60 for avoiding electrical connection between the active layer and the gate electrode; an interlayer insulating layer 70 disposed inside the thin film transistor for preventing the source and drain electrodes from being electrically connected to other connection lines in the display panel, and a passivation layer 90 disposed in a direction away from the substrate to cover the thin film transistor; wherein the source/drain electrodes of the thin film transistor on the display panel are connected to the conductive regions 401 of the active layer 40 through the first via holes 701 provided in the interlayer insulating layer 70; source/drain electrodes in the thin film transistor on the display panel are connected to the light shielding layer 40 through second vias 702 penetrating through the interlayer insulating layer 70 and the buffer layer 30; the source and drain electrodes of the thin film transistor on the display panel are electrically connected with the anode layer 100 through the passivation layer, and the anode layer is made of transparent electrode ITO.
In the display panel, the light shielding unit corresponding to the thin film transistor comprises a first light shielding region 201 and a second light shielding region 202, the second light shielding region surrounds the first light shielding region, and the light shielding layer 20 is designed into a local hollow structure;
the first shading area is positioned in a projection area of the first via hole on the shading area and is contacted with a source electrode or a drain electrode in the first via hole;
The second shading area is positioned outside the projection area of the first via hole on the shading layer and is contacted with the drain electrode or the source electrode in the second via hole;
FIG. 4 is a schematic view of a light shielding unit;
The first shading area is surrounded by the second shading area in the shading unit, wherein the first shading area and the second shading area are isolated from each other and are not connected with each other through gaps in the shading unit; the projection of the gap on the substrate completely falls outside the projection area of the active layer channel region on the substrate. Thus, the slit causes the two regions to be disconnected and not overlapped with the channel region of the active layer, so that the influence of ambient light to the active region in the thin film transistor and the service life of the device is avoided.
The first light shielding region and the second light shielding region are made of conductive materials, and metal materials such as iron, aluminum, silver and the like or nano materials with higher conductivity can be generally selected. On the one hand, the shading function of the shading layer is not affected, and meanwhile, even when the first via hole is contacted with the shading unit due to the technical problem, the first shading area is in an island structure due to the existence of the isolation gap, and a passage between the drain electrode and the anode ITO is not formed, so that bright spot defects caused when the drain electrode is electrified are avoided.
The preparation method of the display panel in the embodiment of the invention comprises the following steps: providing a substrate base plate, and sequentially patterning and depositing a shading layer, a depositing buffer layer, patterning and depositing to form an active layer, depositing a grid insulating layer, patterning and depositing to form a grid, depositing an interlayer insulating layer, patterning and depositing to form a source electrode and a drain electrode;
a plurality of light shielding units are included on the light shielding layer; and forming a first shading area and a second shading area on the shading unit, wherein the second shading area is arranged to surround the first shading area.
Preferably, the display panel manufacturing method further includes: when a plurality of light shielding units are formed, preparing gaps through coating photoresist, masking, exposing, developing and dry etching processes, so that the first light shielding area is surrounded by the second light shielding area and is isolated from the second light shielding area through the gaps; the first shading area and the second shading area are made of metal conductive materials;
Optionally, the material is configured as a metal conductive material such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, and the thickness is 0.20-0.25 um.
Preferably, the method for manufacturing a display panel further includes: depositing a buffer layer on the light shielding unit, patterning the buffer layer by using photoresist to form an active layer pattern, patterning the active layer to form a gate insulating layer pattern, and patterning the gate insulating layer to form a metal gate;
etching the gate insulating layer by adopting a self-alignment process without stripping photoresist used for patterning above the gate, and conducting a conductive process on the exposed edge of the active layer;
depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole through plasma dry etching;
At least a part of the projection area of the first shading area on the shading layer and the projection area of the first through hole on the shading layer are overlapped;
And at least part of the projection area of the second shading area on the shading layer and the projection area of the second through hole on the shading layer are overlapped.
On the one hand, the shading function of the shading unit is not shaded, and meanwhile, even if the interlayer insulating layer via hole etching quantity is excessively etched to the shading layer due to the technical problem, a path from a source electrode to the shading unit to a drain electrode to an anode ITO is not formed, so that bright point defects can not be caused when the drain electrode supplies voltage. The scheme of the embodiment can obviously reduce the occurrence rate of bad bright spots, thereby obviously improving the display quality of the product.
Example 2:
FIG. 5 is a schematic cross-sectional view of another display panel;
The present example provides a display panel including a substrate base plate 10, and a plurality of thin film transistors fabricated thereon, including an active layer 40, a gate electrode 60, and a source/drain electrode layer 80; the projection area of the active layer 40 on the substrate has an overlapping and non-overlapping portion with the projection area of the gate electrode on the substrate. Generally, the active layer is made of amorphous silicon, polysilicon, metal oxide, or other semiconductor materials. Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping portion may be used for making electrical connection by doping metal ions into the conductor region 401; and the overlap constitutes an active region in the thin film transistor, i.e., channel region 402.
A metal shading layer 20 deposited on the substrate 10 is also included between the substrate 10 and the thin film transistor; the light shielding unit 20 is a light shielding metal layer, and is composed of a plurality of light shielding units corresponding to the plurality of thin film transistors one by one, and the projection of each light shielding unit on the substrate is at least overlapped with the projection of each thin film transistor on the substrate, so as to protect the active layer structure in the thin film transistor thereon from being directly irradiated by light, and avoid the functional failure or weakening of the transistor.
The display panel also comprises a plurality of functional layers, wherein: a buffer layer 30 disposed between the light shielding layer 20 and the active layer 40 for relieving the influence of external stress on the inside of the display panel; a gate insulating layer 50 disposed between the active layer 40 and the gate electrode 60 for avoiding electrical connection between the active layer and the gate electrode; an interlayer insulating layer 70 disposed inside the thin film transistor for preventing the source and drain electrodes from being electrically connected to other connection lines in the display panel, and a passivation layer 90 disposed in a direction away from the substrate to cover the thin film transistor; wherein, the source and drain electrodes of the thin film transistor on the display panel are connected with the conductive region 401 of the active layer 40 through the first via 701 arranged in the interlayer insulating layer 70; the source/drain electrodes of the thin film transistor on the display panel are connected to the light shielding layer 40 through the second via holes 702 penetrating the interlayer insulating layer 70 and the buffer layer 30; the source and drain electrodes of the thin film transistor on the display panel are electrically connected with the anode layer 100 through the passivation layer, and the anode layer is made of transparent electrode ITO.
In the display panel, a light shielding unit corresponding to a thin film transistor includes a first light shielding region 201 and a second light shielding region 202 disposed surrounding the first light shielding region; preferably, the light shielding unit is designed into a structure with partial insulation;
the first shading area is positioned in a projection area of the first via hole on the shading area and is contacted with a source electrode or a drain electrode in the first via hole;
The second shading area is positioned outside the projection area of the first via hole on the shading layer and is contacted with the drain electrode or the source electrode in the second via hole;
FIG. 6 is a schematic view of another light shielding unit;
Within the light shielding unit, the first light shielding region is surrounded by the second light shielding region; the light shielding units are of an integrated structure, wherein the first light shielding units and the second light shielding units are connected with each other;
The first light shielding unit is configured as an insulating material, and the second light shielding unit is configured as a conductive material; the insulating material may be a metal oxide or a metal nitride; the conductive material can be selected from metal conductive materials such as iron, aluminum, silver, molybdenum or aluminum-molybdenum-niobium alloy, or nano materials with higher conductivity. On the one hand, the shading function of the shading layer is not affected, and meanwhile, even when the first via hole is contacted with the shading unit due to the technical problem, the existence of the first shading area ensures that the over-etching area corresponding to the shading layer is an insulating area, and a passage between the drain electrode and the anode ITO is not formed, so that the bright spot defect caused by the voltage applied to the drain electrode is avoided.
FIG. 7 is a schematic diagram of a process flow for manufacturing a display panel;
The preparation method of the display panel comprises the following steps: providing a substrate base plate, and sequentially patterning and depositing a shading layer, a depositing buffer layer, patterning and depositing to form an active layer, depositing a grid insulating layer, patterning and depositing to form a grid, depositing an interlayer insulating layer, patterning and depositing to form a source electrode and a drain electrode;
a plurality of light shielding units are included on the light shielding layer; forming a first shading area and a second shading area on the shading unit, wherein the first shading area and the second shading area are arranged in a staggered mode;
Forming a plurality of thin film transistors on the light shielding units correspondingly;
Preferably, when forming a plurality of the light shielding units, the method includes: performing exposure development process by using a half-tone mask, completely reserving photoresist of an opaque region corresponding to the second shading region, partially reserving photoresist of a semi-transparent region corresponding to the first shading region, developing to remove photoresist of the completely transparent region, and performing etching process to form a first shading layer pattern;
Ashing the residual photoresist on the light shielding layer pattern to remove the photoresist in the semi-transparent area;
oxidizing or nitriding the exposed part of the first shading area corresponding to the semi-transparent area to form an insulator;
stripping all photoresist to form the light shielding layer
Wherein the light shielding units are configured as an integral structure, wherein the first light shielding region and the second light shielding region are configured to be directly connected to each other;
The first light shielding region is configured as a metal oxide or metal nitride material, and the second light shielding region is configured as a metal material;
depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole through plasma dry etching;
At least a part of the projection area of the first shading area on the shading layer and the projection area of the first through hole on the shading layer are overlapped;
And at least part of the projection area of the second shading area on the shading layer and the projection area of the second through hole on the shading layer are overlapped.
On the one hand, the shading function of the shading unit is not affected, and meanwhile, even if the interlayer insulating layer hole is punched on the shading layer due to the technical problem, a path from the source electrode to the shading unit to the drain electrode to the anode ITO is not formed, so that bright point defects can not be caused when the drain electrode supplies voltage.
By adopting the technical scheme, the defect of high bright spots caused by short circuit between the source/drain electrodes and the shading layer can be effectively solved, so that the display quality of a product is obviously improved, and the technical proposal does not increase any exposure procedure.
Example 3:
The present embodiment provides a display device including the display panel described in embodiment 1 or embodiment 2. The display device may be: OLED panel, cell phone, tablet computer, digital photo frame, notebook computer, display, TV set, navigator, vehicle-mounted multifunctional rearview mirror device, etc.
The display device of the embodiment has the display panel of the embodiment 1 or 2, so that the preparation process is simple, the process reliability is high, the problem of bad effect caused by local short circuit is solved, and the display effect and the product quality can be effectively improved.
Of course, other conventional structures such as a power supply unit, a display driving unit, a light emitting unit, a packaging unit, and a frame structure may be included in the display device of the present embodiment.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and include, for example, either fixedly attached, detachably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
It is to be understood that the foregoing description is only exemplary embodiments of the application and is made in the context of the principles, structures and process steps employed. It should be understood by those skilled in the art that the scope of the application referred to in the present application is not limited to the specific combination of the above technical features, but also encompasses other technical features formed by any combination of the above technical features or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.
Claims (14)
1. A display panel, characterized by comprising:
a substrate base, and
A shading layer and a plurality of thin film transistors arranged in an array on the substrate;
the light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned at one side of the thin film transistor, which is close to the direction of the substrate base plate;
A buffer layer is arranged on the substrate base plate in the direction away from the shading layer;
The thin film transistor comprises an active layer, a gate insulating layer, a gate, an interlayer insulating layer and a source drain layer which are sequentially arranged in the direction away from the buffer layer;
The active layer comprises a conductive region which is not overlapped with the projection of the active layer and the gate insulating layer on the substrate, and a channel region which is overlapped with the projection of the active layer and the gate insulating layer on the substrate;
The source-drain electrode layer comprises a first electrode and a second electrode;
the light shielding unit comprises a first light shielding area and a second light shielding area, and the second light shielding area is arranged surrounding the first light shielding area;
The projection of the channel region on the substrate is positioned in the projection of the second shading region on the substrate;
The thin film transistor is sequentially provided with a passivation layer and an anode in a direction away from the substrate,
The anode is electrically connected to the second electrode, wherein,
The interlayer insulating layer comprises a first via hole and a second via hole;
at least part of the projection area of the first shading area and the first via hole on the shading layer has an overlapping area;
and at least part of the projection area of the second shading area and the second through hole on the shading layer has an overlapping area.
2. The display panel of claim 1, wherein,
At least a portion of the first electrode is located within the first via; the first shading area is completely overlapped with the projection area of the first via hole on the shading layer, and is contacted with the first electrode through the first via hole.
3. The display panel of claim 1, wherein,
At least a portion of the second electrode is located within the second via; the second shading area is positioned outside the projection area of the first via hole on the shading layer and is contacted with the second electrode through the second via hole.
4. The display panel according to claim 1, wherein the first light shielding region and the second light shielding region are isolated from each other by a slit within the light shielding unit, and are not connected to each other.
5. The display panel of claim 4, wherein a projection of the slit onto the substrate falls entirely outside a projection area of the channel region onto the substrate.
6. The display panel of claim 4, wherein the first and second light shielding regions comprise a metal conductive material such as aluminum, molybdenum or aluminum molybdenum niobium alloy, and have a thickness of 0.20-0.25 um.
7. The display panel of claim 1, wherein the first light-shielding region and the second light-shielding region are integrally seamlessly connected.
8. The display panel of claim 6, wherein the first light shielding region is an insulating material and the second light shielding region is configured as a conductive material.
9. The display panel according to claim 8, wherein the insulating material of the first light shielding region is a metal oxide or a metal nitride, and the conductive material of the second light shielding region is a metal material such as aluminum, molybdenum or an aluminum molybdenum niobium alloy, and has a thickness of 0.20 to 0.25um.
10. A display device comprising the display panel of any one of claims 1-9.
11. A method of manufacturing a display panel, comprising:
providing a substrate base plate, and
Patterning and depositing a plurality of light shielding units forming a light shielding layer, forming a first light shielding region and a second light shielding region on the light shielding units, the second light shielding region being configured to surround the first light shielding region;
depositing a buffer layer, patterning and depositing to form an active layer, depositing a gate insulating layer, patterning and depositing to form a gate, depositing an interlayer insulating layer, patterning and depositing to form a source drain layer,
The interlayer insulating layer comprises a first via hole and a second via hole;
at least part of the projection area of the first shading area and the first via hole on the shading layer has an overlapping area;
and at least part of the projection area of the second shading area and the second through hole on the shading layer has an overlapping area.
12. The manufacturing method of the display panel according to claim 11, comprising:
when a plurality of light shielding units are formed, preparing gaps through photoresist coating, exposure, development and dry etching processes, so that the first light shielding area is surrounded by the second light shielding area and is isolated from the second light shielding area through the gaps;
The first light shielding region and the second light shielding region are both made of metal conductive materials.
13. The display panel manufacturing method according to claim 12, comprising:
Depositing a buffer layer on the light shielding unit, patterning the buffer layer by using photoresist to form an active layer, patterning the active layer to form a gate insulating layer, and patterning the gate insulating layer to form a metal gate;
the photoresist used in the process of patterning above the grid electrode is reserved, a self-alignment process is adopted to etch the grid electrode insulating layer, the edge of the active layer is exposed, and a conductor process is carried out on the edge of the active layer;
And depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming the first via hole and the second via hole through plasma dry etching.
14. The display panel manufacturing method according to claim 11, when forming a plurality of the light shielding units, comprising:
Performing exposure development process by using a half-tone mask, completely reserving photoresist of an opaque region corresponding to the second shading region, partially reserving photoresist of a semi-transparent region corresponding to the first shading region, developing to remove photoresist of the completely transparent region, and performing etching process to form a first shading layer pattern;
Ashing the residual photoresist on the light shielding layer pattern to remove the photoresist in the semi-transparent area;
oxidizing or nitriding the exposed part of the first shading area corresponding to the semi-transparent area to form an insulator;
Stripping all the photoresist to form the shading layer;
Wherein the light shielding units are configured as an integral structure, and the first light shielding area and the second light shielding area are configured as seamless connection;
The first light shielding region is configured as a metal oxide or metal nitride material, and the second light shielding region is configured as a metal material;
And depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming the first via hole and the second via hole through plasma dry etching.
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| CN111370426B (en) * | 2020-03-16 | 2023-06-23 | 合肥鑫晟光电科技有限公司 | Display backboard, manufacturing method thereof and display device |
| CN111415995B (en) * | 2020-04-01 | 2023-05-26 | 合肥鑫晟光电科技有限公司 | Display panel, manufacturing method thereof and display device |
| CN111463252B (en) * | 2020-04-20 | 2022-12-30 | 合肥鑫晟光电科技有限公司 | Display panel, preparation method thereof and display device |
| CN111524954B (en) * | 2020-05-08 | 2022-11-25 | 京东方科技集团股份有限公司 | Display substrate, maintenance method thereof and display device |
| CN111584593B (en) * | 2020-05-25 | 2024-02-23 | 京东方科技集团股份有限公司 | Display panel, display device and manufacturing method of display panel |
| CN113871420A (en) | 2020-06-30 | 2021-12-31 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN111898517A (en) * | 2020-07-28 | 2020-11-06 | 北海惠科光电技术有限公司 | Optical fingerprint sensor, preparation method thereof and display device |
| WO2022183343A1 (en) * | 2021-03-01 | 2022-09-09 | 京东方科技集团股份有限公司 | Display panel and display device |
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