CN114975486A - Array substrate, display panel and manufacturing method of array substrate - Google Patents

Array substrate, display panel and manufacturing method of array substrate Download PDF

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Publication number
CN114975486A
CN114975486A CN202210699732.9A CN202210699732A CN114975486A CN 114975486 A CN114975486 A CN 114975486A CN 202210699732 A CN202210699732 A CN 202210699732A CN 114975486 A CN114975486 A CN 114975486A
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layer
active
active layer
substrate
display area
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陈远鹏
胡凯
刘方梅
其他发明人请求不公开姓名
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer

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Abstract

The embodiment of the application discloses an array substrate, a display panel and a manufacturing method of the array substrate. The array substrate comprises a substrate and a thin film transistor layer, the thin film transistor layer comprises a first active layer, a second active layer and a gate layer, the first active layer comprises a first active part located in a non-display area, the second active layer comprises a second active part located in the non-display area and a third active part located in a display area, the second active part and the first active part are arranged in a stacked mode, the mobility of the first active layer is larger than that of the second active layer, and the gate layer is located on one side, away from the first active layer, of the second active layer. This application is through adopting first active portion and the second active portion of range upon range of setting in the non-display area to set up the grid layer in the one side that is close to the lower second active portion of mobility, make improving non-display area drive current ability, reduce non-display area design size, when realizing the design of narrow frame, can guarantee the drive stability in non-display area.

Description

Array substrate, display panel and manufacturing method of array substrate
Technical Field
The application relates to the field of display, in particular to an array substrate, a display panel and a manufacturing method of the array substrate.
Background
With the development of display technologies, narrow bezel designs are becoming popular. The frame size of the display panel is directly related to the structure of the non-display area driving circuit in the array substrate, and in order to further improve the quality of the display panel and reduce the frame size of the display panel, the driving current capability of the non-display area driving circuit in the array substrate needs to be improved to reduce the size of the driving circuit. However, in the prior art, the driving stability cannot be ensured while the driving current capability of the driving circuit in the non-display area of the array substrate is improved, so that the overall performance is affected.
Disclosure of Invention
The embodiment of the application provides an array substrate, a display panel and a manufacturing method of the array substrate, and can solve the problem that the driving stability cannot be guaranteed while the driving current capability of a driving circuit in a non-display area of the array substrate is improved in the prior art.
An embodiment of the present application provides an array substrate, including:
a substrate including a display region and a non-display region;
the thin film transistor layer is arranged on the substrate base plate; the thin film transistor layer comprises a first active layer, a second active layer and a gate layer, the first active layer comprises a first active part located in the non-display area, the second active layer comprises a second active part located in the non-display area and a third active part located in the display area, the second active part and the first active part are arranged in a stacked mode, and the mobility of the first active layer is larger than that of the second active layer; the gate layer is located on a side of the second active layer facing away from the first active layer.
Optionally, in some embodiments of the present application, the first active layer and the second active layer are sequentially disposed in a direction away from the substrate base plate.
Optionally, in some embodiments of the present application, the second active portion covers a side face of the first active portion.
Optionally, in some embodiments of the present application, the thin film transistor layer further includes an interlayer dielectric layer and a source drain layer sequentially disposed along a direction away from the second active layer; a contact hole is formed in the interlayer dielectric layer, part of the second active part is exposed out of the contact hole, and the source drain layer is electrically connected with the second active part through the contact hole;
the second active part exposed from the contact hole is positioned on one side of the side surface of the first active part; or the like, or, alternatively,
the second active part exposed from the contact hole is positioned on one side of the first active part, which is deviated from the substrate base plate.
Optionally, in some embodiments of the present application, the array substrate further includes a light shielding layer and a buffer layer stacked between the substrate and the thin film transistor layer, the light shielding layer is located in the display area, and the light shielding layer and the third active portion are disposed correspondingly.
Optionally, in some embodiments of the present application, the second active layer and the first active layer are sequentially disposed in a direction away from the substrate base plate.
Optionally, in some embodiments of the present application, an orthogonal projection of the first active portion on the substrate base plate is located within an orthogonal projection of the second active portion on the substrate base plate.
Optionally, in some embodiments of the present application, the material of the first active layer and the second active layer includes an oxide semiconductor material; the content of the indium element in the first active layer is larger than that in the second active layer.
Optionally, in some embodiments of the present application, a material of the first active layer includes one or more of indium gallium zinc tin oxide, indium tin oxide, and indium zinc oxide; the second active layer is made of indium gallium zinc oxide, and the contents of indium element, gallium element and zinc element in the second active layer are the same.
Optionally, in some embodiments of the present application, a thickness of the first active layer is greater than or equal to 50 angstroms and less than or equal to 1000 angstroms; the second active layer has a thickness greater than or equal to 100 angstroms and less than or equal to 1000 angstroms.
Correspondingly, the embodiment of the present application further provides a display panel, where the display panel includes:
the array substrate of any of the above;
a light emitting device disposed on the array substrate;
and the packaging assembly is arranged on one side of the light-emitting device, which is far away from the packaging assembly.
Correspondingly, an embodiment of the present application further provides a manufacturing method of an array substrate, where the method includes:
providing a substrate, wherein the substrate comprises a display area and a non-display area;
forming a thin film transistor layer on the substrate base plate; the thin film transistor layer comprises a first active layer, a second active layer and a gate layer, the first active layer comprises a first active part located in the non-display area, the second active layer comprises a second active part located in the non-display area and a third active part located in the display area, the second active part and the first active part are arranged in a stacked mode, and the mobility of the first active layer is larger than that of the second active layer; the gate layer is located on a side of the second active layer facing away from the first active layer.
Optionally, in some embodiments of the present application, the forming a thin film transistor layer on the substrate includes:
forming a first active layer on the substrate base plate, and carrying out patterning treatment on the first active layer so as to form a first active part on the substrate base plate at a position corresponding to the non-display area;
forming a second active layer on one side of the first active layer, which is far away from the substrate base plate, and carrying out patterning treatment on the second active layer so as to form a second active part in the non-display area and a third active part in the display area, so that the second active part and the first active part are arranged in a stacked mode;
and sequentially forming a gate insulating layer, a gate layer, an interlayer dielectric layer and a source drain layer on one side of the second active layer, which is far away from the substrate, so as to form a thin film transistor layer.
Optionally, in some embodiments of the present application, the forming a thin film transistor layer on the substrate includes:
sequentially forming a gate electrode layer and a gate insulating layer on the substrate;
forming a second active layer on one side, away from the substrate, of the gate insulating layer, and performing patterning treatment on the second active layer to form a second active part in the non-display area and a third active part in the display area;
forming a first active layer on one side of the second active layer, which is far away from the substrate base plate, and carrying out patterning treatment on the first active layer so as to form a first active part in the non-display area, wherein the first active part and the second active part are arranged in a laminated mode;
and sequentially forming an interlayer dielectric layer and a source drain layer on one side of the first active layer, which is far away from the substrate, so as to form a thin film transistor layer.
The array substrate in the embodiment of the application comprises a substrate and a thin film transistor layer, wherein the thin film transistor layer comprises a first active layer, a second active layer and a gate layer, the first active layer comprises a first active part located in a non-display area, the second active layer comprises a second active part located in the non-display area and a third active part located in a display area, the second active part and the first active part are arranged in a stacked mode, the mobility of the first active layer is larger than that of the second active layer, and the gate layer is located on one side, away from the first active layer, of the second active layer. According to the non-display area driving circuit, the first active part and the second active part which are arranged in a stacked mode are adopted in the non-display area, the grid layer is arranged on one side close to the second active part with the lower mobility rate, the non-display area driving current capacity is improved, the design size of the non-display area is reduced, and the driving stability of the non-display area can be guaranteed while the narrow frame design is achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another array substrate provided in the present embodiment;
fig. 3 is a schematic structural diagram of another array substrate provided in the present application;
fig. 4 is a schematic structural diagram of another array substrate provided in the embodiment of the present application;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;
fig. 6 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 7 is a flowchart of step S200 in fig. 6 provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of step S210 in fig. 7 according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of step S220 in fig. 7 according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of step S230 in fig. 7 according to an embodiment of the present application.
Description of reference numerals:
Figure BDA0003703534290000041
Figure BDA0003703534290000051
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
Embodiments of the present application provide an array substrate, a display panel and a method for manufacturing the array substrate, which are described in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
First, an array substrate is provided in an embodiment of the present application. As shown in fig. 1 to 4, the array substrate 100 includes a substrate 110, and the substrate 110 is used as a support structure of the array substrate 100 and is used for supporting a functional structure layer disposed on the substrate 110 to ensure structural stability of the array substrate 100. The substrate 110 may be a glass substrate or other material type, and is not limited herein.
The substrate 110 may be divided into a display area S1 and a non-display area S2, and when a subsequent film is manufactured, a position on the substrate 110 corresponding to the display area S1 is used to form a functional structure layer related to the light emitting pixels, and a position on the substrate 110 corresponding to the non-display area S2 is used to form a peripheral driving circuit, so as to control the display of the corresponding light emitting pixels in the display area S1.
Array substrate 100 includes a thin-film-transistor layer 140, thin-film-transistor layer 140 being disposed on substrate 110. The thin-film transistor layer 140 includes a first active layer 141, a second active layer 142, and a gate layer 144, the first active layer 141 includes a first active portion 1411 located in the non-display region S2, the second active layer 142 includes a second active portion 1421 located in the non-display region S2 and a third active portion 1422 located in the display region S1, and the second active portion 1421 is stacked with the first active portion 1411. That is, in the manufacturing of the array substrate 100, the first thin film transistor in the thin film transistor layer 140 located in the non-display region S2 and the second thin film transistor in the display region S1 share the second active layer 142, and the first thin film transistor includes a dual active layer.
The mobility of the first active layer 141 is greater than that of the second active layer 142, that is, the first thin film transistor and the second thin film transistor share the low mobility active layer, and the first thin film transistor includes two active layers with different mobility levels. By the structural design, the stability of the second thin film transistor is guaranteed, and meanwhile the mobility of the first thin film transistor can be improved, so that the design size of the first thin film transistor in the non-display area S2 can be reduced under the same driving current, and the narrow frame design is realized.
Optionally, the gate layer 144 is located on a side of the second active layer 142 away from the first active layer 141, that is, the second active portion 1421 with lower mobility in the first thin film transistor is disposed close to the gate layer 144. Due to the structural design, in the using process of the first thin film transistor in the non-display area S2, the conductive channel is formed in the second active portion 1421 with low mobility, and compared with the conductive channel formed in the first active portion 1411 with high mobility, the current offset occurring in the driving process can be reduced, so that the driving stability of the first thin film transistor in the non-display area S2 is improved.
In the embodiment of the present invention, the array substrate 100 includes a substrate 110 and a thin-film transistor layer 140, the thin-film transistor layer 140 includes a first active layer 141, a second active layer 142, and a gate layer 144, the first active layer 141 includes a first active portion 1411 located in a non-display region S2, the second active layer 142 includes a second active portion 1421 located in the non-display region S2 and a third active portion 1422 located in a display region S1, the second active portion 1421 is stacked with the first active portion 1411, a mobility of the first active layer 141 is greater than a mobility of the second active layer 142, and the gate layer 144 is located on a side of the second active layer facing away from the first active layer 141. According to the invention, the first active part 1411 and the second active part 1421 which are arranged in a stacked manner are adopted in the non-display area S2, and the gate layer 144 is arranged at one side close to the second active part 1421 with lower mobility, so that the driving current capability of the non-display area S2 is improved, the design size of the non-display area S2 is reduced, the narrow-frame design is realized, and the driving stability of the non-display area S2 can be ensured.
Alternatively, as shown in fig. 1 to 3, the first active layer 141 and the second active layer 142 are sequentially disposed along a direction away from the substrate 110, that is, the first active portion 1411 in the non-display region S2 is located at a side close to the substrate 110, the second active portion 1421 is located at a side away from the substrate 110, and the gate layer 144 is located at a side of the second active layer 142 away from the first active layer 141, that is, the first thin film transistor in the non-display region S2 and the second thin film transistor in the display region S1 are of a top gate structure.
Optionally, as shown in fig. 1, when the first thin film transistor in the non-display area S2 is of a top gate structure, the second active portion 1421 covers a side surface of the first active portion 1411, that is, when the second active layer 142 is subjected to a patterning process, the second active portion 1421 completely wraps the first active portion 1411 to protect the first active portion 1411, so as to avoid affecting the first active portion 1411 when the second active layer 142 is subjected to the patterning process, and improve the structural stability of the first thin film transistor in the non-display area S2.
The thin film transistor layer 140 further includes a gate insulating layer 143 disposed between the gate layer 144 and the second active layer 142, and an interlayer dielectric layer 145 and a source drain layer 146 sequentially disposed along a direction away from the gate layer 144, wherein the interlayer dielectric layer 145 is opened with a contact hole 1451, the contact hole 1451 exposes a portion of the second active portion 1421, and the source drain layer 146 is electrically connected to the second active portion 1421 through the contact hole 1451. The top gate structure design can effectively reduce parasitic capacitance generated by overlapping of the gate in the gate layer 144 and the source and drain in the source and drain layer 146, reduce capacitance-resistance delay in the array substrate 100, and improve the driving quality of the array substrate 100.
In some embodiments, as shown in fig. 1, the second active portion 1421 exposed by the contact hole 1451 is located on one side of the side surface of the first active portion 1411, that is, the position corresponding to the contact hole 1451 only includes the second active portion 1421, that is, after the second active portion 1421 covers the side surface of the first active portion 1411, the second active portion 1421 continues to extend in a direction away from the side surface of the first active portion 1411 for making an electrical connection with the source drain layer 146. Because the gate in the gate layer 144 is stacked on the first active portion 1411 and the second active portion 1421, such a structural design can further avoid the parasitic capacitance generated by the overlap between the gate in the gate layer 144 and the source and drain in the source and drain layer 146, thereby reducing the capacitance-resistance delay in the array substrate 100 and improving the driving quality of the array substrate 100.
In other embodiments, as shown in fig. 2, the second active portion 1421 exposed by the contact hole 1451 is located on a side of the first active portion 1411 facing away from the substrate 110, that is, a position corresponding to the contact hole 1451 includes both the second active portion 1421 and the first active portion 1411 which are stacked. The structural design can reduce the depth of the contact hole 1451 on the interlayer dielectric layer 145, thereby facilitating the improvement of the connection effect between the source/drain layer 146 and the second active portion 1421.
In still other embodiments, as shown in fig. 3, when the first thin film transistor of the non-display region S2 is of a top gate structure, the second active portion 1421 may be disposed only above the first active portion 1411, such that an orthographic projection of the second active portion 1421 on the substrate 110 overlaps with an orthographic projection of the first active portion 1411 on the substrate 110, or such that an orthographic projection of the second active portion 1421 on the substrate 110 is located inside an orthographic projection of the first active portion 1411 on the substrate 110. This structure design is helpful to further reduce the design size of the first thin film transistor in the non-display region S2, so as to realize a narrow frame design.
Optionally, when the first thin film transistor and the second thin film transistor are of a top gate structure, the array substrate 100 may further include a light shielding layer 120 and a buffer layer 130 stacked between the substrate 110 and the thin film transistor layer 140, wherein the light shielding layer 120 is located in the display region S1, and the light shielding layer 120 and the third active portion 1422 are correspondingly disposed to shield the third active portion 1422, so as to prevent external ambient light from directly irradiating the third active portion 1422 to affect the structural stability of the third active portion 1422. The buffer layer 130 is used to separate the light shielding layer 120 from the third active portion 1422, so as to prevent interference between the light shielding layer 120 and the third active portion 1422 from affecting normal use of the array substrate 100.
It should be noted that the buffer layer 130 is designed on the substrate base plate 110 in a whole surface, that is, the buffer layer 130 is located in both the display region S1 and the non-display region S2, and due to the existence of a large amount of impurity ions in the substrate base plate 110, the buffer layer 130 is also configured to effectively block the impurity ions in the substrate base plate 110 from entering the first active layer 141 and the second active layer 142, so as to ensure the structural stability of the first active layer 141 and the second active layer 142.
In some embodiments, when the light-shielding layer 120 is patterned, the light-shielding layer 120 can be simultaneously disposed at the positions of the non-display region S2 corresponding to the first active portion 1411 and the second active portion 1421 to shield the first active portion 1411 and the second active portion 1421, so as to prevent external ambient light from directly irradiating the first active portion 1411 and the second active portion 1421, so as to further improve the structural stability of the first thin film transistor in the non-display region S2, thereby improving the driving stability.
Alternatively, the light-shielding layer 120 may have a single-layer structure or a multi-layer structure. For example, when the light-shielding layer 120 has a double-layer structure, a layer close to the substrate 110 may be a metal layer, including copper or aluminum, and the thickness thereof may be set to be greater than or equal to 2000 angstroms and less than or equal to 5000 angstroms; the layer far from the substrate base plate 110 may be a transition metal layer including molybdenum, titanium, tungsten, chromium, or nickel, and a corresponding metal alloy, etc., and the thickness thereof may be set to be greater than or equal to 50 angstroms and less than or equal to 500 angstroms. The light shielding layer 120 is arranged to be of a double-layer structure, so that the transition metal layer can protect the metal layer to a certain extent, and the phenomenon that when a subsequent film layer is processed, part of the surface of the light shielding layer 120 is oxidized or corroded due to long-time exposure is avoided, and the overall performance of the array substrate 100 is affected.
In the actual manufacturing process, copper can be used as a metal layer, and the thickness is set to 2000 angstroms, 3000 angstroms, 4000 angstroms or 5000 angstroms; a molybdenum-titanium alloy can be used as the transition metal layer and the thickness can be set to 50 angstroms, 100 angstroms, 200 angstroms, 300 angstroms, 400 angstroms, or 500 angstroms. The specific values of the material and the thickness of the light-shielding layer 120 can be adjusted according to the design and the usage requirement, and are not limited herein.
Alternatively, as shown in fig. 4, the second active layer 142 and the first active layer 141 are sequentially disposed in a direction away from the base substrate 110, that is, the second active portion 1421 in the non-display region S2 is located at a side close to the base substrate 110, the first active portion 1411 is located at a side away from the base substrate 110, and the gate layer 144 is located at a side of the second active layer 142 away from the first active layer 141, that is, the first thin film transistor of the non-display region S2 and the second thin film transistor of the display region S1 are of a bottom gate structure.
At this time, the thin film transistor layer 140 further includes a gate insulating layer 143 disposed between the gate layer 144 and the second active layer 142, and an interlayer dielectric layer 145 and a source drain layer 146 sequentially disposed in a direction away from the first active layer 141. The gate layer 144 in the bottom gate structure can shield light, so that the number of the light-shielding layer 120 can be reduced, the thickness of the array substrate 100 can be reduced, and the light and thin design of the array substrate 100 can be facilitated.
Optionally, when the first thin film transistor in the non-display area S2 is of a bottom-gate structure, the first active portion 1411 is disposed above the second active portion 1421, so that an orthogonal projection of the first active portion 1411 on the substrate base 110 is located in an orthogonal projection of the second active portion 1421 on the substrate base 110, and this structure is favorable for effective connection between the source/drain layer 146 disposed subsequently in the non-display area S2 and the second active portion 1421 with lower mobility.
It should be noted that, when the first thin film transistor and the second thin film transistor are of a bottom-gate structure, the array substrate 100 can further include a buffer layer 130 disposed between the substrate 110 and the thin film transistor layer 140, where the buffer layer 130 is of a full-surface design, and the buffer layer 130 can be disposed to planarize the surface of the substrate 110 and isolate impurity ions in the substrate 110.
Since the gate layer 144 has a more stable structure than the active layer and is not easily affected by the impurity ions in the substrate 110, when the gate layer 144 is formed, the gate layer 144 can be directly disposed on the substrate 110 without disposing the buffer layer 130, and this structural design can further reduce the overall thickness of the array substrate 100, which is beneficial to the light and thin design of the array substrate 100.
It should be noted that in the embodiment of the present application, the first thin film transistor located in the non-display area S2 and the second thin film transistor located in the display area S1 are configured as the same type of thin film transistor, that is, both are of a top gate structure or a bottom gate structure, so that when the thin film transistor layer 140 is fabricated, corresponding films in the first thin film transistor and the second thin film transistor can be simultaneously formed by using a mask, which is helpful to simplify the fabrication process of the array substrate 100 and ensure consistency of corresponding structures in the first thin film transistor and the second thin film transistor.
Alternatively, the materials of the first active layer 141 and the second active layer 142 in the embodiment of the present application include oxide semiconductor materials, and the oxide semiconductor has high mobility and low leakage current characteristics compared to amorphous silicon, and has the characteristics of large area uniformity and lower cost compared to low temperature polysilicon, thereby facilitating large and medium size current-driven displays.
The mobility of the first active layer 141 is greater than that of the second active layer 142, and the material of the first active layer 141 includes one or more of Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), and Indium Zinc Oxide (IZO); the material of the second active layer 142 includes Indium Gallium Zinc Oxide (IGZO), and the contents of indium element, gallium element, and zinc element in the second active layer 142 are the same, that is, the second active layer 142 adopts Indium Gallium Zinc Oxide (IGZO) with the content ratio of indium, gallium, and zinc being 1:1:1, so as to ensure the stability of the second thin film transistor in the display region S1.
It should be noted that the first active layer 141 and the second active layer 142 can directly select different types of materials so that the mobility of the first active layer 141 is greater than that of the second active layer 142; alternatively, the same type of material is used for the first active layer 141 and the second active layer 142, and then the content of the indium element in the first active layer 141 is greater than that in the second active layer 142 by adjusting the content of the indium element in the corresponding film layer, so that the mobility of the first active layer 141 is greater than that of the second active layer 142.
Optionally, the thickness of the first active layer 141 is greater than or equal to 50 angstroms and less than or equal to 1000 angstroms. If the thickness of the first active layer 141 is too small, it may result in poor conductivity of the first active layer 141; if the thickness of the first active layer 141 is too large, the overall thickness of the array substrate 100 is too large, which is not favorable for light and thin design. In an actual manufacturing process, the thickness of the first active layer 141 can be designed to be 50 angstroms, 100 angstroms, 200 angstroms, 500 angstroms, 800 angstroms or 1000 angstroms, so as to ensure the conductivity of the first active layer 141 and avoid the excessive thickness of the array substrate 100 as a whole, and the specific value of the thickness can be adjusted according to real-time design requirements, which is not limited herein.
Optionally, the thickness of the second active layer 142 is greater than or equal to 100 angstroms and less than or equal to 1000 angstroms. If the thickness of the second active layer 142 is too small, it may result in poor conductivity of the second active layer 142; if the thickness of the second active layer 142 is too large, the overall thickness of the array substrate 100 is too large, which is not favorable for light and thin design. In an actual manufacturing process, the thickness of the second active layer 142 can be designed to be 100 angstroms, 200 angstroms, 500 angstroms, 800 angstroms or 1000 angstroms, so as to avoid the excessive thickness of the array substrate 100 while ensuring the electrical conductivity of the second active layer 142, and the specific value of the thickness can be adjusted according to real-time design requirements, which is not limited herein.
It should be noted that, since the display region S1 includes only the third active portion 1422 of the second active layer 142, the non-display region S2 includes both the first active portion 1411 of the first active layer 141 and the second active portion 1421 of the second active layer 142, i.e., the arrangement of the first active layer 141 increases the step difference correspondingly generated in the non-display region S2. In the design process, the thickness of the first active layer 141 can be set to be smaller than that of the second active layer 142, so as to reduce the influence of the step difference generated by the first active layer 141 on the subsequent film layer fabrication.
Optionally, the array substrate 100 further includes a passivation layer 150, where the passivation layer 150 is disposed on a side of the source/drain layer 146 away from the substrate 110 to protect an internal structure of the thin film transistor layer 140, and simultaneously isolate the source/drain layer 146 to avoid mutual interference between the array substrate 100 and a subsequent functional structure layer when in use. The passivation layer 150 is made of one or more materials selected from silicon nitride, silicon oxide, and silicon oxynitride, and the thickness thereof may be set to be greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms, and the specific design value of the thickness can be adjusted according to the actual use requirement, which is not limited herein.
Next, an embodiment of the present application provides a display panel, where the display panel includes an array substrate, and a specific structure of the array substrate refers to the above embodiments, and since the display panel adopts all technical solutions of all the above embodiments, the display panel at least has all beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated here.
As shown in fig. 5, the display panel 10 includes an array substrate 100, a light emitting device 200, and a package assembly 300. The light emitting device 200 is disposed on the array substrate 100, and the array substrate 100 is electrically connected to the light emitting device 200 to regulate and control a light emitting manner of the light emitting device 200, so as to regulate and control an overall display manner of the display panel 10. The encapsulation assembly 300 is disposed on the light emitting device 200 to protect the internal structures of the light emitting device 200 and the array substrate 100, and prevent external moisture or oxygen from entering and corroding the internal structures of the light emitting device 200 or the array substrate 100, thereby ensuring the overall performance and the display effect of the display panel 10.
It should be noted that the application range of the display panel 10 in the embodiment of the present application is very wide, and the display device includes various display and illumination display devices such as a television, a computer, a mobile phone, a foldable and rollable display screen, and wearable devices such as an intelligent bracelet and an intelligent watch, and the like, and all of the application ranges of the display panel 10 in the embodiment of the present application are within the application range.
Finally, an embodiment of the present application further provides a manufacturing method of an array substrate, as shown in fig. 6, the manufacturing method of the array substrate mainly includes the following steps:
s100, providing a substrate 110, wherein the substrate 110 comprises a display area S1 and a non-display area S2.
When manufacturing the array substrate 100, firstly, a substrate 110 is provided, and the substrate 110 is cleaned and baked to remove stains on the surface of the substrate 110, so as to facilitate the subsequent film layer manufacturing. The substrate base plate 110 serves as a support structure of the array base plate 100, and is used for supporting the functional structure layer arranged on the substrate base plate 110, so as to ensure the structural stability of the array base plate 100. The substrate 110 may be a glass substrate or other material type, and is not limited herein.
The substrate 110 may be divided into a display area S1 and a non-display area S2, and when a subsequent film layer is manufactured, a position of the substrate 110 corresponding to the display area S1 is used to form a functional structure layer related to the light emitting pixels, and a position of the substrate 110 corresponding to the non-display area S2 is used to form a peripheral driving circuit to control the display of the corresponding light emitting pixels in the display area S1.
S200, forming a thin film transistor layer 140 on the substrate 110; the thin-film transistor layer 140 includes a first active layer 141, a second active layer 142, and a gate layer 144, the first active layer 141 includes a first active portion 1411 located in the non-display region S2, the second active layer 142 includes a second active portion 1421 located in the non-display region S2 and a third active portion 1422 located in the display region S1, the second active portion 1421 is stacked with the first active portion 1411, and mobility of the first active layer 141 is greater than mobility of the second active layer 142; the gate layer 144 is located on a side of the second active layer 142 facing away from the first active layer 141.
After substrate 110 is prepared, a thin-film-transistor layer 140 is formed on substrate 110, and thin-film-transistor layer 140 includes a first active layer 141, a second active layer 142, and a gate layer 144. The relative positions of the first active layer 141, the second active layer 142 and the gate layer 144 are different according to the structure type of the thin-film transistor layer 140, and the manufacturing sequence is also different.
The first active layer 141 includes a first active portion 1411 positioned in the non-display region S2, the second active layer 142 includes a second active portion 1421 positioned in the non-display region S2 and a third active portion 1422 positioned in the display region S1, the second active portion 1421 is stacked with the first active portion 1411, and mobility of the first active layer 141 is greater than mobility of the second active layer 142. That is, the first thin film transistor positioned in the non-display region S2 shares the second active layer 142 having low mobility with the second thin film transistor positioned in the display region S1, and the first thin film transistor includes both the first active layer 141 and the second active layer 142 having different mobility levels.
By the structural design, the stability of the second thin film transistor is guaranteed, and meanwhile the mobility of the first thin film transistor can be improved, so that the design size of the first thin film transistor in the non-display area S2 can be reduced under the same driving current, and the narrow frame design is realized.
The gate layer 144 is located on a side of the second active layer 142 away from the first active layer 141, that is, the second active portion 1421 with lower mobility in the first thin film transistor is disposed close to the gate layer 144. Due to the structural design, in the using process of the first thin film transistor in the non-display area S2, the conductive channel is formed in the second active portion 1421 with low mobility, and compared with the conductive channel formed in the first active portion 1411 with high mobility, the current offset occurring in the driving process can be reduced, so that the driving stability of the first thin film transistor in the non-display area S2 is improved.
Optionally, as shown in fig. 7, forming thin-film transistor layer 140 in step S200 specifically includes the following steps:
s210, a first active layer 141 is formed on the base substrate 110, and patterning is performed on the first active layer 141 to form a first active portion 1411 on the base substrate 110 at a position corresponding to the non-display region S2.
As shown in fig. 8, in fabricating the thin-film transistor layer 140, a first active layer 141 is first deposited on the substrate base 110, and the first active layer 141 is patterned to form a first active portion 1411 on the substrate base 110 at a position corresponding to the non-display region S2. The material of the first active layer 141 may be an oxide semiconductor material with high mobility, such as Indium Gallium Zinc Tin Oxide (IGZTO), Indium Tin Oxide (ITO), or Indium Zinc Oxide (IZO).
S220, forming a second active layer 142 on a side of the first active layer 141 away from the substrate base plate 110, and patterning the second active layer 142 to form a second active portion 1421 in the non-display region S2, and forming a third active portion 1422 in the display region S1, such that the second active portion 1421 and the first active portion 1411 are stacked.
As shown in fig. 9, after forming the first active portion 1411 on the substrate 110 at a position corresponding to the non-display area S2, a second active layer 142 is further deposited on a side of the first active layer 141 away from the substrate 110, and patterning is performed on the second active layer 142 to form a second active portion 1421 in the non-display area S2, a third active portion 1422 in the display area S1, and the second active portion 1421 and the first active portion 1411 are stacked. That is, the first thin film transistor positioned in the non-display region S2 shares the second active layer 142 having low mobility with the second thin film transistor positioned in the display region S1.
By the structural design, the stability of the second thin film transistor is guaranteed, and meanwhile the mobility of the first thin film transistor can be improved, so that the design size of the first thin film transistor in the non-display area S2 can be reduced under the same driving current, and the narrow frame design is realized.
It should be noted that, when the second active layer 142 is subjected to the patterning process, the second active portion 1421 can completely wrap the first active portion 1411 to protect the first active portion 1411, so as to avoid the first active portion 1411 from being affected when the second active layer 142 is subjected to the patterning process, and improve the structural stability of the first thin film transistor in the non-display region S2. Alternatively, the second active portion 1421 is disposed only above the first active portion 1411, so as to further reduce the design size of the first thin film transistor in the non-display region S2, thereby implementing a narrow bezel design.
The second active layer 142 may use indium, gallium, and zinc indium gallium zinc oxide with a zinc content ratio of 1:1:1 to ensure the stability of the second thin film transistor in the display region S1. In addition, the first active layer 141 and the second active layer 142 can directly select different types of materials so that the mobility of the first active layer 141 is greater than that of the second active layer 142; alternatively, the same type of material is used for the first active layer 141 and the second active layer 142, and then the content of the indium element in the first active layer 141 is greater than that in the second active layer 142 by adjusting the content of the indium element in the corresponding film layer, so that the mobility of the first active layer 141 is greater than that of the second active layer 142.
And S230, sequentially forming a gate insulating layer 143, a gate layer 144, an interlayer dielectric layer 145 and a source drain layer 146 on the side, away from the substrate 110, of the second active layer 142 to form the thin film transistor layer 140.
As shown in fig. 10, after the first active layer 141 and the second active layer 142 are fabricated, a gate insulating layer 143 and a gate electrode layer 144 are sequentially formed on the second active layer 142 on a side away from the base substrate 110; then, by photolithography, the gate layer 144 is etched to form gates of the first tft in the non-display region S2 and the second tft in the display region S1; and then, the patterned gate is used as an etching mask to etch the gate insulating layer 143, and the exposed part of the second active layer 142 is subjected to laser plasma treatment, so that the resistance of the exposed part of the second active layer 142 is obviously reduced after treatment, a conductor region is formed, and the part of the second active layer 142 shielded by the gate insulating layer 143 and the gate layer 144 still retains the semiconductor characteristics and is used as a conductive channel layer.
The gate insulating layer 143 is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride, and has a thickness greater than or equal to 300 angstroms and less than or equal to 1000 angstroms. The gate layer 144 may be a single layer structure or a multi-layer structure. For example, when the gate layer 144 has a double-layer structure, a layer close to the substrate 110 may be a metal layer, including copper or aluminum, and the thickness thereof may be set to be greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms; the layer far from the substrate base plate 110 may be a transition metal layer including molybdenum, titanium, tungsten, chromium, or nickel, and a corresponding metal alloy, etc., and the thickness thereof may be set to be greater than or equal to 50 angstroms and less than or equal to 500 angstroms.
The gate layer 144 is set to be a double-layer structure, so that the transition metal layer can protect the metal layer to a certain extent, and oxidation or corrosion of part of the surface of the gate layer 144 due to long-time exposure when a subsequent film layer is processed is avoided, thereby affecting the overall performance of the array substrate 100.
Then depositing an interlayer dielectric layer 145 on the side of the gate layer 144 away from the substrate 110, and etching the interlayer dielectric layer 145 to form a contact hole 1451 exposing the conductive region of the second active layer 142; then, a source/drain layer 146 is deposited on the interlayer dielectric layer 145, and the source/drain layer 146 is etched to form a source and a drain in the first tft in the non-display region S2 and the second tft in the display region S1, respectively, and is connected to the corresponding second active layer 142 through the contact hole 1451 on the interlayer dielectric layer 145, thereby implementing the fabrication of the tft layer 140.
The corresponding thin film transistor in the thin film transistor layer 140 formed at this time is a top gate structure, and this top gate structure design can effectively reduce parasitic capacitance generated by overlapping of the gate in the gate layer 144 and the source and drain in the source and drain layer 146, reduce resistance-capacitance delay in the array substrate 100, and improve the driving quality of the array substrate 100.
The source/drain layer 146 may have a single-layer structure or a multi-layer structure. For example, when the source/drain layer 146 has a double-layer structure, a layer close to the substrate 110 may be a metal layer, including copper or aluminum, and the thickness thereof may be set to be greater than or equal to 2000 angstroms and less than or equal to 10000 angstroms; the layer far from the substrate base plate 110 may be a transition metal layer including molybdenum, titanium, tungsten, chromium, or nickel, and a corresponding metal alloy, or a conductive oxide layer such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or aluminum-doped zinc oxide (AZO), and the thickness thereof may be set to be greater than or equal to 50 angstroms and less than or equal to 500 angstroms.
The source and drain electrode layer 146 is set to be a double-layer structure, so that the transition metal layer or the conductive oxide layer can play a certain protection role on the metal layer, and the phenomenon that when a subsequent film layer is processed, part of the surface of the source and drain electrode layer 146 is oxidized or corroded due to long-time exposure is avoided, and the overall performance of the array substrate 100 is affected.
Optionally, when the first thin film transistor and the second thin film transistor are of a top gate structure, the array substrate 100 further includes a light shielding layer 120 and a buffer layer 130 stacked between the substrate 110 and the thin film transistor layer 140, wherein the light shielding layer 120 is located in the display region S1, and the light shielding layer 120 and the third active portion 1422 are correspondingly disposed to shield the third active portion 1422, so as to prevent external ambient light from directly irradiating the third active portion 1422 to affect the structural stability of the third active portion 1422. The buffer layer 130 is used to separate the light shielding layer 120 from the third active portion 1422, so as to prevent interference between the light shielding layer 120 and the third active portion 1422 from affecting the normal use of the array substrate 100.
It should be noted that the buffer layer 130 is designed on the substrate base plate 110 in a whole surface, that is, the buffer layer 130 is located in both the display region S1 and the non-display region S2, and due to the existence of a large amount of impurity ions in the substrate base plate 110, the buffer layer 130 is also configured to effectively block the impurity ions in the substrate base plate 110 from entering the first active layer 141 and the second active layer 142, so as to ensure the structural stability of the first active layer 141 and the second active layer 142.
When the light-shielding layer 120 is patterned, the light-shielding layer 120 can be simultaneously disposed at positions of the non-display region S2 corresponding to the first active portion 1411 and the second active portion 1421 to shield the first active portion 1411 and the second active portion 1421, so as to prevent external ambient light from directly irradiating the first active portion 1411 and the second active portion 1421, and further improve the structural stability of the first thin film transistor in the non-display region S2, thereby improving the driving stability.
In some embodiments, the thin film transistor in thin film transistor layer 140 formed in step S200 is a bottom-gate structure, and the specific formation process includes the following steps:
first, a gate electrode layer 144 and a gate insulating layer 143 are sequentially formed on a substrate base substrate 110; then, a second active layer 142 is formed on a side of the gate insulating layer 143 away from the substrate 110, and patterning is performed on the second active layer 142 to form a second active portion 1421 in the non-display region S2 and a third active portion 1422 in the display region S1; then, a first active layer 141 is formed on a side of the second active layer 142 away from the substrate base plate 110, and patterning processing is performed on the first active layer 141, so that a first active portion 1411 is formed in the non-display region S2, and the first active portion 1411 and the second active portion 1421 are stacked; and then sequentially forming an interlayer dielectric layer 145 and a source drain layer 146 on the side of the first active layer 141 away from the substrate 110 to form the thin film transistor layer 140.
The materials, thicknesses and specific structural compositions of the film layers can refer to the description in the above embodiments, and are not repeated here.
Compared to the top gate structure in the above embodiment, the bottom gate structure first forms the second active layer 142 with lower mobility, which is shared by the display region S1 and the non-display region S2, including the second active portion 1421 located in the non-display region S2 and the third active portion 1422 located in the display region S1, and then forms the first active layer 141 in the non-display region S2 corresponding to the second active layer 142, that is, forms the first active portion 1411 on the second active portion 1421. To ensure the effective connection between the source/drain layer 146 in the subsequent non-display region S2 and the second active portion 1421 in the second active layer 142, the first active portion 1411 can be disposed in the middle region of the second active portion 1421, such that the orthographic projection of the first active portion 1411 on the substrate base 110 is located within the orthographic projection of the second active portion 1421 on the substrate base 110. The gate layer 144 in the bottom gate structure can shield light, so that the number of the light-shielding layer 120 can be reduced, the thickness of the array substrate 100 can be reduced, and the light and thin design of the array substrate 100 can be facilitated.
It should be noted that, when the first thin film transistor in thin film transistor layer 140 located in non-display region S2 and the second thin film transistor in display region S1 are bottom-gate structures, array substrate 100 may further include buffer layer 130 disposed between substrate 110 and thin film transistor layer 140, where buffer layer 130 is a full-surface design, and buffer layer 130 is disposed to planarize the surface of substrate 110 and isolate impurity ions from substrate 110.
Since the gate layer 144 has a more stable structure than the active layer and is not easily affected by the impurity ions in the substrate 110, the gate layer 144 can be directly disposed on the substrate 110 without disposing the buffer layer 130 when the gate layer 144 is formed, and this structure design can further reduce the overall thickness of the array substrate 100, which is beneficial to the light and thin design of the array substrate 100.
Optionally, after the thin film transistor layer 140 is manufactured, the manufacturing method of the array substrate 100 further includes forming a passivation layer 150 on a side of the source/drain layer 146 away from the substrate 110, so as to protect an internal structure of the thin film transistor layer 140, and simultaneously isolate the source/drain layer 146, so as to avoid mutual interference between the array substrate 100 and a subsequent functional structure layer when in use. The passivation layer 150 is made of one or more materials selected from silicon nitride, silicon oxide, and silicon oxynitride, and the thickness thereof may be set to be greater than or equal to 1000 angstroms and less than or equal to 5000 angstroms, and the specific design value of the thickness can be adjusted according to the actual use requirement, which is not limited herein.
The array substrate, the display panel and the manufacturing method of the array substrate provided by the embodiments of the present application are described in detail above, and a specific example is applied to illustrate the principle and the implementation manner of the present application, and the description of the embodiments above is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (14)

1. An array substrate, comprising:
a substrate including a display region and a non-display region;
the thin film transistor layer is arranged on the substrate base plate; the thin film transistor layer comprises a first active layer, a second active layer and a gate layer, the first active layer comprises a first active part located in the non-display area, the second active layer comprises a second active part located in the non-display area and a third active part located in the display area, the second active part and the first active part are arranged in a stacked mode, and the mobility of the first active layer is larger than that of the second active layer; the gate layer is located on a side of the second active layer facing away from the first active layer.
2. The array substrate of claim 1, wherein the first active layer and the second active layer are sequentially disposed in a direction away from the substrate base plate.
3. The array substrate of claim 2, wherein the second active portion covers a side surface of the first active portion.
4. The array substrate of claim 3, wherein the thin film transistor layer further comprises an interlayer dielectric layer and a source drain layer sequentially arranged along a direction away from the second active layer; a contact hole is formed in the interlayer dielectric layer, part of the second active part is exposed out of the contact hole, and the source drain layer is electrically connected with the second active part through the contact hole;
the second active part exposed from the contact hole is positioned on one side of the side surface of the first active part; or the like, or a combination thereof,
the second active part exposed from the contact hole is positioned on one side of the first active part, which is deviated from the substrate base plate.
5. The array substrate of claim 2, further comprising a light shielding layer and a buffer layer stacked between the substrate and the thin film transistor layer, wherein the light shielding layer is located in the display region, and the light shielding layer is disposed corresponding to the third active portion.
6. The array substrate of claim 1, wherein the second active layer and the first active layer are sequentially disposed in a direction away from the substrate base plate.
7. The array substrate of claim 6, wherein an orthographic projection of the first active portion on the substrate is within an orthographic projection of the second active portion on the substrate.
8. The array substrate according to any one of claims 1 to 7, wherein the material of the first active layer and the second active layer comprises an oxide semiconductor material; the content of the indium element in the first active layer is larger than that in the second active layer.
9. The array substrate of claim 8, wherein the first active layer comprises one or more of indium gallium zinc tin oxide, indium tin oxide and indium zinc oxide; the second active layer is made of indium gallium zinc oxide, and the contents of indium element, gallium element and zinc element in the second active layer are the same.
10. The array substrate of any one of claims 1 to 7, wherein the first active layer has a thickness greater than or equal to 50 angstroms and less than or equal to 1000 angstroms; the second active layer has a thickness greater than or equal to 100 angstroms and less than or equal to 1000 angstroms.
11. A display panel, comprising:
an array substrate according to any one of claims 1 to 10;
a light emitting device disposed on the array substrate;
and the packaging assembly is arranged on one side of the light-emitting device, which is far away from the packaging assembly.
12. A manufacturing method of an array substrate is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a display area and a non-display area;
forming a thin film transistor layer on the substrate base plate; the thin film transistor layer comprises a first active layer, a second active layer and a gate layer, the first active layer comprises a first active part located in the non-display area, the second active layer comprises a second active part located in the non-display area and a third active part located in the display area, the second active part and the first active part are arranged in a stacked mode, and the mobility of the first active layer is larger than that of the second active layer; the gate layer is located on a side of the second active layer facing away from the first active layer.
13. The method for manufacturing the array substrate according to claim 12, wherein the forming a thin film transistor layer on the substrate comprises:
forming a first active layer on the substrate base plate, and carrying out patterning treatment on the first active layer so as to form a first active part on the substrate base plate at a position corresponding to the non-display area;
forming a second active layer on one side of the first active layer, which is far away from the substrate base plate, and carrying out patterning treatment on the second active layer so as to form a second active part in the non-display area and a third active part in the display area, so that the second active part and the first active part are arranged in a stacked mode;
and sequentially forming a gate insulating layer, a gate layer, an interlayer dielectric layer and a source drain layer on one side of the second active layer, which is far away from the substrate, so as to form a thin film transistor layer.
14. The method for manufacturing the array substrate according to claim 12, wherein the forming a thin film transistor layer on the substrate comprises:
sequentially forming a gate electrode layer and a gate insulating layer on the substrate;
forming a second active layer on one side, away from the substrate, of the gate insulating layer, and performing patterning treatment on the second active layer to form a second active part in the non-display area and a third active part in the display area;
forming a first active layer on one side, away from the substrate, of the second active layer, and performing patterning treatment on the first active layer to form a first active part in the non-display area, so that the first active part and the second active part are arranged in a stacked manner;
and sequentially forming an interlayer dielectric layer and a source drain layer on one side of the first active layer, which is far away from the substrate, so as to form a thin film transistor layer.
CN202210699732.9A 2022-06-20 2022-06-20 Array substrate, display panel and manufacturing method of array substrate Pending CN114975486A (en)

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