TWI451479B - Manufacturing method for thin film of poly-crystalline silicon - Google Patents

Description

Method for producing polycrystalline germanium film [related application]

The present application claims the priority of the Korean Patent Application No. 10-2010-0067482 filed on Jan. 13, 2010, to the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

The present invention relates to a method for producing a polycrystalline silicon (poly-crystalline silicon) layer suitable for use in a solar cell, and more particularly to a metal-induced crystallization (metal-induced crystallization, The MIC) process is a method in which an amorphous silicon (a-Si) layer is crystallized to efficiently produce a polycrystalline thin layer.

In general, the production of a poly-Si layer may not work, mainly because the amorphous thin layer cannot be crystallized at a sufficiently high temperature due to the use of a glass substrate which is easily damaged by heat.

In the fabrication of the polysilicon layer, a high temperature annealing process may be required in order to crystallize the amorphous germanium thin layer into a crystalline germanium thin layer and to perform a post-doping dopant activation process.

At present, various low-temperature poly-Si (LTPS) processes for forming a polycrystalline germanium layer in a short period of time at a low temperature allowed by a glass substrate have been proposed. Typical methods for producing a polycrystalline thin layer may include a solid-phase crystallization (SPC) method, an excimer laser annealing (ELA) method, and a metal induced crystallization (MIC) method.

The SPC method may be the most straightforward method for crystallizing an amorphous germanium layer into a polycrystalline germanium layer. In the SPC method, a thin layer of amorphous germanium may be annealed at a temperature of about 600 ° C or higher for several tens of hours, thereby forming a thin layer of polycrystalline germanium having a particle diameter of about several micrometers (μm). Grain. The resulting polycrystalline silicon layer may have a high defect density in the grains. Moreover, since a high annealing temperature is required, a glass substrate cannot be used. In addition, the SPC method may involve performing an annealing process for a long period of time.

The ELA method can include exposing the excimer laser beam to an amorphous thin layer for a few nanoseconds in an instant to melt and recrystallize the amorphous thin layer without damaging the glass substrate.

However, the ELA method is known to have significant problems in mass production processes. The ELA method can result in a very uneven grain size of the polycrystalline germanium layer relative to the laser beam. Moreover, the ELA method can only cover a narrow processing range and thus cannot produce a uniform thin layer of crystal. In addition, the resulting polycrystalline silicon layer may have a rough surface and thus adversely affect the characteristics of the element. These problems can become more serious in organic light-emitting diode (OLED) applications because the organic light-emitting diodes are significantly affected by the uniformity of thin-film transistors (TFTs). influences.

To overcome the above disadvantages, a metal induced crystallization (MIC) process has been proposed. The MIC process may involve coating a metal catalyst on an amorphous crucible by a sputtering process or a spin coating process, and performing an annealing process at a low temperature to induce crystallization of the amorphous germanium. The metal catalyst may be one of various metals such as nickel (Ni), copper (Cu), aluminum (Al) or palladium (Pd). In general, Ni can be used as a metal catalyst to perform the MIC process because the reaction of Ni can be easily controlled and relatively large crystal grains can be obtained. Although the MIC process can be achieved at temperatures as low as 700 ° C, it can be very difficult to apply the MIC process to an actual mass production process. In particular, a large amount of metal diffused into the active region of the TFT can cause typical metal contamination, which in turn leads to an increase in leakage current as a characteristic of the TFT.

With the recent introduction of active-matrix light-emitting diodes (AMOLEDs) and thin-film polycrystalline silicon solar cells, it has become increasingly necessary to develop low temperatures originally used in liquid crystal displays (LCDs). Low-temperature poly-Si (LTPS).

Since AMOLEDs are comparable to amorphous germanium TFT LCDs for display products, there has been a growing interest in the development of inexpensive and highly productive methods for fabricating polycrystalline thin layers. In addition, since AMOLEDs are comparable to crystalline wafers for solar cells, methods for fabricating thin layers of polysilicon are also receiving increasing attention. Therefore, the cost and market competitiveness of the polysilicon layer relative to the amorphous germanium TFT LCD and the crystalline wafer solar cell can depend on an inexpensive and stable polysilicon layer manufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram of a conventional method for fabricating a polycrystalline germanium layer using an MIC process.

Referring to FIG. 1, the conventional method may include forming a buffer layer 2 formed of yttrium oxide (SiO ₂ ) on a substrate 1 such as a glass substrate. The amorphous germanium layer 3 may be formed on the buffer layer 2 by a plasma-enhanced chemical vapor deposition (PECVD) process, and the amorphous germanium layer 3 is coated with, for example, nickel (Ni) by a sputtering process. The metal 4 is annealed at a temperature of about 700 ° C by a rapid thermal annealing (RTA) process, whereby the amorphous germanium layer 3 is crystallized into a crystalline germanium layer 5. However, according to this conventional method, since the amount of the metal coated on the amorphous germanium layer 3 cannot be precisely controlled, it is quite troublesome to remove the applied excess metal. Accordingly, the process of removing excess metal can result in increased manufacturing costs and affect the quality of the crystal crucible.

The present invention provides a method of fabricating a poly-Si layer using a metal induced crystallization (MIC) process whereby the amount of metal catalyst is finely controlled and a crystallization process is achieved at a low temperature.

According to an aspect of the present invention, a method of manufacturing a polycrystalline silicon (poly-Si) thin layer is provided, comprising: forming a metal layer on an insulating substrate; forming a metal oxide layer by annealing a surface of the metal layer, Or depositing the metal oxide layer; stacking a first germanium layer on the formed metal oxide layer; moving atoms of the metal catalyst from the metal layer to the first germanium by using a first annealing process And forming a metal tantalum oxide layer; forming a second tantalum layer by stacking an amorphous germanium (a-Si) layer on the metal tantalum oxide layer; and by using the metal tantalum oxide layer The particles perform a second annealing process as a catalyst, and the amorphous germanium layer is crystallized into the polycrystalline germanium layer.

The metal layer may have a thickness of about 5 angstroms to 1500 angstroms, the gold The oxide layer may have a thickness of about 1 angstrom to 300 angstroms, the first ruthenium layer may have a thickness of about 5 angstroms to 1500 angstroms, and the thickness of the metal layer is opposite to the thickness of the first ruthenium layer. The ratio can range from 1:0.5 to 1:20.

The forming the metal oxide layer may be performed at an annealing temperature of about 50 ° C to 1000 ° C, and the forming the metal tantalum oxide layer may be performed at an annealing temperature of about 50 ° C to 1000 ° C.

The method may further include partially patterning the metal layer by a lithography and etching process after the forming the metal layer and before forming the metal oxide layer to expose the metal Floor.

According to another aspect of the present invention, a method of fabricating a polycrystalline silicon (poly-Si) thin layer comprising: forming a metal layer on an insulating substrate; forming a metal oxide layer by annealing a surface of the metal layer Or depositing the metal oxide layer on the metal layer; forming a first germanium layer by stacking an amorphous germanium layer on the metal oxide layer; using a first annealing process to cause a metal catalyst Moving atoms from the metal layer to the first germanium layer to form a metal germanium oxide layer; by stacking an amorphous germanium (a-SiGe) layer or an amorphous tantalum carbide on the metal tantalum oxide layer a (a-SiC) layer to form a second germanium layer; and performing a second annealing process by using metal particles of the metal germanium oxide layer as a catalyst to crystallize the second germanium layer into a crystalline SiGe layer Or a crystalline SiC layer.

According to another aspect of the present invention, a method of fabricating a polycrystalline silicon (poly-Si) thin layer comprising: forming a metal layer on an insulating substrate; forming a metal oxide layer by annealing a surface of the metal layer Or depositing the metal oxide layer on the metal layer; forming a first germanium layer by stacking a germanium (SiGe) layer or a tantalum carbide (SiC) layer on the metal oxide layer; The first annealing process moves atoms of the metal catalyst from the metal layer to the first germanium layer to form a metal SiGe oxide layer or a metal SiC layer; by stacking amorphous on the metal germanium oxide layer a SiGe (a-SiGe) layer or an amorphous SiC (a-SiC) layer to form a second germanium layer; and performing the same by using the metal tantalum oxide layer or the metal particles of the metal SiC layer as a catalyst The second annealing process is performed to crystallize the second layer to form a crystalline SiGe layer or a crystalline SiC layer.

According to another aspect of the present invention, a method of fabricating a polycrystalline silicon (poly-Si) thin layer is provided, comprising: forming a first metal layer on an insulating substrate; forming by annealing an surface of the first metal layer a first metal oxide layer, or depositing the first metal oxide layer on the first metal layer; formed by stacking an amorphous germanium (a-Si) layer on the first metal oxide layer a first ruthenium layer; forming a first metal ruthenium oxide layer by moving a metal catalyst atom from the first metal layer to the first ruthenium layer by using a first annealing process; oxidizing the metal ruthenium layer Forming a second metal layer on the object layer; forming a second metal oxide layer by annealing the surface of the second metal layer, or depositing the second metal oxide layer on the second metal layer; Forming a second germanium layer by stacking an amorphous germanium layer on the second oxide layer; moving atoms of the metal catalyst from the second metal layer to the second germanium by using a second annealing process a layer to form a second metal tantalum oxide layer; And stacking an amorphous germanium layer on the compound layer to form a third germanium layer; and by using the first metal layer and the second metal layer or the first metal oxide layer or the second metal oxide The metal particles of the layer perform a third annealing process as a catalyst, and the third germanium layer is crystallized into a crystalline germanium layer.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

2 is a diagram showing a manufacturing process in accordance with an embodiment of the present invention. Figure 3 is a cross-sectional view showing the resultant structure in which the first layer 40 of Figure 2 is formed. 4 is a cross-sectional view showing the resultant structure in which the excess catalyst trap layer of FIG. 2 is formed. Figure 5 is a cross-sectional view showing the resulting structure in which the etching process of Figure 2 is performed. Figure 6 is a cross-sectional view showing the resultant structure in which the second layer 60 of Figure 2 is formed. Further, Fig. 7 is a schematic cross-sectional view showing the resultant structure in which a polycrystalline silicon (poly-Si) thin layer is formed after the crystallization process of Fig. 2 is performed.

Referring to FIGS. 1 through 7, a method of manufacturing a polycrystalline silicon thin layer (hereinafter referred to as "manufacturing method") according to the present embodiment may include forming a metal layer 30 (operation S1), forming a metal oxide layer (operation S2), and performing a pattern. a process (operation S3), forming a first germanium layer (operation S4), forming an excess catalyst trap layer (operation S5), performing a first annealing process (operation S6), performing an etching process (operation S7), forming a second defect The layer (operation S8) and the crystallization process (operation S9).

In operation S1, the metal layer 30 may be formed of a metal such as nickel (Ni) on the insulating substrate 10 such as a glass substrate. The insulating layer 10 may include a buffer layer 20 formed of a material such as yttrium oxide (SiO ₂ ). The buffer layer 20 can be used as an insulator. Further, the buffer layer 20 may be prepared to prevent impurities from diffusing from the substrate 10 into the first ruthenium layer 40 or the second ruthenium layer 60 (described later) during operation S2, S6 or S9, thereby preventing contamination by impurities. A layer 40 or a second layer 60. Metal layer 30 can be formed using known processes, such as using a sputtering process or a plasma enhanced chemical vapor deposition (PECVD) process. Metal layer 30 can have a thickness of between about 5 angstroms and 1500 angstroms. When the metal layer 30 has a thickness of less than 5 angstroms, the reproducibility of the process may be deteriorated due to the thickness of the metal layer 30 being too small, and when the metal layer is deposited over a large area, the uniformity of the metal layer 30 may be Deterioration. Moreover, when the metal layer 30 has a thickness greater than 1500 angstroms, an excessive amount of metal may penetrate into the second ruthenium layer 60 (described below), thereby causing the metal to contaminate the second ruthenium layer 60. As such, the characteristics of the elements including the crystal defects formed during operation S9 (which will be described later) may be deteriorated.

In operation S2, the metal layer 30 may be annealed in any atmosphere selected from the group consisting of vacuum, air, oxygen, and nitrogen, thereby forming a metal oxide layer 35, such as nickel oxide, on the surface of the metal layer 30. (NiO or Ni ₂ O ₃ ) layer. Alternatively, metal oxide layer 35 can be deposited on metal layer 30. The metal oxide layer 35 can be formed at an annealing temperature of about 50 ° C to 1000 ° C. When the metal oxide layer 35 is formed at an annealing temperature of less than about 50 ° C, an oxide of nickel (Ni) may not be efficiently formed. Further, when the metal oxide layer 35 is formed at an annealing temperature higher than about 1000 ° C, the substrate 10 formed of glass may be deformed or broken due to thermal shock. In operation S2, the annealing process may be performed using a furnace process, a rapid thermal annealing (RTA) process, or an ultraviolet (UV) heating process. Metal oxide layer 35 can be used to reduce the activation energy that diffuses the metal catalyst during formation of metal tantalum oxide layer 55 in operation S6 (described below). Metal oxide layer 35 can have a thickness of from about 1 angstrom to 300 angstroms. When the metal oxide layer 35 has a thickness of less than 1 angstrom, the metal oxide layer 35 may not function properly due to its thickness being too small. Moreover, when the metal oxide layer 35 has a thickness greater than about 300 angstroms, the metal catalyst from the metal layer 30 can be rendered impermeable.

After operation S2, the metal oxide layer 35 may be partially patterned and removed using photolithography and etching processes in operation S3, thereby exposing the metal layer 30. If necessary, the operation S3 can be omitted. Operation S3 can be performed to evenly distribute the growth nucleus of the crystal crucible.

In operation S4, the first germanium layer 40 formed of amorphous germanium may be formed on the metal oxide layer 35 by a known process such as a PECVD process. The first layer 40 can have a thickness of between about 5 angstroms and 1500 angstroms. When the first ruthenium layer 40 has a thickness of less than 5 angstroms, the reproducibility of the process may be deteriorated because the thickness of the first ruthenium layer 40 is too small, and when the first ruthenium layer 40 is deposited over a large area, the first The uniformity of the ruthenium layer 40 may be degraded. In addition, when the first ruthenium layer 40 has a thickness greater than 1500 angstroms, the first ruthenium layer 40 may be combined with the metal layer 30 to cause a chemical combination, and the compound is formed using the first ruthenium layer 40. The metal ruthenium oxide layer 55 is not required. Further, the ratio of the thickness of the metal layer 30 to the thickness of the first ruthenium layer 40 may range from 1:0.5 to 1:20. When the ratio of the thickness of the metal layer 30 to the thickness of the first tantalum layer 40 deviates from the above range, the combination which is not required at the time of forming the metal tantalum oxide layer 55 can be caused as described above. That is, it is possible to form a combination of the telluride components which are not required for metal inductive coupling, thereby hindering the induction of crystallization.

In operation S5, a tantalum nitride (SiN) layer 50 is formed on the first tantalum layer 40. The formation of the SiN layer 50 can include stacking SiN particles on the first germanium layer 40 using a known process such as a PECVD process. The SiN layer 50 can be formed to a thickness of about 100 angstroms or more. When the SiN layer 50 has a thickness of less than about 100 angstroms, the SiN layer 50 may not be uniformly formed over a large area because its thickness is too small, so that an excessive amount of catalyst may not be effectively captured.

In operation S6, a first annealing process may be used to move atoms of a metal catalyst (eg, nickel (Ni)) from the metal layer 30 through the metal oxide layer 35 to the first germanium layer 40 to form a metal germanium oxide layer. 55. The first annealing process in operation S6 can be performed using a furnace process, an RTA process, or a UV heating process. The metal tantalum oxide layer 55 formed in operation S6 can be used as a core for crystallizing amorphous germanium (a-Si) in operation S9.

After operation S6, the SiN layer 50 stacked in operation S5 may be removed in operation S7. Since the removal of the SiN layer 50 can be removed by a known etching process, it will not be described again.

In operation S8, an amorphous germanium may be stacked on the metal tantalum oxide layer 55, thereby forming the second tantalum layer 60. The formation of the second germanium layer 60 can be performed using, for example, a known PECVD process.

In operation S9, the metal layer of the metal tantalum oxide layer 55 may be used to crystallize the second tantalum layer 60 formed of amorphous germanium into the crystalline germanium layer 70 by an annealing process. In operation S9, this annealing process can be performed using, for example, a temperature of about 630 ° C using an RTA apparatus.

In order to examine the state of the polycrystalline silicon thin layer produced by the above method, the particle size of the polycrystalline tantalum thin layer and the wave number of the polycrystalline thin layer at the highest intensity were analyzed by optical microscopy and Raman spectroscopy.

Figure 8 is an optical microscopic image of the surface of an amorphous crucible. Fig. 9 is a graph showing the analysis of the wave number of the amorphous ytterbium shown in Fig. 8. Figure 10 is an optical microscopy image of the surface of a crystalline germanium wafer. Fig. 11 is a graph showing the analysis of the wave number of the crystal germanium wafer shown in Fig. 10. Figure 12 is an optical micrograph of the surface of a thin layer of polycrystalline silicon produced by a conventional metal induced crystallization (MIC) process. Fig. 13 is a graph showing the analysis of the wave numbers of the polycrystalline silicon thin layer shown in Fig. 12. Figure 14 is an optical microscopy image of the surface of a polycrystalline silicon thin layer made using a method in accordance with an embodiment of the present invention. Further, Fig. 15 is a graph for analyzing the wave numbers of the polycrystalline thin layer shown in Fig. 14.

Referring to Figures 8 and 9, the second tantalum layer 60 formed of amorphous germanium has the highest intensity at a wavenumber of 480 cm ^-1 . In Fig. 9, the abscissa indicates the wave number (cm ^-1 ), which corresponds to the frequency. Wavenumbers are frequency units in atomic spectroscopy, molecular spectroscopy, and nuclear spectroscopy that are equal to the actual frequency divided by the speed of light and are therefore equal to the number of waves in a unit distance. The frequency of any wave (indicated by the Greek letter v) is equal to the speed of light c divided by the wavelength λ: thus v = c / λ. A typical spectral line in the visible region of the spectrum has a wavelength of 5.8 x 10 ^-5 cm, which according to this equation corresponds to a frequency (v) of 5.17 x 10 ¹⁴ Hz (Hertz is equal to one cycle per second). Therefore, the frequency is very large, and it is convenient to divide this number by the speed of light, thereby reducing its size. The frequency divided by the speed of light is equal to v/c, which is 1/λ according to the above equation. When the wavelength is measured in meters (m), 1/λ represents the number of waves of the wave train existing within one meter of length, or if the wavelength is measured in centimeters, 1/λ means The number of waves within the cent. This number is called the wave number of the spectral line. The wave number is usually measured in units of the reciprocal of meters (1/m or m ^-1 ) and the reciprocal of the centimeters (1/cm or cm ^-1 ).

In Figure 9, the ordinate is the sum of the number of waves measured per unit time, which corresponds to the intensity (Count Per Second (CPS)). In Figs. 11, 13, and 15, the units of the abscissa and the ordinate are the same as those in Fig. 9. In contrast, referring to Figures 10 and 11, a typical tantalum wafer formed of crystalline germanium has the highest intensity at a wavenumber of 520 cm ^-1 . Referring to Figures 12 and 13, the polysilicon layer has the highest intensity at wave numbers similar to those of the wafer wafers shown in Figures 10 and 11. However, according to the optical microscopic image of the surface of the polycrystalline thin layer in Fig. 12 (which is magnified 1000 times), it can be observed that the crystal grains are smaller than the crystal germanium wafer in Fig. 10.

Referring to Figure 15, it can be seen that the polycrystalline silicon layer produced in accordance with the present invention has a wave number at the highest intensity which is approximately as significant as the crystalline germanium wafer shown in Figure 11. In addition, when the optical microscopic image of FIG. 14 (which is magnified 1000 times) is compared with the optical microscopic image of FIG. 12, it can be seen that the crystal grains of the polycrystalline silicon thin layer produced according to the present invention are much larger than the use. The crystal grains of a thin layer of polycrystalline silicon produced by a conventional method. Based on the above experimental results, it can be concluded that the method for producing a polycrystalline silicon thin layer according to the present invention is superior to the conventional method. Further, according to the method of the present invention, the crystallization process can be achieved at a temperature lower than the conventional method. In the method of the present invention, a metal catalyst (which corresponds to a reaction nucleus required for crystallizing from an amorphous germanium to a crystalline germanium) may be disposed under the amorphous germanium layer, so that the amount of the metal catalyst can be precisely controlled in advance. And the metal catalyst can be diffused into the amorphous germanium layer. As a result, diffusion of impurities can be prevented, and activation energy can be lowered.

In the first embodiment, although the lithography and etching process is performed to locally pattern the metal oxide layer 35 after the operation S2 of forming the metal oxide layer 35 and before the operation S4 of forming the first germanium layer 40 is described. Operation S3, however, operation S3 may be omitted when needed.

In the first embodiment, although the operation S5 of forming the SiN layer 50 on the first germanium layer 40 is performed after the operation S4 for forming the first germanium layer 40, and the operation for performing the first annealing process is performed. S6 is followed by operation S7 of removing the SiN layer 50 by etching, but the object of the present invention can also be achieved without performing operation S5 and operation S7.

Unlike in the first embodiment, a method of manufacturing a polysilicon thin layer may include forming a first germanium layer by stacking amorphous germanium on an insulating substrate. A metal oxide layer is formed on the amorphous germanium by using a mixture of a metal and an oxide of the metal. The second layer of germanium can be formed by stacking amorphous germanium on the metal oxide layer. The amorphous germanium of the first tantalum layer can be crystallized into a crystalline germanium by performing an annealing process using metal particles of the metal oxide layer as a catalyst. That is, the same process as in the first embodiment of the present invention can be performed on the resulting structure in which a metal layer is not formed on the substrate but a metal oxide layer is formed.

The second embodiment of the present invention is a modified embodiment of the first embodiment. The method of manufacturing a polycrystalline silicon thin layer according to the second embodiment is different from the method according to the first embodiment in that an amorphous germanium layer is not stacked in operation S8 of the first embodiment, but an amorphous germanium is stacked ( An a-SiGe layer or an amorphous tantalum carbide (a-SiC) layer. Therefore, unlike in the first embodiment, according to the second embodiment, a crystalline SiGe layer or a crystalline SiC layer may be formed during the crystallization operation.

The third embodiment of the present invention is a modified embodiment of the second embodiment. The method of manufacturing a polycrystalline silicon thin layer according to the third embodiment is different from the method of the second embodiment in that an amorphous germanium layer is not stacked in operation S4 of the first embodiment, but an a-SiGe layer or a is stacked. - SiC layer.

The fourth embodiment of the present invention is a modified embodiment of the first embodiment. A method of manufacturing a polycrystalline silicon thin layer is different from the first embodiment in that an operation S1 of forming the metal layer 30, an operation S2 of forming the metal oxide layer 35, an operation S4 of forming the first germanium layer 40, and performing the first annealing are performed. The operation S6 of the process is repeated twice in sequence. Specifically, the method according to the fourth embodiment may include forming a first metal layer on the insulating substrate. The surface of the first metal layer may be annealed, or a first metal oxide layer may be deposited on the first metal layer, thereby forming a first metal oxide layer. An amorphous germanium layer may be stacked on the first metal oxide layer, thereby forming a first germanium layer. The first annealing process can be utilized to move atoms of the metal catalyst from the first metal layer into the first germanium layer, thereby forming a first metal tantalum oxide layer. A second metal layer can be formed on the metal tantalum oxide layer. The surface of the second metal layer may be annealed or a second metal oxide layer may be deposited on the surface of the second metal layer, thereby forming a second metal oxide layer. An amorphous germanium layer may be stacked on the second oxide layer, thereby forming a second germanium layer. The second metal ruthenium oxide layer can be formed by moving the atoms of the metal catalyst from the second metal layer into the second ruthenium layer by using a second annealing process. An amorphous germanium layer may be stacked on the second metal tantalum oxide layer, thereby forming a third tantalum layer. The annealing process may be performed using the first metal layer and the second metal layer, the first metal oxide layer or the second metal oxide layer as a catalyst, whereby the third germanium layer is crystallized into a crystalline germanium layer.

According to the first embodiment described above, the second to fourth embodiments will be apparent to those skilled in the art.

In the method for producing a polycrystalline silicon thin layer according to the present invention, the amount of the metal catalyst diffused into the amorphous germanium layer and used as a crystal nucleus in the amorphous germanium layer can be precisely controlled, thereby achieving the effectiveness of the polycrystalline thin layer. Manufacturing. Further, according to the present invention, the amorphous germanium can be crystallized at a temperature lower than the conventional one.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1‧‧‧Substrate

2‧‧‧buffer layer

3‧‧‧Amorphous layer

4‧‧‧Metal

5‧‧‧crystal layer

10‧‧‧Insert substrate

20‧‧‧buffer layer

30‧‧‧metal layer

35‧‧‧ metal oxide layer

40‧‧‧ first layer

50‧‧‧矽 nitride layer

55‧‧‧metal ruthenium oxide layer

60‧‧‧Second layer

70‧‧‧crystal layer

S1~S9‧‧‧ operation

The above and/or other features and advantages of the present invention will become more apparent from the detailed description of the exemplary embodiments of the invention.

1 is a diagram showing a conventional method for producing a polycrystalline silicon (poly-Si) thin layer using a metal induced crystallization (MIC) process.

2 is a diagram showing a manufacturing process in accordance with an embodiment of the present invention.

Figure 3 is a cross-sectional view showing the resultant structure in which the first layer of Figure 2 is formed.

4 is a cross-sectional view showing the resultant structure in which the excess catalyst trap layer of FIG. 2 is formed.

Figure 5 is a cross-sectional view showing the resulting structure in which the etching process of Figure 2 is performed.

Figure 6 is a cross-sectional view showing the resultant structure in which the second layer of Figure 2 is formed.

Fig. 7 is a schematic cross-sectional view showing the resultant structure in which a polycrystalline silicon (poly-Si) thin layer is formed after the crystallization process of Fig. 2 is performed.

Figure 8 is an optical microscopic image of the surface of amorphous germanium (a-Si).

Fig. 9 is a graph showing the analysis of the wave number of the amorphous ytterbium shown in Fig. 8.

Figure 10 is an optical microscopy image of the surface of a crystalline germanium wafer.

Fig. 11 is a graph for analyzing the wave numbers of the tantalum wafer shown in Fig. 10.

Figure 12 is an optical micrograph of the surface of a thin layer of polycrystalline silicon produced by a conventional metal induced crystallization (MIC) process.

Fig. 13 is a graph showing the analysis of the wave numbers of the polycrystalline silicon thin layer shown in Fig. 12.

Figure 14 is an optical microscopy image of the surface of a polycrystalline silicon thin layer made using a method in accordance with an embodiment of the present invention.

Fig. 15 is a graph showing the analysis of the wave number of the polycrystalline thin layer shown in Fig. 14.

S1 ~ S9. . . operating

Claims (7)

A method of manufacturing a polycrystalline silicon thin layer, comprising: forming a metal layer on an insulating substrate; forming a metal oxide layer by annealing the surface of the metal layer, or depositing the metal oxide layer; Depositing a first germanium layer on the metal oxide layer; forming a metal germanium oxide layer by moving a metal catalyst atom from the metal layer to the first germanium layer by using a first annealing process; Depositing an amorphous germanium layer on the metal tantalum oxide layer to form a second germanium layer; and performing a second annealing process by using particles of the metal tantalum oxide layer as a catalyst to crystallize the amorphous germanium layer Into the polycrystalline layer. The method of producing a polycrystalline silicon thin layer according to claim 1, wherein the metal layer has a thickness of about 5 angstroms to 1500 angstroms, and the metal oxide layer has a thickness of about 1 angstrom to 300 angstroms. The first ruthenium layer has a thickness of about 5 angstroms to 1500 angstroms, and a ratio of a thickness of the metal layer to a thickness of the first ruthenium layer is in a range of 1:0.5 to 1:20. The method for producing a polycrystalline silicon thin layer according to claim 1, wherein the forming the metal oxide layer is performed at an annealing temperature of about 50 ° C to 1000 ° C, and forming the metal tantalum oxide layer is Execution at an annealing temperature of about 50 ° C to 1000 ° C. The method for fabricating a polycrystalline silicon thin layer according to claim 1, further comprising: partially forming the metal layer by using a lithography and etching process after forming the metal layer and before forming the metal oxide layer pattern To expose the metal layer. A method of fabricating a thin layer of polycrystalline silicon comprising: forming a metal layer on an insulating substrate; forming a metal oxide layer by annealing a surface of the metal layer, or depositing the metal oxide layer on the metal layer Forming a first germanium layer by stacking an amorphous germanium layer on the metal oxide layer; moving atoms of the metal catalyst from the metal layer to the first germanium layer by using a first annealing process Forming a metal tantalum oxide layer; forming a second tantalum layer by stacking an amorphous tantalum layer or an amorphous tantalum carbide layer on the metal tantalum oxide layer; and using a metal of the metal tantalum oxide layer The particles act as a catalyst to perform a second annealing process to crystallize the second layer of germanium into a crystalline germanium layer or a crystalline tantalum carbide layer. A method of fabricating a thin layer of polycrystalline silicon comprising: forming a metal layer on an insulating substrate; forming a metal oxide layer by annealing a surface of the metal layer, or depositing the metal oxide layer on the metal layer Forming a first germanium layer by stacking a germanium layer or a tantalum carbide layer on the metal oxide layer; moving atoms of the metal catalyst from the metal layer to the first by using a first annealing process Forming a metal tantalum oxide layer or a metal tantalum carbide layer by laminating; stacking an amorphous germanium layer or an amorphous layer on the metal tantalum oxide layer Forming a second layer of tantalum by forming a tantalum layer; and performing a second annealing process by using the metal tantalum oxide layer or the metal particles of the metal tantalum carbide layer as a catalyst to crystallize the second layer A crystalline germanium layer or a crystalline tantalum carbide layer. A method of fabricating a polycrystalline silicon thin layer, comprising: forming a first metal layer on an insulating substrate; forming a first metal oxide layer by annealing a surface of the first metal layer, or in the first metal layer Depositing the first metal oxide layer; forming a first germanium layer by stacking a first amorphous germanium layer on the first metal oxide layer; and atomizing the metal catalyst by using a first annealing process Forming a first metal tantalum oxide layer from the first metal layer to the first tantalum layer; forming a second metal layer on the first metal tantalum oxide layer; by opposing the second metal Forming a surface of the layer to form a second metal oxide layer, or depositing the second metal oxide layer on the second metal layer; stacking a second amorphous layer on the second metal oxide layer Forming a second germanium layer by using a germanium layer; forming a second metal germanium oxide layer by moving a metal catalyst atom from the second metal layer to the second germanium layer by using a second annealing process; Stacking a third amorphous germanium on the second metal tantalum oxide layer Forming a third silicon layer; and by using the first metal layer and the second metal layer or the second A metal oxide layer or a metal particle of the second metal oxide layer is used as a catalyst to perform a third annealing process to crystallize the third layer to form a crystalline layer.