TW200811959A - Method for annealing silicon thin films using conductive layer and polycrystalline silicon thin films prepared therefrom - Google Patents

Method for annealing silicon thin films using conductive layer and polycrystalline silicon thin films prepared therefrom Download PDF

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TW200811959A
TW200811959A TW096141080A TW96141080A TW200811959A TW 200811959 A TW200811959 A TW 200811959A TW 096141080 A TW096141080 A TW 096141080A TW 96141080 A TW96141080 A TW 96141080A TW 200811959 A TW200811959 A TW 200811959A
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film
silicon thin
crystallization
conductive layer
polycrystalline
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TW096141080A
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TWI362704B (en
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Jae-Sang Ro
Won-Eui Hong
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Jae-Sang Ro
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
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    • B82—NANOTECHNOLOGY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters

Abstract

The present invention provides a method of annealing silicon thin film, which comprises providing a conductive layer underneath a silicon thin film, applying an electric field to the conductive layer to induce Joule heating and thereby to generate intense heat, and carrying out crystallization, elimination of crystal lattice defects, dopant activation, thermal oxidation and the like, of the silicon thin film; and a polycrystalline silicon thin film having high quality prepared by the method. The annealing method of the invention provides a polycrystalline silicon thin film which has virtually no crystal lattice defects, which is completely free from contamination by catalyst metal appearing in polycrystalline silicon thin films produced by crystallization methods such as MIC and MILC, and at the same time, is not accompanied by surface protrusions appearing in polycrystalline silicon thin films produced by ELC, while not incurring thermal deformation of glass substrate.

Description

200811959 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種退火矽薄膜之方法及用此方法製備 多晶矽薄膜，且更特定言之，本發明係關於一種退火矽薄 膜之方法，其包含：在矽薄膜下提供導電層；施加一電場 於該導電層以誘發焦耳加熱，產生強熱；且進行矽薄膜之 結晶化、消除晶體晶格缺陷、活化雜質、熱氧化及類似步 驟；且藉此方法製備高品質之多晶矽傳膜。 【先前技術】 一般而言，非結晶矽（a-Si)具有諸如用於充電電池時 之弱電子遷移率、低孔徑比，及與CMOS處理之不相容性 的缺陷.。另一方面，多晶矽（Poly-Si)薄膜裝置，是使影 像訊號輸入圖元所需的操作電路在一基板上形成’在圖元 TFT堆疊中完成該處理，而利用非結晶矽TFT (a-Si TFT) 則無法進行該處理。一多晶矽薄膜裝置不需在複數個終端 及一驅動器1C之間連接，因此該特徵可提昇生產率及可靠 性，且亦降低了面板之厚度。進一步而言，因為多晶石夕TFT 處理可以直接利用矽LSI之微加工技術，所以以導線或類 似物來成形一微結構係可能的。因此，因為不存在該驅動 器1C之TAB安裝之間距的限制（而在一非結晶矽TFT中 該限制係明顯的），所以可以較輕易地達成圖元尺寸之減 少，且可以在較小之視角實施大量之圖元。與使用非結晶 矽之薄膜電晶體相比，在主動層使用多晶矽之薄膜電晶體 200811959 具有南轉紐能’且經過自我對準決定該主動層之通道位 置，因此使該裝置尺寸較小且可 CMos❹成形。因 該等，因’多晶㈣膜電晶體可用作主動矩陣類型之平板 ‘、、、頁不益（例如，液晶顯示器及有機EL裝置）或類似物中 ^圖兀轉換7〇件，且#前，愈來愈多將其用作大螢幕顯示 盗及具有内建式驅動器的C(X}(玻璃板上式晶片）產品之 應用的必需元件。200811959 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method for annealing a tantalum film and a method for preparing a polycrystalline germanium film, and more particularly, to a method for annealing a tantalum film, comprising Providing a conductive layer under the germanium film; applying an electric field to the conductive layer to induce Joule heating to generate strong heat; and performing crystallization of the germanium film, eliminating crystal lattice defects, activating impurities, thermal oxidation, and the like; This method produces a high quality polycrystalline ruthenium film. [Prior Art] In general, amorphous yttrium (a-Si) has defects such as weak electron mobility for a rechargeable battery, a low aperture ratio, and incompatibility with CMOS processing. On the other hand, a poly-Si film device is formed by forming an operation circuit required for inputting an image signal into a picture on a substrate to complete the process in the TFT stack of the element, and using an amorphous germanium TFT (a- This process cannot be performed with Si TFT). A polysilicon film device does not need to be connected between a plurality of terminals and a driver 1C, so this feature can improve productivity and reliability, and also reduce the thickness of the panel. Further, since the polycrystalline lithography process can directly utilize the micromachining technology of 矽LSI, it is possible to form a microstructure by wires or the like. Therefore, since there is no limitation in the distance between the TAB mounting of the driver 1C (and the limitation is obvious in an amorphous 矽 TFT), the reduction in the size of the primitive can be achieved relatively easily, and the viewing angle can be small. Implement a large number of primitives. Compared with the thin film transistor using amorphous germanium, the thin film transistor 200811959 using polycrystalline germanium in the active layer has a south turn and can determine the channel position of the active layer by self-alignment, thus making the device smaller in size and CMos is formed. Because of this, the 'polycrystalline (tetra) film transistor can be used as an active matrix type of flat panel, ', a page (for example, a liquid crystal display and an organic EL device) or the like, and #前,, more and more, it is used as a necessary component for the application of large screen display and C (X} (glass on-wafer) products with built-in drivers.

. 夕TFT 了以在南溫或低溫下製 麩 高溫下製造該等TFT之产、、兄丁.不热。 …、 寺 之^况下，需要諸如石英的昂貴材料 來製作基板，且因此不適料大螢幕顯示H。因此，進行 積極的研究，尋找在低溫條件下训非結晶”膜來大規 拉製造多晶發之方法。 在低溫下形成多晶歡該方法之範例包含_結晶化 (SPC)金屬誘發之結晶化（MIC)、金屬誘發之側向結蟲 化（MILC)、準分子雷射結晶化（扯〇及類似方法。 SPC方去之優勢在於：使用廉價設備獲取均質晶體結 冓而口為舄要咼結晶溫度及較長之處理時間，該方 去不利於使用諸如玻璃基板，其為具有相對較低之熱變形 溫度的基板，且生產率較低。根據Spc方法，僅當非結晶 石夕薄膜一般在600至700°C經受約1至24小時之退火時， 可達成結晶化。進一步而言，在使用SPC方法製備多晶矽 之情況下，當發生非結晶相至結晶相的固態相轉移後，可 觀察到孿晶生長，且因此晶體晶粒具有大量晶體晶格缺 陷。該等因素導致了該等已產生的多晶矽TFT之電子及電 200811959 洞之遷移率減少，以及臨界電壓之增力1 MIC方法之優勢係使非結晶石夕與特定金屬接觸，使該 非結晶柯以在遠低於該SPC方法之結晶溫度下結晶。可 用於该跳方法之金屬之範例包含Ni、Pd、Ti、μ、Ag、In the case of TFT, the production of these TFTs is made at a high temperature in the south or low temperature, and the brothers are not hot. In the case of ..., the temple requires expensive materials such as quartz to make the substrate, and therefore it is not suitable for the large screen to display H. Therefore, active research is being conducted to find a method for producing polycrystalline hair by a non-crystalline film under low temperature conditions. Formation of polycrystalline at low temperatures This example of the method includes crystallization (SPC) metal induced crystallization. (MIC), metal-induced lateral worming (MILC), excimer laser crystallization (drag and so on). The advantage of SPC is that it uses cheap equipment to obtain homogeneous crystal crusting and the mouth is a must. The crystallization temperature and the longer processing time, which is disadvantageous for the use of a substrate such as a glass substrate, which is a substrate having a relatively low heat distortion temperature, and has low productivity. According to the Spc method, only when the amorphous crystal film is generally Crystallization can be achieved when the annealing is performed at 600 to 700 ° C for about 1 to 24 hours. Further, in the case where polycrystalline germanium is produced by the SPC method, it can be observed after solid phase transfer from the amorphous phase to the crystalline phase occurs. To the twin growth, and thus the crystal grains have a large number of crystal lattice defects. These factors lead to the reduction of the mobility of the electrons and electricity of the 200811959 hole of the polycrystalline germanium TFTs that have been produced, and The boosting force of the threshold voltage 1 MIC method has the advantage of contacting the amorphous metal with a specific metal, so that the amorphous crystal is crystallized at a temperature far lower than the crystallization temperature of the SPC method. An example of a metal that can be used in the jumping method includes Ni. , Pd, Ti, μ, Ag,

Au、Co、Cn、Fe、Mn及類似物。該等金屬與非結晶矽反 應以形成共晶相或魏物相，藉此促進低溫結晶。然而， 當該MIC方法應用於多㈣抓製造之實際處理時，在該 通道中很可能存在金屬污染。 、,MILC方法係MIC方法之酿，錢祕金屬沉積於 通這，該方法包含在通道上形成—_，然後使―薄金屬 層沉積於自朗準結射的雜及祕，以促進金屬誘發 之結晶化’且隨後誘發朝向該通道之側向結晶化。在MILXC 方法中最常使狀金屬係N i及p d。儘管與S p c方法之產 ，相比’MILC產生之多晶⑦具有優良結晶度及高場效應遷 移率，但已通報該MILC產物顯示高茂漏電流特徵。因此， 即使與MIC方法相比，MILC方法減少了金屬污染之問題， 但仍然沒有完全地解。另—方面，另—可得之方 法係作為MILC之改I的場辅助側向結晶化（Falc)。與 c方法相比，FALC方法顯示較高之結晶率且具有結晶 化方向之各向異性，但該方法仍然未能提供金屬污染問題 之理想解決方案。 與SPC方法相比，因為降低了結晶溫度，所以諸如 MIC MILC及FALC之該等結晶方法係有效的；然而，其 共同之缺陷在於結晶化持續㈣仍然較長，且結晶化係由 200811959 發^此’其意味著該等方法並未完全擺脫金屬污 :=冋8:，新近開發出ELC方法，其可在一玻璃基板 上故由低溫處理來製備多S石々、續y βρ減“产 夕曰日石夕厚膜’同時解決金屬污染問 喊。低壓化學氣相沉積（Lpcv # π VD)或電漿增強化學氣相沉 H 3㈣結㈣軸科㈣於紫外線區 τ吸收係數，該紫外線區域對應於準 非結密度:輕“發生 薄臈受結晶化時，亦伴隨著射之方式使非結晶石夕 程。從此丢+Λ ^ 者在極短時間内的熔融及凝固過 然而，咖處理包，，法意義上並非嚴格的低溫處理:。 顯著影響之局部溶晶t之程序，在受準分權 間完成該結晶化 /巾迅錢生之熔融及凝固處理期 幾十奎料 且因此有可能在一極短時間内（猿 πτ宅微秒之内）違 當雷射朵給.厘生夕晶矽而不損害該基板。換言之審， 薄膜組成之I吊短暫地照射由玻璃基板/介電層/非結晶梦 非結晶成非結晶石夕時，僅選擇性歸 基板。同樣，在^ 而不損害安置於下層之玻璃 優勢係庐得—文相至固相之相轉移期間產生之多晶石夕之 產生之多又學穩定晶粒結構咖^ 此，ELC方、、該等晶粒中的晶體缺陷明顯減少。因 物。 '產生之多晶矽優於該等其他結晶化方法之產 然而，丑乙匸古、 之問題係雷射央法具有若干嚴重缺陷，例如， 田光束本身之照射劑量不均一；雷备 200811959 題係獲得大晶粒所需之雷射能量密度所能處理之區域極产 受限；及大尺寸石夕薄膜上遺留照射痕跡之問題。該等因ς 導致組成多晶⑪TFT线層之多晶残_晶^寸不規 則。另外，從液相轉移至固相之過程中 、 /生土夕日日取，歷經 體積，張，從形成晶粒邊界之—輯察到向表面突起的嚴 重問題。該現象在後處理中對閘極介電層施加直接影響， 使介電質崩潰電壓減少，且歸因於多晶發/閘極介電層;面 之不規則平面，度，嚴重影響諸如熱載體應力裝置之可胃靠性。 近年來，已開發出一種速續侧向凝固（SLS)之方法 解決上述ELC方法穩定性之_，且成功地用於雷射能 里始、度之處理區域之穩定化 '然❿，該方法仍然無法消除 照射痕跡及表面突起之問題。由於當前平板顯示器工業快 速成長，將雷射用於lmx 1 m尺寸或更大尺寸之該等堆疊 之結晶化處理的技術需在不遠的將來用於大規模生產，但 該技術仍然存在問題。而且，進行該ELC方法及SLS方法 之該等儀器非常昂貴，因此需要較高之啟動及維護成本。 為解決先前技術之該等問題，本發明之發明人在κρ 2004-37952中首次建議一方法，該種進行矽結晶化之方法 係藉由在處理期間不使基板發生變形之溫度範圍内預熱矽 薄膜’為產生时載體，導致阻抗降低至可啟動焦耳加熱 之數值，隨後將-電場直接施加於預鮮薄膜以利用載體 移動之方式誘發料.加熱。該方法係—麟方法，其著眼 於在-較短時間内於—相對較低之溫度下產生具有高品質 之多晶矽薄膜。 200811959 然而，仍需要一種在短時間内最好是比室溫更低溫度 下執行結晶化的方法，使其可以實施於各種應用，且可以 更有效地達成結晶化、活化雜質、熱氧化薄膜處理，及晶 體晶格缺陷之消除。 對非結晶矽薄膜之方法有增加之需求，其中，雷射結 晶化方法所具有之優勢在於因為可在短時間内完成處理， 所以不損告戈置於下層之基板，且在高溫相轉移過程中可 瞻產生I質上不具有缺陷之尚品質晶粒；同時，克服了該等 雷射結晶化方法之缺陷，諸如歸因於處理區域之局部化的 不規則照射劑量、處理操作之限制，及所用設備之昂滅 本。詳言之’若使用因為適用於下一代平板顯示器，而漆 最近倍受矚目之主動矩陣有機發光二極體，則該裝置在電 流驅動模式中操作，反之，TFT-LCD在電壓驅動模式^ 作。因此，晶粒尺寸之均-性係大尺寸基板的關鍵因舊。 實際上，當使用包含ELC或SLS (其利用雷射）之低落結 鲁晶化方法時，平板顯示器工業將面臨限制。考慮到該等事 實，在非雷射模式中利用低溫結晶化生產高品質之多晶石夕 薄膜的新技術係受到極高期待的。 阳 【發明内容】 [技術問題】 關技術 本發明希望同時解決上述先前技術問題及該相 中存在之該等技術問題。. 具體言之，本發明之目的係提供—種方法，該方法係: 200811959 在形成於一透明基板上之一介電層上連續形成一導電層及 一介電層，然後在其上形成一矽薄膜，且使一電場施加於 該導電層，進而誘發焦耳加熱以產生強熱，該強熱在極短 時間内反過來啟動該上述非結晶矽薄膜之結晶化、晶體晶 格缺陷之消除、晶體生長、活化雜質及類似現象，而不損 害該基板。同樣，本發明提供一種方法，其中，不同於包 含液相至固相之相轉移的雷射結晶化，相轉移以固態形式 發生，且從一固相轉移至另一固相，藉此，有可能在相同 • * · 之反應器中連續進行非結晶矽之沉積及閘氧化物薄膜之連· 續沉積。意即，本發明提供一種在非結晶矽/閘氧化物結構 中啟動結晶化的方法。 本發明之另一目的係提供利用該等上述方法獲得高品 質的多晶石夕.薄膜。 [技術問題之解決] 為達成該等上述目的，本發明所建議之退火矽薄膜之 | 方法，包含之步驟係：在形成於一透明基板上之一介電層— 上連續且依次形成一導電層及一介電層；然後，在其上形 成一石夕薄膜；施加一電場於該導電層上，進而誘發焦耳加 熱以產生強熱；措著傳導該強熱’熱處理該發薄膜。 以待結晶之非結晶發薄膜、非結晶/多晶混合相發薄 膜、低溫多晶矽薄膜，或用於活化雜質之摻有雜質的多晶 矽薄膜作為該矽薄膜之範例。 根據本發明，藉由施加一電場於安置於矽薄膜層下的 12 200811959 =二在相對較短之時間内產生強熱，且主要經由傳導 缺陷、活化雜質、執氧I = # . ”、、匕及颏似步驟。即使已產生啟動矽 /專膜熱處理之強熱，下一 卜3之基板亦不經受熱變形。因為與 :二:比具有相對極小厚度之矽薄膜之總熱量係極小， ，熱傳導導致的溫度提昇之增量顯著高於基板之溫 度增置。 该結果與ELC方法之結晶化處理具有她樣態，該 方法係種產生回品質多晶石夕薄膜之雷射結晶化方 法’該相似之樣態係：該處理係在短時間内於高溫下完減 ^然而，本發明所述均係迄今為止尚未通報的新方法， 一方法係：在下部的介電層之間引入—導電層，且在上部 =入一石夕薄膜，且施加-電場於該導電層，經由類㈣射 m晶化方法之結晶化處理，在該堆叠之全部範圍内進行非 結晶矽薄膜及非結晶/多晶矽薄膜結晶化之方法；另一方法 ，：在該堆4之全部區域進行減理，達成多㈣薄膜中 晶體晶格缺陷之消除及晶粒之生長。 根據本發明熱處理摻有雜情況下，本 =用之料膜可以係摻有雜質的非結^薄膜、換㈣ 貝、非結晶/多晶混合相石夕薄膜或振有雜質的多晶石夕薄膜。 板據本發明，該導電層最好為鋼錫氡化物（Ιτ〇)薄膜 2類型的透明導電薄膜，或金屬一，且其更好為細 =勿⑽)薄膜。因為銦錫氧化物(ΙΤ〇)薄膜賴 逐明潯膜，其特別適用於顯示裝置。 13 200811959 ，視情況將基板預熱至不 在施加〜電場於導電層之前 使該基板發生變形之程度。 林月亦提供利用上述退火方法結晶之高品質多晶石夕 薄膜、，或，、有以，亥相同方法啟動的摻有雜質之多晶石夕薄 膜。當利用局部結晶化處理所使狀雷射結晶化方法時， 發生該等上相題，^本發明之方法在安置於施加電場之 導電層上的薄膜之全部區域範圍内同時進行結晶化處理， 因此可迅速結晶及啟動且提供高品質之多晶矽薄膜。 與習知技術相比，本發明之退火方法及由此獲得之多 晶矽薄膜具有如下特徵或優勢。 首先，實施結晶化之該處理非常簡易且具有經濟優 勢。作為最新技術之一的ELC方法藉由直線光束之重複掃 描來進行該處理，且SLS方法利用照射通過圖案化遮罩之 雷射，隨後利用在極短距離内精確移動之雷射光束重複掃 描，來進行該處理。因此，該堆疊全部區域之雷射光束強 度非均一性係不可避免的。然而，本發明之方法可在極短 時間内，於堆疊全部區域内進行非結晶矽薄膜、非結晶/多 晶混合相薄膜或多晶矽薄膜之結晶化及缺陷消除，板 無=何變形。而且，ELC方法需要額外之脫氫退火處二， 以伙非結晶矽薄膜中移除氫，該步驟係雷射照射之預備步 驟，所以ELC方法比本發明之方法更複雜。 第二，實施本發明之處理設備係廉價的，且可利用在 此項技街中已確立之技術。提供優良結晶效應之E L c方法 及類似方法’使用包含雷射裝置的昂貴設備。另—方面， 200811959 因為在半導體及抑 明之方法体+ "、、示為工業中已較佳地確定進行本發 “ π寓之設備， 等習知技術 、所以可直接應用該等習知技術或該 第二，^正來進行本發明之方法。 高品質之多於大規模生產具有均-性及 進行堆疊全部二 利於處理大面積之^内之、，曰曰化’因此本發明之方法有 提#高口 &B二土板。利用上述方法獲得之多晶矽薄膜 马表面私之結晶域物。 明之方法t明之方法可用於低溫活化雜質處理。本發 TFT結構中之、^^結晶化’亦可有效應用於低溫下的 熱處理極電極附近的離子植人的活化雜質之 理方本發明之方法可賴似於非結晶打FT生產處 中，積閑氧化物薄膜。在mosfet結構之雕 TFT 3之=膜之薄臈品f及_氧化物薄膜介面在 晶所生產；:學特性中扮演極其重要的角色。在非結 生產處理中，使用PECVD方法 轉性係優良的。相反，在LTPS生產處理之情 ^當前祕錢财產之結晶化技_雷射處H ，用啦VI)方法進行非結晶石夕之沉積及在熱處理爐中脫 =後進灯雷射結晶化。根據PECVD方法，間氧 :==結晶的多晶彻上。換言之，用於非 、、、口曰曰石夕TFT·生產處理之連續沉積係不可能的。然而，因為 15 200811959 本㈣之^化技術係非雷射處理，财^積係可能的。 弟六，高溫多晶石夕處理可在低溫下實施。在使用石英 作為透明基板之高溫多㈣處理的情況τ，湘延長時間 或更低溫度之熱處理，製備具有相對較大晶粒尺 不具有諸如孿晶之諸多晶體晶格缺陷）之低溫多晶 ，=:遺後沉積閘氧化物薄臈。在低溫多晶石夕處理之情 玻璃基板t溫度叫所以_四㈣方法沉 板-产而在⑽多晶發處理之情況〒，不存在基 板酿度之限制，因此利用熱氧化處理。當在管c或更高 之溫度使用熱氧化處理時，可產 〆 氧化物膜，且亦可在熱氧化薄膜紋理之開 薄膜之下的低溫多晶w存在：===: 據本發明，.因為瞬間（較佳係在i 曰曰體曰曰格缺陷。根Au, Co, Cn, Fe, Mn and the like. The metals react with the amorphous ruthenium to form a eutectic phase or a Wei phase, thereby promoting low temperature crystallization. However, when the MIC method is applied to the actual processing of multi (four) scratch manufacturing, metal contamination is likely to be present in the channel. The MILC method is based on the MIC method, and the money secret metal is deposited on the channel. The method comprises forming a -_ on the channel, and then depositing a "thin metal layer" on the impurity and the secret of the self-alignment to promote metal induced Crystallization' and subsequent induction of lateral crystallization towards the channel. The most commonly used metal systems N i and p d are in the MILXC process. Although the polymorph 7 produced by the 'MILC has superior crystallinity and high field-effect mobility compared to the S p c method, it has been reported that the MILC product exhibits high leakage current characteristics. Therefore, even if the MILC method reduces the problem of metal contamination compared with the MIC method, it is still not completely solved. Alternatively, another method is available as field assisted lateral crystallization (Falc) of MILC. Compared with the c method, the FALC method shows a higher crystallization rate and anisotropy of the crystallization direction, but the method still fails to provide an ideal solution to the metal contamination problem. Compared with the SPC method, such crystallization methods such as MIC MILC and FALC are effective because the crystallization temperature is lowered; however, the common drawback is that crystallization continues (4) is still long, and the crystallization is performed by 200811959^ This means that these methods are not completely rid of metal stains: = 冋 8:, the ELC method has been newly developed, which can be used to prepare multi-S 々 々 々 々 々 々 々 々 在一夕曰日石夕厚膜' Simultaneously solves the problem of metal pollution. Low pressure chemical vapor deposition (Lpcv # π VD) or plasma enhanced chemical vapor deposition H 3 (four) junction (four) axis (4) absorption coefficient in the ultraviolet region, the ultraviolet The area corresponds to the quasi-non-junction density: light "when the thin enamel is crystallized, the non-crystalline stone eve is also accompanied by the way of shooting. Since then, the person who lost +Λ ^ melted and solidified in a very short time. However, the coffee processing package, in the sense of the law is not strictly low temperature treatment: A program that significantly affects the local crystallization of t, completes the crystallization of the crystallization/drinking of the crystallization and the solidification treatment period of tens of tens of kiln and thus is likely to be in a very short time (猿πτ宅微Within seconds, it is illegal to give a laser to the substrate without damaging the substrate. In other words, when the film composition I hangs briefly from the glass substrate/dielectric layer/amorphous crystal to a non-crystalline stone, it is selectively returned to the substrate. Similarly, in the absence of damage to the glass dominant system placed in the lower layer, the polycrystalline stone produced during the phase transition from the phase to the solid phase has a large number of stable crystal structure, ELC, Crystal defects in the grains are significantly reduced. Cause of things. 'The resulting polycrystalline germanium is superior to the production of these other crystallization methods. However, the problem of the ugly ray is that the laser central method has several serious defects. For example, the radiation dose of the field beam itself is not uniform; Lei Bei 200811959 The area where the laser energy density required for large crystal grains can be handled is extremely limited; and the problem of leaving traces on the large-scale stone film. These factors cause the polycrystalline residual crystals of the polycrystalline 11 TFT line layer to be irregular. In addition, in the process of transferring from the liquid phase to the solid phase, / in the day of the birth, the volume, Zhang, from the formation of grain boundaries - the serious problem of protruding to the surface. This phenomenon exerts a direct influence on the gate dielectric layer in the post-processing, which causes the dielectric breakdown voltage to decrease, and is attributed to the polycrystalline/gate dielectric layer; the irregular plane of the surface, the degree, seriously affecting such as heat The gastric stress of the carrier stress device. In recent years, a method of rapid lateral solidification (SLS) has been developed to solve the stability of the ELC method described above, and it has been successfully used for stabilization of the processing region of the laser energy, and the method is The problem of illuminating marks and surface protrusions cannot be eliminated. Due to the rapid growth of the flat panel display industry today, the use of lasers for crystallization of such stacks of lmx 1 m size or larger is required for mass production in the near future, but the technology still has problems. Moreover, such instruments that perform the ELC method and the SLS method are very expensive and therefore require high startup and maintenance costs. In order to solve the problems of the prior art, the inventors of the present invention first proposed a method in κρ 2004-37952, which performs the crystallization of ruthenium by preheating in a temperature range in which the substrate is not deformed during the treatment. The tantalum film 'is the carrier when it is produced, causing the impedance to decrease to a value that can initiate Joule heating, and then the - electric field is directly applied to the pre-formed film to induce the material heating by means of the carrier movement. This method is a lining method which focuses on producing a high quality polycrystalline germanium film at a relatively low temperature in a relatively short period of time. 200811959 However, there is still a need for a method of performing crystallization in a short time, preferably at a temperature lower than room temperature, so that it can be applied to various applications, and can more efficiently achieve crystallization, activation of impurities, thermal oxidation film treatment. , and the elimination of crystal lattice defects. There is an increasing demand for a method for amorphous ruthenium film, wherein the laser crystallization method has the advantage that since the treatment can be completed in a short time, the substrate placed on the lower layer is not damaged, and the phase transition process at high temperature is performed. It is possible to produce a quality grain having no defects in the quality of the core; at the same time, overcome the defects of the laser crystallization method, such as the irregular irradiation dose due to the localization of the treatment area, the limitation of the processing operation, And the equipment used. In particular, if the active matrix organic light-emitting diodes, which are recently used in the next generation of flat panel displays, are recently used, the device operates in the current drive mode. Conversely, the TFT-LCD operates in the voltage drive mode. . Therefore, the uniformity of grain size is a key factor in large-size substrates. In fact, the flat panel display industry will face limitations when using low-level crystallization methods including ELC or SLS (which utilizes lasers). In view of such facts, new technologies for producing high-quality polycrystalline film in low-temperature crystallization in a non-laser mode are highly anticipated. [Explanation] [Technical Problem] The present invention is intended to solve the above-mentioned prior art problems and the technical problems existing in the phase. Specifically, the object of the present invention is to provide a method, which is: 200811959 continuously forming a conductive layer and a dielectric layer on a dielectric layer formed on a transparent substrate, and then forming a layer thereon. Forming a thin film and applying an electric field to the conductive layer to induce Joule heating to generate strong heat, which in turn initiates crystallization of the amorphous ruthenium film and elimination of crystal lattice defects in a very short time. Crystal growth, activation of impurities and the like without damaging the substrate. Also, the present invention provides a method in which, unlike laser crystallization including phase transfer from a liquid phase to a solid phase, phase transfer occurs in a solid form and is transferred from one solid phase to another, whereby It is possible to continuously perform the deposition of amorphous germanium and the continuous deposition of the gate oxide film in the same * * · reactor. That is, the present invention provides a method of initiating crystallization in an amorphous germanium/gate oxide structure. Another object of the present invention is to provide a high quality polycrystalline stone film using the above methods. [Solution to Problem] In order to achieve the above objects, the method for annealing an annealed film according to the present invention comprises the steps of: continuously and sequentially forming a conductive layer on a dielectric layer formed on a transparent substrate a layer and a dielectric layer; then, a film is formed thereon; an electric field is applied to the conductive layer to induce Joule heating to generate strong heat; and the film is heat treated by conducting the strong heat. As the ruthenium film, an amorphous film to be crystallized, an amorphous/polycrystalline mixed phase film, a low temperature polycrystalline film, or an impurity-doped polycrystalline silicon film for activating impurities is used. According to the present invention, strong heat is generated in a relatively short period of time by applying an electric field to 12200811959=2 disposed under the ruthenium film layer, and mainly via conduction defects, activation impurities, oxygenation I = #.匕 and the like steps. Even if the strong heat of the starting 矽/specific film heat treatment has been generated, the substrate of the next layer 3 is not subjected to thermal deformation. Because the ratio of the total heat of the bismuth film having a relatively small thickness is extremely small, The increase in temperature rise caused by heat conduction is significantly higher than the temperature increase of the substrate. This result has her appearance with the crystallization treatment of the ELC method, which is a laser crystallization method for producing a back quality polycrystalline film. 'This similar pattern: the treatment is completed at a high temperature in a short time. However, the present invention is a new method that has not been reported so far, and one method is: introducing between the lower dielectric layers - a conductive layer, and in the upper part = a film, and an electric field applied to the conductive layer, through the crystallization treatment of the (four) shot m crystallization method, the amorphous ruthenium film and the non-crystal are carried out in the entire range of the stack / A method for crystallizing a polycrystalline germanium film; another method of: performing a reduction in the entire region of the stack 4 to achieve elimination of crystal lattice defects and growth of crystal grains in the (four) film. According to the heat treatment of the present invention, The film used for the present invention may be a non-junction film doped with impurities, a (four) shell, an amorphous/polycrystalline mixed phase film or a polycrystalline film with impurities. The plate according to the invention, the conductive layer Preferably, it is a transparent conductive film of the type of steel tin telluride (Ιτ〇) film 2, or a metal one, and it is more preferably a thin film (10). Because the indium tin oxide (ΙΤ〇) film is a film of the film It is particularly suitable for display devices. 13 200811959 , The substrate is preheated as appropriate to the extent that the substrate is not deformed before the application of the electric field to the conductive layer. Lin Yue also provides high quality polycrystalline crystallization crystallized by the above annealing method. a film, or, or a polycrystalline doped film which is activated by the same method as that of the same method. When the laser crystallization method is used by the local crystallization treatment, the above-mentioned upper phase problem occurs. Method in safety Simultaneously performing crystallization treatment over the entire area of the film on the conductive layer to which the electric field is applied, thereby rapidly crystallizing and starting and providing a high quality polycrystalline germanium film. Compared with the prior art, the annealing method of the present invention and thus obtained The polycrystalline germanium film has the following characteristics or advantages. First, the process of performing crystallization is very simple and economical. The ELC method, which is one of the latest technologies, performs this process by repeated scanning of a straight beam, and the SLS method uses illumination. The laser of the patterned mask is then subjected to repeated scanning with a laser beam that is precisely moved over a very short distance. Therefore, the non-uniformity of the intensity of the laser beam over the entire area of the stack is unavoidable. The method of the invention can perform crystallization and defect elimination of the amorphous ruthenium film, the amorphous/polycrystalline mixed phase film or the polycrystalline ruthenium film in the entire region of the stack in a very short time, and the plate has no = deformation. Moreover, the ELC method requires an additional dehydrogenation anneal to remove hydrogen from the amorphous ruthenium film. This step is a preliminary step for laser irradiation, so the ELC method is more complicated than the method of the present invention. Second, the processing equipment embodying the present invention is inexpensive and utilizes the techniques already established in the art street. The E L c method and the like which provide an excellent crystallization effect use expensive equipment including a laser device. On the other hand, 200811959, because in the semiconductor and the method of the method, the industry has been better defined in the industry, such as "the equipment of π, such as the technology, so can directly apply these conventional technologies. Or the second method is to carry out the method of the present invention. The high quality is more than the mass production and the stacking is performed to facilitate the processing of a large area, and thus the method of the present invention. There are mentioning #高口&B two soil plates. The crystal surface of the polycrystalline tantalum film surface obtained by the above method is obtained. The method of the method of Ming Ming can be used for low temperature activation impurity treatment. In the TFT structure of the present invention, crystallization 'It can also be effectively applied to the treatment of ion-implanted activated impurities in the vicinity of the heat-treated electrode at low temperature. The method of the present invention can be used in the production of non-crystalline FT, and the oxide film is accumulated in the mosfet structure. TFT 3 = thin film f and _ oxide film interface are produced in the crystal; play an extremely important role in the study of properties. In the non-junction production process, the PECVD method is excellent. In the LTPS production and processing situation ^ the current crystallization technology of the secret money property _ laser H, using VI) method for the deposition of amorphous shixi and in the heat treatment furnace = after the laser crystallization of the posterior lamp. According to PECVD Method, inter-oxygen: == crystallized polycrystals. In other words, continuous deposition for non-,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Non-laser processing, financial system is possible. Sixth, high temperature polycrystalline stone processing can be carried out at low temperatures. In the case of using quartz as a transparent substrate for high temperature (four) treatment, τ, extended time or lower temperature The heat treatment, the preparation of a low-temperature polycrystal having a relatively large crystal grain size without many crystal lattice defects such as twin crystals, =: a post-mortem deposition gate oxide thin crucible. The glass substrate is treated at a low temperature polycrystalline stone t temperature is called _ four (four) method of sinking - production and in the case of (10) polycrystalline hair treatment, there is no limitation of substrate brewing, so use thermal oxidation treatment. When using thermal oxidation treatment at tube c or higher When the oxide film is produced, May open under low temperature thermal oxide film of a polycrystalline film texture exists w: ===: According to the present invention, since the moment (preferably said lines in said body i said root said lattice defects.

或 卿、平又仏係在1秒内）即可達到l_〇C : ·度’所以’藉由在氧、臭氧或水蒸汽環境下重 係可能的。 ，、、、破肖基板上貫施熱氧化處理 【實施方式】 缺而下將*照圖式詳細描述本發明之具體實施例， 4而，該等具體實施例不限定本發明之範疇。 第-圖所不係根據用於非結晶石夕薄膜結晶化之本發明 之—具體實施例的基板構造之示意圖。 =第：圖.，在基板1〇上，連續形成第一介電層2〇、 h層3〇、第二介電層40及非結晶石夕（a_Si)薄膜％，且 16 200811959 一電場施加於該導電層3〇。 ‘ 璃、之材料並無特定之·限制，且可以使用諸如玻 『央=膠的透明基板材料，而從經濟樣態而言玻璃 :車广然而’根據平板顯示器領域近 於具有優良作用的阻抗及處理能力的塑膠基 U 。本發明之方法可直接應用於該㈣膠基礎之 丞販。 :¾. 排出使H ;丨電層2G之目的係防止基板ig包含物質之 =、、’料物質可能在隨後之處理中產生，例如於玻璃基 月况下的驗性物質。—般利用沉積氧切（Si⑹或真 ^石夕來形成該層，且鮮度較佳係在2G00至5_ A範圍 ^不限定此範圍。基於將來技術之進步，非結晶石夕薄 太广不需要該介電層2G便可直接形成於基板上，且酿為 該方法可應用於該結構，應暸解本發明之範脅齡 空蒸二Γ諸如，、真 以使隨後施加之電I導需維持均―厚度 勹 电每導致的焦耳加熱處理期間之加熱岣 n^ZZ 3〇 /厚膝50之污染，且絕緣TFT裝 之材料可與第—介電層2〇所用之材料相同。^成該層 將利用例如低壓化學氣相沉積、高壓化學氣相 水增強化學氣相沉積（PECVD)、喷錢、真空蒸錄或卖= 17 200811959 法，可形成非結晶矽薄膜50，但較佳地是使用PECVD方 法。薄膜的厚度最好在300至1000 A之範圍内，但不限在 此範圍。 在施加一電場於導電層30之前，將該等上述構造（意 即10、20、30、40及50)或至少將基板10預熱至一適當 之溫度範圍。該適當之溫度範圍意味在整個處理中基板10 不受到損害，且對應之溫度範圍應最好是低於基板10之熱 變形溫度。該預熱方法並無特定限制，且可使用如下之方 • · - * 法：例如，將堆疊置於普通熱處理爐且使用燈或類似物之 輻射熱進行照射。 藉由施加具有功率密度之能量來進行對於導電層30 之電場應用，該能量可產生足夠之強熱以誘發非結晶矽薄 膜50之結晶化.，如上文所述之焦耳加熱。藉由諸如導電材 料之阻抗，及導電層30之長度及厚度的各種因素來決定該 能量數值，因此無法列出。施加之電流可以係直流電或交 流電。以連續應用之時間計，該電場應用之持續時間係 1/1，000,000秒至100秒，且最好是從1/10000秒至10秒， 且更好是從1八〇〇〇秒至1秒。可規律地或不規律地多次重 複施加一電場。因此，該總計之熱處理時間長於上述電場 施加時間，但與習知結晶方法至少一次之處理時間相比， 該熱處理時間係極短的。 在一些情況下，亦可使用導電層30與非結晶矽薄膜 50互相交換位置的結構。 作為本發明之另一具體實施例，第二圖所示之示意圖 18 200811959 說明利用第一圖之相同方法施加一電場，同時進行結晶化 及活化雜質之處理。繼沉積非結晶矽薄膜50之後，經由微 影處理完成了關於個別TFT裝置之圖案化處理。利用 PECVD方法在其上沉積閘氧化物薄膜42,隨後利用噴濺而 沉積閘極44。為形成該閘極44，利用微影處理及蝕刻處理 執行圖案化。因此利用摻有雜質對已製備之自我對準閘結 構實施離子植入，以形成源極及汲極，隨後利用第一圖相 同之方法施加一電場，同時進名*結晶化及活化雜質。因為 • 作為導電層之銦錫氧化物（IT〇)薄膜3〇並非電性短路， 所以上述處理係可能的。 乂 - 作為本發明之另一具體實施例，第三圖所示之示意圖 說明使用第一圖相同之方法施加一電場，同時進行結晶化 處理及熱氧化。因為根據本發明，一旦進行焦耳加熱1非 結晶矽薄膜50之溫度將提昇至至少1〇〇〇〇c或更高，應以 在氧氣環境下的熱氧化處理係可能的。視情況，可在臭氧 • 環境，水蒸汽環境或甚至在去離子水中進行該處理，而非 j氧氣環境中。一般而言，在TFT裝置生產期間，因為玻 j基板10之熱缺陷而無法使用具有優良特性之熱氧化物 薄膜，且"几積PECVD氧化物薄膜。然而，根據本發明，因 為電場僅施加於較短時間，所以，於氧氣環境下，以重複 %加私場之方式同時進行極薄熱氧化物薄膜⑼之產生與 :曰曰化利用PECVD方法在其上沉積相對較厚之氧化物薄 膜（未圖示），可實施TFT產生之處理，且以此方式可改 良Si/Si02介面之該等特徵。 19 200811959 作為本發明之另一具體實施例，第四圖所示之示意圖 说明的方法係以第一圖相同之方法施加一電場，對經低溫 熱處理而預結晶之多晶石夕薄膜進行熱處理。一般而言，低 溫多晶矽薄膜具有之一優勢係其晶粒之尺寸大於高溫多晶 矽之晶粒尺寸，但其包含諸如晶粒中之孿晶的許多晶體晶 格缺卩曰。根據本發明之方法，因為可以進行高溫處理且該 玻璃基板10不產生熱變形，所以，施加一電場，對在低溫 下已預結晶之多晶矽薄膜52進行高溫熱處理，，藉由此方 法’可產生不具有晶體晶格缺陷之大尺寸多晶矽薄膜。 作為本發明之另一具體實施例，第五圖所示之示意圖 說明之方法係：在一氧氣、臭氧或水蒸汽環境或去離子水 中’以第一圖相同之方法施加一電場，在經低溫熱處理而 預結晶化的多晶矽薄膜上形成熱氧化物膜。第五圖說明該 處理與使用石英基板產生高溫多晶矽薄膜之處理係大體相 同的。在該熱氧化處理之情況下，因為需要氧氣環境及 900°C以上之高溫，所以不可能使用玻璃基板。在本發明 之方法之情況下，因為在極短時間内達到高溫，所以可形 成熱氧化物薄膜60而不招致玻璃基板1〇之熱變形。然而， 需重複施加電場時之加熱及移除電場時之冷卻，達成熱氧 化處理。因為利用本發明之方法沉積之熱氧化物薄膜6〇之 厚度係極小，所以添加額外PECVD氧化物薄膜處理以形成 閘氧化物膜（未圖示）。意即，實施本發明之方法可導致閘 氧化物薄膜及_多晶矽薄膜之間之介面特性之改良。而且， 在熱氧化處理期間，可移除低溫多晶矽中出現的大量晶體 200811959 晶格缺陷。 %明=t發明之另一具體實施例’第六圖所示之示意圖 月方法係在相同之CVD腔室时續沉積非結晶㈣ :二及閘魏物薄膜7〇 ’然後以第-圖相同之方法施加 :琢仃熱處理。-般而言，連續沉積形成之閑氧化 物薄膜之優勢在於該介面特性係優良的，但其不能用於雷 射處理。因為本發明之方法係非雷射處理，所以可使用連 •讀沉積形成之_化㈣進而使得該裝置特性之改良 及该處理之簡化。 作為本發明之另-具體實施例，第七圖所示之示意圖 既明之方法係連續沉積非結晶石夕薄膜50及閑氧化物薄膜 70 ’隨後以第-圖相同之方法施加一電場，對經低溫熱處 理而預結晶之薄膜52進行熱處理。藉由此方法，可同時獲 得具有大尺寸晶粒及少1缺陷之多晶矽薄膜，以及具有優 良介面特性之閘氧化物薄膜。 .: • 本發明之方法中使用之焦耳加熱發生在施加電場之導 電層中，將其界定為：利用電流通過時一導電材料之阻抗 所產生之熱量所進行的加熱。 藉由如下公式表達電場施力σ所導致之焦耳加熱施加於 導電層時，單位時間之能量數值： 在上述公式中，將W定義“耳加餘供之單位時間 之能罝數值，將V界定為施加於導電層兩端之電壓，將] 界定為電流。 21 200811959 可從上述公式中看出，當電壓（v)增加時，及/或電 流（I)增加時，利用焦耳加熱施加於導電層之單位時間之 能量數值亦增加。當焦耳加熱使導電層之溫度增加時，敎 ^ i、、、 量傳導至安置於導電層上之石夕薄膜及安置於導電層下之美 板（例如，玻璃基板）。因此，以本發明之方法對樣本施加 短時間之合適的電壓及電流，利用不導致玻璃基板產生熱 變形之熱傳導，以使矽薄膜之溫度提昇至可以啟動結晶化 及活化雜質的溫度。若施加之能量數值係足夠的，則經由 單個照射即可完成談處理’若數值係不足，則經由呈有適 當時間間隔之若干次照射來完成該結晶化處理。 如上所述，根據習知MIC方法、MILC方法及其他結 晶方法，存在如下情況，一情況係施加電場或磁場以促進 低溫之催化金屬之垂直感應或側向感應，另外之情況係經 由圖案化處理，且在極短時間内（約pSec)使一電場施: 於一極小樣本（例如，25〇pmX5〇Hm)，以通過安置於上 層之金屬傳導膜（Cr)達成結晶化。然而，該等情況不能 進行如下步驟：藉由將電場施加於需要熱處理之石夕薄膜下 安置的導電層，更特定言之，將電場施加於覆蓋該；電層 之石夕薄膜下設置的導電層，及使用導電Μ夕隹甘丄& 士 、 弘尽 < 黑耳加熱來產 生導電熱，在該基板之全部區域内進行結晶化而不進行圖 案化處理。 用於比較本發明與該等習知方法之另一因素係該電場 ，用之持續時間，本發明之方法中電場應用之持續時間^二 單次應.用之持續時間）較佳係上述之1/1 〇〇〇至1秒。节》士 22 200811959 晶化之較短時間可使結晶化及活化雜質在上層之矽薄膜中 達成，且儘管可將導電層加熱至一極高溫度， 々、 r t ^之基板 C例如，玻璃基板）不變形。 範例; 、在下文中’將參照樣本詳細插述本發明，且該等樣 不以任何方式限定本發明之範疇。 ^ [範例1] 利用PECVD方法，在寬2 em、長22 em且厚〇 7 _ 之玻璃基板上形成具有3_ A厚度的_層（第, 由喷賤在第一介電層上沉積具有麵A厚度之^ ^物）薄膜(導電層），且隨後利用舰VD方 利沉積具有圆A厚度之Si〇2層（第二介電層）萬 CVD方法在第二介電層幻冗積具有s〇〇A厚度之非 。因此’製備了第一圖所示之包含一非結晶石夕 錢之溥膜堆疊。測得該導電層之阻抗係2〇q。 在室溫下’將·ν_15Α之電場在以此方式製備的樣 兩3 $龟層上應用〇·〇5秒，總計重複五次該處理。結果， 電場應用總計進行了大約〇.25秒。在一單次場應用中，施 力於士電層上之能量數值係Π25 Watt/cm2。第八圖所示係 根據電場施加於導電層期間的應用時間測得之能量密度之 波形。 在第九圖中，（a)係一照片，其顯示在電場施加之前， 23 200811959 室溫下之非結晶㈣m之樣本，⑴係—照片，其 力：耳，導致之高溫所引起之㈣膜:發 薄膜之彻樣本照片。根據⑻中之發光== 該導電層之即時溫度升至至少酬H更高。該即時埶= 傳導^安置於上層切薄膜且·非結晶奴結晶化Γ里 第十圖所不係繼該熱處理之後對矽薄膜執行拉甚八 之結果1第十圖可看出，非結晶矽薄膜已4_地：： 多晶矽狀態。 · 、成 第十一圖所示係繼該熱處理之後對矽薄膜執 TEM分析之結果。在第十一圖中，根據本發明製備之多曰Γ 石夕薄膜之微結構具有高溫製備之多晶梦薄膜之結構。換= t、,’儘官晶體晶粒尺寸小於低溫多晶矽薄膜之晶粒尺寸， 晶粒之形態係多角形的，且在該晶粒中，諸如孿晶之a曰體 晶=缺陷數量係減少的。已證實儘管存在結晶化熱處=，一 該導電層下之玻璃基板完全不歷經變形。 [範例2】 利用PECVD方法，在寬2 cm、長2 cm且厚〇·7 mm 之玻璃基板上成形具有3000 A厚度之Si〇2層（第一介電 層）°利用噴濺在第一介電層上沉積厚度15〇〇 A之銦锡氧 化物（IT0)薄膜（導電層），隨後利用PECVD在其上沉積 具有厚度1〇〇〇 Α之si〇2層（第二介電層）。利用PECV^ 在第二介電層沉積厚度500 Λ之非結晶矽薄膜。因此，努 200811959 備了第-圖所示之包含非結晶矽… 導電層之阻抗係㈣。 錢之賴堆疊。測得該 將3〇〇 V_3〇A之電場在以此 應用〇._秒，該處理重複總^I、樣本之導電層上 應用於該導電層之單位時狀能〜人。在該電場應用中， 在第十二时，（a)係—日^數值係3_伽W。 前，室溫下之非結晶石夕薄膜的樣本:其:顯不3場施加之 示者電場施加期間’焦耳加熱產 ：：照片’其顯 薄膜發光現象，且（e)係繼itt 熱所導致之石夕 JL、A Q 免场施加之後，且有韓換 ^曰曰㈣膜之㈣膜的樣本照片。根據⑴中㈣色發 光現象，可推斷鱗電層之即時溫度已升至至少刚㈣或 更高。該強熱傳導至安置於上層切薄膜且誘發非結晶石夕 之結晶化。 第十三目所示係親減理之後執射薄膜之暗視緣 TEM分析之結果。在第十一圖中，根據本發明製備之多晶 •石夕薄膜之微結構具有奈米尺寸多晶矽薄膜之結構。僅在管 形爐中進行高溫固相結晶化或利用RTA (快速熱退火）方 式，較難達成該微結構，且本發明首次通報該結構。在本 發明之方法中，因為#亥加熱速率超過至少1〇〇〇〇q〇C/秒，所 以完整地反映出形成於咼溫之微結構。另一方面，即使RTA 利用習知熱處理方法中的最高加熱速率，因為該熱處理速 率僅係約l〇〇°C/秒，所以在該加熱過程中發生了形成多晶 矽之相轉移，因此無法反映形成於高溫下之所需之微結 構。產生於該範例之多晶矽具有極小尺寸之晶粒且顯示等 25 200811959 軸形態之晶粒。該結構係一種無法在其他熱處理方法中獲 得的微結構，且因為保證該晶粒尺寸之均一性，預期該結 構非常適用於OLED應用。已證實儘管存在該結晶化熱處 理，安置於導電層下之玻璃基板完全不歷經變形。 工業適用性 如上所述，根據本發明之退火方法提供多晶矽薄膜， 其完全不具有諸如MIC及MILC方法之結晶化方法產生的 多晶矽薄膜中所呈現之催化金屬導致的污染問題，且同時 籲 不伴隨發生ELC方法產生之多晶矽薄膜中所呈現之表面突 起，且不產生玻璃基板之熱變形，且顧著地減少了晶體晶 格缺陷量。多晶矽薄膜之製備技術構成了本發明之該等特 徵，該等特徵在先前技術中未通報。 普遍熟習關於本發明之此項技術者可以基於該上述描 述進行各種修正及應用。 【圖式簡單說明】 第一圖係一示意圖，根據本發明之一具體實施例，其 說明多晶矽薄膜製備樣本之構造。 第二圖係一示意圖，根據本發明之一具體實施例，其 說明源極/汲極及閘極分別形成之後，同時進行非結晶矽薄 膜結晶化及活化雜質的熱處理之方法。 第三圖係一示意圖，根據本發明之一具體實施例，其 說明於氧氣環境下，藉著如第一圖相同之方法，藉著施加 26 200811959 琶琢π日守進行非結晶梦薄膜結晶化處理及熱氧化處理 之方法。 第四圖係一示意圖，根據本發明之一具體實施例，其 祝明藉著如第一圖相同之方法，藉著施加一電場，熱處理 一已經由低溫熱處理而預結晶之多晶矽薄膜之方法。 第五圖係一示意圖，根攄本發明之一具體實施例，其 說明在氧氣環境下，藉著如第一圖相同之方法，藉著施^ 龜.一電場，形成熱氧化薄膜於已經由低溫熱處理而預結晶之 多晶梦薄膜上之方法。 第六圖係一示意圖，根據本發明之一具體實施例，臭 說明藉著如第一圖相同之方法，藉著施加一電場，在相同〜 CVD反應為中 >儿積非結晶矽薄膜且在其上連續沉積閘氧化 物薄膜，隨後熱處理該非結晶石夕薄膜之方法。 第七圖係一示意圖，根據本發明之一具體實施例，焉 說明藉著如第一圖相同之方法，藉著施加_電場，連續= • 積非結晶矽薄膜及閘氧化物薄膜，隨後熱處理一已經 溫熱處理而預結晶之多晶石夕薄膜之方法。 - 第八圖係一曲線圖，其說明範例1中，在施加一命η 於導電層期間，依照施加電場的時間，量測的能量密^^ 第九圖顯示（a)範例1樣本的照片，复 又 ^ w ^ 具為室溫下施加 %场於非結晶石夕薄膜之前，⑴藉著施加電場時的 熱所產生的高溫加熱，導致石夕薄膜發光之照片 =下施加一電場之後’樓轉換成多晶” 尸、?、/ΐ。 27 200811959 第十圖係一曲線圖，其說明範例1之多晶矽薄膜在退 火之後的拉曼分析結果。 第十一圖係一照片（放大率：X 60,000)，其顯示範例 1之多晶石夕薄膜在退火之後的亮視場TEM分析結果。 第十二圖顯示（a)範例2的樣本照片，其為室溫下施 加電場於非結晶矽薄膜之前，（b)藉著施加電場時的焦耳 加熱所產生的高溫加熱，導致矽薄膜發光之照片，及（Ο 在室溫下施加一電場之後，矽薄膜轉換成多晶矽薄膜之樣 - * * 本照片。 第十三圖係一照片（放大率：X 100,000)，其顯示範例 2之多晶矽薄膜在退火之後的暗視場TEM分析結果。 【主要元件符號說明】 10 基板 20 第一介電層 30 導電層 40 第二介電層 42 閘氧化物薄膜 44 閘極 50 非結晶矽薄膜 52 多晶矽薄膜 60 熱氧化物薄膜 70 連續沉積閘氧化物薄膜 28Or qing, Ping and 仏 in 1 second) can reach l_〇C: · degree 'so' by relying on oxygen, ozone or water vapor environment. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The first drawing is not a schematic view of the substrate construction according to the specific embodiment of the present invention for crystallization of amorphous crystalline films. =第图图, on the substrate 1〇, the first dielectric layer 2〇, the h layer 3〇, the second dielectric layer 40, and the amorphous a-Si film % are continuously formed, and 16 200811959 is applied by an electric field In the conductive layer 3 〇. There are no specific restrictions on the materials of the glass, and it is possible to use a transparent substrate material such as glass, and from the economical aspect, the glass: the car is wide. According to the field of flat panel display, the impedance is excellent. And processing capacity of the plastic base U. The method of the present invention can be directly applied to the seller of the (4) gum base. :3⁄4. Discharge to make H; the purpose of the layer 2G is to prevent the substrate ig from containing the substance =, , and the material may be produced in a subsequent process, for example, in the case of glass-based materials. Generally, the layer is formed by depositing oxygen (Si(6) or 真石石, and the freshness is preferably in the range of 2G00 to 5_A. The range is not limited. Based on the progress of the future technology, the amorphous shi shi is too wide to be required. The electric layer 2G can be directly formed on the substrate, and the method can be applied to the structure, and it should be understood that the present invention can be used to maintain the electric conductivity of the subsequent application. The thickness of the heating is caused by the heating of the 岣n^ZZ 3〇/thick knee 50 during the Joule heating process, and the insulating TFT is filled with the same material as that of the first dielectric layer 2 . The amorphous germanium film 50 can be formed by, for example, low pressure chemical vapor deposition, high pressure chemical vapor water enhanced chemical vapor deposition (PECVD), spray money, vacuum evaporation, or sold = 17 200811959, but preferably PECVD is used. The thickness of the film is preferably in the range of 300 to 1000 A, but is not limited thereto. The above configuration (ie, 10, 20, 30, 40, and 50) is applied before applying an electric field to the conductive layer 30. Or at least preheat the substrate 10 to a suitable temperature range The appropriate temperature range means that the substrate 10 is not damaged throughout the process, and the corresponding temperature range should preferably be lower than the heat distortion temperature of the substrate 10. The preheating method is not particularly limited and the following may be used. • · - * Method: For example, the stack is placed in a conventional heat treatment furnace and irradiated with radiant heat of a lamp or the like. The electric field application to the conductive layer 30 is performed by applying energy having a power density, which can generate sufficient energy. Strong heat to induce crystallization of the amorphous ruthenium film 50. Joule heating as described above. The energy value is determined by various factors such as the impedance of the conductive material and the length and thickness of the conductive layer 30, and thus cannot be listed. The applied current may be direct current or alternating current. The duration of the application of the electric field is from 1/1,000,000 seconds to 100 seconds, and preferably from 1/10000 second to 10 seconds, and more preferably in terms of continuous application time. Preferably, it is from 1 to 8 seconds to 1 second. An electric field can be repeatedly applied a plurality of times regularly or irregularly. Therefore, the total heat treatment time is longer than the above-described electric field application time. However, the heat treatment time is extremely short compared to the conventional crystallization method at least once. In some cases, a structure in which the conductive layer 30 and the amorphous ruthenium film 50 are exchanged with each other may be used. A specific embodiment, the schematic diagram 18 shown in the second figure, 200811959, illustrates the application of an electric field in the same manner as in the first figure, while simultaneously performing crystallization and activation of impurities. After deposition of the amorphous germanium film 50, it is completed by lithography. A patterning process for an individual TFT device is performed. A gate oxide film 42 is deposited thereon by a PECVD method, and then a gate electrode 44 is deposited by sputtering. To form the gate electrode 44, patterning is performed by lithography processing and etching processing. . Therefore, ion implantation is performed on the prepared self-aligned gate structure by doping with impurities to form a source and a drain, and then an electric field is applied by the same method as in the first figure, while naming* crystallizing and activating impurities. Since the indium tin oxide (IT〇) film 3〇 as a conductive layer is not electrically short-circuited, the above treatment is possible.乂 - As another embodiment of the present invention, the schematic diagram shown in the third figure illustrates the application of an electric field in the same manner as in the first drawing, while performing crystallization treatment and thermal oxidation. Since, according to the present invention, the temperature of the non-crystalline ruthenium film 50 is raised to at least 1 〇〇〇〇c or higher, it is possible to perform thermal oxidation treatment in an oxygen atmosphere. This treatment may be carried out in an ozone environment, a water vapor environment or even in deionized water, as appropriate, rather than in an oxygen environment. In general, during the production of a TFT device, a thermal oxide film having excellent characteristics cannot be used because of the thermal defects of the glass substrate 10, and a "splitting PECVD oxide film." However, according to the present invention, since the electric field is applied only for a short period of time, in an oxygen atmosphere, the production of the extremely thin thermal oxide film (9) is simultaneously performed in a repeating % plus private field: the deuteration is performed by the PECVD method. A relatively thick oxide film (not shown) is deposited thereon, and a TFT-generating process can be performed, and in this manner, the features of the Si/SiO 2 interface can be improved. 19 200811959 As another embodiment of the present invention, the method illustrated in the schematic diagram of the fourth embodiment applies an electric field in the same manner as in the first embodiment to heat-treat the pre-crystallized polycrystalline stone film which has been subjected to low-temperature heat treatment. In general, low temperature polycrystalline germanium films have one advantage in that the size of the crystal grains is larger than the grain size of the high temperature polycrystalline germanium, but it contains many crystal lattice defects such as twins in the crystal grains. According to the method of the present invention, since the high temperature treatment can be performed and the glass substrate 10 is not thermally deformed, an electric field is applied to heat-treat the polycrystalline germanium film 52 which has been precrystallized at a low temperature, by which the method can be produced. A large-sized polycrystalline germanium film that does not have a crystal lattice defect. As another specific embodiment of the present invention, the schematic diagram shown in the fifth diagram illustrates the method of applying an electric field in the same manner as in the first diagram in an oxygen, ozone or water vapor environment or deionized water. A thermal oxide film is formed on the polycrystalline germanium film which is pre-crystallized by heat treatment. The fifth figure illustrates that this treatment is substantially the same as that of a quartz substrate to produce a high temperature polycrystalline germanium film. In the case of this thermal oxidation treatment, since an oxygen atmosphere and a high temperature of 900 ° C or higher are required, it is impossible to use a glass substrate. In the case of the method of the present invention, since the high temperature is reached in a very short time, the thermal oxide film 60 can be formed without incurring thermal deformation of the glass substrate. However, the heating at the time of application of the electric field and the cooling at the time of removing the electric field are required to achieve thermal oxidation treatment. Since the thickness of the thermal oxide film 6〇 deposited by the method of the present invention is extremely small, an additional PECVD oxide film is added to form a gate oxide film (not shown). That is, the method of carrying out the invention can result in an improvement in the interface characteristics between the gate oxide film and the polycrystalline germanium film. Moreover, during the thermal oxidation process, a large number of crystal 200811959 lattice defects appearing in the low temperature polysilicon can be removed. Another embodiment of the invention is shown in the sixth figure. The schematic method shown in the sixth figure is to deposit amorphous (4) in the same CVD chamber: the second and the gate film 7〇' and then the same as the first figure. Method of application: heat treatment. In general, the advantage of the continuous deposition of the idle oxide film is that the interface characteristics are excellent, but it cannot be used for laser processing. Since the method of the present invention is non-laser processing, the formation of a continuous read deposition can be used to further improve the characteristics of the device and simplify the process. As another embodiment of the present invention, the schematic diagram shown in the seventh figure shows that the method of continuously depositing the amorphous quartz film 50 and the idle oxide film 70' is followed by applying an electric field in the same manner as in the first embodiment. The film 52 pre-crystallized by low-temperature heat treatment is subjected to heat treatment. By this method, a polycrystalline germanium film having a large-sized crystal grain and a defect of 1 and a gate oxide film having excellent interface characteristics can be obtained at the same time. • Joule heating used in the method of the present invention occurs in a conductive layer to which an electric field is applied, which is defined as heating by the heat generated by the impedance of a conductive material as it passes. The energy value per unit time when the Joule heating caused by the electric field applying force σ is applied to the conductive layer by the following formula: In the above formula, W is defined as the energy value of the unit time of the ear plus the remaining time, and V is defined For the voltage applied across the conductive layer, it is defined as a current. 21 200811959 It can be seen from the above formula that when the voltage (v) increases, and/or the current (I) increases, Joule heating is applied to the conductive The energy value per unit time of the layer is also increased. When Joule heating increases the temperature of the conductive layer, the amount of 敎^, , , is transmitted to the shi shi film disposed on the conductive layer and the slab disposed under the conductive layer (for example, Glass substrate. Therefore, a suitable voltage and current for a short time is applied to the sample by the method of the present invention, and heat conduction without causing thermal deformation of the glass substrate is utilized to raise the temperature of the ruthenium film to initiate crystallization and activate impurities. Temperature. If the applied energy value is sufficient, the processing can be completed via a single irradiation. If the numerical value is insufficient, the appropriate time interval is The crystallization treatment is completed by the secondary irradiation. As described above, according to the conventional MIC method, the MILC method, and other crystallization methods, there are cases where an electric field or a magnetic field is applied to promote vertical or lateral induction of a catalytic metal at a low temperature. In addition, the pattern is processed, and an electric field is applied in a very short time (about pSec): in a very small sample (for example, 25 〇 pm X 5 〇 Hm) to pass through the metal conductive film (Cr) disposed in the upper layer. The crystallization is achieved. However, in such cases, the following steps cannot be performed: by applying an electric field to the conductive layer disposed under the film of the heat treatment, more specifically, applying an electric field to cover the electric layer; The conductive layer provided under the film, and the conductive heat generated by the use of conductive enamel, ampere, and black ear heating, are crystallized in all areas of the substrate without patterning. Another factor comparing the present invention with such conventional methods is the electric field, the duration of use, the duration of the application of the electric field in the method of the present invention, and the duration of use. Preferably, it is 1/1 〇〇〇 to 1 second as described above. Section 22 200811959 The shorter time of crystallization allows crystallization and activation of impurities to be achieved in the upper layer of the ruthenium film, and although the conductive layer can be heated To a very high temperature, the substrate C of 々, rt ^, for example, a glass substrate, is not deformed. Examples; hereinafter, the present invention will be described in detail with reference to the accompanying drawings, which are not intended to limit the scope of the invention in any way. ^ [Example 1] Using a PECVD method, a layer having a thickness of 3_A is formed on a glass substrate having a width of 2 em, a length of 22 em, and a thickness of 〇7 _ (first, deposited by a squirt on a first dielectric layer having a surface) A thickness of the film (conductive layer), and then using the ship VD to deposit a layer of Si 〇 2 with a thickness of circle A (second dielectric layer) 10,000 CVD method has a phantom redundancy in the second dielectric layer s〇〇A thickness is not. Therefore, the stack of ruthenium films containing a non-crystalline Shih-hsien shown in the first figure was prepared. The impedance of the conductive layer was measured to be 2 〇 q. The electric field of '··ν_15Α was applied to the tortoise layer prepared in this manner at room temperature for 5 seconds, and the treatment was repeated five times in total. As a result, the electric field application totaled approximately 〇25 seconds. In a single-field application, the energy value applied to the electrical layer is Wat25 Watt/cm2. The eighth graph shows the waveform of the energy density measured based on the application time during which the electric field is applied to the conductive layer. In the ninth figure, (a) is a photograph showing a sample of amorphous (tetra) m at room temperature before the application of an electric field, (1) a photograph, a force of the ear: the ear caused by the high temperature (four) film : A photo of the sample of the film. According to the luminescence in (8) == the instantaneous temperature of the conductive layer rises to at least the higher H. The instant 埶 = conduction ^ is placed in the upper layer of the film and the eleventh picture of the non-crystal crystallization crystallization is not subjected to the heat treatment after the heat treatment of the ruthenium film. The tenth figure can be seen that the amorphous ruthenium film 4_ ground:: Polycrystalline state. · Fig. 11 shows the results of TEM analysis of the tantalum film after the heat treatment. In the eleventh diagram, the microstructure of the polysilicon film prepared according to the present invention has a structure of a polycrystalline dream film prepared at a high temperature. Change = t,, 'The crystal size of the crystal is smaller than the grain size of the low-temperature polycrystalline germanium film, and the morphology of the crystal grains is polygonal, and in the crystal grains, such as a crystal of a twin crystal = the number of defects is reduced of. It has been confirmed that although there is a heat of crystallization =, the glass substrate under the conductive layer is not deformed at all. [Example 2] Using a PECVD method, a Si〇2 layer (first dielectric layer) having a thickness of 3000 A was formed on a glass substrate having a width of 2 cm, a length of 2 cm, and a thickness of 〇·7 mm. A 15 Å thick indium tin oxide (ITO) film (conductive layer) is deposited on the dielectric layer, and then a layer of Si 〇 2 (second dielectric layer) having a thickness of 1 Å is deposited thereon by PECVD. . An amorphous ruthenium film having a thickness of 500 Å was deposited on the second dielectric layer using PECV^. Therefore, Nuo 200811959 has prepared the impedance system (4) of the conductive layer including the amorphous 矽.... The money is stacked. It is measured that the electric field of 3 〇〇 V_3 〇 A is applied for 〇._ sec., the process repeats the total ^I, and the conductive layer of the sample is applied to the unit of the conductive layer. In this electric field application, at the twelfth hour, the (a) system-day value is 3_gamma. Before, at room temperature, a sample of amorphous Shishi film: it: shows the application of electric field during the application of the three fields of 'Joule heating:: photo's film luminescence phenomenon, and (e) is followed by itt heat After the Shih JL and AQ were applied, the sample photo of the film of the (4) film was replaced by Han. According to the (4) color luminescence phenomenon in (1), it can be inferred that the instantaneous temperature of the scaly layer has risen to at least just (four) or higher. This strong heat is conducted to the upper cut film and induces crystallization of the amorphous stone. The thirteenth item shows the results of TEM analysis of the dark-rim of the film after the pro-degradation. In the eleventh diagram, the microstructure of the polycrystalline stone film prepared according to the present invention has a structure of a nano-sized polycrystalline germanium film. It is difficult to achieve the microstructure only by high-temperature solid phase crystallization in a tubular furnace or by RTA (rapid thermal annealing), and the present invention is first notified of the structure. In the method of the present invention, since the heating rate exceeds at least 1 〇〇〇〇 q 〇 C / sec, the microstructure formed at the enthalpy temperature is completely reflected. On the other hand, even if RTA utilizes the highest heating rate in the conventional heat treatment method, since the heat treatment rate is only about 10 ° C / sec, phase transition of polycrystalline germanium occurs during the heating process, and thus cannot be formed. The desired microstructure at high temperatures. The polysilicon produced in this example has crystal grains of a very small size and exhibits crystal grains of the shape of the axis of 2008. This structure is a microstructure that cannot be obtained in other heat treatment methods, and since the uniformity of the grain size is ensured, the structure is expected to be very suitable for OLED applications. It has been confirmed that despite the crystallization heat treatment, the glass substrate disposed under the conductive layer is not deformed at all. Industrial Applicability As described above, the annealing method according to the present invention provides a polycrystalline germanium film which does not have the problem of contamination caused by a catalytic metal present in a polycrystalline germanium film produced by a crystallization method such as MIC and MILC method, and is not accompanied at the same time. The surface protrusions appearing in the polycrystalline silicon film produced by the ELC method occur, and no thermal deformation of the glass substrate occurs, and the amount of crystal lattice defects is reduced. The fabrication techniques of polycrystalline germanium films constitute such features of the present invention, which are not disclosed in the prior art. Those skilled in the art of the present invention will be able to make various modifications and applications based on the above description. BRIEF DESCRIPTION OF THE DRAWINGS The first drawing is a schematic view showing the construction of a sample prepared by a polycrystalline silicon film according to an embodiment of the present invention. The second drawing is a schematic view showing a method of simultaneously performing crystallization of an amorphous germanium film and heat treatment of activated impurities after forming a source/drain and a gate, respectively, according to an embodiment of the present invention. The third figure is a schematic diagram illustrating the crystallization of a non-crystalline dream film by applying 26 200811959 琶琢π日守 in the same manner as in the first figure in an oxygen environment according to an embodiment of the present invention. Treatment and thermal oxidation treatment methods. The fourth drawing is a schematic view of a method of heat-treating a polycrystalline germanium film which has been pre-crystallized by low-temperature heat treatment by applying an electric field in accordance with an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a schematic view showing a specific embodiment of the present invention, which shows that in an oxygen environment, by the same method as in the first figure, a thermal oxidation film is formed by applying an electric field. A method of pre-crystallizing a polycrystalline dream film by low temperature heat treatment. Figure 6 is a schematic view showing, according to an embodiment of the present invention, a non-crystalline germanium film by the same method as in the first figure, by applying an electric field, in the same ~ CVD reaction as a > A method of continuously depositing a gate oxide film thereon, followed by heat treating the amorphous film. Figure 7 is a schematic view showing, according to an embodiment of the present invention, by applying the _ electric field, by continuously applying a non-crystalline ruthenium film and a gate oxide film, followed by heat treatment. A method of pre-crystallizing a polycrystalline stone film which has been subjected to a warm heat treatment. - Figure 8 is a graph illustrating the energy density measured according to the time of application of the electric field during the application of a lifetime to the conductive layer in Example 1. The ninth figure shows (a) the photo of the sample of sample 1. , and ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ The building is converted into polycrystalline "corpse, ?, / ΐ. 27 200811959 The tenth figure is a graph illustrating the results of Raman analysis of the polycrystalline silicon film of Example 1 after annealing. The eleventh picture is a photo (magnification: X 60,000), which shows the results of bright field TEM analysis of the polycrystalline film of Example 1 after annealing. Figure 12 shows a sample photograph of (a) Example 2, which is an amorphous field applied at room temperature. Before the film, (b) heating at a high temperature caused by Joule heating when an electric field is applied, resulting in a photograph of the luminescence of the ruthenium film, and (Ο after the application of an electric field at room temperature, the ruthenium film is converted into a polycrystalline ruthenium film - * * This photo. The thirteenth picture is a Sheet (magnification: X 100,000), which shows the dark field TEM analysis result of the polycrystalline silicon film of Example 2 after annealing. [Main component symbol description] 10 substrate 20 First dielectric layer 30 Conductive layer 40 Second dielectric layer 42 Gate oxide film 44 Gate 50 Amorphous germanium film 52 Polycrystalline germanium film 60 Thermal oxide film 70 Continuous deposition gate oxide film 28

Claims (1)

200811959 十、申請專利範圍： 1· 一種多晶矽薄膜，其製備係藉由在一透明基板上層積之 一第一介電層上形成一導電層，依序於其上形成一第二 介電層及一石夕薄膜，施加一電場於該導電層以誘發焦耳 加熱且藉此產生強熱，並利用如此方式產生之強熱對該 石夕薄膜進行熱處理，其中該多晶石夕薄膜之該微結構於一 TEM分析下係顯示一奈米尺寸多晶矽薄膜結構。200811959 X. Patent Application Range: 1. A polycrystalline germanium film prepared by forming a conductive layer on a first dielectric layer layered on a transparent substrate, sequentially forming a second dielectric layer thereon a stone film, applying an electric field to the conductive layer to induce Joule heating and thereby generating intense heat, and heat treating the stone film by the strong heat generated in such a manner, wherein the microstructure of the polycrystalline film is A TEM analysis shows a nanocrystalline polycrystalline germanium film structure. 2929
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