TWI362704B - Method for annealing silicon thin films using conductive layer and polycrystalline silicon thin films prepared therefrom - Google Patents

Method for annealing silicon thin films using conductive layer and polycrystalline silicon thin films prepared therefrom Download PDF

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TWI362704B
TWI362704B TW096141080A TW96141080A TWI362704B TW I362704 B TWI362704 B TW I362704B TW 096141080 A TW096141080 A TW 096141080A TW 96141080 A TW96141080 A TW 96141080A TW I362704 B TWI362704 B TW I362704B
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film
crystallization
conductive layer
polycrystalline
electric field
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TW200811959A (en
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Jae-Sang Ro
Won-Eui Hong
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Ensiltech Corp
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Description

1362704 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種退火矽薄膜之方法及用此方法製備 多晶矽薄膜，且更特定言之，本發明係關於一種退火矽薄 膜之方法，其包含：在矽薄膜下提供導電層；施加一電場 於該導電層以誘發焦耳加熱，產生強熱，·且進行矽薄膜之 結晶化、消除晶體晶格缺陷、活化雜質、熱氧化及類似步 驟；且藉此方法製備高品質之多晶矽薄膜。 . · / 【先前技術】 一般而言，非結晶矽（a-Si)具有諸如用於充電電池時 之弱電子遷移率、低孔徑比，及與CMOS處理之不相容性 的缺陷。另一方面，多晶矽（Poly-Si)薄膜裝置，是使影 像訊號輸入圖元所需的操作電路在一基板上形成，在圖元 TFT堆疊中完成該處理，而利用非結晶矽TFT (a-Si TFT) 則無法進行該處理。一多晶矽薄膜裝置不需在複數個終端 及一驅動器1C之間連接，因此該特徵可提昇生產率及可靠 性，且亦降低了面板之厚度。進一步而言，因為多晶矽TFT 處理可以直接利用矽LSI之微加工技術，所以以導線或類 似物來成形一微結構係可能的。因此，因為不存在該驅動 器1C之TAB安裝之間距的限制（而在一非結晶矽TFT中 該限制係明顯的），所以可以較輕易地達成圖元尺寸之減 少，且可以在較小之視角實施大量之圖元。與使用非結晶 矽之薄膜電晶體相比，在主動層使用多晶矽之薄膜電晶體 1362704 具有高轉換性能，且經過自我對準決定該主動層之通道位 置，因此使該裝置尺寸較小且可利用CMOS使其成形。因 該等原因，多晶矽薄膜電晶體可用作主動矩陣類型之平板 顯示器（例如，液晶顯示器及有機EL裝置）或類似物中 之圖元轉換元件，且當前，愈來愈多將其用作大螢幕顯示 器及具有内建式驅動器的COG (玻璃板上式晶片）產品之 應用的必需元件。 該等多晶矽TFT可以在高溫或低溫下製造。然而，在 高溫下製造該等TFT之情況下，需要諸如石英的昂貴材料 來製作基板，且因此不適用於大螢幕顯示器。因此，進行 積極的研究，尋找在低溫條件下利用非結晶矽薄膜來大規 模製造多晶矽之方法。 在低溫下形成多晶矽之該方法之範例包含固相結晶化 ((SPC)、金屬誘發之結晶化（MIC)、金屬誘發之側向結晶 化（MILC)、準分子雷射結晶化（ELC)及類似方法。 SPC方法之優勢在於：使用廉價設備獲取均質晶體結 構。然而，因為需要高結晶溫度及較長之處理時間，該方 法不利於使用諸如玻璃基板，其為具有相對較低之熱變形 溫度的基板，且生產率較低。根據SPC方法，僅當非結晶 矽薄膜一般在600至700°C經受約1至24小時之退火時， 可達成結晶化。進一步而言，在使用SPC方法製備多晶矽 之情況下，當發生非結晶相至結晶相的固態相轉移後，可 觀察到孿晶生長，且因此晶體晶粒具有大量晶體晶格缺 陷。該等因素導致了該等已產生的多晶矽TFT之電子及電 1362704 洞之遷移率減少，以及臨界電壓之增加。 MIC方法之優勢係使非結晶石夕與特定金屬接觸，使該 非結晶矽可以在遠低於該SPC方法之結晶溫度下結晶。可 用於該MIC方法之金屬之範例包含犯、Pd、Ti、A卜Ag、 Au、Co、Cu、Fe、Mn及類似物。該等金屬與非結晶矽反 應以形成共晶相或矽化物相，藉此促進低溫結晶。然而， 當該MIC方法應用於多晶矽TFT製造之實際處理時，在該 通道中很可邊存在金屬污染.。 MILC方法係MIC方法之調整，其並非將金屬沉積於 通運該法包含在通道上形成m然後使―薄金屬 層’儿積於自我準結構巾的源極及没極，以促進金屬誘發 之結晶化’且隨後誘發朝向該通道之侧向結晶化。在MILC 方法中最常使狀金屬係Ni及Pd。儘管與spc方法之產 2比’ MILC產生之多晶梦具有優良結晶度及高場效應遷 移率’但已通㈣MILC產物顯示高&漏電流特徵。因此， 方法相比，MILC方法減少了金屬污染之問題， 技有完全地解決該_。另-方面，另-可得之方 2作方之改良的場輔助侧向結晶化（爾）。與 化方向之久Π FALC方法顯示較高之結晶率且具有結晶 之理想解決^案性’但該方法仍然未能提供金屬污染問題 與SPC方法相比，因為降 mic、Milcafalc ^晶溫度’所以諸 共同之缺陷在於結晶化持；二有效的;然而’ 才间仍然幸父長，且結晶化係 1362704 金屬誘發。因此，其意味著該等方法並未完全擺脫金屬污 染問題。同時，新近開發出ELC方法，其可在一玻璃基板 上經由低溫處理來製備多晶矽薄膜，同時解決金屬污染問 .題。低壓化學氣相沉積（LPCVD)或電漿增強化學氣相沉 積（PECVD)所沉積的非結晶矽薄膜具有相對於紫外線區 域（λ =308 nm)的極大吸收係數，該紫外線區域對應於準 分子雷射之波長，因此可在合適的能量密度較輕易地發生 -非結晶矽薄膜之熔融。當以準分子雷射之方式使非結晶矽 • . - · 薄膜受結晶化時，亦伴隨著在極短時間内的熔融及凝固過 程。從此觀點看來，ELC方法意義上並非嚴格的低溫處理。 然而，ELC處理包含完成結晶化之程序，在受準分子雷射 顯-著影響之局部熔融區域中迅速發生之熔融及凝固處理期 間完成該結晶化程序，且因此有可能在一極短時間内（在 幾十毫微秒之内）產生多晶矽而不損害該基板。換言之， 當雷射光線非常短暫地照、射由玻璃基板/介電層/非結晶矽 薄膜組成之已成型堆疊之非結晶石夕時，僅選擇性地加熱該 非結晶矽薄膜，且完成結晶化而不損害安置於下層之玻璃 基板。同樣，在液相至固相之相轉移期間產生之多晶矽之 優勢係獲得一熱力學穩定晶粒結構，且與利用固相結晶化 產生之多晶矽相比，.該等晶粒中的晶體缺陷明顯減少。因 此，ELC方法產生之多晶矽優於該等其他結晶化方法之產 物。 然而，ELC方法具有若干嚴重缺陷，例如，雷射系統 之問題係雷射光束本身之照射劑量不均一；雷射處理之問 9 1362704 =獲==需之f射能量密度所能處理之區域極度 又，及大尺寸矽薄膜上遺留照射痕鄉之 導致組成多晶石夕TFT主動層之多晶石夕該專因素 則。另外，從液相轉移至固相之過程::尺寸不規 體積擴張’從形成日日日粒邊界之—简二^日日日發’歷經 重問題。該現象在後處理中對閘極介電層施：：突=嚴 使介電質崩潰電壓減少，且歸 W 17接影 之不楣目丨丨羊而庠"。去 夕日曰矽/閘極介電層介面 之不規則千面度:嚴重影響諸如熱 折车來，P鬥狄'山 .碼刀裒置之可靠性。 近年來6開發出一種連續側向凝固（SLS)之方法 以解決上述ELC方法稃定性之門哨 旦^ “〜問靖’且成功地用於雷射能 = ί = 之穩定化。然而’該方法仍然無法消除 知、射痕跡及表面大起之問題。由於當前平板顯示器工業快 速成長’將雷射祕lmx lm尺寸或更大尺寸之該等堆疊 之結晶化處理的技術需在不遠的將來用於大規模生產，但 該技術仍緋在卩顿。巾且，進賴Εΐχ方法及sls方法 之該等儀H非常$貴，g此需要較高之啟動及維護成本。 為解決先前技術之該等問題，本發明之發明人在κρ 2刪_37952中首錢議—方法，該種進行賴晶化之方法 係藉由在處理期間不使基板發生變形之溫度範圍内預熱石夕 薄膜’為產生固有載體，導致阻抗降低至可啟動焦耳加熱 之數值’隨後將一電場直接施加於預熱矽薄膜以利用載體 移動之方式誘發焦耳加熱v該方法係一創新方法，其著眼 於在一較短時間内於一相對較低之溫度下產生具有高品質 之多晶矽薄膜。 "j^7〇4 然而’仍需要一種在短時間 - 』円取好疋比室溫更低溫度 更右只轭於各種應用，且可以 有效地k成結晶化、活化雜質 體晶格缺陷之消除。 辑處理，及曰曰 對非結晶矽薄膜之方法有增加之 晶古：±· H /、中’雷射結 曰日化方法所具有之優勢在於因為 ^ 勹』在短時間内完成處理， /Γ以不扣害文置於下層之基板， 產咮容所μ 了 且在问舰·相轉移過程中可 雷具有缺陷之高品質晶粒'同時，克服了該等 陷，諸如歸因於處理區域之局部化的 規處理操作之限制，及所用設備之昂貴成 最^:、:：，右使用因為適用於下一代平板顯示器，而在 目之絲轉有機發光 流驅動模式中操作，反之，τ 職裝置在私 Λ, m t Ur-LCD在電壓驅動模式中操 4 ’晶粒尺寸之均—性係A尺寸基板的騎因素。 貫際上’當使用包含ELC或SLS (其利用雷射.）之低溫結 晶化方法時，平板顯示器工業將面臨限制。考慮到該等事 實，在非雷射模式中利用低溫結晶化生產高品質之多晶石夕 薄膜的新技術係受到極高期待的。 【發明内容】 [技術問題] 本發明希望同時解決上述先前技術問題及該相 關技術 中存在之該等技術問題。 具體言之，本發明之目的係提供一種方法，該方法係： 在形成於一透明基板一人恭 一介電層’然後在其切上連續形成—導電層及 該導電層，進而誘上夕㈣，且使―電場施加於 時間内反過來啟動強熱’㈣熱在極短 格缺陷之消除、晶體生2薄膜之結晶化、晶體晶 害該基板。同樣，4;提:化:質及類似現象’而不損 ，相之相轉移 發生，-且從彳t，相轉料固怨形式 之反應器中連續進行非相’藉此’务可能在相同 續沉積。意即，本取日日、Γ日日夕積及閘氧化物薄膜之連 中啟動結晶化的方i，供_種在非結晶破/閘氧化物結構 質的的係提供利用讀等上述方法獲得高品 [技術問題之解決] 、為達成料上述目的’本發明所建議之退火破薄膜之 方法包3之步驟係：在形成於—遷明基板上之一介電層 上連續^依次形成—導電層及—介電層；然後，在其上形 成一矽薄膜；施加一電場於該導電層上，進而誘發焦耳加 "、、以產生強熱，藉著傳導該強熱，熱處理該石夕薄膜。 以待結晶之非結晶麥薄膜、非結晶/多晶混合相石夕薄 膜、低溫多晶矽薄膜，或用於活化雜質之摻有雜質的多晶 矽薄膜作為該矽薄膜之範例。 根據本發明，藉由施加一電場於安置於矽薄膜層下的 12 1362704 導電層，在相對較短之時間内產生強熱，且主要經由傳導 將強熱傳送至矽薄膜，且實施非結晶矽結晶化、消除晶體 缺陷、活化雜質、熱氧化及類似步驟。即使已產生啟動矽 薄膜熱處理之強熱，下層之基板亦不經受熱變形。因為與 基板相比，具有相對極小厚度之矽薄膜之總熱量係極小， 且因此，熱傳導導致的溫度提昇之增量顯著高於基板之溫 度增量。 .該結果與，ELC方法之結晶化處理具有相似樣態，該 • · · · · • ELC方法係一種產生高品質多晶矽薄膜之雷射結晶化方 法，該相似之樣態係：該處理係在短時間内於高溫下完成 的。然而，本發明所述均係迄今為止尚未通報的新方法， 二方法係：在下部的介電層之間引入一導電層，且在上部 引入一矽薄膜.，且施加一電場於該導電層，經由類似雷射 結晶化方法之結晶化處理，在該堆疊之全部範圍内進行非 結晶矽薄膜及非結晶/多晶矽薄膜結晶化之方法；另一方法 φ 係：在該堆疊之全部區域進行熱處理，達成多晶矽薄膜中 晶體晶格缺陷之消除及晶粒之生長。 在根據本發明熱處理摻有雜質的矽薄膜之情況下，本 文使用之矽薄膜可以係摻有雜質的非結晶矽薄膜、摻有雜 質的非結晶/多晶混合相矽薄膜或摻有雜質的多晶矽薄膜。 根據本發明，該導電層最好為銦錫氧化物（ITO)薄膜、 各種類型的透明導電薄膜，或金屬薄膜，且其更好為銦錫 氧化物（ITO)薄膜。因為銦錫氧化物（ITO)薄膜係導電 透明薄膜，其特別適用於顯示裝置。 13 1362704 •在施加1場於導電層之前，視情 使該基板發生變形之程度。 ·，、'至不 …本發明亦提供利用上述退火方法結晶之高品質多 ㈣，或具有㈣相同方法啟動的摻有雜質之多晶^ 膜。當利用局部結晶化處理所使用之雷射結晶化方 發生該等上”題，而本發明之方法在安置於施加 導電層上的_之全部區域範圍内同時進行結晶化處理 因此可迅速結晶及啟動且提供高品f之多晶石夕薄膜。 與習知技術相比，本發明之退火方法及由此獲得之夕 晶石夕薄膜具有如下特徵或優勢。 夕 首先’實施結晶化之該處理非常簡易且具有經濟户 勢。作為最新技術之一的ELC方法藉由直線光束之重複掃 描來進行該處理’且SLS方法利用照射通過圖案化遮罩之 雷射，隨後利用在極短距離内精確移動之雷射光束重複掃 描，來進行該處理。因此’該堆疊全部區域之雷射光束強 度非均一性係不可避免的。然而’本發明之方法可在極短 時間内，於堆疊全部區域内進行非結晶矽薄膜、非結晶/多 晶混合相薄膜或多晶發薄膜之結晶化及缺陷消除，且基板 無任何變形。而且，ELC方法需要額外之脫氫退火處理， 以從非結晶矽薄膜中移除氫，該步驟係雷射照射之預備步 驟，所以ELC方法比本發明之方法更複雜。 第二，實施本發明之處理設備係廉價的，且可利用在 此項技術中已確立之技術。提供優良結晶效應之ELC方法 及類似方法，使用包含雷射裝置的昂貴設備。另一方面， 14 1362704 因為在半導體及平板顯示器工業中已較佳地衫進行本發 =之方法所需之設備，所以可直接應用該等習知技術或該 4習知技術之修正來進行本發明之方法。 - ΐ本發月之方法適用於大規模生產具有均一性及 兩品貝之多晶”膜。根據本發明，在低溫及短時間内可 進行堆疊全部區域範圍內夕彡士 s _ 心^ X靶固円之結晶化，因此本發明之方法有 利於處理大面積之基板。女丨E L .+· 士， 切、 利用上述方法獲得之多晶矽薄膜1362704 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method for annealing a tantalum film and a method for preparing a polycrystalline germanium film, and more particularly, to a method for annealing a tantalum film, comprising Providing a conductive layer under the germanium film; applying an electric field to the conductive layer to induce Joule heating, generating intense heat, and performing crystallization of the germanium film, eliminating crystal lattice defects, activating impurities, thermal oxidation, and the like; A high quality polycrystalline germanium film is prepared by this method. • [Prior Art] In general, amorphous yttrium (a-Si) has defects such as weak electron mobility for a rechargeable battery, a low aperture ratio, and incompatibility with CMOS processing. On the other hand, a poly-Si film device is formed by forming an operation circuit required for inputting an image signal into a picture element on a substrate, and performing the process in the TFT stack of the picture element, and using an amorphous 矽 TFT (a- This process cannot be performed with Si TFT). A polysilicon film device does not need to be connected between a plurality of terminals and a driver 1C, so this feature can improve productivity and reliability, and also reduce the thickness of the panel. Further, since the polysilicon TFT processing can directly utilize the micromachining technology of 矽LSI, it is possible to form a microstructure by wires or the like. Therefore, since there is no limitation in the distance between the TAB mounting of the driver 1C (and the limitation is obvious in an amorphous 矽 TFT), the reduction in the size of the primitive can be achieved relatively easily, and the viewing angle can be small. Implement a large number of primitives. Compared with the thin film transistor using amorphous germanium, the thin film transistor 1362704 using polycrystalline germanium in the active layer has high conversion performance, and self-alignment determines the channel position of the active layer, thus making the device small in size and available. CMOS makes it shape. For these reasons, a polycrystalline germanium film transistor can be used as a pixel conversion element in an active matrix type flat panel display (for example, a liquid crystal display and an organic EL device) or the like, and currently, it is increasingly used as a large Required components for screen displays and COG (glass on-wafer) products with built-in drivers. The polycrystalline germanium TFTs can be fabricated at high or low temperatures. However, in the case of manufacturing such TFTs at high temperatures, expensive materials such as quartz are required to fabricate substrates, and thus are not suitable for large screen displays. Therefore, active research has been conducted to find a method for large-scale fabrication of polycrystalline germanium by using an amorphous germanium film under low temperature conditions. Examples of the method for forming polycrystalline germanium at low temperatures include solid phase crystallization (SPC), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and excimer laser crystallization (ELC). A similar approach. The advantage of the SPC method is that it uses a cheap device to obtain a homogeneous crystal structure. However, because of the high crystallization temperature and long processing time, this method is not conducive to the use of a glass substrate, which has a relatively low heat distortion temperature. Substrate, and low productivity. According to the SPC method, crystallization can be achieved only when the amorphous ruthenium film is subjected to annealing at 600 to 700 ° C for about 1 to 24 hours. Further, polycrystalline ruthenium is prepared by the SPC method. In the case where the solid phase transfer of the amorphous phase to the crystalline phase occurs, twin growth can be observed, and thus the crystal grains have a large number of crystal lattice defects. These factors cause the polycrystalline germanium TFTs which have been produced. Electron and electricity 1362704 hole mobility reduction, and the increase of the threshold voltage. The advantage of the MIC method is to make the amorphous stone contact with a specific metal, so that the non-knot The ruthenium can be crystallized at a temperature far below the crystallization temperature of the SPC method. Examples of metals that can be used in the MIC method include pirates, Pd, Ti, A, Ag, Au, Co, Cu, Fe, Mn, and the like. The metal reacts with the amorphous ruthenium to form a eutectic phase or a ruthenium phase, thereby promoting low temperature crystallization. However, when the MIC method is applied to the actual processing of polycrystalline germanium TFT fabrication, metal contamination is likely to be present in the channel. The MILC method is an adjustment of the MIC method, which does not deposit metal in the transport method. The method comprises forming m on the channel and then causing the "thin metal layer" to accumulate in the source and the immersion of the self-aligned structure to promote metal induced crystallization. And then induced lateral crystallization towards the channel. The most commonly used metal systems are Ni and Pd in the MILC method. Despite the fact that it is superior to the spc method, the polycrystalline dream produced by MILC has excellent crystallinity and high field. The effect mobility 'but has passed (iv) the MILC product shows high & leakage current characteristics. Therefore, compared to the method, the MILC method reduces the problem of metal contamination, and the technology completely solves the problem. Another-side, another-available 2 improvement Field-assisted lateral crystallization (I). Long-term crystallization with the direction of the FALC method shows a higher crystallization rate and has the ideal solution of crystallization. However, this method still fails to provide metal contamination problems compared with the SPC method. Because of the reduction of mic, Milcafalc ^ crystal temperature 'the common defects are crystallization; two effective; however, 'there is still a good father, and the crystallization system is 1362704 metal induced. Therefore, it means these methods and Not completely rid of the metal pollution problem. At the same time, the ELC method has been newly developed, which can prepare polycrystalline germanium film by low temperature treatment on a glass substrate, and solve the problem of metal contamination. Low pressure chemical vapor deposition (LPCVD) or plasma enhanced The amorphous ruthenium film deposited by chemical vapor deposition (PECVD) has a maximum absorption coefficient relative to the ultraviolet region (λ = 308 nm), which corresponds to the wavelength of the excimer laser, and thus can be compared at a suitable energy density. Easily occurs - melting of the amorphous ruthenium film. When the amorphous 矽···· film is crystallized by excimer laser, it is accompanied by melting and solidification in a very short time. From this point of view, the ELC method is not strictly low temperature treatment. However, the ELC process includes a procedure for completing the crystallization, which is completed during the rapid melting and solidification process in the localized melting region where the excimer laser is significantly affected, and thus it is possible to perform the crystallization process in a very short time. Polycrystalline germanium is produced (within tens of nanoseconds) without damaging the substrate. In other words, when the laser beam is irradiated for a very short period of time, and the amorphous layer of the formed stack composed of the glass substrate/dielectric layer/amorphous germanium film is irradiated, only the amorphous germanium film is selectively heated, and crystallization is completed. Without damaging the glass substrate placed in the lower layer. Similarly, the advantage of polycrystalline germanium produced during the phase transition from liquid phase to solid phase is to obtain a thermodynamically stable grain structure, and the crystal defects in the grains are significantly reduced compared to the polycrystalline germanium produced by solid phase crystallization. . Therefore, the polycrystalline germanium produced by the ELC method is superior to the products of these other crystallization methods. However, the ELC method has several serious drawbacks. For example, the problem of the laser system is that the irradiation dose of the laser beam itself is not uniform; the laser processing is 9 1362704 = the area of the laser energy density that can be processed is required Moreover, the polycrystalline stone that constitutes the polycrystalline slab TFT active layer is left behind on the large-sized ruthenium film. In addition, the process of transferring from the liquid phase to the solid phase:: size irregularity volume expansion 'from the formation of the daily grain boundary - the simple day ^ day hair issue" has experienced serious problems. This phenomenon applies to the gate dielectric layer in the post-processing:: = = the dielectric breakdown voltage is reduced, and the W 17 is inconspicuous. Irregularity of the interface of the 介 曰矽 / gate dielectric layer: seriously affects the reliability of the car, such as the hot folding car. In recent years, 6 a method of continuous lateral solidification (SLS) has been developed to solve the above-mentioned ELC method's deterministic singularity "~Qing Jing" and successfully used for the stabilization of laser energy = ί =. However, The method still can't eliminate the problems of knowing, shooting traces and surface rise. Due to the rapid growth of the current flat panel display industry, the technology of crystallization of such stacks of laser lmx lm size or larger needs to be in the near future. It is used in large-scale production, but the technology is still in the process of being used. It is very expensive to use the method and the sls method, which requires high startup and maintenance costs. These problems are the first method of the inventors of the present invention in the method of crystallization, which is to preheat the film by a temperature range in which the substrate is not deformed during the treatment. 'In order to generate an intrinsic carrier, causing the impedance to decrease to a value that can initiate Joule heating' then an electric field is applied directly to the preheated tantalum film to induce Joule heating by means of carrier movement. This method is an innovative method. Focus on producing a high quality polysilicon film at a relatively low temperature in a short period of time. "j^7〇4 However, 'still need a short time - 』 疋 better than room temperature The temperature is more yoke to various applications, and can effectively k-crystallize and aggravate the elimination of lattice defects of the impurity body. The treatment and the method of 曰曰 on the amorphous ruthenium film have increased crystal: ±· H / In the middle of the 'laser crusting method, the advantage is that ^ 勹 』 is completed in a short time, / Γ 不 不 不 不 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于 置于In the phase transfer process, the high-quality crystal grains having defects are eliminated. At the same time, the depressions are overcome, such as the limitation of the processing operation due to the localization of the processing region, and the cost of the equipment used is the most::,: The right use is suitable for the next-generation flat panel display, but it operates in the wire-to-organic light-emitting flow drive mode. Conversely, the τ device is in private mode, and the mt Ur-LCD operates in the voltage-driven mode. The riding factor of the uniform-size A-size substrate "The flat panel display industry will face limitations when using low temperature crystallization methods that include ELC or SLS (which utilizes lasers.). Taking into account these facts, low temperature crystallization is used in non-laser modes. [Technical Problem] The present invention is intended to solve the above-mentioned prior art problems and the technical problems existing in the related art at the same time. The object of the present invention is to provide a method for: forming a dielectric layer on a transparent substrate and then continuously forming a conductive layer and a conductive layer on the cut surface thereof, thereby enticing the eve (four), and making the electric field The application of the strong heat in the time period is reversed. (4) The heat is eliminated in the extremely short lattice defect, the crystal is crystallized, and the crystal is crystallized. Similarly, 4; mention: chemical: quality and similar phenomena 'do not damage, the phase shift occurs, and from the 彳t, the phase-converted form of the reactor in the continuous non-phase 'by this' may be The same continuous deposition. In other words, the method of starting crystallization in the connection of the day and the day of the day and the gate oxide film is provided for the system of the non-crystalline/gate oxide structure to be obtained by reading the above method. [Technical Problem Solving], in order to achieve the above object, the method of the method for annealing the broken film proposed by the present invention is as follows: forming a conductive layer on a dielectric layer formed on the substrate a layer and a dielectric layer; then, forming a thin film thereon; applying an electric field to the conductive layer, thereby inducing Joule plus, to generate strong heat, by conducting the strong heat, heat treating the stone film. A non-crystalline wheat film to be crystallized, an amorphous/polycrystalline mixed phase stone film, a low temperature polycrystalline film, or an impurity-doped polycrystalline germanium film for activating impurities is used as an example of the tantalum film. According to the present invention, by applying an electric field to the 12 1362704 conductive layer disposed under the ruthenium film layer, strong heat is generated in a relatively short period of time, and strong heat is mainly transmitted to the ruthenium film via conduction, and amorphous 实施 is performed. Crystallization, elimination of crystal defects, activation of impurities, thermal oxidation, and the like. Even if the strong heat of the heat treatment of the starting film is generated, the substrate of the lower layer is not subjected to thermal deformation. Since the total heat of the tantalum film having a relatively small thickness is extremely small compared to the substrate, and therefore, the increase in temperature rise due to heat conduction is significantly higher than the temperature increase of the substrate. This result is similar to the crystallization process of the ELC method, which is a laser crystallization method for producing a high-quality polycrystalline ruthenium film, the similar pattern is: Completed at high temperatures in a short time. However, the present invention is a new method that has not been reported so far. The second method is: introducing a conductive layer between the lower dielectric layers, and introducing a thin film on the upper portion, and applying an electric field to the conductive layer. a method of crystallization of an amorphous ruthenium film and an amorphous/polycrystalline ruthenium film in the entire range of the stack by a crystallization treatment similar to a laser crystallization method; another method φ: heat treatment in all regions of the stack The elimination of crystal lattice defects and the growth of crystal grains in the polycrystalline germanium film are achieved. In the case of heat-treating a ruthenium film doped with impurities according to the present invention, the ruthenium film used herein may be an amorphous ruthenium film doped with impurities, an amorphous/polycrystalline mixed phase ruthenium film doped with impurities or a polycrystalline ruthenium doped with impurities. film. According to the present invention, the conductive layer is preferably an indium tin oxide (ITO) film, various types of transparent conductive films, or a metal film, and more preferably an indium tin oxide (ITO) film. Since the indium tin oxide (ITO) film is a conductive transparent film, it is particularly suitable for use in a display device. 13 1362704 • The extent to which the substrate is deformed as appropriate before applying a field to the conductive layer. ·, 'To none... The present invention also provides a high quality multi-crystal (4) which is crystallized by the above annealing method, or an impurity-doped polycrystalline film which is activated by the same method. When the laser crystallization used in the local crystallization treatment occurs, the method of the present invention simultaneously performs crystallization treatment in the entire region of _ disposed on the applied conductive layer, thereby rapidly crystallizing and The polycrystalline film of the high-quality product is started and provided. Compared with the prior art, the annealing method of the present invention and the oligocrystalline film obtained thereby have the following characteristics or advantages. Very simple and economical. The ELC method, one of the latest technologies, performs this process by repeated scanning of a straight beam' and the SLS method uses illumination to illuminate the laser through the patterned mask, which is then used to be accurate over very short distances. The moving laser beam is repeatedly scanned for this processing. Therefore, the non-uniformity of the intensity of the laser beam in the entire area of the stack is unavoidable. However, the method of the present invention can be carried out in all areas of the stack in a very short time. The crystallization and defect elimination of the amorphous ruthenium film, the amorphous/polycrystalline mixed phase film or the polycrystalline film are performed, and the substrate is free from any deformation. The ELC method requires an additional dehydrogenation annealing treatment to remove hydrogen from the amorphous ruthenium film, which is a preliminary step of laser irradiation, so the ELC method is more complicated than the method of the present invention. Processing equipment is inexpensive and can utilize the techniques established in the art. ELC methods and similar methods that provide excellent crystallization effects, using expensive equipment including laser devices. On the other hand, 14 1362704 in semiconductors and flat panels In the display industry, it is preferred to have the device required for the method of the present invention, so that the method of the present invention can be directly applied by using the prior art or the modification of the conventional technique. It is suitable for mass production of polycrystalline film with uniformity and two products. According to the present invention, crystallization of the 彡 _ _ X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Nuwa E L.+· Shi, cut, polycrystalline germanium film obtained by the above method

k供尚品質且無表面突起之結晶化產物。 第四，本發明之方法可用於低溫活化雜質處理。本發 月之方法可有效制於結晶化，亦可有效應驗低溫下的 TFT結構巾之雜/汲極電_近_子植人的活化雜質之 熱處理。 ...1 、 第五本發明之方法可以類似於非結晶石夕tft生產處 理方式連續沉積閘氧化物薄膜。在M〇SFET結構之丁ft 中’閘氧化物薄膜之薄膜品質及矽/閘氧化物薄膜介面在 TFT裝置之該等電學特性中扮演極其重要的角色。在非结 晶TFT生產處理中，使用PECVD方法在相同腔室中連續 沉積非結晶矽及閘氧化物薄膜，因此矽/閘氧化物薄膜介^ 之該等特性係優良的。相反，在LTPS生產處理之情況下， 因為田鈉用於大規模生產之結晶化技術係雷射處理，所以 7用PECVD $法進行非結晶石夕之沉積及在熱處理爐中脫 氫之後進行雷射結晶化。根據PECVD方法，閘氧化物薄膜 沉積於利用雷射而結晶的多晶矽薄膜上。換言之，用於非 結晶矽TFT生產處理之連續沉積係不可能的。然而，因為 15 1362704 本發明之結晶化技術係非雷射處理’則連縯〉儿積係可能的。 第六，高溫多晶矽處理町在低溫下實施。在使用石英.. 作為透明基板之高溫多晶矽處理的情況下，利用延長時間 之600。(：或更低溫度之熱處理，製備具有相對較大晶粒尺 寸（但不具有諸如孿晶之諸多晶體晶格缺陷）之低溫多晶 矽薄膜，隨後沉積閘氧化物薄族。在低溫多晶矽處理之情 況下，因為玻璃基板之溫度限制，所以利用peCVD方法沉 積氧化物薄膜，而在高溫多晶矽處理之情況下’不存在基 •- . .. 板溫度之限制，因此利用熱氧化處理。當在900。(：或更高 · 之溫度使用熱氧化處理時，可產生具有優良薄膜紋理之閘 氧化物膜，且亦可在熱氧化處理期間消除安置於閘氧化物 薄膜之下的低溫多晶石夕膜中存在的該等晶體晶格缺陷。根 據本發明，因為瞬間（較佳係在1秒内）即可達到l〇〇〇°C 或更高之溫度’所以，藉由在氧、臭氧或水蒸汽環境下重 複施加電場，在一易於受熱之玻璃基板上實施熱氧化處理 係可能的。 【實施方式】 下文中’將參照圖式詳細描述本發明之具體實施例， 然而’該等具體實施例不限定本發明之範疇。 第一圖所示係根據用於非結晶矽薄膜結晶化之本發明 之一具體實施例的基板構造之示意圖。 根據第一圖，在基板i0上，連續形成第一介電層2〇、 導電層30、第二介電層4〇及非結晶矽（a-Si)薄膜50，且 16 1362704 一電場施加於該導電層3〇。 基板10之材料並無特定之限制，且 璃、石英及塑膠的透明㈣㈣P 使用省如玻 传m月基板材枓，而從經濟樣態而言破璃 2^ '"據平板顯示器領域近期之研究趨勢，研 有優良作用的阻抗及處理能力的塑勝基 ^基板上。树明之方法可聽應用於該㈣膠基礎之 —山^用帛"包層20之目的係防止基板10包含物質之 該等物質可能在隨後之處理中產生，例如於破;: ^情況下的驗性物質一般利用沉積氧切⑽2) ^ 石夕來形成該層，且該厚度較㈣在鳩至5_ 内，但不限定此範圍。基於將來技術之進步，非处曰^ 電層2〇便可直接形成於基板上I為 該、^構。 用於該結構，應瞭解本發明之範_包含 —導電層30係電傳導材料之薄層，且使用諸如 工續或類似方法可形成該層。導電層3G需維持均〜” =使Ik後施加之電場導致的焦耳加熱處理期間‘厚度 勻。 <力口熱岣 第二介電層4Q之作用係防止社處理㈣ 与結晶石夕薄膜5〇之污染，且絕緣TFT裂置 与3〇 之材料可與第—介電層2G所用之材料相同。 '該層 利用例如低壓化學氣相沉積、高壓化學氣相 水增強化學氣相沉積（PECVD)、喷激、真空 『、電 畈或類似方 1362704 法，可形成非結晶矽薄膜50，但較佳地是使用PECVD方 法。薄膜的厚度最好在300至1000 A之範圍内，但不限在 此範圍。 在施加一電場於導電層30之前，將該等上述構造（意 即10、20、30、40及50)或至少將基板10預熱至一適當 之溫度範圍。該適當之溫度範圍意味在整個處理中基板10 不受到損害，且對應之溫度範圍應最好是低於基板10之熱 變形溫度。該預熱方法並無特定限制，且可使用如下之方 . . . · 法：例如，將堆疊置於普通熱處理爐且使用燈或類似物之 輻射熱進行照射。 藉由施加具有功率密度之能量來進行對於導電層30 之電場應用，該能量可產生足夠之強熱以誘發非結晶矽薄 膜50之結晶化.，如上文所述之焦耳加熱。藉由諸如導電材 料之阻抗，及導電層30之長度及厚度的各種因素來決定該 能量數值，因此無法列出。施加之電流可以係直流電或交 流電。以連續應用之時間計*該電場應用之持績時間係 1/1,000,000秒至100秒，且最好是從1/10000秒至10秒， 且更好是從1/1000秒至1秒。可規律地或不規律地多次重 複施加一電場。因此，該總計之熱處理時間長於上述電場 施加時間，但與習知結晶方法至少一次之處理時間相比， 該熱處理時間係極短的。 在一些情況下，亦可使用導電層30與非結晶矽薄膜 50互相交換位置的結構。 作為本發明之另一具體實施例，第二圖所示之示意圖 1362704k is a crystallization product of good quality and no surface protrusions. Fourth, the method of the present invention can be used for low temperature activation impurity treatment. The method of the present month can be effectively used for crystallization, and can also be used for the heat treatment of the activated structure impurities of the TFT structure towel at a low temperature. The method of the fifth invention can continuously deposit a gate oxide film similar to the amorphous X-ray production process. The film quality of the gate oxide film and the germanium/gate oxide film interface play an extremely important role in the electrical characteristics of the TFT device in the M 〇 SFET structure. In the non-crystalline TFT production process, the amorphous ruthenium and the gate oxide film are successively deposited in the same chamber by the PECVD method, and thus the characteristics of the ruthenium/gate oxide film are excellent. On the contrary, in the case of LTPS production processing, because the sodium crystallization technology used for large-scale production is laser treatment, 7 the PECVD $ method is used for the deposition of amorphous shi shi and after dehydrogenation in the heat treatment furnace. Crystallization. According to the PECVD method, a gate oxide film is deposited on a polycrystalline germanium film which is crystallized by laser. In other words, continuous deposition for the production process of amorphous 矽 TFT is not possible. However, since 15 1362704 the crystallization technique of the present invention is non-laser processing, it is possible to carry out a series of experiments. Sixth, the high-temperature polysilicon processing town is implemented at a low temperature. In the case of using quartz: high temperature polysilicon as a transparent substrate, an extension time of 600 is utilized. (: or heat treatment at a lower temperature to prepare a low-temperature polycrystalline germanium film having a relatively large grain size (but without many crystal lattice defects such as twins), followed by deposition of a gate oxide thin family. In the case of low temperature polysilicon treatment Next, because of the temperature limitation of the glass substrate, the oxide film is deposited by the peCVD method, and in the case of the high temperature polysilicon treatment, there is no limitation of the substrate temperature, and therefore the thermal oxidation treatment is used. When the temperature of (: or higher) is treated by thermal oxidation, a gate oxide film having an excellent film texture can be produced, and the low temperature polycrystalline film disposed under the gate oxide film can also be eliminated during the thermal oxidation treatment. The crystal lattice defects present in the crystal. According to the present invention, since the temperature is preferably 10 ° C or higher in an instant (preferably within 1 second), by using oxygen, ozone or water It is possible to repeatedly apply an electric field in a steam environment and perform a thermal oxidation treatment on a glass substrate which is easily heated. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the drawings. The specific embodiments, however, are not intended to limit the scope of the invention. The first figure is a schematic diagram of a substrate construction according to one embodiment of the invention for crystallization of amorphous ruthenium film. In one figure, a first dielectric layer 2, a conductive layer 30, a second dielectric layer 4, and an amorphous germanium (a-Si) film 50 are continuously formed on the substrate i0, and an electric field is applied to the conductive layer 16 1362704. Layer 3 〇. The material of the substrate 10 is not particularly limited, and the transparent (4) (4) P of the glass, quartz and plastic is used as a glass-transparent m-based sheet, and the glass is broken from the economical state. Recent research trends in the field of display, research on the excellent impedance and processing ability of the plastic substrate. The method of the tree is audible for the application of the (four) glue foundation - the use of the cladding layer 20 to prevent the substrate 10 The substance containing the substance may be produced in a subsequent treatment, for example, in the case of breaking;: In the case of ^, the test substance is generally formed by depositing oxygen (10) 2) ^ Shi Xi to form the layer, and the thickness is higher than (4) Within 5_, but not limited to this range. In the future advancement of technology, the electrical layer 2 can be directly formed on the substrate. I is the structure. For this structure, it should be understood that the invention includes the conductive layer 30 being an electrically conductive material. Thin layer, and the layer can be formed by using, for example, a process or the like. The conductive layer 3G needs to maintain a uniform thickness of "the thickness of the Joule heating process caused by the electric field applied after Ik. The function of the electric layer 4Q is to prevent the contamination of the film (4) and the crystallized film, and the material of the insulating TFT is 3 R can be the same as that of the first dielectric layer 2G. 'This layer utilizes, for example, low pressure chemistry. The amorphous ruthenium film 50 can be formed by vapor deposition, high pressure chemical vapor phase enhanced chemical vapor deposition (PECVD), spray, vacuum, electrophoresis or the like, 1362704, but preferably using a PECVD method. The thickness of the film is preferably in the range of 300 to 1000 A, but is not limited thereto. The above structures (i.e., 10, 20, 30, 40, and 50) or at least the substrate 10 are preheated to a suitable temperature range before an electric field is applied to the conductive layer 30. This suitable temperature range means that the substrate 10 is not damaged throughout the process, and the corresponding temperature range should preferably be lower than the heat distortion temperature of the substrate 10. The preheating method is not particularly limited, and the following may be used. . . . Method: For example, the stack is placed in a general heat treatment furnace and irradiated with radiant heat of a lamp or the like. The application of an electric field to the conductive layer 30 is performed by applying energy having a power density which generates sufficient intense heat to induce crystallization of the amorphous thin film 50. Joule heating as described above. The energy value is determined by various factors such as the impedance of the conductive material and the length and thickness of the conductive layer 30, and thus cannot be listed. The applied current can be either direct current or alternating current. The duration of the application of the electric field application is from 1/1,000,000 seconds to 100 seconds, and preferably from 1/10000 second to 10 seconds, and more preferably from 1/1000 second to 1 second. An electric field can be repeatedly applied a plurality of times regularly or irregularly. Therefore, the total heat treatment time is longer than the above-described electric field application time, but the heat treatment time is extremely short compared to the conventional crystallization method at least once. In some cases, a structure in which the conductive layer 30 and the amorphous germanium film 50 are exchanged with each other may also be used. As another embodiment of the present invention, the schematic diagram shown in the second figure 1362704

說明利用第一圖之湘同方法施加一電場，同時進行結晶化 及活化雜質之處理。繼沉積非結晶矽薄膜50之後，經由微 影處理完成了關於個別TFT裝置之圖案化處理。利用 PECVD方法在其上沉積閘氧化物薄膜42,隨後利用喷機而 沉積閘極44。為形成該閘極44，利用微影處理及蝕刻處理 執行圖案化。因此利用摻有雜質對已製備之自我對準閘結 構實施離子植入，以形成源極及汲極，隨後利用第一圖相 同之方法施加一電場，同時進行結晶化及活化雜質。因為 作為導電層之銦錫氧化物（ΓΓΟ)薄膜3〇並非電性短 所以上述處理係可能的。 、 作為本發明之另一具體實施例，第三圖所示之示意圖 說明使用第一圖相同之方法施加一電場’同時進行結=化 處理及熱氧化。因為根據本發明…旦進行焦耳加熱，非 結晶石夕薄膜50之溫度將提昇至至少1〇〇〇〇c或更高，所以 在氧氣環境下的減化處縣可能的。視情況，^在臭氧 環境或水該環境或甚至在絲子水巾進行料理，=非 在氧氣環境中。-般而言，在TFT裝置生產期間，因為玻 璃基板10之熱缺陷而無法使用具有優良雜之熱氧化物 薄膜，且沉積PECVD氧化物薄膜。然:而，根據本發明，因 為電場僅施加於較短時間，㈣，於氧氣環境下，以重複 施加電場之方式同時進行極薄熱氧化物薄膜60之產生斑 結晶化。利用押㈣方法在其上沉積相.對較厚之氧化物薄 膜（未圖示）‘.，可實施TFT產生之處理，且以此方式可改 良Si/Si〇2介面之該等特徵。 19 1362704 作為本發明之另一具體實施例，第四圖所示之示意圖 說明的方法係以第一圖相同之方法施加電場，對經低溫 熱處理而預結晶之多晶矽薄膜進行熱處理。一般而言，低 溫多晶矽薄膜具有之一優勢係其晶粒之尺寸大於高溫多晶 矽之晶粒尺寸，但其包含諸如晶粒中之孿晶的許多晶體晶 格缺陷。根據本發明之方法’因為可以進行局溫處理且該 玻璃基板1 〇不產生熱變形，所以，施加一電場，對在低溫 下已預結晶之多晶矽薄膜52進行高溫熱處理，藉由此方 • / · . 法，可產生不具有晶體晶格缺陷之大尺寸多晶矽薄膜。 作為本發明之另一具體實施例，第五圖所示之示意圖 說明之方法係：在一氧氣、臭氧或水蒸汽環境或去離子水 中，以第一圖相同之方法施加一電場，在經低溫熱處理而 預結晶化的多晶矽薄膜上形成熱氧化物膜。第五圖說明該 處理與使用石英基板產生高溫多晶矽薄膜之處理係大體相 同的。在該熱氧化處理之情況下，因為需要氧氣環境及 900°C以上之高溫，所以不可能使用玻璃基板。在本發明 之方法之情況下，因為在極短時間内達到高溫，所以可形 成熱氧化物薄膜60而不招致玻璃基板10之熱變形。然而， 需重複施加電場時之加熱及移除電@時之冷卻，達成熱氧 化處理。因為利用本發明之方法沉積之熱氧化物薄膜60之 厚度係極小，所以添加額外PECVD氧化物薄膜處理以形成 閘氧化物膜（未圖示）。意即，實施本發明之方法可導致閘 氧化物薄膜及多晶石夕薄膜之間之介面特性.之改良。而且， 在熱氧化處理期間，可移除低溫多晶矽中出現的大量晶體 1362704 晶格缺陷。 作為本發明之另一具體實施例，第六圖所示之示意圖 說明之方法係在相同之CVD腔室内連續沉積非結晶矽薄 膜50及閘氧化物薄膜70，然後以第一圖相同之方法施加 一電場，進行熱處理。一般而言，連續沉積形成之閘氧化 物薄膜之優勢在於該介面特性係優良的，但其不能用於雷 射處理。因為本發明之方法係非雷射處理，所以可使用連 續沉積形成之閘氧化物薄膜，進而使得該裝置特性之改良 • . · 及該處理之簡化。 作為本發明之另一具體實施例，第七圖所示之示意圖 說用之方法係連續沉積非結晶矽薄膜50及閘.氧化物薄膜 70，隨後以第一圖相同之方法施加一電場，對經低溫熱處 理而預結晶之薄膜52進行熱處理。藉由此方法，可同時獲 得^具有大尺寸晶粒及少量缺陷之多晶矽薄膜，以及具有優 良介面特性之閘氧化物薄膜。 本發明之方法中使用之焦耳加熱發生在施加電場之導 電層中，將其界定為：利用電流通過時一導電材料之阻抗 所產生之熱量所進行的加熱。 藉由如下公式表達電場施加所導致之焦耳加熱施加於 導電層時，單位時間之能量數值：It is explained that an electric field is applied by the same method as in the first figure, and crystallization and activation of impurities are simultaneously performed. Following the deposition of the amorphous germanium film 50, patterning processing for individual TFT devices is completed via lithography. A gate oxide film 42 is deposited thereon by a PECVD method, and then a gate 44 is deposited using a nozzle. To form the gate 44, patterning is performed by lithography processing and etching processing. Therefore, ion implantation is performed on the prepared self-aligned gate structure by doping with impurities to form a source and a drain, and then an electric field is applied by the same method as in the first embodiment, while crystallization and activation of impurities are simultaneously performed. Since the indium tin oxide film 3 as a conductive layer is not electrically short, the above treatment is possible. As another embodiment of the present invention, the schematic diagram shown in the third figure illustrates the application of an electric field while performing the junction=chemical treatment and thermal oxidation in the same manner as in the first embodiment. Since the temperature of the amorphous crystalline film 50 is raised to at least 1 〇〇〇〇c or higher according to the present invention, it is possible to reduce the temperature in an oxygen environment. Depending on the situation, ^ in the ozone environment or water in the environment or even in the silk water towel for cooking, = not in an oxygen environment. In general, during the production of the TFT device, a film having a fine heterothermal oxide film cannot be used due to thermal defects of the glass substrate 10, and a PECVD oxide film is deposited. However, according to the present invention, since the electric field is applied only for a short period of time, (4), spot crystallization of the extremely thin thermal oxide film 60 is simultaneously performed by repeatedly applying an electric field in an oxygen atmosphere. The phase is deposited thereon by the method of (4). For a thick oxide film (not shown), a TFT-generating process can be performed, and in this way, the features of the Si/Si〇2 interface can be improved. 19 1362704 As another embodiment of the present invention, the method illustrated in the fourth diagram illustrates the method of applying an electric field in the same manner as in the first drawing, and heat-treating the polycrystalline germanium film pre-crystallized by the low-temperature heat treatment. In general, low temperature polycrystalline germanium films have one advantage in that the size of the crystal grains is larger than the grain size of the high temperature polycrystalline germanium, but it contains many crystal lattice defects such as twins in the crystal grains. According to the method of the present invention, since the local temperature treatment can be performed and the glass substrate 1 is not thermally deformed, an electric field is applied to heat-treat the polycrystalline germanium film 52 which has been precrystallized at a low temperature, thereby The method can produce a large-sized polycrystalline germanium film without crystal lattice defects. As another specific embodiment of the present invention, the schematic diagram shown in the fifth diagram illustrates a method of applying an electric field in an oxygen, ozone or water vapor environment or deionized water in the same manner as in the first diagram, at a low temperature. A thermal oxide film is formed on the polycrystalline germanium film which is pre-crystallized by heat treatment. The fifth figure illustrates that this treatment is substantially the same as that of a quartz substrate to produce a high temperature polycrystalline germanium film. In the case of this thermal oxidation treatment, since an oxygen atmosphere and a high temperature of 900 ° C or higher are required, it is impossible to use a glass substrate. In the case of the method of the present invention, since the high temperature is reached in a very short time, the thermal oxide film 60 can be formed without incurring thermal deformation of the glass substrate 10. However, it is necessary to repeatedly heat the electric field and remove the cooling at the time of electric heating to achieve thermal oxidation treatment. Since the thickness of the thermal oxide film 60 deposited by the method of the present invention is extremely small, an additional PECVD oxide film is added to form a gate oxide film (not shown). That is, the method of carrying out the invention can result in an improvement in the interface characteristics between the gate oxide film and the polycrystalline film. Moreover, during the thermal oxidation process, a large number of crystal 1362704 lattice defects appearing in the low temperature polysilicon can be removed. As another embodiment of the present invention, the method illustrated in the sixth diagram illustrates the continuous deposition of the amorphous germanium film 50 and the gate oxide film 70 in the same CVD chamber, and then applied in the same manner as in the first figure. An electric field is applied for heat treatment. In general, the advantage of continuous deposition of a gate oxide film is that the interface characteristics are excellent, but it cannot be used for laser processing. Since the method of the present invention is non-laser processing, it is possible to use a gate oxide film formed by continuous deposition, thereby improving the characteristics of the device and the simplification of the process. As another embodiment of the present invention, the schematic diagram shown in the seventh embodiment shows that the amorphous ruthenium film 50 and the gate oxide film 70 are successively deposited, and then an electric field is applied in the same manner as in the first figure. The film 52 pre-crystallized by low-temperature heat treatment is subjected to heat treatment. By this method, a polycrystalline germanium film having a large-sized crystal grain and a small amount of defects, and a gate oxide film having excellent interface characteristics can be obtained at the same time. The Joule heating used in the method of the present invention occurs in a conductive layer to which an electric field is applied, which is defined as the heating by the heat generated by the impedance of a conductive material as it passes. The energy value per unit time when Joule heating caused by electric field application is applied to the conductive layer by the following formula:

W = V X I 在上述公式中，將W定義為焦耳加熱提供之單位時間 之能量數值，將V界定為施加於導電層兩端之電壓，將I 界定為電流。 21 1362704 可從上述公式中看出，當電壓（v)增加時，及/成电 流（I)增加時，利用焦耳加熱施加於導電層之單位時間之 能量數值亦增加。當焦耳加熱使導電層之溫度增加時，熱 量傳導至安置於導電層上之矽薄膜及安置於導電層下之基 板（例如’玻璃基板h因此，以本發明之方法對樣本施加 短時間之合適的電壓及電流，利用不導致玻璃基板產生熱 變形之熱傳導，以使矽薄膜之溫度提昇至可以啟動結晶化 及活化雜質的溫度。若施加之能量數值係足夠的，則經由 * · ♦ - . · 單個照射即可完成該處理，若數值係不足，則經由具有適 當時間間隔之若干次照射來完成該結晶化處理。 如上所述’根據習知MIC方法、MILC方法及其他結 晶方法，存在如下情況，一情況係施加電場或磁場以促進 低溫之催化金屬之垂直感應或側向感應，另外之情況係經 由圖案化處理’且在極短時間内（約l^sec)使一電場施力u 於一極小樣本（例如’ 250 μπι X 50 μιη) ’以通過安置於上 層之金屬傳導膜（Cr )達成結晶化。然而，該等情況不能 進行如下步驟：藉由將電場施加於需要熱處理之矽薄取下 安置的導電廣’更特定言之’將電場施加於覆蓋該介電爲 之矽薄膜下設置的導電層’及使用導電層之焦耳加熱來產 生導電熱，在該基板之全部區域内進行結晶化而不進行圖 案化處理。 用於比較本發明與該等習知方法之另一因素係該電場 應用之持續時間’本發明之方法中電場應用之持續時間 單次應用之持續時間）較佳係上述之1/1000至1秒。讀社 22 1362704 晶化之較短時間可使結晶化及活化雜質在上層之矽薄膜中 達成，且儘管可將導電層加熱至一極高溫度，下層之基板 (例如，玻璃基板）不變形。 範例 在下文中，將參照樣本詳細描述本發明，且該等樣本 不以任何方式限定本發明之範疇。 - -. · • . -* . · •[範例1] 利用PECVD方法，在寬2 cm、長22 cm且厚0.7 mm 之玻璃基板上形成具有3000 A厚度的Si02層（第一介電 層）。藉由喷藏在第一介電層上沉積具有1000 A厚度之銦 錫.氧化物（ITO)薄膜（導電層），且隨後利用PECVD方 法在其上沉積具有1000 A厚度之Si02層（第二介電層）。 利用PECVD方法在第二介電層上沉積具有500 A厚度之非 I 結晶矽薄膜。因此，製備了第一圖所示之包含一非結晶矽 薄膜之薄膜堆疊。測得該導電層之阻抗係20 Ω。 在室溫下，將300 V-15 A之電場在以此方式製備的樣 本之導電層上應用0.05秒，總計重複五次該處理。結果， 電場應用總計進行了大約0.25秒。在一單次場應用中，施 加於導電層上之能量數值係1125 Watt/cm2。第八圖所示係 根據電場施加於導電層期間的應用時間測得之能量密度之 波形。 在第九圖中，（a)係一照片，其顯示在電場施加之前， 23 1362704 至溫下之非結晶矽薄骐之樣本，（b)係一照片，其顯示在 電場施加期間，焦耳加熱導致之高溫所引起之矽薄膜的發 光現象，且（C)係繼—電場施加之後，具有轉換成多晶矽 薄膜之矽薄膜樣本照片。根據（b)中之發光現象，可推斷 該導電層之即時溫度升至至少1000〇C或更高。該即時熱量 傳導至安置於上層之矽薄膜且誘發非結晶矽之結晶化。 第十圖所示係繼該熱處理之後對矽薄暝執行拉曼分析 之結果。從第十圖可看出，非結晶矽薄膜已100%地轉換成 多晶碎狀態。. 第十一圖所示係繼該熱處理之後對矽薄膜執行明視場 TEM分析之結果。在第十一圖中，根據本發明製備之多晶 石夕薄膜之微結構具有高溫製備之多晶矽薄膜之結構。換言 之，儘管晶體晶粒尺寸小於低溫多晶矽薄膜之晶粒尺寸， 晶粒之形態係多角形的，且在該晶粒中，諸如孿晶之晶體 晶格缺陷數量係減少的。已證實儘管存在結晶化熱處理， 該導電層下之玻璃基板完全不歷經變形。 [範例2]W = V X I In the above formula, W is defined as the energy value per unit time provided by Joule heating, and V is defined as the voltage applied across the conductive layer, defining I as the current. 21 1362704 It can be seen from the above formula that as the voltage (v) increases and the current (I) increases, the energy value per unit time applied to the conductive layer by Joule heating also increases. When Joule heating increases the temperature of the conductive layer, heat is transferred to the tantalum film disposed on the conductive layer and the substrate disposed under the conductive layer (eg, 'glass substrate h. Therefore, it is suitable to apply the sample for a short time by the method of the present invention. The voltage and current are transferred by heat that does not cause thermal deformation of the glass substrate, so that the temperature of the ruthenium film is raised to a temperature at which crystallization and activation of impurities can be initiated. If the applied energy value is sufficient, it is via * ♦ - . · The treatment can be completed by a single irradiation, and if the numerical value is insufficient, the crystallization treatment is completed by several irradiations with appropriate time intervals. As described above, 'according to the conventional MIC method, the MILC method, and other crystallization methods, the following In one case, an electric field or a magnetic field is applied to promote vertical or lateral sensing of the catalytic metal at a low temperature, and in other cases, an electric field is applied through a patterning process and in an extremely short time (about 1 sec). A very small sample (for example, '250 μπι X 50 μιη)' is used to achieve crystallization by a metal conductive film (Cr) disposed in the upper layer. However, in such cases, the following steps cannot be performed: an electric field is applied to the conductive layer provided under the dielectric film covering the dielectric by applying an electric field to the conductive layer which is disposed under the thinning of the heat treatment. And the use of Joule heating of the conductive layer to generate conductive heat, crystallization in all areas of the substrate without patterning. Another factor for comparing the present invention with such conventional methods is the application of the electric field. The duration "the duration of the single application of the duration of the application of the electric field in the method of the invention" is preferably from 1/1000 to 1 second as described above. Read Society 22 1362704 The shorter time of crystallization allows crystallization and activation of impurities to be achieved in the upper layer of tantalum film, and although the conductive layer can be heated to a very high temperature, the underlying substrate (e.g., glass substrate) is not deformed. EXAMPLES Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, which are not intended to limit the scope of the invention. - -. · • . -* . · • [Example 1] Using a PECVD method, a SiO 2 layer (first dielectric layer) having a thickness of 3000 A is formed on a glass substrate having a width of 2 cm, a length of 22 cm, and a thickness of 0.7 mm. . An indium tin oxide (ITO) film (conductive layer) having a thickness of 1000 A is deposited on the first dielectric layer by spraying, and then a SiO 2 layer having a thickness of 1000 A is deposited thereon by a PECVD method (second Dielectric layer). A non-I crystalline germanium film having a thickness of 500 A was deposited on the second dielectric layer by a PECVD method. Thus, a film stack comprising an amorphous ruthenium film as shown in the first figure was prepared. The impedance of the conductive layer was measured to be 20 Ω. The electric field of 300 V-15 A was applied to the conductive layer of the sample prepared in this manner for 0.05 second at room temperature, and the treatment was repeated five times in total. As a result, the electric field application was totaled for about 0.25 seconds. In a single field application, the energy applied to the conductive layer is 1125 Watt/cm2. The eighth graph shows the waveform of the energy density measured based on the application time during which the electric field is applied to the conductive layer. In the ninth figure, (a) is a photograph showing a sample of 23 1362704 to a non-crystalline 矽 thin 温 before temperature application, and (b) a photograph showing Joule heating during application of an electric field. The luminescence phenomenon of the ruthenium film caused by the high temperature is caused, and (C) is a photo of the ruthenium film sample converted into a polycrystalline ruthenium film after the application of the electric field. According to the luminescence phenomenon in (b), it can be inferred that the instantaneous temperature of the conductive layer rises to at least 1000 〇 C or higher. This instantaneous heat is conducted to the ruthenium film disposed in the upper layer and induces crystallization of the amorphous ruthenium. The tenth graph shows the results of performing Raman analysis on the tantalum crucible after the heat treatment. As can be seen from the tenth graph, the amorphous ruthenium film has been 100% converted into a polycrystalline state. Figure 11 shows the results of a bright field TEM analysis of the tantalum film after this heat treatment. In the eleventh diagram, the microstructure of the polycrystalline film prepared according to the present invention has a structure of a polycrystalline germanium film prepared at a high temperature. In other words, although the crystal grain size is smaller than the grain size of the low-temperature polycrystalline germanium film, the morphology of the crystal grains is polygonal, and in this crystal grain, the number of crystal lattice defects such as twin crystals is reduced. It has been confirmed that despite the crystallization heat treatment, the glass substrate under the conductive layer is not deformed at all. [Example 2]

利用PECVD方法，在寬2 cm、長2 cm且厚〇 7 mm 之玻璃基板上成形具有3000 A厚度之Si〇2層（第一介電 層）。利用喷濺在第一介電層上沉積厚度15〇〇 A之銦錫氧 化物（ITO)薄膜（導電層），隨後利用PECVD在其上沉積 具有厚度1000 A之Si02層（第二介電層）。利用PECVD 在第二介電層沉積厚度500 A之非結·晶矽薄膜。因此，製 24 2第-圖所示之包含非結晶石夕薄膜之薄膜堆疊。測得該 導电層之阻抗係10Ω。. 將300 V-3〇 A之電場在以此方式預熱樣本之導電層上 用0.009 & ’該處理重複總計5〇二欠。在該電場應用中， 於，導電層之單位時間之能量數值係纖伽/啦2。 _ j第十二圖中’（a)係一照片，其顯示在電場施加之 蚋，室溫下之非結晶矽薄膜的樣本，係一照片，其顯 =在電場施加期間，.焦耳加熱產生之高溫加熱所導致之矽 溥膜發光現象，且（c)係繼一次電場施加之後，具有轉換 成多晶矽薄膜之矽薄膜的樣本照片。根據（b)中的白色發 光現象’可推斷該筹.電層之即時溫度.已升至至少」刪。c或 更高。該強熱傳導至安置於上層之石夕薄膜且誘發非結晶石夕 之結晶化。 ，第十三圖所示係繼該熱處理之後執行矽薄膜之暗視場 ΊΈΜ分析之、纟#果。在第十-SJ中’根據本發明製備之多晶 石夕薄膜之微結構具有奈米尺寸多晶矽薄膜之結構。僅在管 形爐中進行高溫固相結晶化或利用RTA (快速熱退火）方 式，較難達成該微結構，且本發明首次通報該結構。在本 發明之方法中，因為該加熱速率超過至少1 〇〇〇〇〇〇C/秒，所 以完整地反映出形成於高溫之微結構。另一方面，即使RTA 利用習知熱處理方法中的最高加熱速率，因為該熱處理速 率僅係約100oC/秒’所以在該加熱過程中發生了形成多晶 矽之相轉移，因此無法反映形成於高溫下之所需之微結 構。產生於該範例之多晶石夕具有極小尺寸之晶粒且顯示等 25 1362704 轴形態之晶粒。該結構係一種無法在其他熱處理方法中獲 得的微結構，且因為保證該晶粒尺寸之均一性，預期該結 構非常適用於OLED應用。已證實儘管存在該結晶化熱處 理，安置於導電層下之玻璃基板完全不歷經變形。 工業適用性 如上所述，根據本發明之退火方法提供多晶矽薄膜， 其完全不具有諸如MIC及MILC方法之結晶化方法產生的. . · · . · · · · * 多晶矽薄膜中所呈現之催化金屬導致的污染問題，且同時 · 不伴隨發生E L C方法產生之多晶矽薄膜中所呈現之表面突 起，且不產生玻璃基板之熱變形，且顯著地減少了晶體晶 格缺陷量。多晶矽薄膜之製備技術構成了本發明之該等特 徵，該等特徵在先前技術中未通報。 普遍熟習關於本發明之此項技術者可以基於該上述描 述進行各種修正及應用。 【圖式簡單說明】 第一圖係一示意圖，根據本發明之一具體實施例，其 說明多晶矽薄膜製備樣本之構造。 第二圖係一示意圖，根據本發明之一具體實施例，其 說明源極/汲極及閘極分別形成之後，同時進行非結晶矽薄 膜結晶化及活化雜質的熱處理之方法。 第三圖係一示意圖，根據本發明之一具體實施例，其 說明於氧氣環境下，藉著如第一圖相同之方法，藉著施加 26 1362704 一電場，同時進行非結晶矽薄膜結晶化處理及熱氧化處理 之方法。 第四圖係一示意圖，根據本發明之一具體實施例，其 說明藉著如第一圖相同之方法，藉著施加一電場，熱處理 一已經由低溫熱處理而預結晶之多晶矽薄膜之方法。 第五圖係一示意圖，根據本發明之一具體實施例，其 說明在氧氣環境下，藉著如第一圖相同之方法，藉著施加 ——電場，.形成熱氧化薄膜於已經由低溫熱處理而預結晶之 * . . · · • 多晶矽薄膜上之方法。 第六圖係一示意圖，根據本發明之一具體實施例，其 說明藉著如第一圖相同之方法，藉著施加一電場，在相同 C V D反應器中沉積非結晶矽薄膜且在其上連續沉積閘氧化 物薄膜，隨後熱處理該非結晶矽薄膜之方法。 二 第七圖係一示意圖，根據本發明之一具體實施例，其 說明藉著如第一圖相同之方法，藉著施加一電場，連續沉 ^ 積非結晶矽薄膜及閘氧化物薄膜，隨後熱處理一已經由低 溫熱處理而預結晶之多晶梦缚膜之方法。 第八圖係一曲線圖，其說明範例1中，在施加一電場 於導電層期間，依照施加電場的時間，量測的能量密度。 第九圖顯示（a)範例1樣本的照片，其為室溫下施加 電場於非結晶矽薄膜之前，（b)藉著施加電場時的焦耳加 熱所產生的高溫加熱，導致矽薄膜發光之照片，及（c)在 室溫下施加一電場之後，矽薄膜轉換成多晶矽薄膜之樣本 照片。 27 1362704 第十圖係一曲線圖，其說明範例1之多晶矽薄膜在退 火之後的拉曼分析結果。 第十一圖係一照片（放大率：X 60,000)，其顯示範例 1之多晶矽薄膜在退火之後的亮視場TEM分析結果。 第十二圖顯示（a)範例2的樣本照片，其為室溫下施 加電場於非結晶矽薄膜之前，（b)藉著施加電場時的焦耳 加熱所產生的高溫加熱，導致矽薄膜發光之照片，及（Ο 在室溫下施加一電場之後，矽薄膜轉換成多晶矽薄膜之樣 • · · - . 本照片。 第十三圖係一照片（放大率：X 100,000)，其顯示範例 2之多晶矽薄膜在退火之後的暗視場TEM分析結果。 【主要元件符號說明】 10 基板 20 第一介電層 30 導電層 40 第二介電層 42 閘氧化物薄膜 44 閘極 50 非結晶矽薄膜 52 多晶矽薄膜 60 熱氧化物薄膜 70 連續沉積閘氧化物薄膜 28Using a PECVD method, a Si 2 layer (first dielectric layer) having a thickness of 3000 A was formed on a glass substrate having a width of 2 cm, a length of 2 cm, and a thickness of 7 mm. A 15 Å thick indium tin oxide (ITO) film (conductive layer) is deposited on the first dielectric layer by sputtering, and then a SiO 2 layer having a thickness of 1000 A is deposited thereon by PECVD (second dielectric layer) ). A non-junction crystal film having a thickness of 500 A was deposited on the second dielectric layer by PECVD. Thus, a film stack comprising amorphous crystalline films is shown in Fig. 2-2. The impedance of the conductive layer was measured to be 10 Ω. The electric field of 300 V-3 〇 A was preheated on the conductive layer of the sample in this manner by repeating a total of 5 〇 欠 0.00 with 0.009 & In this electric field application, the energy value per unit time of the conductive layer is 纤//2. _ j In the twelfth figure, '(a) is a photograph showing a sample of an amorphous ruthenium film at room temperature after application of an electric field, which is a photograph, which shows that during the application of an electric field, Joule heating is generated. The ruthenium film luminescence phenomenon caused by the high temperature heating, and (c) is a sample photograph of the ruthenium film which is converted into a polycrystalline ruthenium film after the application of the primary electric field. According to the white luminescence phenomenon in (b), it can be inferred that the instantaneous temperature of the electric layer has risen to at least "deleted". c or higher. This strong heat is conducted to the stone film disposed in the upper layer and induces crystallization of the amorphous stone. The thirteenth figure shows the dark field ΊΈΜ analysis of the tantalum film after the heat treatment. In the tenth-SJ, the microstructure of the polycrystalline thin film prepared according to the present invention has a structure of a nano-sized polycrystalline germanium film. It is difficult to achieve the microstructure only by high-temperature solid phase crystallization in a tubular furnace or by RTA (rapid thermal annealing), and the present invention is first notified of the structure. In the method of the present invention, since the heating rate exceeds at least 1 〇〇〇〇〇〇C/sec, the microstructure formed at a high temperature is completely reflected. On the other hand, even if the RTA utilizes the highest heating rate in the conventional heat treatment method, since the heat treatment rate is only about 100 ° C / sec, the phase transition of polymorph formation occurs during the heating process, and thus cannot be reflected at the high temperature. The required microstructure. The polycrystalline spine produced in this example has crystal grains of extremely small size and exhibits crystal grains of the shape of 25 1362704. This structure is a microstructure that cannot be obtained in other heat treatment methods, and since the uniformity of the grain size is ensured, the structure is expected to be very suitable for OLED applications. It has been confirmed that despite the crystallization heat treatment, the glass substrate disposed under the conductive layer is not deformed at all. Industrial Applicability As described above, the annealing method according to the present invention provides a polycrystalline germanium film which does not have a crystallization method such as MIC and MILC method at all. The catalytic metal present in the polycrystalline germanium film The resulting contamination problem, and at the same time, does not accompany the surface protrusions present in the polycrystalline germanium film produced by the ELC method, and does not cause thermal deformation of the glass substrate, and the amount of crystal lattice defects is remarkably reduced. The fabrication techniques of polycrystalline germanium films constitute such features of the present invention, which are not disclosed in the prior art. Those skilled in the art of the present invention will be able to make various modifications and applications based on the above description. BRIEF DESCRIPTION OF THE DRAWINGS The first drawing is a schematic view showing the construction of a sample prepared by a polycrystalline silicon film according to an embodiment of the present invention. The second drawing is a schematic view showing a method of simultaneously performing crystallization of an amorphous germanium film and heat treatment of activated impurities after forming a source/drain and a gate, respectively, according to an embodiment of the present invention. The third figure is a schematic diagram illustrating the simultaneous crystallization of an amorphous ruthenium film by applying an electric field of 26 1362704 in the same manner as in the first diagram in an oxygen environment according to an embodiment of the present invention. And thermal oxidation treatment methods. The fourth drawing is a schematic view showing a method of heat-treating a polycrystalline germanium film which has been pre-crystallized by low-temperature heat treatment by applying an electric field by the same method as in the first drawing, according to an embodiment of the present invention. Figure 5 is a schematic view showing the formation of a thermally oxidized film by low temperature heat treatment in an oxygen environment by the same method as in the first figure by applying an electric field. Pre-crystallized * . . . • • Method on polycrystalline germanium film. Figure 6 is a schematic view showing, according to an embodiment of the present invention, by depositing an electric field, depositing an amorphous germanium film in the same CVD reactor and continuing thereon by the same method as in the first figure. A method of depositing a gate oxide film and subsequently heat treating the amorphous germanium film. 2 is a schematic view showing a method of continuously depositing an amorphous germanium film and a gate oxide film by applying an electric field, according to an embodiment of the present invention, by the same method as in the first figure. Heat treatment A method of polycrystalline dream binding film which has been pre-crystallized by low temperature heat treatment. The eighth figure is a graph illustrating the energy density measured in accordance with the time during which an electric field is applied during application of an electric field to the conductive layer in the example 1. The ninth image shows (a) a photograph of the sample of Example 1, which is a photo of the film which is heated by the Joule heating by applying an electric field before the application of an electric field to the amorphous ruthenium film at room temperature, resulting in the luminescence of the ruthenium film. And (c) after applying an electric field at room temperature, the tantalum film is converted into a sample photograph of the polycrystalline tantalum film. 27 1362704 The tenth figure is a graph illustrating the results of Raman analysis of the polycrystalline silicon film of Example 1 after annealing. The eleventh photograph is a photograph (magnification: X 60,000) showing the results of bright field TEM analysis of the polycrystalline germanium film of Example 1 after annealing. Figure 12 shows (a) a sample photograph of Example 2, which is an application of an electric field at room temperature before the amorphous ruthenium film, and (b) high temperature heating by Joule heating by application of an electric field, causing the ruthenium film to emit light. Photo, and (Ο After the application of an electric field at room temperature, the tantalum film is converted into a polycrystalline tantalum film. • · · - . This photo. The thirteenth image is a photo (magnification: X 100,000), which shows the example 2 Dark field TEM analysis results of polycrystalline germanium film after annealing. [Main component symbol description] 10 substrate 20 first dielectric layer 30 conductive layer 40 second dielectric layer 42 gate oxide film 44 gate 50 amorphous germanium film 52 Polycrystalline germanium film 60 thermal oxide film 70 continuous deposition gate oxide film 28

Claims (1)

1362704 十、申請專利範圍： 1. 一種多晶石夕薄膜，其製備係藉由在一透明基板上層積之 一第一介電層上形成一導電層，依序於其上形成一第二 介電層及一石夕薄膜，施加一電場於該導電層以誘發焦耳 加熱且藉此產生強熱，並利用如此方式產生之強熱對該 矽薄膜進行熱處理，其中該多晶矽薄膜之該微結構於一 TEM分析下係顯示一奈米尺寸多晶矽薄膜結構。1362704 X. Patent Application Range: 1. A polycrystalline stone film prepared by forming a conductive layer on a first dielectric layer laminated on a transparent substrate, and sequentially forming a second dielectric layer thereon. An electric layer and a film, applying an electric field to the conductive layer to induce Joule heating and thereby generating strong heat, and heat treating the tantalum film by the strong heat generated in such a manner that the microstructure of the polycrystalline film is The TEM analysis shows a nanocrystalline polycrystalline germanium film structure. 2929
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