KR101193226B1 - Manufacturing method for thin film of poly-crystalline silicon - Google Patents

Abstract

PURPOSE: A method for manufacturing a polycrystalline silicon thin film is provided to improve productivity by sufficiently supplying heat to a chemical reactant. CONSTITUTION: A metal oxide layer is formed by thermally processing a catalyst layer. A first silicon layer is formed by laminating an amorphous silicon layer on the metal oxide layer. A metal silicide oxide layer(45) is formed by moving catalyst metal elements from the catalyst layer to the first silicon layer. A second silicon layer(50) is formed by laminating the amorphous silicon layer on the metal silicide oxide layer. Crystalline silicon is generated in the second silicon layer by using the metal elements of the metal silicide oxide layer as a catalyst.

Description

Manufacturing method for thin film of Poly-Crystalline Silicon}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film for use in a solar cell, and more particularly, to a method for effectively producing a polycrystalline silicon thin film of an amorphous silicon thin film by metal induction crystallization.

In general, most problems arising in the production of poly-silicon (poly-Si) are due to the use of glass substrates that are vulnerable at high temperatures, and the process temperature cannot be raised sufficiently to the temperature at which the amorphous silicon (a-Si) thin film is crystallized.

The process requiring high temperature heat treatment in the production of poly-Si is a crystallization heat treatment (Crystallization) that converts the amorphous silicon (a-Si) thin film to a crystalline silicon thin film and an activation heat treatment (Dopant) that is electrically activated after doping Activation).

At present, a variety of processes (LTPS: Low Temperature poly-Si) have been proposed for forming a polycrystalline silicon thin film in a short time at a low temperature that the glass substrate allows. Representative methods for forming a polycrystalline silicon thin film include solid phase crystallization (SPC), excimer laser annealing (ELA), and metal induced crystallization (MIC).

Solid Phase Crystallization (SPC) is the most direct and long used method of obtaining polycrystalline silicon (poly-Si) thin films from amorphous silicon (a-Si). SPC is a method of obtaining a polycrystalline silicon thin film having a grain size of about several micro by heat-treating the amorphous silicon thin film at a temperature of 600 ℃ or more for several tens of hours. The polycrystalline silicon thin film obtained by this method has a disadvantage in that it is difficult to use a glass substrate because of high defect density in crystal grains and a high heat treatment temperature, and a long process time due to long heat treatment.

Excimer Laser Annealing (ELA) is a method of instantaneously irradiating an excimer laser to a amorphous silicon thin film for nanoseconds to melt and recrystallize the amorphous silicon thin film without damaging the glass substrate.

However, ELA is known to have significant problems in mass production processes. ELA has a very non-uniform grain structure of polycrystalline silicon (poly-Si) thin film according to the laser irradiation amount. ELA has a problem that it is difficult to manufacture a uniform crystalline silicon thin film because of the narrow process range. In addition, the surface of the polycrystalline silicon thin film is rough, which adversely affects the characteristics of the device. This problem is more serious in the application of organic light emitting diodes (OLEDs) in which the uniformity of thin film transistors (TFTs) is important.

The method proposed to overcome this problem is a metal induced crystallization method (MIC, for example) as disclosed in Korean Patent Laid-Open No. 2006-0025624. MIC is a method of inducing crystallization of silicon by applying a metal catalyst to amorphous silicon by sputtering or spin coating, followed by heat treatment at low temperature. As the metal catalyst, various metals such as nickel (Ni), copper (Cu), aluminum (Al), and palladium (Pd) may be used. In general, nickel (Ni) is used as a metal catalyst in MIC, in which reaction control is easy and large grains are obtained. MIC can be crystallized at low temperatures below 700 ° C, but there are significant problems in the actual production process. This problem is that a significant amount of metal diffused in the active region in the TFT causes typical metal contamination, increasing leakage current, one of the TFT characteristics.

The development of low temperature poly-silicon (LTPS) has been carried out for the purpose of application to liquid crystal display devices, but recently, active matrix organic light emitting diodes (AMOLED) and thin film polycrystalline silicon solar cells In addition, the need for development is increasing.

Inexpensive, high-productivity poly-Si fabrication methods will compete with amorphous silicon thin-film transistor liquid crystal displays (a-Si TFT LCDs) in the display family with many active organic light emitting diodes (AMOLEDs) in the market. It is important in that it is. The method of manufacturing polycrystalline silicon is also important in that active organic light emitting diodes (AMOLEDs) will compete with crystalline wafer forms in solar cells. Therefore, the production cost and market competitiveness of the product can be stably polycrystalline at a low price compared to an amorphous silicon thin film transistor liquid crystal display (a-Si TFT LCD) and a crystalline wafer type solar cell in which the production technology has reached a stabilization stage. It depends on whether you can make silicon.

1 schematically shows a manufacturing process for obtaining a polycrystalline silicon thin film from amorphous silicon by a metal induction crystallization method. Referring to FIG. 1, in the conventional process, a buffer layer 2 made of silicon oxide (SiO ₂ ) is formed on a substrate 1 such as glass, and an amorphous silicon layer 3 is formed on the buffer layer 2 by plasma chemical vapor deposition (PECVD). After forming by Plasma Enhanced Chemical Vapor Deposition, sputtering and coating a metal such as nickel (Ni) on the amorphous silicon layer (3) and then heat-treated by RTA (Rapid Thermal Annealing) at about 700 ℃ The crystalline silicon 4 is formed from the silicon layer 3. However, according to the conventional method, since it is difficult to precisely control the amount of the metal applied to the upper portion of the amorphous silicon layer 3, there is an uncomfortable problem of having to remove the excessively applied metal. This process not only increases manufacturing costs but also adversely affects the quality of the crystallized silicon.

An object of the present invention is to solve the above problems, in the method of manufacturing a polycrystalline silicon thin film using the metal induction crystallization method, precisely control the amount of catalyst metal and enable crystallization at low temperature By providing an efficient method for producing a polycrystalline silicon thin film.

In order to achieve the above object, a method of manufacturing a polycrystalline thin film according to an embodiment of the present invention includes: forming a first metal layer on a substrate;

An insulating layer forming step of forming an insulating layer on the first metal layer;

A second metal layer forming step of forming a second metal layer on the insulating layer;

A catalyst layer forming step of forming a catalyst layer by stacking the second metal layer and another metal on the second metal layer;

Forming a metal oxide film by heat-treating the catalyst layer or forming a metal oxide film by depositing a metal oxide film on the catalyst layer;

Forming a first silicon layer by stacking an amorphous silicon layer on the metal oxide film;

A heat treatment step of moving the catalyst metal atoms from the catalyst layer to the first silicon layer to form a metal silicide oxide layer;

Forming a second silicon layer by laminating an amorphous silicon layer on the metal silicide oxide layer;

And a crystallization step of heat treating the crystalline silicon in the second silicon layer using the metal particles of the metal silicide oxide layer as a catalyst.

Metals forming the second metal layer include chromium (Cr), molybdenum (Mo), tantalum (Ta), tungsten (W), iridium (Ir), AZO (zinc oxide), cadmium (Cd), and manganese (Mn) It is preferable that it is either.

And patterning the electrode pattern on the second metal layer by removing a portion of the second metal layer by a photolithography method or a lift-off method after the second metal layer forming step.

It is preferable that the thickness of the said electrode pattern is 6 kPa-100 micrometers.

The material stacked on the second silicon layer may be substituted with amorphous silicon germanium (SiGe) or amorphous silicon carbide (SiC).

In the method of manufacturing a polycrystalline silicon thin film according to the present invention, the first metal layer disposed between the substrate and the insulating layer reflects and blocks the heat incident on the substrate during the heat treatment process to protect the substrate from thermal shock, The bimetallic layer transfers the heat reflected from the first metal layer to the upper part, thereby sufficiently supplying heat to the chemically reacted material during the heat treatment process, thereby improving productivity and improving the quality of the crystallized silicon.

1 is a view for explaining a conventional method for producing a polycrystalline silicon thin film by a metal induction crystallization method.
2 is a view showing a manufacturing process according to an embodiment of the present invention.
3 is a view showing a cross section after the catalyst layer forming step shown in FIG.
4 is a view showing a cross section after the first silicon layer forming step shown in FIG.
5 is a view showing a cross section after the heat treatment step shown in FIG.
FIG. 6 is a view illustrating a cross section after the second silicon layer forming step illustrated in FIG. 2.
FIG. 7 is a cross-sectional view schematically illustrating how crystalline silicon is formed on a substrate after the crystallization step of FIG. 2.
8 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention under an optical microscope.
FIG. 9 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 8.
10 is an experimental result comparing the grain size of the polycrystalline silicon thin film manufactured by the present invention with the grain size of the polycrystalline silicon thin film manufactured by the conventional method.

Hereinafter, an embodiment (first embodiment) according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a view showing a manufacturing process according to an embodiment of the present invention. 3 is a view showing a cross section after the catalyst layer forming step shown in FIG. 4 is a view showing a cross section after the first silicon layer forming step shown in FIG. 5 is a view showing a cross section after the heat treatment step shown in FIG. FIG. 6 is a view illustrating a cross section after the second silicon layer forming step illustrated in FIG. 2. FIG. 7 is a cross-sectional view schematically illustrating how crystalline silicon is formed on a substrate after the crystallization step of FIG. 2.

2 to 7, a method of manufacturing a polycrystalline silicon thin film according to the first embodiment of the present invention (hereinafter, referred to as a "manufacturing method") includes a first metal layer forming step S10 and an insulating layer forming step S20. ), The second metal layer forming step (S25), the catalyst layer forming step (S40), the metal oxide film forming step (S50), the first silicon layer forming step (S60), the heat treatment step (S70), and the second Silicon layer forming step (S80), and crystallization step (S90) is included.

In the first metal layer forming step S10, for example, nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gold (Au), aluminum (Al), and indium (In) may be formed on the substrate 10. ), A first metal layer 15 such as titanium (Ti) is formed. The first metal layer 15 may be performed by a known method such as sputtering or plasma chemical vapor deposition (PECVD). The role of the first metal layer 15 is a reaction of materials disposed on the substrate 10 by reflecting heat incident from the upper side of the substrate 10 in the heat treatment step (S70) or crystallization step (S90) to be described later. To promote productivity. In addition, the role of the first metal layer 15 is that the substrate 10 using a material such as glass reflects and blocks heat incident on the substrate 10 during the heat treatment process, thereby preventing the substrate 10 from thermal damage. By suppressing, the number of heat treatment cycles can be increased. Increasing the heat treatment cycle in this way has the effect of increasing the productivity.

In the insulating layer forming step (S20), the insulating layer 20 is formed on the first metal layer 15. The insulating layer 20 may be performed by a known method such as sputtering or plasma chemical vapor deposition (PECVD). The insulating layer 20 may be formed of, for example, oxides (SiO ₂ , Al ₂ O ₃ , MgO, etc.), nitrides (SiN, AlN, Si ₃ N _4, etc.), fluorine compounds (CaF ₂ , MgF ₂ , LaF ₃ , LiF, etc.). It may be made of either. The insulating layer 20 is provided to perform an insulating function. In addition, the insulating layer 20 diffuses impurities from the substrate 10 to the first silicon layer 40 or the second silicon layer 50 to be described later in the heat treatment step (S70) or the crystallization step (S90) to be described later. In order to prevent contamination of impurities in the first silicon layer 40 or the second silicon layer 50. It is preferable that the thickness of the said insulating layer 20 is 1 kPa-300 kPa, respectively. If the thickness of the insulating layer 20 is less than 1Å, the insulating function is relatively poor in the crystallization step (S90) described later. On the other hand, when the thickness of the insulating layer 20 exceeds 300 kW, the manufacturing cost increases, and there is almost no improvement in the insulating function. The heat treatment temperature in the insulating layer forming step (S20) is preferably 50 ℃ to 1000 ℃. When the heat treatment temperature in the insulating layer forming step (S20) is less than 50 ℃, there is a problem that the oxide, nitride, fluorine compound forming the insulating layer is not properly formed. On the other hand, when the heat treatment temperature in the insulating layer forming step (S20) exceeds 1000 ℃ there is a problem that the glass substrate may be damaged by thermal shock.

In the second metal layer forming step S25, the second metal layer 25 is stacked on the insulating layer 20. The second metal layer 25 may be formed by the same method as the first metal layer 15. The metal constituting the second metal layer 25 may be the same as or different from the metal constituting the first metal layer 15. However, the metal constituting the second metal layer 25 must be different from the metal constituting the catalyst layer 30 to be described later. The metal constituting the second metal layer 25 is, for example, chromium (Cr), molybdenum (Mo), tantalum (Ta), tungsten (W), iridium (Ir), AZO (zinc oxide), cadmium (Cd), Manganese (Mn) or the like may be employed.

After the second metal layer forming step S25, a portion of the second metal layer 25 may be removed by a lift off method or a photolithography method to form a patterning step S30. . The electrode pattern may be an electrode when the crystallized silicon thin film is manufactured as a solar cell. The patterning step S30 may be performed as necessary, and the patterning step S30 may not be performed. It is preferable that the height of the electrode pattern formed in the patterning step (S30) is 6Å to 100㎛. If the height of the electrode pattern is less than 6Å, there is a problem difficult to realize in the process. On the other hand, when the height of the electrode pattern exceeds 100㎛ there is a problem in that the productivity takes a long time because the process takes a lot.

In the catalyst layer forming step (S40), for example, nickel (Ni), copper (Cu), cobalt (Co), iron (Fe), gold (Au), aluminum (Al), and indium (In) on the second metal layer 25. ), And a catalyst layer 30 such as titanium (Ti) is formed. The catalyst layer 30 may be performed by known methods such as sputtering or plasma chemical vapor deposition (PECVD). The catalyst layer 30 should be a material different from the material constituting the second metal layer 25. The reason is that the second metal layer 25 is the catalyst layer in the process of forming the metal silicide oxide layer 45 by reacting the catalyst layer 30 with the first silicon layer 40 and the metal oxide layer 35 in the heat treatment process described later. It is for preventing reaction with (30). That is, the material constituting the second metal layer 25 is preferably relatively less reactive with amorphous silicon (a-Si) than the material constituting the catalyst layer 30. It is preferable that the thickness of the said catalyst layer 30 is 5 kPa-1500 kPa. In the case where the thickness of the catalyst layer 30 is less than 5 mm, there is a problem in that the process reproducibility and the uniformity of the catalyst layer 30 deteriorate when the catalyst layer 30 is deposited in a large area due to the too thin thickness. On the other hand, when the thickness of the catalyst layer 30 exceeds 1500Å, a large amount of metal penetrates and causes a metal contamination problem, thereby degrading the characteristics of a device including a crystallized silicon layer. The thickness of the catalyst layer 30 is preferably determined in relation to the thickness of the first silicon layer 40 to be described later.

In the metal oxide film forming step (S50), the catalyst layer 30 is heat-treated to form a metal oxide film 35 on the surface of the catalyst layer 30, or a metal oxide film 35 is deposited on the catalyst layer 30 to form a metal oxide film ( 35). The thickness of the metal oxide film 35 is preferably 1 kPa to 300 kPa. If the thickness of the metal oxide film 35 is less than 1 mm, the metal oxide film 35 may be too thin to perform its function. On the other hand, when the thickness of the metal oxide film 35 exceeds 300 kPa, it is difficult to penetrate the catalyst metal from the catalyst layer 30, and the execution time of the process is too long, resulting in uneconomical problems. When the metal oxide film 35 is formed by the heat treatment in the metal oxide film forming step (S50), the heat treatment temperature is preferably 50 ° C to 1000 ° C. When the heat treatment temperature in the metal oxide film forming step S50 is less than 50 ° C., the metal oxide film 35 may not be well formed. On the other hand, when the heat treatment temperature in the metal oxide film forming step (S50) exceeds 1000 ℃ may cause a problem that the glass substrate is damaged or damaged by thermal shock.

In the first silicon layer forming step (S60), an amorphous silicon layer is stacked on the metal oxide layer 35 to form a first silicon layer 40. The first silicon layer 40 is formed by laminating on the metal oxide film 35 using a known means such as plasma chemical vapor deposition. It is preferable that the thickness of the said 1st silicon layer 40 is 5 kPa-1500 kPa. When the thickness of the first silicon layer 40 is less than 5Å, the thickness of the first silicon layer 40 is so thin that the process reproducibility deteriorates and the uniformity of the first silicon layer 40 when deposited in a large area. There is a problem of poor uniformity. On the other hand, when the thickness of the first silicon layer 40 exceeds 1500Å, the metal silicide oxide layer 45, which will be described later, is formed by combining with the metal element of the catalyst layer 30. There is a problem that chemical bonds are generated that are not necessary to produce. In addition, the ratio of the thickness of the catalyst layer 30 and the thickness of the first silicon layer 40 is preferably 1: 0.5 to 1:20. When the ratio of the thickness of the catalyst layer 30 and the thickness of the first silicon layer 40 is out of the range, as described above, there is a problem in that chemical bonds that are not necessary to form the metal silicide oxide layer 45 are generated. have. That is, a chemical bond of a composition other than the composition of the metal silicide oxide layer 45 required for the metal inductive coupling is formed to interfere with inductive crystallization.

In the heat treatment step (S70), the catalyst metal atoms are moved from the catalyst layer 30 to the first silicon layer 40 to form the metal silicide oxide layer 45. The metal silicide oxide layer 45 is formed by chemically bonding particles of the catalyst layer 30, the metal oxide layer 35, and the first silicon layer 40 by thermal energy. That is, catalyst metal atoms, such as nickel (Ni), move from the catalyst layer 30 to the first silicon layer 40 and combine with oxygen (O) transferred from the metal oxide film 35 to form a metal such as NiSiO. The silicide oxide layer 45 is formed. The heat treatment performed in the heat treatment step S70 may be performed by a high temperature furnace, rapid heat treatment (RTA), ultraviolet (UV) heating, or the like. The metal silicide oxide layer 45 formed in the heat treatment step S70 serves as a nucleus for crystallizing the second silicon layer 50 in the crystallization step S90 described later. The heat treatment temperature in the heat treatment step (S70) is preferably 50 ℃ to 1000 ℃. When the heat treatment temperature of the heat treatment step (S70) is less than 50 ℃ there is a problem that the metal silicide oxide layer 45 is not formed well. If the heat treatment temperature of the heat treatment step (S70) exceeds 1000 ℃ there is a problem that the glass substrate (10) is deformed or damaged by heat shock. The thickness of the metal silicide oxide layer 45 formed in the heat treatment step (S70) is preferably 15 kPa to 3000 kPa. If the thickness of the metal silicide oxide layer 45 is less than 15 μm, it is difficult to implement the process and the overall thickness uniformity is poor. When the thickness of the metal silicide oxide layer 45 exceeds 3000 kV, there is a problem in that unnecessary chemical bonds are generated due to the thick oxide layer.

In the second silicon layer forming step (S80), an amorphous silicon layer is stacked on the metal silicide oxide layer 45 to form a second silicon layer 50. As the method of forming the second silicon layer 50, the method employed in the first silicon layer forming step S60 may be adopted.

In the crystallization step (S90), heat treatment is performed such that the crystalline silicon 60 is generated in the second silicon layer 50 using the metal particles of the metal silicide oxide layer 45 as a catalyst. The heat treatment temperature in the crystallization step (S90) is preferably 300 ℃ to 1000 ℃. In this embodiment, the heat treatment in the crystallization step (S90) was performed at 630 ° C using Rapid Thermal Annealing (RTA) equipment. When the heat treatment temperature of the crystallization step (S90) is less than 300 ℃ there is a problem that the crystallization is not good because the temperature is low to crystallize. When the heat treatment temperature of the crystallization step (S90) exceeds 1000 ° C., the substrate 10 may be deformed or broken due to thermal shock.

8 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention under an optical microscope. FIG. 9 is a graph analyzing the wave number of the polycrystalline silicon thin film illustrated in FIG. 8. 10 is an experimental result comparing the grain size of the polycrystalline silicon thin film manufactured by the present invention with the grain size of the polycrystalline silicon thin film manufactured by the conventional method.

In FIG. 9, the horizontal axis represents a wave number (cm ⁻¹ ) and corresponds to a frequency. Wave number is a unit of frequency that represents the number of waves in unit distance by dividing the frequency of light by the speed of light in atomic, molecular, and nuclear spectroscopy. In other words, the frequency of a wave is represented by the Greek letter ν (nu), which is equal to the luminous flux c divided by the wavelength λ. That is, ν〓c / λ. In the visible region of the spectrum, a typical spectral line has a wavelength of 5.8 × 10 ⁻⁵ cm and corresponds to a frequency of 5.17 × 10 ¹⁴ kHz. However, because such a frequency has a value that is too large, it is convenient to divide the number by the speed of light to reduce the size. The frequency divided by the speed of light is ν / c, which is 1 / λ in the above equation. When the wavelength is measured in m, 1 / λ represents the number of waves found within 1m. The wavenumber is usually measured in units of 1 / m, i.e. m- ¹ and 1 / cm, i.e. cm- ¹ . In FIG. 9, the vertical axis is a sum of waves measured per unit time and corresponds to intensity (CPS, Count Per Second).

Referring to FIG. 9, the maximum strength is shown at 520 cm ⁻¹ , indicating that crystalline silicon is well formed. 8 is a photograph of the surface of the polycrystalline silicon thin film prepared according to the present invention with a 1000 times optical microscope. FIG. 10 cited experimental data comparing sizes of polycrystalline silicon grains prepared by the conventional method shown in FIG. 1 with respect to grain sizes of polycrystalline silicon prepared according to the present invention. 10 shows that when evaluating the grain size of a polycrystalline silicon thin film generally used for solar cells, an arbitrary region of the polycrystalline silicon thin film formed on the substrate is set to 10 cm × 10 cm and the grains present in that region are determined. This is the result of measuring the ratio of the size of 20 micrometers or more. Referring to FIG. 10, the polycrystalline silicon thin film manufactured by the conventional method was measured at 0% ratio, while the polycrystalline silicon thin film manufactured according to the present invention was measured at 90% ratio. As such, it can be seen that the manufacturing method according to the present invention is remarkably superior in quality of the crystallized silicon as compared to the conventional method. In addition, the manufacturing method according to the present invention is capable of efficient heat treatment in the heat treatment process by the first metal layer and provides an effect of improving the yield by inhibiting damage to the substrate by thermal shock even in the repeated heat treatment process.

Meanwhile, in the second embodiment according to the present invention as a modified example of the above-described embodiment, the material stacked in the forming of the second silicon layer may be formed of amorphous silicon germanium (SiGe) or amorphous silicon carbide (SiC) instead of amorphous silicon. Replace. As a result, it will be apparent that the material formed in the crystallization step will be polycrystalline silicon germanium (SiGe) or amorphous silicon carbide (SiC).

While the present invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not to be limited by the example, and various changes and modifications may be made without departing from the spirit and scope of the invention.

10: substrate 15: first metal layer
20: insulating layer 25: second metal layer
30 catalyst layer 35 metal oxide film
40: first silicon layer 45: metal silicide oxide layer
50: second silicon layer 60: crystalline silicon
S10: forming the first metal layer S20: forming the insulating layer
S25: forming the second metal layer S30: patterning step
S40: catalyst layer forming step S50: metal oxide film forming step
S60: first silicon layer forming step S70: heat treatment step
S80: forming the second silicon layer S90: crystallization step

Claims (5)

Forming a first metal layer on the substrate;
An insulating layer forming step of forming an insulating layer on the first metal layer;
A second metal layer forming step of forming a second metal layer on the insulating layer;
A catalyst layer forming step of forming a catalyst layer by stacking the second metal layer and another metal on the second metal layer;
Forming a metal oxide film by heat-treating the catalyst layer or forming a metal oxide film by depositing a metal oxide film on the catalyst layer;
Forming a first silicon layer by stacking an amorphous silicon layer on the metal oxide film;
A heat treatment step of moving the catalyst metal atoms from the catalyst layer to the first silicon layer to form a metal silicide oxide layer;
Forming a second silicon layer by laminating an amorphous silicon layer on the metal silicide oxide layer;
And a crystallization step of heat treating the crystalline silicon in the second silicon layer by using the metal particles of the metal silicide oxide layer as a catalyst. The method of claim 1,
Metals forming the second metal layer include chromium (Cr), molybdenum (Mo), tantalum (Ta), tungsten (W), iridium (Ir), AZO (zinc oxide), cadmium (Cd), and manganese (Mn) Method for producing a polycrystalline silicon thin film, characterized in that any one of. The method of claim 1,
And patterning an electrode pattern on the second metal layer by removing a portion of the second metal layer by a photolithography method or a lift-off method after the forming of the second metal layer. The method of claim 3,
The electrode pattern has a thickness of 6 ~ 100㎛ manufacturing method of a polycrystalline silicon thin film. 5. The method according to any one of claims 1 to 4,
The method of manufacturing a polycrystalline silicon thin film, characterized in that the material laminated on the second silicon layer is substituted with amorphous silicon germanium (SiGe) or amorphous silicon carbide (SiC).

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