TWI449134B - 積體封裝 - Google Patents
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- TWI449134B TWI449134B TW094143257A TW94143257A TWI449134B TW I449134 B TWI449134 B TW I449134B TW 094143257 A TW094143257 A TW 094143257A TW 94143257 A TW94143257 A TW 94143257A TW I449134 B TWI449134 B TW I449134B
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Description
本發明係關於積體電路之封裝,且尤其係關於包括在一全密式密封腔中待封裝之元件的積體電路之封裝。
對於較薄封裝之需求愈來愈大。此外,對於在一單一封裝中組合一個以上裝置(通常已知為"系統級封裝"(SIP))的需求愈來愈大。此已封裝裝置可為一完整模組。因此,需要較薄裝置。
一些裝置包括需在一全密式外罩中加以封裝之敏感元件。該等裝置包括微機電系統(MEMS)裝置、聲波濾波器及諧振器。此對於一全密式外罩之需求增加此等裝置之厚度,使其比常規預封裝裝置或裸晶粒電路的厚度大,此可使得其難以包含於一SIP中。
一用於裝置之封閉封裝的現有解決方法已知為晶片尺度封裝(CSP)。在此方法中,裝置包括一載運敏感元件之基板。敏感元件安裝於一以一蓋密封之封裝體中。通常封裝體由塑料材料製成。此方法相當於一小型習知封裝,且該裝置之尺寸(詳言之該裝置之厚度)可經常危及其於一模組中之包括。
一替代方法為晶圓級封裝(WLP)。在此方法中,如圖1所說明,一基板2在一表面6上具有一敏感元件4。一蓋8密封至此表面6,界定一含有該敏感元件之腔10。經由蓋8之通道12提供電連接至基板,且覆晶凸塊14係提供於通道上,以允許晶圓級封裝在一模組內得以接合。
然而,當安裝於一模組基板上時,該WLP封裝保持顯著厚於一裸晶粒。
根據本發明,提供一種積體半導體裝置,其包括:一裝置基板,其具有一裝置主表面、一在該裝置主表面上之半導體元件及越過該裝置主表面延伸之導電裝置連接器;及一互連基板,其具有一互連主表面,該互連基板界定自該互連主表面凹陷之至少一密封凹座,該密封凹座由一密封環圍繞;其中該裝置基板係安裝於該互連基板上且該互連主表面面向該裝置主表面,該密封環在半導體元件周圍且該裝置主表面緊靠該密封環而得以密封,使得該凹座形成一含有該半導體元件的密封腔;該積體半導體裝置進一步包含:越過該互連主表面之電互連;及在該密封環外部之互連凸塊,該等互連凸塊將該等裝置電連接器電連接至該等互連。
藉由使用此方法,可將一需要全密式密封之半導體元件作為一裸晶粒安裝於整合基板上,該密封環視需要而密封半導體元件。因此,本發明在一較薄配置中提供一密封電元件。已安裝裝置之總厚度不厚於裝置與互連基板厚度之和。因此,一需要全密式密封之裝置基板可以一導致厚度不大於一不需要任何密封之單裸晶粒的方式安裝。
該裝置較佳包括在互連主表面上之密封環周圍的至少一接合渠溝。該接合渠溝可容納一或多個互連凸塊。該渠溝可便利地為一完全圍繞密封環之渠溝,意即以一同心環繞密封環之環渠溝的形式,或者,在密封環周圍可有複數個接合渠溝,每一接合渠溝固持一或多個互連凸塊。
以此方式,可提供裝置與互連基板之習知凸塊接合而不干擾密封環之密封或增加基板之厚度。
在較佳實施例中,至少一額外半導體裝置安裝於互連基板上。該裝置基板可藉由電互連連接至該至少一額外半導體裝置。因此,整合基板本身係互連一模組之各種半導體組件的基板。請注意,額外半導體裝置可以與第一半導體裝置相同之方式安裝用於全密式密封,或其可習知地加以安裝。
互連基板可界定一用於固持半導體裝置之裝置凹座,半導體裝置、密封環及密封凹座係提供於該裝置凹座內。其進一步減小總厚度。
較佳地,該半導體裝置不延伸出互連主表面。以此方式,半導體裝置及整合基板之總厚度不超過整合基板的厚度。
在實施例中,可使用此來形成一極薄裝置。
一額外半導體裝置可安裝於在裝置凹座上延伸之互連主表面上。因此,對一裝置凹座之使用允許額外裝置覆蓋裝置凹座中之裝置,以節省空間。
整合基板可由矽製成。矽表示一形成密封凹座、密封環及(若必要)接合渠溝及裝置凹座之便利材料。
在另一態樣中,提供一種安裝一裝置基板之方法,該裝置基板具有一裝置主表面、一在該裝置主表面上之半導體元件及在該裝置主表面上之裝置電連接器,該方法包含:提供一具有一互連主表面及越過該互連主表面之電互連的互連基板,該互連基板界定自該互連主表面凹陷之至少一密封凹座,該密封凹座係由一密封環圍繞;在該等電互連或電連接墊上形成互連凸塊;對準裝置基板與互連基板且互連主表面面向裝置主表面,密封環在半導體元件周圍;且互連凸塊在裝置電連接器與互連之間對準;及將裝置基板接合至互連基板且裝置主表面緊靠密封環得以密封,使得凹座形成一含有半導體元件的密封腔,且互連凸塊連接裝置電連接器及電互連。
較佳地,該提供一互連基板之步驟包括:蝕刻密封凹座及在一基板之互連主表面中之密封凹座周圍的至少一接合渠溝;及在包括至少一接合渠溝中之互連主表面上沉積電互連。
在另一態樣中,本發明係關於一種用於安裝一裝置基板之互連基板,該裝置基板具有一裝置主表面、一在該裝置主表面上之半導體元件及在該裝置主表面上之裝置電連接器,其中該互連基板包含:一互連主表面;越過該互連主表面延伸之電互連;自互連主表面凹陷之至少一密封凹座;一圍繞該密封凹座之密封環;在該密封環周圍及外部之接合墊,其用於經由互連凸塊連接至裝置主表面上之裝置電連接器,使得裝置基板可安裝於互連基板上且互連主表面面向裝置主表面,密封環在半導體元件周圍且裝置主表面緊靠密封環得以密封,使得凹座形成一含有半導體元件之密封腔。
參看圖2,一矽半導體裝置基板2在一第一主表面6(在下文將稱為裝置主表面)上具有一表面聲波(SAW)濾波裝置元件4。該矽基板之裝置主表面6具有沿其延伸之裝置電連接器16,其藉由接合線18連接至裝置元件4。或者,可藉由一在裝置基板2內之一底部導電層或多層形成連接。
另一半導體基板20充當一被動互連基板。此互連基板20可於圖2之側視圖及圖3之俯視圖中看出。
互連基板20具有一第一主表面21,其將稱為互連主表面21以避免與裝置主表面6混淆。
為向一裝置提供一安裝點,一凹座24形成於互連主表面中。在凹座24周圍,提供為在凹座24周圍之環之形式的另一凹座26,該凹座26由於稍後將變得顯而易見而被稱為接合渠溝26。
在凹座24與接合渠溝26之間有互連基板之一環形部分,其將稱為密封環22。密封環22在整個凹座24周圍延伸。該實施例中之密封環22因此在第二主表面21之水平面處,並且相應地相對於凹座24上升。
在互連基板20上提供金屬互連30,該等金屬互連30延伸入接合渠溝26。如圖3所示,此等互連30之端得以加寬以提供接合墊32。
互連基板便利地由矽製成,使得其可直接製造凹座24、渠溝26及密封環22,且沉積互連30。
在使用中,為將矽基板2安裝於互連基板20上,接合"凸塊"28形成於裝置主表面上之互連16上。可使用任一適當材料以形成此等凸塊,且熟習此項技術者將瞭解若干該單一材料或材料組合。矽基板經配置以使得裝置主表面6面向互連主表面21且MEMS元件4面向凹座24。
接著集合裝置基板2及互連基板20,使得裝置主表面接觸密封環22,凹座24從而形成一密封裝置元件4之全密式密封腔24。
同時,接合凸塊28接觸接合墊32。接合凸塊之接合可遵循使用熟習此項技術者已知的技術,例如,假使凸塊為焊料凸塊,則回焊接合凸塊28;或簡單應用壓力或熱與壓力。應注意,凸塊28終止於接合渠溝26中且因此由凸塊引起之任何額外厚度不會增加最終裝置之厚度。
藉由在密封環外部配置接合凸塊,密封環之密封基本上獨立於電互連。
此外,若使用一回焊處理來熔合接合凸塊,則熔合之接合凸塊之毛細作用將傾向於促使基板集合在一起,從而輔助一較佳密封。
如在圖3中可看出,互連基板包括若干凹座24,每一凹座用於接合一獨立基板2。為清楚起見,在圖3中以虛線展示僅一個該基板2。
亦可使用相同互連基板來安裝不需要全密式密封之習知晶片38。此等晶片可安裝於具有連接至互連30之複數個接合墊34的額外晶片安裝點36上。此實施例中之額外晶片安裝點36不具有凹座或接合渠溝並且可便利地係平坦的,以避免需要額外處理。然而,在替代實施例中,可用類似於需要全密式密封之裝置基板2的方式來安裝所有額外晶片。
圖4展示一第二實施例,其中裝置凹座40提供於互連基板20中。此等凹座足夠大以容納裝置基板2。
在此實施例中,裝置元件為一MEMS元件4。
密封環22、凹座24及接合渠溝26提供於裝置凹座的基底。當裝置基板2如圖1之實施例加以安裝時,裝置基板2整個包含於裝置凹座40中且並未延伸出互連主表面21。
此意味互連基板20與裝置基板2之總厚度不大於互連基板20之厚度。
此方法之一進一步益處為:一額外裝置42可安裝於裝置凹座40之上,使用額外凸塊44以連接至接合墊34,該接合墊34又連接至互連30,互連30在所示之實例中經由接合墊32、接合凸塊28、互連16及接合線18連接至MEMS裝置元件4。
因此,在此實施例中,額外裝置42有效地覆蓋裝置2,因此節省互連基板20之面積。
第一及第二實施例皆易於實施而無額外處理成本。
此等實施例之各種修正係可能的。
所述之安裝技術並非僅可用於接合SAW或MEMS裝置,且可用於任一裝置,尤其係具有需要一全密式密封腔之敏感元件的裝置。熟習此項技術者將瞭解,基板2無需由矽製成,且可為另一半導體如GaAs或InP、或絕緣體如石英或藍寶石,或任一其它基板材料。
互連基板20不必要由矽製成,且包括陶瓷或塑料之其它材料亦可加以使用。
視情況,若需要改良密封,則可尤其在密封環22上提供額外密封材料。然而,此通常係不需要的。
儘管在上述實施例中互連基板係被動的,但是若需要則可使用包括主動裝置之主動基板。
若在互連基板中使用一裝置凹座,則在實施例中裝置基板可延伸於互連主表面之水平面之上。
在所述實施例中之額外裝置使用凸塊技術加以附著。然而,亦可能以任一已知方式將額外裝置安裝於互連基板上,該已知方式包括例如藉由附著其且使非主動側面向基板且接著使用線接合來將其電連接至互連。
2...裝置基板
4...半導體元件/敏感元件
6...裝置主表面
8...蓋
10...腔
12...通道
14...覆晶凸塊
16...裝置電連接器/電連接墊/互連
18...接合線
20...互連基板
21...互連主表面
22...密封環
24...密封凹座/腔
26...接合渠溝/凹座
28...互連凸塊
30...電互連
32...接合墊
34...接合墊
36...額外晶片安裝點
38...習知晶片/額外半導體裝置
40...裝置凹座
42...額外半導體裝置
44...額外凸塊
圖1展示一先前技術封裝;圖2展示本發明之一第一實施例的側截面;圖3展示本發明之一第一實施例的俯視圖;及圖4展示本發明之一第二實施例的側截面。
類似組件以類似參考數字在不同圖式中給出,其純粹係示意性的且並未按比例繪製。
2...裝置基板
4...半導體元件/敏感元件
6...裝置主表面
16...裝置電連接器/電連接墊/互連
18...接合線
20...互連基板
21...互連主表面
22...密封環
24...密封凹座/腔
26...接合渠溝/凹座
28...互連凸塊
30...電互連
Claims (11)
- 一種積體半導體裝置,其包括:一裝置基板(2),其具有一裝置主表面(6)、一在該裝置主表面(6)上之半導體元件(4)及越過該裝置主表面(6)延伸之導電裝置連接器(16);及一互連基板(20),其具有一互連主表面(21),該互連基板(20)界定自該互連主表面(21)凹陷之至少一密封凹座(24),該密封凹座(24)係由一密封環(22)圍繞;其中該裝置基板(2)係安裝於該互連基板(20)上且該互連主表面(21)面向該裝置主表面(6),該密封環(22)在該半導體元件(4)周圍且該裝置主表面(6)緊靠該密封環(22)得以密封,使得該凹座(24)形成一含有該半導體元件(4)的密封腔;該積體半導體裝置進一步包含:越過該互連主表面(21)之電互連(30);及在該密封環(22)外部之互連凸塊(28),該等互連凸塊(28)將該等裝置電連接器(16)電連接至該等互連(30)。
- 如請求項1之積體半導體裝置,其進一步包含在該互連主表面上之該密封環(22)周圍的至少一接合渠溝(26),用於容納該等互連凸塊(28)中之一或多者。
- 如請求項1或2之積體半導體裝置,其進一步包含安裝於該互連基板(20)上之至少一額外半導體裝置(38);其中該裝置基板(2)係藉由該等互連(30)連接至該至少一額外半導體裝置(38)。
- 如請求項1或2之積體半導體裝置,其中該互連基板(20)界定一用於固持該裝置基板(2)之裝置凹座(40),其中該密封環(22)及密封凹座(24)係提供於該裝置凹座(40)內。
- 如請求項4之積體半導體裝置,其進一步包含一安裝於該互連基板(20)上之額外半導體裝置(42);其中該額外半導體裝置(42)係安裝於該互連主表面(21)上且越過該裝置凹座延伸。
- 如請求項1或2之積體半導體裝置,其中該互連基板(20)係由矽所製成。
- 一種用於安裝一裝置基板(2)的互連基板,該裝置基板(2)具有一裝置主表面(6)、一在該裝置主表面上之半導體元件(4)及在該裝置主表面(6)上之裝置電連接器(16),其中該互連基板包含:一互連主表面(21);越過該互連主表面(21)延伸之電互連(30);自該互連主表面凹陷之至少一密封凹座(24);一圍繞該密封凹座之密封環(22);在該密封環(22)周圍及外部之接合墊(32),其用於經由互連凸塊(28)連接至該裝置主表面(6)上之該等裝置電連接器(16),使得該裝置基板(2)可安裝於該互連基板(20)上且該互連主表面(21)面向該裝置主表面(6),該密封環(22)在該半導體元件(4)周圍且該裝置主表面(6)緊靠該密封環(22)得以密封,使得該凹座(24)形成一含有該半導體元件(4)的密封腔。
- 如請求項7之互連基板,其進一步包含在該密封環(22)周圍的至少一接合渠溝(26),用於容納一或多個互連凸塊(28)。
- 一種安裝一裝置基板(2)的方法,該裝置基板(2)具有一裝置主表面(6)、一在該裝置主表面(6)上之半導體元件(4)及在該裝置主表面(6)上之裝置電連接器(16),該方法包含:提供一具有一互連主表面(21)及越過該互連主表面之電互連(30)的互連基板(20),該互連基板(20)界定自該互連主表面(21)凹陷之至少一密封凹座(24),該密封凹座係由一密封環(22)圍繞;在該等電互連(30)或該等電連接墊(16)上形成互連凸塊(28);對準該裝置基板(2)與該互連基板(20)且該互連主表面(21)面向該裝置主表面(6),該密封環(22)在該半導體元件(4)周圍;且該等互連凸塊(28)在該等裝置電連接器(16)與該等互連(30)之間對準;及將該裝置基板(2)接合至該互連基板(20)且該裝置主表面(6)緊靠該密封環(22)得以密封,使得該凹座(24)形成一含有該半導體元件(4)之密封腔且該等互連凸塊(28)連接該等裝置電連接器(16)及該等電互連(30)。
- 如請求項9之方法,其中該提供一互連基板之步驟包括:蝕刻該密封凹座及在該互連主表面中之該密封凹座周圍的至少一接合渠溝;及在包括該至少一接合渠溝中之該互連主表面上沉積該電互連。
- 如請求項9或10之方法,其中該將該裝置基板(2)接合至該互連基板(20)之步驟包括:熔合該等互連凸塊(28)且允許該等熔合之互連凸塊(28)固化。
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EP2259018B1 (en) | 2009-05-29 | 2017-06-28 | Infineon Technologies AG | Gap control for die or layer bonding using intermediate layers of a micro-electromechanical system |
DE102009036033B4 (de) * | 2009-08-04 | 2012-11-15 | Austriamicrosystems Ag | Durchkontaktierung für Halbleiterwafer und Herstellungsverfahren |
US8390083B2 (en) | 2009-09-04 | 2013-03-05 | Analog Devices, Inc. | System with recessed sensing or processing elements |
WO2012051340A1 (en) | 2010-10-12 | 2012-04-19 | Analog Devices, Inc. | Microphone package with embedded asic |
GB2516079A (en) | 2013-07-10 | 2015-01-14 | Melexis Technologies Nv | Method for hermetically sealing with reduced stress |
US9847462B2 (en) | 2013-10-29 | 2017-12-19 | Point Engineering Co., Ltd. | Array substrate for mounting chip and method for manufacturing the same |
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