WO2006061792A3 - Hermetically sealed integrated circuit package - Google Patents

Hermetically sealed integrated circuit package Download PDF

Info

Publication number
WO2006061792A3
WO2006061792A3 PCT/IB2005/054119 IB2005054119W WO2006061792A3 WO 2006061792 A3 WO2006061792 A3 WO 2006061792A3 IB 2005054119 W IB2005054119 W IB 2005054119W WO 2006061792 A3 WO2006061792 A3 WO 2006061792A3
Authority
WO
WIPO (PCT)
Prior art keywords
major surface
interconnection
substrate
sealing ring
integrated circuit
Prior art date
Application number
PCT/IB2005/054119
Other languages
French (fr)
Other versions
WO2006061792A2 (en
Inventor
Fabrice Verjus
Jean-Marc Yannou
David Chevrie
Francois Lecornec
Veen Nicolaas J A Van
Original Assignee
Koninkl Philips Electronics Nv
Fabrice Verjus
Jean-Marc Yannou
David Chevrie
Francois Lecornec
Veen Nicolaas J A Van
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Fabrice Verjus, Jean-Marc Yannou, David Chevrie, Francois Lecornec, Veen Nicolaas J A Van filed Critical Koninkl Philips Electronics Nv
Publication of WO2006061792A2 publication Critical patent/WO2006061792A2/en
Publication of WO2006061792A3 publication Critical patent/WO2006061792A3/en
Priority to US12/702,041 priority Critical patent/US8237256B2/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/058—Holders; Supports for surface acoustic wave devices
    • H03H9/059—Holders; Supports for surface acoustic wave devices consisting of mounting pads or bumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1057—Mounting in enclosures for microelectro-mechanical devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1071—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS

Abstract

A device substrate (2) has a device major surface (6), a semiconductor element (4) on the device major surface (6), and electrically conductive device connectors (16) extending across the device major surface (4). An interconnection substrate has an interconnection substrate (20) having an interconnection major surface (21 ), the interconnection substrate (20) defining at least one sealing recess (24) recessed from the interconnection major surface (21 ) , the sealing recess (24) being surrounded by a sealing ring (22). The device substrate (2) is mounted on the interconnection substrate (20) with the interconnection major surface (21 ) facing the device major surface (6), the sealing ring (22) around the semiconductor element (4) and with the device major surface (6) sealed against the sealing ring (22) so that the recess (24) forms a sealed cavity containing the semiconductor element (4). Electrical interconnects (30) extend across the interconnection major surface (21 ). Interconnection bumps (28) are provided outside the sealing ring (22) to electrically connect the device (2) to the interconnect substrate (20).
PCT/IB2005/054119 2004-12-10 2005-12-08 Hermetically sealed integrated circuit package WO2006061792A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/702,041 US8237256B2 (en) 2004-12-10 2010-02-08 Integrated package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04300878 2004-12-10
EP04300878.8 2004-12-10

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11721435 A-371-Of-International 2005-12-08
US12/702,041 Continuation US8237256B2 (en) 2004-12-10 2010-02-08 Integrated package

Publications (2)

Publication Number Publication Date
WO2006061792A2 WO2006061792A2 (en) 2006-06-15
WO2006061792A3 true WO2006061792A3 (en) 2006-08-31

Family

ID=36370856

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/054119 WO2006061792A2 (en) 2004-12-10 2005-12-08 Hermetically sealed integrated circuit package

Country Status (2)

Country Link
TW (1) TWI449134B (en)
WO (1) WO2006061792A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8767983B2 (en) 2007-06-01 2014-07-01 Infineon Technologies Ag Module including a micro-electro-mechanical microphone
WO2009145726A1 (en) * 2008-05-27 2009-12-03 Agency For Science, Technology And Research Micro electro mechanical device package and method of manufacturing a micro electro mechanical device package
EP2259018B1 (en) 2009-05-29 2017-06-28 Infineon Technologies AG Gap control for die or layer bonding using intermediate layers of a micro-electromechanical system
DE102009036033B4 (en) * 2009-08-04 2012-11-15 Austriamicrosystems Ag Through-hole for semiconductor wafers and manufacturing process
US8390083B2 (en) 2009-09-04 2013-03-05 Analog Devices, Inc. System with recessed sensing or processing elements
US9407997B2 (en) 2010-10-12 2016-08-02 Invensense, Inc. Microphone package with embedded ASIC
GB2516079A (en) * 2013-07-10 2015-01-14 Melexis Technologies Nv Method for hermetically sealing with reduced stress
CN104576883B (en) 2013-10-29 2018-11-16 普因特工程有限公司 Chip installation array substrate and its manufacturing method
US9666558B2 (en) 2015-06-29 2017-05-30 Point Engineering Co., Ltd. Substrate for mounting a chip and chip package using the substrate

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049978A (en) * 1990-09-10 1991-09-17 General Electric Company Conductively enclosed hybrid integrated circuit assembly using a silicon substrate
US20020043706A1 (en) * 2000-06-28 2002-04-18 Institut National D'optique Miniature Microdevice Package and Process for Making Thereof
US6661084B1 (en) * 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window
US6713876B1 (en) * 1999-11-04 2004-03-30 Stmicroelectronics S.A. Optical semiconductor housing and method for making same
US20040077154A1 (en) * 2002-10-17 2004-04-22 Ranganathan Nagarajan Wafer-level package for micro-electro-mechanical systems
EP1433742A2 (en) * 2002-12-27 2004-06-30 Shinko Electric Industries Co. Ltd. Electronic devices and production methods

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6878040B2 (en) * 2002-08-30 2005-04-12 Wei-Min Wang Method and apparatus for polishing and planarization
KR100447851B1 (en) * 2002-11-14 2004-09-08 삼성전자주식회사 Wafer level Bonding method of flip-chip manner for semiconductor apparatus in lateral bonded type

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049978A (en) * 1990-09-10 1991-09-17 General Electric Company Conductively enclosed hybrid integrated circuit assembly using a silicon substrate
US6713876B1 (en) * 1999-11-04 2004-03-30 Stmicroelectronics S.A. Optical semiconductor housing and method for making same
US6661084B1 (en) * 2000-05-16 2003-12-09 Sandia Corporation Single level microelectronic device package with an integral window
US20020043706A1 (en) * 2000-06-28 2002-04-18 Institut National D'optique Miniature Microdevice Package and Process for Making Thereof
US20040077154A1 (en) * 2002-10-17 2004-04-22 Ranganathan Nagarajan Wafer-level package for micro-electro-mechanical systems
EP1433742A2 (en) * 2002-12-27 2004-06-30 Shinko Electric Industries Co. Ltd. Electronic devices and production methods

Also Published As

Publication number Publication date
TWI449134B (en) 2014-08-11
TW200639983A (en) 2006-11-16
WO2006061792A2 (en) 2006-06-15

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