TWI429053B - 射頻超壓模導線架封裝件 - Google Patents
射頻超壓模導線架封裝件 Download PDFInfo
- Publication number
- TWI429053B TWI429053B TW095118985A TW95118985A TWI429053B TW I429053 B TWI429053 B TW I429053B TW 095118985 A TW095118985 A TW 095118985A TW 95118985 A TW95118985 A TW 95118985A TW I429053 B TWI429053 B TW I429053B
- Authority
- TW
- Taiwan
- Prior art keywords
- pin
- capacitor
- package
- circuit board
- wire
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30105—Capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
本發明有關於毫米波(millimeter-wave)封裝,特別是四方扁平無引腳(quad flat no-lead,QFN)封裝。
目前,低成本元件封裝包含使用陶瓷螺栓向下封裝件(ceramic bolt-down packages)、軟基板螺栓向下封裝件(soft substrate bolt-down packages)、基於印刷電路板的(PCB-based)封裝件,以及超模壓導線架封裝件(over-molded leadframe packages)。超模壓導線架封裝件,特別是四方扁平無引腳(QFN)封裝件為這些封裝形式中成本最低者。超模壓導線架封裝件的分類包含但不限於以下數種:小外形塑膠封裝件(SOIC)、四分之一尺寸小外形封裝件(QSOP)、超薄緊縮小外形塑膠封裝件(TSSOP)、微小外形塑膠封裝件(MSOP)、雙列扁平無引腳塑膠封裝件(DFN)、四方扁平無引腳塑膠封裝件(QFN)、小外形電晶體塑膠封裝件(SOT),小外形電晶體塑膠封裝件(SC70-6)、緊縮小外形塑膠封裝件(SSOP)、塑膠雙列直插式封裝件(PDIP)、緊縮塑膠雙列直插式封裝件(SPDIP)、微引腳塑膠封裝件(MLFP)、功率小外形塑膠封裝件(PSOP)、塑膠帶引腳晶片載體封裝件(PLCC)、公制四方扁平塑膠封裝件(MQFP)、超薄四方扁平塑膠封裝件(TQFP)、超薄塑膠功率四方扁平封裝件(PQ-LQFP)、單邊插腳塑膠封裝件(SIP)、以及球柵陣列封裝件(BGA)。這些超模壓導線架封裝件的電子特性於高頻時都面臨到明顯的性能減退,也因
此限制這種封裝件只能在15GHz以下的使用。這些性能的減退包含由積體電路晶片/打線/印刷電路板介面間的能量損耗及阻抗不匹配。
典型的QFN封裝件之打線通常是由一條或二條打線控制。這些打線的作用,如電感或其他類似電路,而就是這些打線產生的電感效應降低了典型QFN封裝件的性能。因此,需要一種QFN封裝件,其能降低或抵銷一條或多條打線所產生電感效應。
於一例舉的實施例中,一種超模壓導線架封裝件包含:一導線架;一超模壓材料,環繞部分該導線架且形成該超模壓導線架封裝件之一底部表面,其中該底部表面係組態成與一印刷電路板(PCB)連接;一積體電路,電性連接該導線架且包含於該超模壓導線架封裝件內;以及一電容引腳,位於該超模壓導線架封裝件內,其中該電容引腳係置於該超模壓導線架封裝件內,而未接觸該印刷電路板,且其中該電容引腳係組態成用於形成一電容之一第一部分,以對齊該印刷電路板上之一相對應電容引腳。
於另一例舉的實施例中,一種超模壓導線架封裝件包含:一電容引腳,組態成用於形成該超模壓導線架封裝件內之一電容的一部分;以及至少一打線,連接該電容引腳並連接一積體電路,其中該積體電路係置於該超模壓導線架封裝件內;其中,該電容引腳係組態成用於對齊一印刷電路板內之一相對應電容引腳,亦組態成用於降低與抵銷該至少一打線所產生的電感。
於另一例舉的實施例中,一種超模壓導線架封裝件包
含:一輸入/輸出引腳;以及一電容引腳,打線至該輸入/輸出引腳;其中,該電容引腳無法與該超模壓導線架封裝件外之任何東西形成實體接觸。
於另一例舉的實施例中,一種超模壓導線架封裝件包含:至少一隆起引腳(raised lead),其中該至少一隆起引腳為一個雙平板電容的一第一平板,且該雙平板電容僅藉由將該超模壓導線架封裝件安裝(mount)於一印刷電路板上而形成,其中該印刷電路板包含該雙平板電容的一第二平板。
另一例舉的實施例揭露一種製造電子元件的方法。該電子元件包含一封裝件,該封裝件包含一積體電路晶片、一第一引腳、以及一第二引腳,該方法包含:將一第一打線耦合至該積體電路晶片與該第一引腳;將一第二打線耦合至該第一引腳與該第二引腳,其中該第一引腳為一電容引腳,且包含一個雙平板電容的一平板,其中該第一引腳係組態成不與一印刷電路板接觸,其中該第二引腳為一射頻輸入/輸出引腳,且具有一表面,而該表面係與該封裝件之一表面齊平,其中該第二引腳係組態成與該印刷電路板接觸,其中該印刷電路板更包含一金屬區;以及實質上將該印刷電路板上之該金屬區對齊該第一引腳,因而該印刷電路板之該金屬區形成該雙平板電容之一第二平板。
於另一例舉的實施例中,一種超模壓導線架封裝件,包含:一導線架;一超模壓材料,環繞部分該導線架且形成該超模壓導線架封裝件之一底部表面,其中該底部表面連接一印刷電路板(PCB);一積體電路,電性連接該導線架且包含於該超模壓導線架封裝件內;一電容引腳,位於該超模壓導線架封裝件內,其中該電容引腳係置於該超模
壓導線架封裝件內,而未接觸該印刷電路板,且其中該電容引腳形成一電容之一第一部分,以對齊該印刷電路板上之一相對應電容引腳;以及一介電空間,形成於該電容引腳與該印刷電路板上之該相對應電容引腳之間。
於此參閱附隨的圖式,本發明例舉的實施例將詳細地描述,其藉圖例說明以及最佳運作模式來呈現例舉的實施例。雖然這些例舉的實施例盡可能地詳細描述,使熟悉本發明人士能實施本發明,但應該瞭解於那些基於邏輯與機械修飾且不失本發明精神與範圍的改變下,亦可實施其他實施例。因此,於此詳細地描述僅是為了說明目的,而非限制本發明範圍。例如,任何方法或過程中所提到的步驟有可能以不同的順序實現,而不限於例示的順序。
為了簡潔起見,裝置與系統中的功能性實施例(與系統中單獨運作的元件)將不會詳細地介紹。而且,顯示在本文不同圖中的連接線是為了表示例舉的功能關係及/或不同元件間的物理連接。要注意到在實際的系統中可能會有許多變化或額外的功能性關係或物理連接。
本發明許多實施例包含但不限於:放大器(例如,功率放大器、低雜訊放大器及其他類似物)、相移器、混波器、切換器及其他類似物。在例舉的實施例中,這些電子裝置用來降低及/或抵銷打線所產生之不想要的電感,這些打線通常是用來將訊號從積體電路晶片傳送到電路板。藉由降低及/或抵銷打線所產生的電感,現有電子裝置所面臨的性能減退情況也能因此減小及/或實質地消除。因此,本發明實施例,使得通常用在低頻段的電子裝置可被轉換及/或製
造供高頻段應用(例如,從5千兆赫(GHz)到300GHz,較佳是從20GHz到40GHz之範圍)。也就是說,本發明之實施例提高一般QFN封裝件之運作頻率。
現在參考圖式,圖1為一超模壓導線架之一例舉的實施例之示意圖,即可在高頻操作的一QFN封裝件100。
於一例舉的實施例之一態樣,QFN封裝件100也包含一個單晶微波積體電路(〝MMIC〞)晶片120。MMIC晶片120可能是任何習知技術中習知的或即將發展的單晶微波積體電路晶片。在一實施例中,MMIC晶片120是一個運作在Ku頻段的單晶微波積體電路晶片。在另一實施例中,MMIC晶片120是一個運作在頻率高於Ku頻段的單晶微波積體電路晶片。在另一實施例中,MMIC晶片120是一個運作頻率在5千兆赫(GHz)至300GHz,較佳是20GHz至40GHz之頻段間的單晶微波積體電路晶片。此外,本發明也可應用在低於5GHz或高於300GHz的頻段。
就其本身而論,QFN封裝件100可為目前技術可及或即將發展的任何尺寸大小。例如,QFN封裝件100可小到如2x2(即2mmx2mm)QFN封裝件,也可大到如15x15(即15mmx15mm)QFN封裝件。如圖1所例舉的實施例,QFN封裝件100為一6x6(即6mmx6mm),具36引腳的QFN封裝件。需要注意的是本發明考量到QFN封裝件100可為比15mmx15mm還大的QFN封裝件,而且可包含任何數目的引腳。
引腳130可由任何習知技術中習知的或即將發展的適合的導電材料製成。例如,引腳130可由一金屬,一合金或其他類似物製成。在許多例舉的實施例中,引腳130係由銅及/或銅合金製造。在其他實施例中,引腳130係由金及/或金的合金製造。在其他實施例中,引腳130係由鋁及
QFN封裝件,而且可包含任何數目的引腳。
引腳130可由任何習知技術中習知的或即將發展的適合的導電材料製成。例如,引腳130可由一金屬,一合金或其他類似物製成。在許多例舉的實施例中,引腳130係由銅及/或銅合金製造。在其他實施例中,引腳130係由金及/或金的合金製造。在其他實施例中,引腳130係由鋁及/或鋁合金製造。
於一例舉的實施例,QFN封裝件100包含至少一電容引腳132,透過一打線140連接至MMIC晶片120。電容引腳132可適當地用來降低及/或抵銷打線140所產生的電感效應,其中打線140係用來將訊號傳出及/或傳入MMIC晶片120。在一例舉的實施例中,電容引腳被恰當地組態成一個電容。就其本身而論,電容引腳132可以是至少兩金屬板其中之一,其中兩金屬板間夾一空間(例如空氣)及/或一介電質。此外,電容引腳132可包含任何已知可用來形成電容的材料。在一例舉的實施例中,電容引腳132可適當地用來降低及/或抵銷大約0.1nH到1.0nH範圍間的電感,且較佳是0.5nH。因此,電容引腳132可以適當地組態(例如尺寸、形狀、材料及其他相似物),以產生一預先決定的適合大小之電容,來降低及/或抵銷打線140所產生的電感。
打線140可為任何適合用來將訊號傳出或傳入MMIC 120之裝置。因此,打線140可為任何已知或日後發展出來的打線。就其本身而論,打線140可藉任何已知的導電材料(例如銅、金、鋁、銀及其他類似材料)形成。於許多實施例之一態樣,QFN封裝件100可包含不只一條的打線140,其將MMIC 120耦合至電容引腳132。
在另一例舉的實施例中,QFN封裝件100包含一輸入
質量、體積及其他類似物。
打線144可為任何適合用來將訊號傳入或傳出QFN封裝件100的裝置。就其本身而論,打線144可為任何目前已知或未來發展出來的打線。因此,打線144可由任何導電材料(例如銅、金、鋁、銀及其他類似材料)製成。於許多實施例之一態樣,QFN封裝件100可包含不只一條打線144,其將I/O引腳134耦合至電容引腳132。
如圖1所示之插入的方框內,打線140連接至電容引腳132,且電容引腳132連接至打線144,以形成一個電感-電容-電感架構(即一個三極(three-pole)的低通濾波器)。就其本身而論,藉由適當組態的電容引腳132,可降低及/或抵銷任何打線140及/或144所產生之不想要的電感。同樣地,藉由適當組態的打線140及/或144,較佳是打線144,亦可降低及/或抵銷任何電容引腳132所產生之不想要的電容。
於一例舉的實施例,QFN封裝件100包含一超模壓材料150超模壓材料150可為任何習知技術中習知的或即將發展的超模壓材料。在一例舉的實施例中,超模壓材料150為塑膠。
圖2為可操作在高頻的QFN封裝件200另一例舉的實施例之示意圖。於一實施例中,QFN封裝件200為與上述QFN封裝件100類似的一QFN封裝件。此外,於許多實施例中,QFN封裝件200包含一MMIC晶片220、複數個引腳230,以及超模壓材料250,其分別類似討論於上之MMIC 120、引腳130及超模壓物質150。
在許多例舉的實施例中,QFN封裝件200也包含一電容引腳232,透過打線一240與MMIC 220連接,其類似
上述之電容引腳132透過打線140與MMIC 120連接。此外,QFN封裝件200也包含一I/O引腳234,透過一打線244與電容引腳232連接,其類似上述之I/O引腳134透過打線144與電容引腳132連接。
於一例舉的實施例中,電容引腳232組態成包含任何適當的尺寸、形狀、高度、寬度、深度、質量、體積、厚度、材料及其他類似物,以降低及/或抵銷打線240及/或打線244、248所產生的電感。於一例舉的實施例之一態樣中,電容引腳232更可進一步透過至少額外的打線248,其類似上述之打線140、144、240及244連接至I/O引腳234。因此,於本發明之一例舉的實施例中,QFN封裝件200包含另一條打線248,將電容引腳232連接至I/O引腳234。
值得注意的是於許多例舉的實施例中,QFN封裝件200包含習知技術中習知的或即將發展的任何尺寸之QFN封裝件。類似QFN封裝件100,QFN封裝件200可小到如2x2(即2mmx2mm)QFN封裝件,也可大到如15x15(即15mmx15mm)QFN封裝件。於圖2所例舉的實施例中,QFN封裝件200為一4x4(即4mmx4mm)具12引腳的QFN封裝件。此外,本發明考量到QFN封裝200件可為比15mmx15mm還大的QFN封裝件,且可包含任何數目的引腳。
圖3為可執行在高頻之QFN封裝件300另一例舉的實施例之示意圖。於一實施例中,QFN封裝件300為與上述QFN封裝100件類似的一QFN封裝件。此外,於許多實施例中,QFN封裝件300包含一MMIC晶片320、複數個引腳330,以及超模壓材料350,其分別類似討論於上
之MMIC 120、引腳130及超模壓物質150。
在許多例舉的實施例中,QFN封裝件300也包含一電容引腳332,透過打線一340與MMIC 320連接,其類似上述之電容引腳132透過打線140與MMIC 120連接。此外,QFN封裝件300也包含一I/O引腳336,透過一打線344與電容引腳332連接,其類似上述之I/O引腳134透過打線144與電容引腳132連接。
於本發明一例舉的實施例,QFN封裝件300包含一I/O引腳334,類似上述之I/O引腳134與336,I/O引腳336透過打線348,類似上述之打線140與144,連接至電容引腳332。如圖中插入的A方格所示,當I/O引腳334與336透過一打線352彼此相連接時(其中打線352類似上述之打線140與144),其組態為:打線340連接至電容引腳332,電容引腳332連接至打線344,以及電容引腳332連接至打線348,形成一個三極低通濾波器(即一個L-C-L組態)。如圖中插入的B方格所示,當I/O引腳334與336分別獨立耦合至一個外界元件(未顯示)時,其組態為:打線340連接至電容引腳332,電容引腳332連接至打線344,以及電容引腳332連接至打線348,形成一個二極低通濾波器(即一個L-C架構)。因此,藉由適當地組態電容引腳332可降低及/或抵銷任何打線340、344及/或348所產生之不想要的電感。同樣地,藉由適當地組態打線340、344及/或348,較佳是344及/或348,可降低及/或抵銷任何電容引腳332所產生之不想要的電容。此外,QFN封裝件300可包含大於三極(L-C-L),供使用於更寬的頻寬之應用。
值得注意的是在許多例舉的實施例中,QFN封裝件
300包含習知技術中習知的或即將發展的任何尺寸大小之QFN封裝件。類似QFN封裝件100,QFN封裝件300可小到如2x2(即2mmx2mm)QFN封裝件,也可大到如15x15(即15mmx15mm)QFN封裝件。於圖3所例舉的實施例中,QFN封裝件300為一10x10(即10mmx10mm),具28引腳的QFN封裝件。此外,本發明考量到QFN封裝300可為比15mmx15mm還大的QFN封裝件,且可包含任何數目的引腳。
圖4為可執行在高頻之QFN封裝件400另一例舉的實施例之示意圖。於一實施例中,QFN封裝件400為與上述QFN封裝件100類似的一QFN封裝件。此外,於許多實施例中,QFN封裝件400包含一MMIC晶片420、複數個引腳430,以及超模壓材料450,其分別類似討論於上之MMIC 120、引腳130及超模壓物質150。
在許多例舉的實施例中,QFN封裝件400也包含一電容引腳432,透過打線一440與MMIC 420連接,其類似上述之電容引腳132透過打線140與MMIC 120連接。此外,QFN封裝件400也包含一I/O引腳434,透過一打線444與電容引腳432連接,其類似上述之I/O引腳134透過打線144與電容引腳132連接。
於本發明一例舉的實施例,QFN封裝件400包含一I/O引腳438,類似上述之I/O引腳134,I/O引腳438透過打線448,類似上述之打線140,連接至電容引腳432。與QFN封裝件300相似,打線440連接至電容引腳432,電容引腳432連接至打線444,以及電容引腳432連接至打線448之組態,形成一個三極低通濾波器(即一個L-C-L組態)。因此,藉由適當地組態電容引腳432可降低及/或
抵銷任何打線440、444及/或448所產生之不想要的電感。同樣地,藉由適當地組態打線440、444及/或448,較佳是444及/或448,可降低及/或抵銷任何電容引腳432所產生之不想要的電容。值得注意的是於此的討論係將I/O引腳438與電容引腳432定向於QFN封裝件400的同一側,然而,本發明考量到各種I/O引腳及/或電容引腳不需在封裝件的同一側,而可以擺放在任何適當的位置或不同側。
在許多例舉的實施例中,QFN封裝件400包含習知技術中習知的或即將發展的任何尺寸大小的QFN封裝件。類似QFN封裝件100,QFN封裝件400可小到如2x2(即2mmx2mm)QFN封裝件,也可大到如15x15(即15mmx15mm)QFN封裝件。於圖3所例舉的實施例中,QFN封裝件400為一5x5(即5mmx5mm),具16引腳的QFN封裝件。此外,本發明考量到QFN封裝件400可為比15mmx15mm還大的QFN封裝件,且可包含任何數目的引腳。
圖5為可執行在高頻之QFN封裝件500另一例舉的實施例之示意圖。於一實施例中,QFN封裝件500為與上述QFN封裝件100類似的一QFN封裝件。此外,於許多實施例中,QFN封裝件500包含一MMIC晶片520、複數個引腳530,以及超模壓材料550,其分別類似討論於上之MMIC 120、引腳130及超模壓物質150。
在許多例舉的實施例中,QFN封裝件500也包含一電容引腳532,透過打線一540與MMIC 520連接,其類似上述之電容引腳132透過打線140與MMIC 120連接。此外,QFN封裝件500也包含一I/O引腳534,透過一透過傳輸線560與電容引腳532連接。
傳輸線560可為任何適合用來在電容引腳532與I/O引腳534間傳輸訊號的裝置。就其本身而論,傳輸線560可為任何習知技術中習知的或即將發展的傳輸線。就其本身而論,傳輸線560可由任何導電材料(例如銅、金、鋁、銀及其他相似材料)形成。於本發明之許多例舉的實施例之一態樣中,傳輸線560實質上使用與電容引腳532及/或I/O引腳534相同的材料製成。於本發明之其他態樣中,傳輸線560可使用與電容引腳532及/或I/O引腳534不同的材料製成。此外,傳輸線560可包含任何適當的尺寸、形狀、高度、寬度、深度、質量、體積、厚度、材料及其他相似物,來適當地於電容引腳532與I/O引腳534間傳遞訊號。
值得注意的是在許多例舉的實施例中,QFN封裝件500包含習知技術中習知的或即將發展的任何尺寸大小的QFN封裝件。類似QFN封裝件100,QFN封裝件500可小到如2x2(即2mmx2mm)QFN封裝件,也可大到如15x15(即15mmx15mm)QFN封裝件。於圖5所例舉的實施例中,QFN封裝件500為一7x7(即7mmx7mm),具20引腳的QFN封裝件。此外,本發明考量到QFN封裝件500可為比15mmx15mm還大的QFN封裝件,且可包含任何數目的引腳。
圖6為QFN封裝件600之一例舉的實施例之一部份的示意圖。於一實施例中,QFN封裝件600為與上述QFN封裝100類似的一QFN封裝件。此外,於許多實施例中,QFN封裝件600包含一MMIC晶片620、複數個引腳630,以及超模壓材料650,其分別類似討論於上之MMIC 120、引腳130及超模壓物質150。
在許多例舉的實施例中,QFN封裝件600也包含一電
容引腳632,透過打線一640與MMIC 620連接,其類似上述之電容引腳132透過打線140與MMIC 120連接。此外,QFN封裝件600也包含一I/O引腳634,透過一打線644與電容引腳632連接,其類似上述之I/O引腳134透過打線144與電容引腳132連接。
於一例舉的實施例中,電容引腳632可用來包含任何適合的尺寸、形狀、高度、寬度、深度、質量、體積、厚度、材料及其他相類物,其可達成降低及/或減少打線640及/或644所產生之電感效應的效果。於本發明之一例舉的實施例的一態樣,電容引腳632於超模壓物質650內為〞浮接的〞,使得電容引腳632形成一電容的至少一部份(例如一電容板、及空氣、塑膠或其他介電質填充物)。
在許多例舉的實施例中,QFN封裝件600包含習知技術中習知的或即將發展的任何尺寸大小的QFN封裝件。類似QFN封裝件100,QFN封裝件600可小到如2x2(即2mmx2mm)QFN封裝件,也可大到如15x15(即15mmx15mm)QFN封裝件。於圖6所例舉的實施例中,QFN封裝件600為一8x8(即8mmx8mm),具16引腳的QFN封裝件。此外,本發明考量到QFN封裝件600可為比15mmx15mm還大的QFN封裝件,且可包含任何數目的引腳。
值得注意的是上述討論所提及的封裝件100、200、300、400、500及600係QFN封裝件,然而,本發明考量到QFN封裝件100、200、300、400、500及600可以是任何超模壓導線架封裝件。就其本身而論,上述所有的討論也可適用但不限於SOIC封裝件、QSOP、TSSOP、MSOP、DFN封裝件、SOT封裝件、SC70-6封裝件、SSOP
封裝件、PDIP封裝件、SPDIP封裝件、MLFP封裝件、PSOP封裝件、PLCC封裝件、MQFP封裝件、TQFP封裝件、PQ-LQFP封裝件、SIP封裝件、BGA封裝件(BGA)、以及任何其他超模壓導線架封裝件。
圖7A與圖7B分別為一例舉的系統700之透視示意圖,其增加上述QFN封裝件600之操作頻率。圖7A說明QFN封裝件600被連接至一印刷電路板(PCB)760。PCB 760可為現有技術可用於QFN封裝件之任何的PCB元件。
於一例舉的實施例中,PCB 760包含電容引腳770,當適當地組態時,其可由目前已知適合用來形成電容之至少一部份的任何材料製成。於另一例舉的實施例中,PCB 760包含一I/O引腳780,其可由目前已知的任何材料製成,且可包含習知技術中習知適合將訊號傳入及/或傳出QFN封裝件600之任何形狀。
圖7B說明封裝件600連接至PCB 760,以形成一個完整的電容775。於一例舉的實施例中,電容775是由電容引腳632、電容引腳770及空間(即空氣、塑膠,或其他適合的材料)778形成。就其本身而論,電容引腳632形成電容775之至少一部份,電容引腳770形成電容775之至少第二部份,且空間778形成電容775所需之間隙。於例舉的實施例中,電容775的電容值介於0.001pF至0.2pF間,較佳的電容值為0.02pF。然而,本發明考量到電容775可為任意電容值的電容,以用於抵銷及/或降低打線640所產生之電感效應,如上述。
此外,系統700包含I/O引腳780,其類似上述之引腳634。就其本身而論,I/O引腳634可由任何習知技術中習知的材料製成,且可包含習知技術中習知適合將訊號傳
入及/或傳出QFN封裝件600之任何形狀。而且,I/O引腳780可包含適合於QFN封裝件600與PCB 760間轉送訊號之任何引腳。
此外,雖然系統700利用QFN封裝件600來討論,系統700也可包含類似上述之封裝件100、200、300、400及500之一QFN封裝件。就其本身而論,電容引腳132、232、332、432及532可組態來形成介於電容引腳132、232、332、432及532與電容引腳770間的空間778。
圖8為一方法800之一例舉的實施例之流程圖,其降低及/或抵銷一QFN封裝件(例如QFN封裝件100、200、300、400、500及600)之電感效應。於本發明一例舉的實施例,方法800開始於透過一第一打線(例如打線140、240、340、440、540及640)將一IC晶片(例如IC晶片120、220、320、420、520及620)連接至一電容引腳(例如電容引腳132、232、332、432、532及632)(步驟810)。於另一例舉的實施例,電容引腳透過一第二打線(例如打線144、244、344、444及644)或一傳輸線(例如傳輸線560)連接至一I/O引腳(例如I/O引腳134、234、334、434、534及634)(步驟820)。
於許多實施例中,電容引腳透過一打線(例如打線348及448)連接至一第二I/O引腳(例如I/O引腳336及438)(步驟830)。於另一例舉的實施例中,量測、估計或得知第一打線(即連接IC晶片與電容引腳的打線)所產生的電感效應(步驟840),且適當地組態電容引腳以實質地降低及/或實質地抵銷此電感效應(步驟850)。於一例舉的實施例之一態樣,調整電容引腳的尺寸、體積、質量、材料及/或形狀來形成一具有所需要的電容值之電容,以適當地降低及
/或抵銷第一打線所產生的電感效應(步驟860)。
益處、其他優點與問題的解決方式皆於此使用特定的實施例描述。然而,益處、優點、問題的解決方式與任何元件,其可產生或使之更明顯的任何益處、優點、或解決方式並非作為任一或全部的申請專利範圍或本發明之關鍵、需要或必要的特徵或元件。僅隨附的專利申請範圍能限制本發明之範圍,其中所參考的一元件除非特別指明,否則並非意指為〝一個以及唯一的一個〞,而是要表明〝這一個或更多個〞。對於熟習此技藝人士,所有上述之例舉的實施例中元件之結構的、化學的與功能性的均等係於此一併為參考且涵蓋於本發明之申請專利範圍中。
100,200,300,400,500,600‧‧‧QFN封裝件
120,220,320,420,520‧‧‧MMIC晶片
130,132,134,230,232,234,330,332,334,336‧‧‧引腳
140,144,240,244,248,340,344,348,352‧‧‧打線
150,250,350,450,650‧‧‧超模壓材料
430,432,434,438,530,532,534,630,632,634‧‧‧引腳
440,444,448,640,644‧‧‧打線
560‧‧‧傳輸線
700‧‧‧系統
760‧‧‧印刷電路板
770‧‧‧電容引腳
775‧‧‧電容
778‧‧‧空間
780‧‧‧I/O引腳
藉著參考詳細的描述與申請專利範圍並連結圖式,將對本發明有更完整的瞭解,於圖式中類似的參考數字意指類似的元件,且圖1為一高頻四方扁平無引腳(QFN)封裝件之一例舉的實施例之示意圖;圖2為一高頻QFN封裝件之另一例舉的實施例之示意圖;圖3為一高頻QFN封裝件之又一例舉的實施例之示意圖;圖4為一高頻QFN封裝件之再一例舉的實施例之示意圖;圖5為一高頻QFN封裝件之另一例舉的實施例之示意圖;圖6為一高頻QFN封裝件的一例舉的實施例之示意
圖,其包含一引腳作為一電容之至少一部份;圖7A與圖7B分別為一例舉的系統之透視示意圖,其增加圖6所示之高頻QFN封裝件的操作頻率;以及圖8為一例舉的方法之流程圖,其降低及/或抵銷一QFN封裝件之電感效應。
100‧‧‧QFN封裝件
120MMIC‧‧‧晶片
130,132,134‧‧‧引腳
140,144‧‧‧打線
150‧‧‧超模壓材料
Claims (45)
- 一種電子裝置,包含:一晶粒銲墊;一積體電路晶片,耦合至該晶粒銲墊;一第一引腳,耦合至該晶粒銲墊;一介電空間(dielectric space),由該第一引腳與該晶粒銲墊定義,其中該介電空間由該第一引腳延伸至該晶粒銲墊之一表面;一第二引腳,耦合至該晶粒銲墊,其中該第二引腳與該晶粒銲墊之該表面齊平,且其中該第二引腳組態成與一電路板接觸,且其中該第一引腳組態成不與該電路板接觸;一第一打線,將該積體電路晶片耦合至該第一引腳(lead),其中該第一引腳為一電容引腳,且組態成用來降低與抵銷(offset)該第一打線所產生的電感量;以及一第二打線,將該第一引腳耦合至該第二引腳,其中該第二引腳為一射頻輸入/輸出引腳。
- 如請求項1所述之電子裝置,其中該第一引腳為一低通濾波器。
- 如請求項1所述之電子裝置,更包含:一第三打線,將該第一引腳耦合至一第三引腳,其中該第二引腳與該第三引腳各為射頻輸入/輸出引腳,且該第一引腳用來降低與抵銷該第一打線所產生之電感效應兩者之至少其中之一。
- 如請求項3所述之電子裝置,其中該第二引腳與該第三引 腳各與該第一引腳相鄰。
- 如請求項3所述之電子裝置,其中該第二引腳與該第三引腳中至少其中之一與該第一引腳不相鄰。
- 如請求項1所述之電子裝置,更包含:一第三打線,將該第一引腳耦合至該第二引腳。
- 如請求項1所述之電子裝置,其中該第一打線耦合至該第一引腳,且該第二打線耦合至該第一引腳,以形成一電感-電容-電感架構。
- 如請求項7所述之電子裝置,其中該電感-電容-電感架構用來降低該第一打線所產生的電感量。
- 如請求項1所述之電子裝置,更包含:一模封材料,填充在該晶粒銲墊未被至少該積體電路晶片與該第一引腳與該第二引腳佔據的區域。
- 如請求項9所述之電子裝置,其中至少一部份之該第一引腳在該模封材料內為浮接的。
- 如請求項1所述之電子裝置,其中該電子裝置用來運作在約五千兆赫(5GHz)到約三百千兆赫(300GHz)之範圍。
- 一種電子裝置,包含:一晶粒銲墊; 一積體電路晶片,耦合至該晶粒銲墊;一第一引腳、一第二引腳、與一第三引腳,耦合至該晶粒銲墊;一第一打線,將該積體電路晶片耦合至該第一引腳;一第二打線,將該第一引腳耦合至該第二引腳;以及一第三打線,將該第一引腳耦合至該第三引腳,其中該第二引腳與該第三引腳皆為射頻輸入/輸出引腳,且該第一引腳非射頻輸入/輸出引腳但為一電容引腳,其中該電容引腳組態成用來降低或/及抵銷至少該第一、第二與第三打線之一所產生的電感效應;以及其中,該第一引腳包含一電容的一第一平板,且其中該電容的一第二平板不在該晶粒銲墊上。
- 如請求項12所述之電子裝置,其中,該電容僅形成於當該電子裝置位於該第二平板附近,而該第二平板與該第一平板排成一列且該第一、二平板之間有一空間時。
- 如請求項12所述之電子裝置,其中,該電容僅形成於當該電子裝置位於該第二平板附近,而該第二平板與該第一平板排成一列且該第一、二平板之間有一介電質時。
- 一電子裝置,包含:四方扁平無引腳(QFN)封裝件,其中該QFN封裝件包含:一積體電路(IC)晶片;一第一引腳與一第二引腳;一第一打線,將該積體電路晶片耦合至該第一引腳;一第二打線,將該第一引腳耦合至該第二引腳;以及 一空間,由該第一引腳與QFN封裝件定義,其中該空間由該第一引腳延伸至該QFN封裝件之一表面,其中該第一引腳包含一電容之一第一平板,其中該電容之一第二平板未位於該QFN封裝件上,且其中該第一打線耦合至該第一引腳,且該第二打線耦合至該第一引腳,以形成一電感-電容-電感架構。
- 如請求項15所述之電子裝置,其中該第一引腳為一電容引腳,其中該第二引腳與該QFN封裝件之該表面齊平,其中該第二引腳組態成與一電路板接觸,且其中該第一引腳組態成不與該電路板接觸。
- 一種電子系統,包含:一電路板;一晶粒銲墊;一積體電路晶片,耦合至該晶粒銲墊,其中該晶粒銲墊更包含一第一引腳與一第二引腳;其中,該第一引腳接收一射頻訊號但是不與該電路板形成直接實體接觸,而該第二引腳直接與該電路板連接以與該電路板傳輸射頻訊號;其中,該電路板包含一第三引腳,其中,當該晶粒銲墊與該電路板連接時,該第一引腳與該第三引腳排成一列且該第一、三引腳之間有一空間,且其中該第一、三引腳與該空間形成一電容;一第一打線,將該積體電路晶片耦合至該第一引腳,其中該第一引腳為一電容引腳,且組態成用來降低或/及抵銷(offset)該第一打線所產生的電感量;以及 一第二打線,將該第一引腳耦合至該第二引腳,其中該第二引腳為一射頻輸入/輸出引腳。
- 一種電子系統,包含:一印刷電路板,包含一第一電容引腳;以及一四方扁平無引腳(QFN)封裝件,與該印刷電路板連接,其中該QFN封裝件包含一與該第一電容引腳對齊之第二電容引腳;其中該QFN封裝件係組態成,當該QFN封裝件與該印刷電路板連接時,在該第一電容引腳與該第二電容引腳之間形成一空間;且其中該第一電容引腳、該空間、以及該第二電容引腳形成一電容。
- 如請求項18所述之電子系統,其中該空間係填充一介電材料。
- 如請求項18所述之電子系統,其中該印刷電路板更包含一第一射頻輸入/輸出引腳,且其中該QFN封裝件更包含一與該第一射頻輸入/輸出引腳對齊之第二射頻輸入/輸出引腳,且該第二射頻輸入/輸出引腳組態成用於在該QFN封裝件與該印刷電路板之間傳輸射頻訊號;且其中該第二電容引腳藉由一打線而與該第二射頻輸入/輸出引腳連接。
- 如請求項18所述之電子系統,其中該空間為空氣。
- 一種超模壓導線架封裝件,包含:一導線架;一超模壓材料,環繞部分該導線架且形成該超模壓導線架 封裝件之一底部表面,其中該底部表面係組態成與一印刷電路板(PCB)連接;一積體電路,電性連接該導線架且包含於該超模壓導線架封裝件內;以及一電容引腳,位於該超模壓導線架封裝件內,其中該電容引腳係置於該超模壓導線架封裝件內,而未接觸該印刷電路板,且其中該電容引腳係組態成用於形成一電容之一第一部分,以對齊該印刷電路板上之一相對應電容引腳。
- 如請求項22所述之超模壓導線架封裝件,更包含:一第一打線,與位於該第一打線之一第一端上的該電容引腳連接,且與位於該第一打線之一第二端上的該積體電路連接;一第一輸入/輸出引腳,位於該超模壓導線架封裝件內,其中該第一輸入/輸出引腳係置於該超模壓導線架封裝件內,以接觸該印刷電路板;以及一第二打線,將該第一輸入/輸出引腳連接至該電容引腳。
- 如請求項23所述之超模壓導線架封裝件,其中該電容引腳係組態成用來降低與抵銷該第一打線所產生的電感量。
- 如請求項22所述之超模壓導線架封裝件,其中,當該超模壓導線架封裝件與該印刷電路板連接時,該電容引腳與該印刷電路板上之該相對應電容引腳之間係形成有一介電空間。
- 如請求項22所述之超模壓導線架封裝件,其中該電容引腳為一低通濾波器。
- 如請求項23所述之超模壓導線架封裝件,其中該第一打線耦合至該電容引腳,且該第二打線耦合至該電容引腳,以形成一電感-電容-電感架構。
- 如請求項23所述之超模壓導線架封裝件,更包含:一第三打線,將該電容引腳耦合至一第二輸入/輸出引腳。
- 如請求項22所述之超模壓導線架封裝件,其中該超模壓導線架封裝件係組態成在約五千兆赫到約三百千兆赫之範圍內運作。
- 如請求項22所述之超模壓導線架封裝件,其中該積體電路為一單晶微波積體電路晶片。
- 一種超模壓導線架封裝件,包含:一電容引腳,組態成用於形成該超模壓導線架封裝件內之一電容的一部分;以及至少一打線,連接該電容引腳並連接一積體電路,其中該積體電路係置於該超模壓導線架封裝件內;其中,該電容引腳係組態成用於對齊一印刷電路板內之一相對應電容引腳,亦組態成用於降低與抵銷該至少一打線所產生的電感。
- 如請求項31所述之超模壓導線架封裝件,其中該電容引腳未與該印刷電路板直接實體接觸。
- 如請求項32所述之超模壓導線架封裝件,更包含:一輸入/輸出引腳,組態成直接與該印刷電路板連接,以與該印刷電路板傳送射頻訊號。
- 如請求項31所述之超模壓導線架封裝件,其中該電容引腳在該超模壓導線架封裝件內為浮接的。
- 如請求項31所述之超模壓導線架封裝件,更包含:一介電空間,形成於該電容引腳與該印刷電路板之該相對應電容引腳之間。
- 如請求項31所述之超模壓導線架封裝件,其中該電容引腳包含一第一電容之一第一平板,且其中該電容之一第二平板未位於該超模壓導線架封裝件上。
- 如請求項36所述之超模壓導線架封裝件,其中該電容僅形成於當該超模壓導線架封裝件位於該第二平板附近,而該第二平板與該第一平板排成一列且該第一、二平板之間有一空間時。
- 如請求項37所述之超模壓導線架封裝件,其中位於該第一、二平板之間的該空間包含一介電材料。
- 一種超模壓導線架封裝件,包含:一輸入/輸出引腳;以及一電容引腳,打線至該輸入/輸出引腳;其中,該電容引腳無法與該超模壓導線架封裝件外之任何 東西形成實體接觸。
- 一種超模壓導線架封裝件,包含:至少一隆起引腳(raised lead),其中該至少一隆起引腳為一個雙平板電容的一第一平板,且該雙平板電容僅藉由將該超模壓導線架封裝件安裝(mount)於一印刷電路板上而形成,其中該印刷電路板包含該雙平板電容的一第二平板。
- 一種製造電子元件的方法,該電子元件包含一封裝件,該封裝件包含一積體電路晶片、一第一引腳、以及一第二引腳,該方法包含:將一第一打線耦合至該積體電路晶片與該第一引腳;將一第二打線耦合至該第一引腳與該第二引腳,其中該第一引腳為一電容引腳,且包含一個雙平板電容的一平板,其中該第一引腳係組態成不與一印刷電路板接觸,其中該第二引腳為一射頻輸入/輸出引腳,且具有一表面,而該表面係與該封裝件之一表面齊平,其中該第二引腳係組態成與該印刷電路板接觸,其中該印刷電路板更包含一金屬區;以及實質上將該印刷電路板上之該金屬區對齊該第一引腳,因而該印刷電路板之該金屬區形成該雙平板電容之一第二平板。
- 如請求項41所述之方法,更包含:將一第三打線耦合至該第一引腳與一第三引腳,其中該第二、第三引腳為射頻輸入/輸出引腳。
- 如請求項41所述之方法,更包含:估計由該第一打線所產生的電感;以及 將該第一引腳組態成用於降低與抵銷該電感效應兩者之至少其中之一。
- 如請求項43所述之方法,其中該將該第一引腳組態之步驟包含調整該第一引腳的一尺寸、一體積、一質量、一形狀及組態之至少其中之一,以形成具有預定電容值的一電容。
- 一種超模壓導線架封裝件,包含:一導線架;一超模壓材料,環繞部分該導線架且形成該超模壓導線架封裝件之一底部表面,其中該底部表面連接一印刷電路板(PCB);一積體電路,電性連接該導線架且包含於該超模壓導線架封裝件內;一電容引腳,位於該超模壓導線架封裝件內,其中該電容引腳係置於該超模壓導線架封裝件內,而未接觸該印刷電路板,且其中該電容引腳形成一電容之一第一部分,以對齊該印刷電路板上之一相對應電容引腳;以及一介電空間,形成於該電容引腳與該印刷電路板上之該相對應電容引腳之間。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/161,420 US7489022B2 (en) | 2005-08-02 | 2005-08-02 | Radio frequency over-molded leadframe package |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200707697A TW200707697A (en) | 2007-02-16 |
TWI429053B true TWI429053B (zh) | 2014-03-01 |
Family
ID=36754350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095118985A TWI429053B (zh) | 2005-08-02 | 2006-05-29 | 射頻超壓模導線架封裝件 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7489022B2 (zh) |
EP (1) | EP1929523B1 (zh) |
TW (1) | TWI429053B (zh) |
WO (1) | WO2007018643A1 (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7489022B2 (en) * | 2005-08-02 | 2009-02-10 | Viasat, Inc. | Radio frequency over-molded leadframe package |
US20080061408A1 (en) * | 2006-09-08 | 2008-03-13 | National Semiconductor Corporation | Integrated circuit package |
US20090032917A1 (en) * | 2007-08-02 | 2009-02-05 | M/A-Com, Inc. | Lead frame package apparatus and method |
US20090127694A1 (en) * | 2007-11-14 | 2009-05-21 | Satoshi Noro | Semiconductor module and image pickup apparatus |
US8536692B2 (en) | 2007-12-12 | 2013-09-17 | Stats Chippac Ltd. | Mountable integrated circuit package system with mountable integrated circuit die |
US8084849B2 (en) * | 2007-12-12 | 2011-12-27 | Stats Chippac Ltd. | Integrated circuit package system with offset stacking |
US8102668B2 (en) * | 2008-05-06 | 2012-01-24 | International Rectifier Corporation | Semiconductor device package with internal device protection |
US9293385B2 (en) | 2008-07-30 | 2016-03-22 | Stats Chippac Ltd. | RDL patterning with package on package system |
US8485724B2 (en) | 2010-03-31 | 2013-07-16 | Microchip Technology Incorporated | Thermocouple electromotive force voltage to temperature converter with integrated cold-junction compensation and linearization |
AU2011276451B2 (en) * | 2010-07-09 | 2014-03-06 | Eco Technol Pty Ltd | Syngas production through the use of membrane technologies |
US8994157B1 (en) | 2011-05-27 | 2015-03-31 | Scientific Components Corporation | Circuit system in a package |
US9515032B1 (en) * | 2015-08-13 | 2016-12-06 | Win Semiconductors Corp. | High-frequency package |
US10069465B2 (en) | 2016-04-21 | 2018-09-04 | Communications & Power Industries Llc | Amplifier control system |
US11342260B2 (en) * | 2019-10-15 | 2022-05-24 | Win Semiconductors Corp. | Power flat no-lead package |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100306988B1 (ko) * | 1992-10-26 | 2001-12-15 | 윌리엄 비. 켐플러 | 장치패키지 |
US5907769A (en) * | 1996-12-30 | 1999-05-25 | Micron Technology, Inc. | Leads under chip in conventional IC package |
DE10031843A1 (de) * | 2000-06-30 | 2002-01-10 | Alcatel Sa | Elektrisches oder opto-elektrisches Bauelement mit einer Verpackung aus Kunststoff und Verfahren zur Variation der Impedanz einer Anschlussleitung eines solchen Bauelements |
JP2002076228A (ja) * | 2000-09-04 | 2002-03-15 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置 |
JP3851845B2 (ja) * | 2002-06-06 | 2006-11-29 | 株式会社ルネサステクノロジ | 半導体装置 |
CN100423255C (zh) | 2002-09-10 | 2008-10-01 | 半导体元件工业有限责任公司 | 具有引线接合电感器的半导体器件和方法 |
US7215012B2 (en) * | 2003-01-03 | 2007-05-08 | Gem Services, Inc. | Space-efficient package for laterally conducting device |
TW200520121A (en) * | 2003-08-28 | 2005-06-16 | Gct Semiconductor Inc | Integrated circuit package having an inductance loop formed from a multi-loop configuration |
TWI229422B (en) * | 2003-12-05 | 2005-03-11 | Via Tech Inc | A bonding-wire structure having desirable high-frequency characteristics for using in metal frame package |
US7060536B2 (en) * | 2004-05-13 | 2006-06-13 | St Assembly Test Services Ltd. | Dual row leadframe and fabrication method |
TWI277192B (en) * | 2004-07-08 | 2007-03-21 | Siliconware Precision Industries Co Ltd | Lead frame with improved molding reliability and package with the lead frame |
DE102005008195A1 (de) * | 2005-02-23 | 2006-08-24 | Atmel Germany Gmbh | Hochfrequenzanordnung |
US7489022B2 (en) * | 2005-08-02 | 2009-02-10 | Viasat, Inc. | Radio frequency over-molded leadframe package |
-
2005
- 2005-08-02 US US11/161,420 patent/US7489022B2/en active Active
-
2006
- 2006-05-01 WO PCT/US2006/016355 patent/WO2007018643A1/en active Application Filing
- 2006-05-01 EP EP06751843A patent/EP1929523B1/en active Active
- 2006-05-29 TW TW095118985A patent/TWI429053B/zh active
-
2009
- 2009-02-09 US US12/367,932 patent/US8035203B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8035203B2 (en) | 2011-10-11 |
TW200707697A (en) | 2007-02-16 |
US7489022B2 (en) | 2009-02-10 |
WO2007018643A1 (en) | 2007-02-15 |
US20070029647A1 (en) | 2007-02-08 |
EP1929523B1 (en) | 2013-01-16 |
EP1929523A1 (en) | 2008-06-11 |
US20090174042A1 (en) | 2009-07-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI429053B (zh) | 射頻超壓模導線架封裝件 | |
US12027465B2 (en) | Impedance controlled electrical interconnection employing meta-materials | |
US7145511B2 (en) | Apparatus of antenna with heat slug and its fabricating process | |
US8034664B2 (en) | Method of fabricating passive device applied to the three-dimensional package module | |
US7834435B2 (en) | Leadframe with extended pad segments between leads and die pad, and leadframe package using the same | |
US20070235855A1 (en) | Methods and apparatus for a reduced inductance wirebond array | |
KR20010110421A (ko) | 집적 고주파 능력을 갖는 다중 칩 모듈 | |
WO2003036717A1 (en) | Thin thermally enhanced flip chip in a leaded molded package | |
US20210313283A1 (en) | Multi level radio frequency (rf) integrated circuit components including passive devices | |
US5631809A (en) | Semiconductor device for ultrahigh frequency band and semiconductor apparatus including the semiconductor device | |
US6507110B1 (en) | Microwave device and method for making same | |
TW506089B (en) | Wiring board and semiconductor device using the same | |
US20200411418A1 (en) | Semiconductor package structures for broadband rf signal chain | |
CN112928995A (zh) | 具有表面安装封装的载波和峰化放大器的多赫蒂放大器 | |
US20060138613A1 (en) | Integrated circuit package with inner ground layer | |
JP4137059B2 (ja) | 電子装置および半導体装置 | |
US20230178464A1 (en) | Electronic Package and Electronic Device Comprising the Same | |
US20090032917A1 (en) | Lead frame package apparatus and method | |
US8039957B2 (en) | System for improving flip chip performance | |
CN108807293A (zh) | 用于射频微波功放器件的封装结构 | |
TW202117953A (zh) | 半導體裝置 | |
JP2001185654A (ja) | インテグレーテッドフィルタを備えた電子パッケージ | |
WO2022119437A1 (en) | Electronic package and device comprising the same | |
KR200426929Y1 (ko) | 내부 접지층을 갖는 집적회로 패키지 |