TWI427744B - Memory architecture of 3d array with diode in memory string - Google Patents

Description

Three-dimensional array memory architecture with diodes in memory strings

This invention relates to high density memory devices, and more particularly to memory devices having multiple layers of planar memory cells to provide a three dimensional array.

When the critical size of the device in the integrated circuit is reduced to the limit of the usual memory cell technology, the designer turns to the memory cell multi-stack plane technology to achieve higher storage density and lower cost per bit. . For example, thin film transistor technology has been applied to charge trapping memory, see the paper "A multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory", IEEE Int'l Electron Device Meeting, December 11-13, 2006; and Jung et al.'s paper "Three Dimensionally Stack NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS structure for Beyond 30nm Node", IEEE Int'l Electron Device Meeting, December 11-13, 2006.

In addition, intersection point array technology has also been applied to anti-fuse memory, see the paper "512-Mb PROM with a Three Dimensional Array of Diode/Anti-fuse Memory Cells" by IEEE J. of Solid-state Circuits, vol. 38, no. 11, November 2003. In the design described by Johnson et al., multi-layer word lines and bit lines are used with memory elements at the intersection. The memory element comprises a p+ polysilicon anode connected to a word line, and the n+ polysilicon cathode is connected to the bit line, and the cathode and anode are separated by an antifuse material.

In the process described by Lai, Jung, et al., each memory layer uses multiple key lithography steps. Thus, the number of critical lithography steps required to fabricate this device will be a multiple of the number of memory layers used. Thus, while higher densities can be achieved by using three-dimensional arrays, higher manufacturing costs also limit the scope of use of this technology.

Another technique for using vertical anti-gate memory cell structures in charge trapping memory has also been published in Tanaka et al., "Bit Cost Scaleable Technology with Punch and Plug Process for Ultra High Density Flash Memory", 2007 Symposium on VLSI Technology Digest. Of Technical Papers, pp. 14~15, June 12-14, 2007, described. In the structure described by Tanaka et al., including a multi-gate field-effect transistor structure, which has a vertical channel similar to the anti-gate operation, uses a SONOS type charge trapping memory cell structure to A storage location is created at a gate/vertical channel interface. The memory structure is based on a columnar semiconductor material arranged as a vertical channel to form a multi-gate memory cell having a lower select gate close to the substrate and a higher select gate above it. A plurality of horizontal control gates are formed using a planar electrode layer that intersects the pillars. The planar electrode layer as a horizontal control gate does not require critical lithography, and thus saves cost. However, many critical lithography steps are still required for each vertical memory cell. In addition, the number of control gates in the multilayer structure of this method is still limited, which is determined by factors such as vertical channel conductivity, stylization used, and erase operations.

There is therefore a need to provide a three-dimensional integrated circuit memory structure that is low in manufacturing cost, including reliable, very small memory components.

The technique described herein is a memory device comprising an integrated circuit substrate, a plurality of strips of semiconductor material stacked, a plurality of word lines, memory elements and diodes. The plurality of strips of semiconductor material stack extend out of the integrated circuit substrate, the plurality of stacks having a ridge shape and comprising at least two elongated semiconductor materials separated by an insulating layer to form different planar locations in the plurality of planar locations. The plurality of word line lines are arranged orthogonal to the plurality of stacks, and are aligned with the plurality of stacks, such that a three-dimensional array of intersections is established between the plurality of stacked surfaces and the plurality of word line intersections region. The memory element is in the intersection region, and the memory cells of the three-dimensional array are accessible through the strip of semiconductor material and the plurality of word lines, the memory elements being arranged in a series of bit line structures and sources Between the lines. The diode is coupled to the series between the memory cell string and one of the bit line structure and the source line.

In some embodiments, the string is a reverse gate sequence.

In some embodiments, a combination of a particular bit line in the bit line structure, a particular source line in the source line, and a particular word line in the plurality of word line lines can be identified A specific memory cell in the memory cell of the three-dimensional array.

In some embodiments, the diode is coupled to the string between the memory cell string and the bit line structure.

In some embodiments, the diode is coupled to the string between the memory cell string and the source line.

Some embodiments include a series of select lines and a ground select line. The series of select lines are arranged orthogonal to the plurality of stacks and are conformed to the plurality of stacks such that a series selection means is established at the intersection of the plurality of stacked surfaces and the series select line intersections. The ground selection line is arranged orthogonal to the plurality of stacks and conforms to the plurality of stacks such that a ground selection device is established at the intersection of the plurality of stacked surfaces and the ground selection line.

In some embodiments, the diode is coupled between the string selection device and the bit line structure. In some embodiments, the diode is coupled between the ground selection device and the source line.

In some embodiments, the memory elements in the intersection region each comprise a tunneling layer, a charge trapping layer, and a barrier layer.

In some embodiments, the elongated semiconductor material comprises an n-type germanium and the diode comprises a p-type region in the elongated semiconductor material. In some embodiments, the elongated semiconductor material comprises an n-type germanium and the diode comprises a p-type plug in contact with the elongated semiconductor material.

Some embodiments include logic to apply a reverse bias to a diode in the unselected string of memory cells when the memory cell is programmed.

Another object of the present invention is to provide a memory device including an integrated circuit substrate and a three-dimensional array of memory cells in the integrated circuit substrate. The three-dimensional array includes a stack of anti-gate string memory cells; and the diode is coupled to the string between the memory cell string and one of the bit line structure and the source line.

In some embodiments, a combination of a particular bit line in the bit line structure, a particular source line in the source line, and a particular word line in the plurality of word line lines can be identified. A specific memory cell in the memory cell of the three-dimensional array.

In some embodiments, the diode is coupled to the string between the memory cell string and the bit line structure. In some embodiments, the diode is coupled to the string between the memory cell string and the source line.

Some embodiments include a string selection device between the bit line structure and the memory cell string; and a ground selection device interposed between the source line and the memory cell string.

In some embodiments, the diode is coupled between the string selection device and the bit line structure. In some embodiments, the diode is coupled between the ground selection device and the source line.

In some embodiments, the charge trapping structures in the intersection region comprise a tunneling layer, a charge trapping layer, and a barrier layer, respectively.

It is still another object of the present invention to provide a method of operating a three-dimensional anti-gate flash memory. The step includes applying a stylized adjustment bias sequence to the three-dimensional anti-gate flash memory, the three-dimensional array including a diode coupled to the series, such that the two-pole system is interposed between the memory string and the bit Between the line structure and the source line structure.

One or more unselected strings are charged, wherein the unselected string does not contain a memory cell to be stylized by the stylized adjustment bias. In various embodiments, this charging is performed from a source line structure or a self-bit line structure. In various embodiments, this charging is performed via a diode or not via a diode. The bit line structure and the source line structure are decoupled from the unselected series and a selected string containing one or more of the memory cells to be programmed by the stylized adjustment bias. The programmed voltage is applied to the unselected string and the selected string via one or more word lines of the memory cell to be programmed by the stylized adjustment bias.

The memory component is arranged in a string between the bit line structure and the common source line, and includes a diode coupled to the string, and is in a memory string and a bit line structure of the respective series And between one of the source lines. The first selection gate (eg, the serial selection gate SSL) may be coupled between the corresponding bit line structure and the memory cell string, and the second selection gate (eg, the ground selection gate GSL) may be coupled Between the corresponding common source line and the memory cell string. The diode can be coupled between the first select gate and the corresponding bit line structure. The diode can be coupled between the second selection gate and the corresponding common source line.

The three-dimensional memory device includes a plurality of ridge-like stacks separated by a plurality of elongated semiconductor materials separated by an insulating layer, arranged in a series as described herein, which can be coupled to the sense amplifier via a decoding circuit Pick up. The plurality of elongated semiconductor materials have side surfaces on sides of the plurality of stacks. In this example, the plurality of wires as word lines can be coupled to the column decoder and arranged orthogonal to the plurality of stacks. The wire has a surface that conforms to the plurality of stacks (eg, a bottom surface). Such a conformal surface configuration results in the creation of a multi-layered intersection region at the intersection with the side surface of the elongated semiconductor material and the plurality of wires. The memory element is disposed in an intersection region between a side surface of the elongated semiconductor material and the wire. The memory elements are programmable, similar to the programmable resistive structures or charge trapping structures described in the following embodiments. The combination of the compliant wire, the memory element, and the elongated semiconductor material in the stack in a particular intersection region constitutes a stack of memory cells. The result of this array structure can provide the memory cells of the three dimensional array.

The plurality of ridge-shaped stacks and the plurality of wires are formed into a memory cell by means of automatic alignment. For example, a long strip of semiconductor material in a plurality of ridge-like stacks can be defined using a single etch mask, resulting in the formation of staggered trenches, which can be relatively deep and the side surfaces of the elongated semiconductor material in the stack are vertical or It is aligned with the sloping side of the ridge forming the ditch. This memory element can be formed using one or more layers of material that are deposited entirely on top of the stack and formed using other processes that do not require critical alignment steps. In addition, a plurality of wires may be deposited antegradely on one or more layers of the material as a memory element, after which an etching process for defining the wires using the single etch mask is performed. As a result, only one alignment step is used to define the elongated semiconductor material in the stack, and an alignment step defines a plurality of wires.

In addition, a three-dimensional, buried channel, junctionless reverse gate flash structure based on the energy gap engineering polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS) technique is also described herein.

The invention provides a very efficient array decoding method for the three-dimensional vertical gate and gate flash design. The die size can be applied to current floating gate and gate flash designs while extending the density to one megabit.

The invention also provides a feasible circuit design architecture for ultra-high density three-dimensional anti-gate flash design.

The objects, features, and embodiments of the present invention will be described in the accompanying drawings.

The following description of the embodiments of the present invention is described in conjunction with Figures 1 through 41.

Figure 1 shows a schematic diagram of a 2x2 memory cell portion of a three-dimensional programmable resistive memory array in which the fill material is omitted to clearly represent the stacked and orthogonal wires of the elongated semiconductor material that make up the three dimensional array. In this illustration, only two planes are shown. However, the number of planes can be extended to a very large number. As shown in Fig. 1, the memory array is formed over an integrated circuit substrate having a semiconductor or other structure (not shown) underlying an insulating layer 10. This memory array comprises a stack of a plurality of elongated semiconductor materials 11, 12, 13, 14 separated from one another by insulating materials 21, 22, 23, 24. The stack is ridge shaped and extends along the Y-axis direction in the figure, so the elongated semiconductor materials 11-14 can be configured as bit lines and extend out of the substrate. The elongated semiconductor material 11, 13 can be used as a bit line on the first memory plane, and the elongated semiconductor material 12, 14 can be used as a bit line on the second memory plane. A layer of memory material 15, such as an anti-fuse material, is overlaid on the elongated semiconductor material in this example, and in other examples, at least on the sidewalls of the elongated semiconductor material. A plurality of wires 16, 17 are orthogonal to the stack of elongated semiconductor materials. The plurality of wires 16, 17 have a smooth surface that is stacked with the elongated semiconductor material and filled into the trenches (e.g., 20) defined by the stacks, and stacked and plural between the elongated semiconductor materials 11-14 The intersection of the side surfaces between the strips 16, 17 defines the interface area of the multilayer array. A layer of metal telluride (e.g., tungsten telluride, cobalt telluride, titanium telluride) 18, 19 is formed on the upper surface of the plurality of wires 16, 17.

The memory material layer 15 may comprise an antifuse material such as cerium oxide, cerium oxynitride or other cerium oxide, for example, having a thickness on the order of 1 to 5 nanometers. Other antifuse materials, such as tantalum nitride, can also be utilized. The elongated semiconductor materials 11-14 may be semiconductor materials having a first conductivity type (e.g., p-type). The wires 16, 17 may be semiconductor materials having a second conductivity type (e.g., n-type). For example, the elongated semiconductor materials 11-14 may use p-type polysilicon and the wires 16, 17 may use a heavily doped n+ type polysilicon. The width of the strip of semiconductor material must be sufficient to provide the depletion region required for diode operation. Therefore, the memory cell includes a PN junction formed between the strip polysilicon and the wire rectifier in an array of three-dimensional intersection points, the PN mask having a programmable antifuse layer between the cathode and the anode. In other embodiments, different programmable resistive memory materials can be used, including converting metal oxides, such as tungsten oxide over tungsten or elongated semiconductor materials doped with metal oxide. Such materials can be programmed and erased, and can be used in operational applications where multiple bits are stored in a memory cell.

Figure 2 shows a cross-sectional view along the Z-X plane of the memory cell at the intersection of the conductor 16 and the elongated semiconductor material 14. The active regions 25, 26 form both sides of the elongated semiconductor material 14 and between the wires 16 and the elongated semiconductor material 14. In the natural state, the antifuse memory material layer 15 has a high electrical resistance. After stylization, the anti-fuse memory material collapses, causing one or both of the active regions 25, 26 within the anti-fuse memory material to return to a low resistance state. In the embodiment described herein, each memory cell has two active regions 25, 26 forming the sides of the elongated semiconductor material 14. Figure 3 shows a cross-sectional view along the X-Y plane of the memory cell where the wires 16, 17 meet the elongated semiconductor material 14. The figure shows the current path of the word line defined by the free wire 16 through the antifuse memory material layer 15 to the elongated semiconductor material 14.

The flow of electrons is shown by the dashed line in Figure 3, from the n+ wire 16 into the p-type elongated semiconductor material 14, and along the elongated semiconductor material 14 (dashed arrow) to the sense amplifier, which can be measured at the sense amplifier The test indicates the state of the selected memory cell. In an exemplary embodiment, about 1 nm thick yttria is used as the anti-fuse material, and a pulse of 5-7 volts and a pulse width of about 1 microsecond are applied using the in-wafer control circuit of FIG. Stylized pulses. The read pulse is applied with a pulse of 1 to 2 volts and a configuration-dependent pulse width using the in-wafer control circuit of FIG. This read pulse can be much shorter than the programmed pulse.

Figure 4 shows two memory cell planes, each with six memory cells. These memory cells are represented by a diode with a layer of antifuse material (represented by dashed lines) between the cathode and the anode. The two memory cell planes are composed of the wires 60 and 61 as the first word line WLn and the second word line WLn+1 and the first and second sums as the bit lines BLn, BLn+1 and BLn+2, respectively. The intersection of the third strip of semiconductor material stacks 51, 52, 53, 54 and 55, 56 defines the first and second layers of the array. The first plane of the memory cell includes memory cells 30, 31 on the elongated semiconductor material stack 52, memory cells 32, 33 on the elongated semiconductor material stack 54, and memory cells 34 on the elongated semiconductor material stack 56, 35. The second plane of the memory cell includes memory cells 40, 41 on the elongated semiconductor material stack 51, memory cells 42, 43 on the elongated semiconductor material stack 53, and memory cells 44 on the elongated semiconductor material stack 55, 45. As shown in the figure, the wire 60 is used as the word line WLn, which includes vertically extending 60-1, 60-2, 60-3 corresponding to the material in the trench between the stacks in FIG. 1 to connect the wire 60. Coupled with three exemplary strips of semiconductor material in each plane. An array can be implemented with as many layers as described herein to form a very high density memory that approaches or reaches megabits per wafer.

Figure 5 shows a schematic diagram of a 2x2 memory cell portion of a three-dimensional programmable resistive memory array with fill material in the figure to clearly represent the stack and orthogonal conductors of the long strip of semiconductor material that make up the three-dimensional array. . In this illustration, only two layers are shown. However, the number of levels can be extended to very large numbers. As shown in Fig. 5, the memory array is formed over an integrated circuit substrate having a semiconductor or other structure (not shown) underlying an insulating layer 110. This memory array includes a stack 111, 112, 113, 114 of a plurality of elongated semiconductor materials separated from one another by insulating materials 121, 122, 123, 124. The stack is ridge shaped and extends along the Y-axis direction in the figure, so the elongated semiconductor materials 111-114 can be configured as bit lines and extend out of the substrate. The elongated semiconductor material 111, 113 can be used as a bit line on the first memory plane, and the elongated semiconductor material 112, 114 can be used as a bit line on the second memory plane.

The insulating material 121 interposed between the elongated semiconductor materials 111 and 112 in the first stack and the insulating material 123 interposed between the elongated semiconductor materials 113 and 114 in the second stack have an equivalent oxidation of about 40 nm or more. The layer thickness (EOT), wherein the equivalent oxide thickness (EOT) is the thickness of the insulating material multiplied by the thickness of the oxide layer converted by the ratio of the dielectric constant of the tantalum oxide to the insulating layer. The term "about 40 nm" as used herein is the result of an approximately 10% order of magnitude change in the process of a typical such device. The thickness of this insulating layer has an important influence on reducing interference between adjacent memory cells in this structure. In some embodiments, the equivalent oxide thickness (EOT) of the insulating material can be as small as 30 nanometers while still having sufficient isolation between adjacent layers.

A layer of memory material 115, such as a dielectric charge trapping structure, is overlaid over the elongated semiconductor material in this example. A plurality of wires 116, 117 are orthogonal to the stack of elongated semiconductor materials. The plurality of wires 116, 117 have a surface that is stacked with the elongated semiconductor material and filled into the trenches (eg, 120) defined by the stacks, and stacked and plural between the elongated semiconductor materials 111-114 The intersection of the side surfaces between the strips 116, 117 defines the interface area of the multilayer array. A layer of metal telluride (e.g., tungsten telluride, cobalt telluride, titanium telluride) 118, 119 is formed on the upper surface of the plurality of wires 116, 117.

The gold-oxygen half-field effect transistor pattern of the nanowire is also configured in such a way by providing a channel region of the nanowire or nanotube structure over the conductors 111-114, as Paul et al. Impact of a Process Variation on Nanowire and Nanotube Device Performance", IEEE Transactions on Electron Device, Vol. 54, No. 9, September 11-13, 2007, which is incorporated herein by reference.

Thus, a SONOS-type memory cell configured to be a three-dimensional array of anti-gate flash arrays can be formed. Source, drain and channel are formed in the germanium strip semiconductor material 111-114. The memory material layer 115 includes a tunneling dielectric layer 97 of germanium oxide (O), a charge storage layer 98 of tantalum nitride (N), and oxidation.矽(O) blocks the dielectric layer 99 and the wires 116, 117 of the polysilicon (S).

The elongated semiconductor materials 111-114 may be p-type semiconductor materials and the wires 116, 117 may use the same or different semiconductor materials (e.g., p+ type). For example, the elongated semiconductor materials 111-114 may be p-type polycrystalline germanium or p-type epitaxial single crystal germanium, and the wires 116, 117 may use relatively heavily doped p+ polycrystalline germanium.

Alternatively, the elongated semiconductor materials 111-114 may be n-type semiconductor materials and the wires 116, 117 may use semiconductor materials of the same or different conductivity types (eg, p+ type). This n-type semiconductor material arrangement results in a buried-channel depletion pattern of charge trapping memory cells. For example, the elongated semiconductor materials 111-114 may be n-type polysilicon or n-type epitaxial single crystal germanium, and the wires 116, 117 may use relatively heavily doped p+ polysilicon. The doping concentration of a typical n-type elongated semiconductor material is about 10 ¹⁸ /cm ³ , and the range of embodiments can be used to be between about 10 ¹⁷ /cm ³ and 10 ¹⁹ /cm ³ . The use of n-type strip semiconductor materials is a preferred choice for junctionless embodiments because the conductivity along the anti-gate string and thus the higher read current can be improved.

Thus, this memory cell containing a field effect transistor has a charge storage structure formed in a three dimensional array structure at this intersection. A strip of semiconductor material and wire thickness on the order of about 25 nanometers is used, and the pitch of the ridge-shaped stack is also on the order of about 25 nanometers, and devices having tens of layers (for example, thirty layers) can reach megas in a single wafer (10) ¹² ) The capacity of the bit.

This memory material layer 115 can comprise other charge storage structures. For example, a gap-engineered (BE) SONOS charge storage structure can be used, which includes a dielectric tunneling layer 97 with an inverted U-type valence band at 0V bias between layers. In an embodiment, the multilayer tunneling layer includes a first layer called a tunneling layer, a second layer called a band compensation layer, and a third layer called an isolation layer. In this embodiment, the tunneling layer 97 includes a ruthenium dioxide layer formed on a side surface of the elongated semiconductor material, which may be formed by a method such as in-situ steam generation (ISSG), and optionally Nitriding is carried out by annealing nitric oxide after deposition or by adding nitric oxide during deposition. The thickness of the cerium oxide in the first layer is less than 20 angstroms, and preferably less than 15 angstroms, and in a representative embodiment is 10 or 12 angstroms.

In this embodiment, the band compensation layer comprises a tantalum nitride layer on top of the tunnel tunnel layer, and the system uses a technique such as low pressure chemical vapor deposition LPCVD to use dichlorosilane at 680 ° C. DCS) is formed with an ammonia precursor. In other processes, the bandgap compensation layer includes bismuth oxynitride, which is formed using a similar process and a nitrous oxide precursor. The thickness of the tantalum nitride layer in the energy compensation layer is less than 30 angstroms, and preferably 25 angstroms or less.

In this embodiment, the spacer layer comprises a ruthenium dioxide layer on the band compensation layer and is formed by means of LPCVD high temperature oxide HTO deposition. The thickness of the ruthenium dioxide layer in the spacer layer is less than 35 angstroms, and preferably 25 angstroms or less. Such a three-layer tunneling dielectric layer produces a valence band energy level of an "inverted U" shape.

The first valence band energy system allows the electric field to be sufficient to induce tunneling through the thin region between the first portion and the semiconductor body (or strip of semiconductor material) interface, and which is sufficient to enhance the valence band after the first portion Energy level, in order to effectively eliminate the hole tunneling phenomenon in the composite tunneling dielectric layer after the first portion. Such a structure, in addition to establishing the "U-shaped" valence band of the three-layer tunneling dielectric layer, can also achieve electric field-assisted high-speed hole tunneling, which may also exist in the electric field or for other operational purposes (like from In the case where the memory cell reads data or stylizes adjacent memory cells and induces only a small electric field, it effectively prevents charge loss through the composite tunneling dielectric layer structure.

In a representative device, the memory material layer 115 comprises a bandgap engineering (BE) composite tunneling dielectric layer comprising a first layer of cerium oxide having a thickness of less than 2 nanometers and a thickness of a layer of tantalum nitride layer. The thickness of the ceria layer of less than 3 nm and a second layer is less than 4 nm. In one embodiment, the composite tunneling dielectric layer comprises an ultra-thin yttria layer O1 (eg, 15 angstroms or less), an ultra-thin tantalum nitride layer N1 (eg, 30 angstroms or less), and an ultra-thin yttrium oxide layer O2 ( For example, less than or equal to 35 angstroms, and it can increase the valence band energy of about 2.6 electron volts with a compensation of 15 angstroms or less from the interface of the semiconductor body or the strip of semiconductor material. The O2 layer can separate the N1 layer from the charge trapping layer by a second compensation (eg, from about 30 angstroms to 45 angstroms from the interface) by a low energy band energy region (high hole tunneling barrier) and a high conduction band energy level. ). Since the second distance interface is far enough, the electric field sufficient to induce tunneling can increase the valence band energy level after the second portion, so as to effectively eliminate the tunneling barrier. Therefore, the O2 layer does not seriously interfere with the electric field-assisted hole tunneling, and at the same time enhances the ability of the engineered tunneling dielectric structure to resist charge loss at low electric fields.

The charge trapping layer in the memory material layer 115 in this embodiment comprises a tantalum nitride layer having a thickness greater than 50 angstroms, including, for example, tantalum nitride having a thickness of about 70 angstroms, and which is formed using, for example, LPCVD. Other charge trapping materials and structures can also be used in the present invention, including, for example, cerium oxynitride (Si _x O _y N _z ), high cerium-containing nitrides, high cerium oxides, including embedded nanoparticles. Capture layers and more.

The blocking dielectric layer in the memory material layer 115 in this embodiment is yttrium oxide having a thickness greater than 50 angstroms and comprising 90 angstroms in this embodiment, and a wet furnace for wet converting tantalum nitride may be used. Tube oxidation process. In other embodiments, cerium oxide formed by high temperature oxide (HTO) or LPCVD deposition may be used. Other barrier dielectric material such as high dielectric constant materials of alumina can also be used.

In a representative embodiment, the thickness of the cerium oxide in the tunneling layer is 13 angstroms; the thickness of the lanthanum nitride layer of the energy compensation layer is 20 angstroms; and the thickness of the cerium oxide layer of the isolation layer is 25 Å; the thickness of the tantalum nitride layer of the charge trap layer is 70 angstroms; and the barrier dielectric layer may be yttrium oxide having a thickness of 90 angstroms. The gate material of the wires 116, 117 may be p+ polysilicon (having a work function of 5.1 electron volts).

Figure 6 shows a cross-sectional view of the charge trapping memory cell formed at the intersection of the conductor 116 and the elongated semiconductor material 114 along the Z-X plane of the memory cell. The active regions 125, 126 form a strip of semiconductor material 114 on either side of the wire 116 and the elongated semiconductor material 114. In the embodiment depicted in FIG. 6, each of the memory cells is a double gate field effect transistor having two active regions 125, 126 forming the sides of the elongated semiconductor material 114.

Figure 7 shows a cross-sectional view of the charge trapping memory cell formed at the intersection of the wire 116 and the elongated semiconductor material 114 along the X-Y plane of the memory cell. The current path to the elongated semiconductor material 114 is also shown. The flow of electrons, as indicated by the dashed lines in the figure, flows along the p-type elongated semiconductor material to a sense amplifier that can be measured to indicate the state of the selected memory cell. The source/drain regions 128, 129, 130 between the wires 116, 117 as word lines may be "no junction", that is, the source/drain doping type does not need to be associated with word lines. The doping profile of the underlying channel region is different. In this "no junction" embodiment, the charge trapping field effect transistor can have a p-type channel structure. Moreover, in some embodiments, source/drain doping can be formed using auto-aligned implants after defining word lines.

In an alternate embodiment, the elongated semiconductor materials 111-114 may use a lightly doped n-type semiconductor body in a "joint-free" arrangement, resulting in the formation of a buried-channel field effect transistor that can operate in a depletion mode, The charge trapping memory cell has a natural offset to a lower threshold voltage distribution.

Figure 8 shows two memory cell planes, each having nine charge trapping memory cells arranged in a reverse gate configuration, which is a representative example of a cube, which may include many planes and many word lines. The two memory cell planes are by wires 160, 161 and 162 as word lines WLn-1, WLn and WLn+1, which are respectively a stack of first, second and third elongated semiconductor materials.

The first plane of the memory cell includes memory cells 70, 71, and 72 in a reverse gate train, and is located on the stack of elongated semiconductor materials, and the memory cells 73, 74, and 75 are in a reverse gate train. And above the stack of elongated semiconductor materials, and the memory cells 76, 77 and 78 are in a reverse gate train and are placed over the stack of elongated semiconductor materials. In this illustration, the second plane of the memory cell corresponds to the bottom plane of the cube, and the memory cells (e.g., 80, 82, and 84) are arranged in the inverse gate train in a manner similar to the first plane.

As shown in the figure, the wire 161 as the word line WLn includes a vertically extending portion corresponding to the material in the trench 120 between the stacks in FIG. 5 to sandwich the wire 161 with the planar semiconductor material in all planes. The memory cells of the interface region within the trench (e.g., 71, 74, and 77 of the memory cells in the first plane) are coupled.

The bit line and the source line are located at opposite ends of the memory string. Bit lines 106, 107, and 108 are connected to different stacks in the memory string by control of bit line signals BLn-1, BLn, and BLn+1. In this arrangement, the source line 86 controlled by the signal SLn terminates the inverse and gate series of the upper half plane. Similarly, the source line 87 controlled by the signal SLn+1 in this arrangement terminates the inverse gate sequence of the lower half plane.

In this arrangement, the series selection transistors 85, 88, and 89 are connected between the respective AND gate columns and the bit lines BLn-1, BLn, and BLn+1. The string selection line 83 is parallel to the word line.

In this arrangement, the block selection transistors 90-95 couple the reverse gate series to one of the source lines. In this example, the ground select line GSL is coupled to the block select transistors 90-95 and can be implemented using conductors 160, 161, and 162. In some embodiments, the tandem selection transistor and the block selection transistor can use the same dielectric stack as the gate oxide layer in the memory cell. In other embodiments, a typical gate oxide layer can be used instead. In addition, the channel length and width can be adjusted as needed to provide the proper switching of these transistors.

Figure 9 shows a schematic diagram of an alternative structure similar to Figure 5, in which similar reference numerals are used in similar structures and will not be described again. The difference between the ninth and fifth aspects is that the surface 110A of the insulating layer 110 and the side surfaces 113A, 114A of the elongated semiconductor materials 113, 114 are etched into a word line (eg, 160) as a word line. Bare exposed. Thus, the memory material layer 115 can be completely or partially etched between the word lines without affecting operation. However, in some structures it is not necessary to form a dielectric charge trapping structure through the memory material layer 115 as is generally etched as described herein.

Figure 10 shows a cross-sectional view of the memory cell similar to Figure 6 along the Z-X plane. Fig. 10 is exactly the same as Fig. 6, showing the structure in the memory cell of Fig. 9, which is the same as the cross-sectional view of the structure implemented in Fig. 5 in this sectional view. Figure 11 shows a cross-sectional view of the memory cell similar to Figure 7 along the X-Y plane. The difference between the 11th and 7th views is that the memory material in the regions 128a, 129a and 130a along the side surfaces (e.g., 114A) of the elongated semiconductor material 114 is removed.

Figures 12 through 16 show a basic process stage flow diagram for implementing a three-dimensional memory array as described herein, using only two patterned mask steps that are critical to the alignment of the array. In Fig. 12, the structure after interleaving the deposition insulating layers 210, 212, 214 and the semiconductor layers 211, 213 is shown. For example, the semiconductor layer can be formed on the array region of the wafer using the fully deposited doped semiconductor. Depending on the embodiment, the semiconductor layer may use polycrystalline germanium or epitaxial single crystal germanium having an n-type or p-type doping. The interlayer insulating layers 210, 212, 214 may be, for example, cerium oxide, other cerium oxide or cerium nitride. These layers can be formed in a number of different ways, including techniques well known in the art, such as low pressure chemical vapor deposition (LPCVD).

Figure 13 shows the results of a first lithographic patterning step for defining a plurality of ridge-like elongated semiconductor material stacks 250, wherein the elongated semiconductor material is comprised of semiconductor layers 211, 213 and is comprised of an insulating layer 210, 212, 214 separated. Ditches with deep and very high aspect ratios can be formed between multilayer stacks using a lithography-based process and applying a carbon-containing hard mask and reactive ion etching.

14A and 14B respectively show a programmable charge memory structure including, for example, an anti-fuse memory cell structure and a programmable charge trap memory structure including, for example, a SONOS type memory cell structure. A section view of the next stage.

Figure 14A shows the results of a comprehensive deposition of a memory material 215 by a programmable resistive memory structure embodiment comprising a single layer anti-fuse memory cell structure as shown in Figure 1. Alternatively, an oxidative process can be performed without the use of a full deposition to form an oxide on the exposed side of the elongated semiconductor material, with the oxide being the memory material.

Figure 14B shows the result of a comprehensive deposition of a memory material 315 comprising a tunneling layer 397, a charge trapping, comprising a programmable resistive memory structure embodiment comprising a multilayer charge trapping structure as shown in Figure 4; Layer 398 and a barrier layer 399. As shown in Figures 14A and 14B, the memory material layers 235, 315 are deposited in a sinuous manner over a ridged strip of elongated semiconductor material (250 in Figure 13).

Figure 15 shows the results of a step of filling a high aspect ratio trench with a conductive material, which may be, for example, an n-type or p-type doped, used as a wire for a word line, to be deposited to form layer 225. Moreover, in embodiments using polysilicon, a layer of germanide 226 is formed over layer 225. As shown in the figure, a polyhedral equal aspect ratio deposition technique such as low pressure chemical vapor deposition (LPCVD) is used in this embodiment to fill the trench between the ridged stacks, even if it is very narrow with a high aspect ratio of 10 Nano-scale ditches are also feasible.

Figure 16 shows the results of a second lithography patterning step for defining a plurality of wires 260 as word lines in the three dimensional memory array. This second lithography patterning step uses a single mask to define the critical dimensions of the etched high aspect ratio trenches in the array without the need to engrave through the ridge-like stack. The polysilicon can be etched using an etching process that is highly selective for polysilicon and tantalum oxide or tantalum nitride. Therefore, instead of the etching process, the same mask as the etching of the semiconductor and the insulating layer can be used, and the process stops at the bottom insulating layer 210.

An optional process step includes forming a hard mask over a plurality of wires including word lines, ground selection lines, and serial selection lines. This hard mask can be formed using relatively thick nitride or other materials that block ion implantation. After the hard mask is formed, ion implantation can be performed to increase the doping concentration in the elongated semiconductor material, and thus reduce the electrical resistance along the current path of the elongated semiconductor material. By using the control implant energy, the implant can result in a long strip of semiconductor material that passes through the bottom strip and each of the upper strips of semiconductor material in the stack.

After that, the hard mask is removed to expose the germanium above the plurality of wires. After an interlevel dielectric layer is formed over the array, via holes are formed and filled therein, for example, using a plug of tungsten. The upper metal line as the bit line BL is patterned and connected to the decoding circuit. A three-dimensional decoding circuit is constructed in the manner of a picture, using a word line, a bit line, and a source line to access a selected memory cell. See U.S. Patent No. 6,069,940, entitled "Plane Decoding Method and Device for Three Dimensional Memories."

In order to program a selected anti-fuse type memory cell, the word line selected in this embodiment is biased to -7V, and the unselected word line can be set to 0V, and the selected bit line can also be set to 0V, the unselected bit line can be set to 0V, the selected source line can be set to -3.3V, and the unselected source line can be set to 0V. In order to read a selected memory cell, the word line selected in this embodiment is biased to -1.5V, the unselected word line can be set to 0V, and the selected bit line can also be set to 0V, which is not selected. The bit line can be set to 0V, the selected source line SL can be set to -3.3V, and the unselected source line can be set to 0V.

Figure 17 is a simplified schematic diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 875 includes the use of a three-dimensional programmable resistive read only memory (RRAM) array 860 as described herein over a semiconductor substrate. A column of decoders 861 is coupled to and electrically coupled to a plurality of word lines 862 arranged along the direction of the column of memory array 860. Row decoder 863 is in electrical communication with a plurality of bit lines 864 (or string select lines as previously described) arranged along the row direction of memory array 860 to read and program data from memory cells of array 860. . A planar decoder 858 is coupled to the previously described source string select line 859 (or previously described bit line) on the array 860 plane. The address is provided by bus 865 to row decoder 863, column decoder 861 and plane decoder 858. The sense amplifier and data input structure in block 866 is coupled to row decoder 863 via data bus 867. The data is provided to the data input line 871 by the input/output ports on the integrated circuit 875, or to other data sources of the integrated circuit 875, to the data input structure in block 866. Other circuits 874 are included within integrated circuit 875, such as a general purpose processor or special purpose application circuit, or a combination of modules to provide system single chip functionality supported by a programmable resistive memory cell array. The data is provided by sense amplifiers in block 866, via data output line 872, to integrated circuit 875, or to other data terminals internal/external to integrated circuit 875.

The controller used in this embodiment uses a bias adjustment state mechanism 869 and controls the application of bias voltage adjustment supply voltages generated or provided by voltage supply or block 868, such as read and program voltages. . The controller can be utilized with special purpose logic circuitry as is well known to those skilled in the art. In an alternate embodiment, the controller includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic circuitry and a general purpose processor.

Figure 18 is a simplified schematic diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit 975 includes the use of a three-dimensional three-dimensional inverse gate flash memory array array 960 as described herein over a semiconductor substrate. A column of decoders 961 is coupled to and electrically coupled to a plurality of word lines 962 arranged along the direction of the column of memory arrays 960. Row decoder 963 is in electrical communication with a plurality of bit lines 964 (or string select lines as previously described) arranged along the row direction of memory array 960 to read and program data from memory cells of array 960. . A planar decoder 958 is coupled to the previously described string select line 959 (or previously described bit line) on the array 960 plane. The address is provided by bus 965 to row decoder 963, column decoder 961 and plane decoder 958. The sense amplifier and data input structure in block 966 is coupled to row decoder 963 via data bus 967. The data is supplied to the data input line 971 by the input/output port on the integrated circuit 975, or is input to the data input structure in block 966 by other internal/external data sources of the integrated circuit 975. In this exemplary embodiment, other circuits 974 are included in the integrated circuit 975, such as a general purpose processor or a special purpose application circuit, or a combination of modules to provide support by the anti-gate flash memory array. System single chip function. The data is provided by the sense amplifier in block 966, via the data output line 972, to the integrated circuit 975, or to other data terminals internal/external to the integrated circuit 975.

The controller used in this embodiment uses a bias adjustment state mechanism 969 and controls the application of bias voltage adjustment supply voltage generated or provided by the voltage supply source or block 868, such as reading, programming, Erase, erase verify, and program verify voltage. The controller can be utilized with special purpose logic circuitry as is well known to those skilled in the art. In an alternate embodiment, the controller includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller is a combination of special purpose logic circuitry and a general purpose processor.

Figure 19 is a cross-sectional view of a tunneling electron microscope of a portion of a 8-layer vertical channel thin film transistor energy gap engineering polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS) charge trapping anti-gate device. It is manufactured, tested and arranged for decoding in the manner of Figures 8 and 23. This device was formed using a half pitch of 75 nm. The channel is an approximately 180 nm thick n-type polysilicon. No joints were implanted to form a jointless structure. The insulating material used to isolate the channels between the semiconductor strips is in the Z-axis direction and is a tantalum oxide having a thickness of about 40 nm. The gate provided is extremely P+ polysilicon. This serial selection and ground selection device has a longer channel length than the memory cell. The test device has 32 word lines, no junctions, and gate series. Since the trench etch used to form the illustrated structure has an inclined shape with a wide twist line at the bottom of the trench, and the insulating material between the thin lines is etched more from the polysilicon, the width of the lower thin line in Fig. 19 It is wider than the width of the upper thin line.

Figure 20 is a cross-sectional view showing a memory cell having a diode (e.g., diode 1492) in the opposite end of the gate semiconductor body in an embodiment. The structure includes a plurality of ridge-like stacks including elongated semiconductor materials 1414, 1413, 1412 on a substrate of respective ridge-like stacked planes. A plurality of conductors 1425-1 through 1425-n (shown only as two in the figure for simplicity) are orthogonal to the stack and extend across, and are formed substantially above the memory layer as previously described. . The wire 1427 as the tandem selection line SSL and the wire 1428 as the integral source line GSL and the other such lines are arranged in parallel with the plurality of wires as the word line. These wires may be formed using, for example, a conductive material 1491 having an n-type or p-type doped polysilicon for use as a wire of a word line. The telluride layer 1426 can be formed over a plurality of wires that are a word line, a string select line SSL, and an overall source line GSL.

In region 1415, elongated semiconductor materials 1414, 1413, 1412 are connected to other elongated semiconductor materials in the same plane via integral source line interconnects and to a planar decoder (not shown). The strip of semiconductor material extends in the overall source line interconnect using the step contact regions previously described.

A diode (e.g., 1492) is placed between the memory cells connected to the wires 1425-1 through 1425-n and the plugs 1450, 1451 connecting the bit lines BLn and BLn+1 to the elongated semiconductor material 1414, 1413, 1412. . In this exemplary embodiment, the diode is formed from a P+ implanted region (e.g., 1449) in the elongated semiconductor material. Plugs 1450, 1451 can include doped polysilicon, tungsten, or other vertical interconnect techniques. The upper azimuth lines BLn and BLn+1 are connected between the plugs 1450, 1451 and a row decoding circuit (not shown).

In the structure shown in Fig. 20, it is not necessary to form a contact between the tandem selection gates in the array and the common source selection gate.

Figure 21 shows two memory cell planes, each having six charge trapping memory cells arranged in a reverse gate configuration, which is a representative example of a cube, which may include many planes and many word lines. The two memory cell planes are composed of wires 1160, 1161, and 1162 as word lines WLn-1, WLn, and WLn+1, which are stacks of first, second, and third elongated semiconductor materials, respectively.

The first plane of the memory cell includes memory cells 1170, 1171, and 1172 in a reverse gate sequence, and is located above the stack of elongated semiconductor materials, and the memory cells 1173, 1174, and 1175 are in a reverse gate sequence. And located on the stack of long strips of semiconductor material. In this illustration, the second plane of the memory cell corresponds to the bottom plane of the cube, and the memory cells (e.g., 1182 and 1184) are arranged in the inverse gate train in a manner similar to the first plane.

As shown in the figure, the wire 1161 as the word line WLn includes a vertically extending portion corresponding to the material in the trench 120 between the stacks in FIG. 5 to sandwich the wire 1161 between the long semiconductor materials and all the planes. The memory cells of the interface region within the trench (e.g., 1171, 1174 of the memory cells in the first plane) are coupled.

Tandem select transistors 1196, 1197 are connected between respective inverted gate columns and bit lines BL1 and BL2. Similarly, in this arrangement, a similar series-selective transistor connection in the bottom plane of the cube is interposed between the respective AND gate columns and bit lines BL1 and BL2 such that row decoding is applied to the bit lines. Tandem select line 1106 is coupled to serial select transistors 1196, 1197 and parallel to the word lines, as shown in FIG.

In this example, diodes 1110, 1111, 1112, 1113 are connected between this string and the corresponding bit line.

The ground selection transistors 1190, 1191 are arranged on opposite sides of the reverse gate train and are used to couple the reverse gate train in a selected layer to a common source reference line. This common source reference line is decoded by the planar decoder in this structure. The ground select line GSL can be implemented in a manner similar to the wires 1160, 1161, and 1162. In some embodiments, the tandem selection transistor and ground selection transistor can use the same dielectric stack as the gate oxide layer in the memory cell. In other embodiments, a typical gate oxide layer can be used instead. In addition, the channel length and width can be adjusted as needed to provide the proper switching of these transistors. The stylized operation will be described below, in which the target memory cell is the memory cell A in Fig. 21, and the representative plane and the source cell A are in the same plane/source line and the same column/character line, respectively, but different lines/ The memory cell B of the bit line is in the same row/bit line and the same column/character line as the target memory cell A, but the memory cell C of the different plane/source line is opposite to the target memory cell A. Same column/word line, but different row/bit lines and memory cells D of different plane/source lines are in the same plane/source line and the same row/bit line as the target memory cell A, but different The memory cell E of the column/character line considers the interference condition of the memory cell.

According to this arrangement, the serial selection line and the common source selection line can be decoded in a cube-based manner in a cube. This character line can be decoded in a column-based manner in one column. This common source line can be decoded in a plane-based manner in a plane. This bit line can be decoded on a behavior-based basis in one line.

Figure 22 shows a timing diagram similar to the stylized operation of the array in Figure 20. This stylized interval is divided into three main sections labeled T1, T2, and T3. In the first part of T1, the ground select line GSL and the unselected common source line CSL (shown as SL in the figure) are set to VCC, which is approximately 3.3V and the common source line is selected. CSL is retained at approximately 0V. In addition, this serial select line SSL also remains at approximately 0V. In this way, the coupling effect between the selected plane and 0V can be achieved, and the unselected plane is floating, so that the difference between the unselected common source line and the common source selection line is insufficient to open the common source. Select the gate of the line. After a short transition time, the unselected word lines and other pass gates (eg, dummy word lines and select gates) in the circuit are coupled to a turn-on voltage value of approximately 10V. Similarly, the selected word line is coupled to the same or close voltage value, while the ground select line GSL and the unselected common source line CSL are retained at VCC. This will cause the self-pressure effect of the body region in the plane not selected. Referring to Fig. 21, memory cells C and D have a pressure rise region in the interval T1 as a result of this operation.

In the T2 segment, the ground select line GSL and the unselected common source line CSL transition back to 0V, while the word line and the turn-on gate remain at the turn-on voltage. After a short period of time when the ground select line GSL and the unselected common source line CSL transition back to 0V, the tandem select line SSL in this cube transitions to VCC, which may be about 3.3V as previously described. Similarly, the unselected bit lines also transition to VCC. The bias result in T2 time will result in the same plane/source line and the same column/word line, but the channel of the memory cell (such as memory cell B) of different row/bit lines and the same column/word line However, the channels of different row/bit lines and memory cells of different plane/source lines (such as memory cell D) are boosted by self-pressure rise. The boost channel voltage of the memory cell C is not leaked by the bit line BL due to the diode. After the T2 paragraph, the tandem select line SSL and the unselected bit line transition back to 0V.

In the T3 section, after the ground selection line GSL and the unselected common source line CSL transition back to 0V, the voltage of the selected word line is boosted to a stylized potential of, for example, 20V, and the serial selection line SSL The ground selection line GSL, the selected bit line, the unselected bit line, the selected common source line CSL, and the unselected common source line CSL are maintained at 0V. A reversed channel is formed in the selected memory cells in the time segments of T1 and T2, and thus stylization can be achieved even in the case where both the serial selection gate and the selected common source gate are turned off. It must be noted that in the same plane/source line and the same row/bit line as the target memory cell A, but the memory cell E of the different column/character line will only be applied to the unselected word line because the turn-on voltage is applied. Being disturbed. Therefore, the applied turn-on voltage must be low enough (for example, less than 10V) to prevent the data stored in these memory cells from being disturbed.

After the stylized interval, all voltages return to approximately 0V.

Different embodiments of the structure in Fig. 20 use 汲 extreme (bit line) forward sensing. In various embodiments, the diode suppresses the lost current path during read and program inhibit operations.

Fig. 23 is a view showing a bias condition similar to the reading operation of the array in Fig. 20. According to FIG. 23, the bias conditions applied to the structure on the substrate 410 are shown. The read bias of the memory cell on a plane in a cube is the applied turn-on voltage to the unselected word line, and a read reference voltage is applied to the Select the word line. The selected common source line CSL is coupled to about 0V, and the unselected common source line CSL is coupled to about VCC, and the ground select line GSL and the tandem select line SSL in the cube are coupled to about 3.3V. The bit lines BLn and BLn+1 in this cube are then coupled to a precharge stage of approximately 1.5V.

Page decoding in this example can be achieved by planar decoding using a common source line. Thus, for a given bias condition, because each selected common source line or plane in the cube has a page with the same number of bits that the bit line that can be read. The selected common source line CSL is coupled to about 0V or set to a reference voltage, while the other common source line CSL is set to about 3.3V. In this case, the unselected common source line is floating. The diode of the bit line path on the unselected plane prevents current from diverging.

In a page read operation, each word line on each plane in a cube is read once. Similarly, in a page-based stylization operation, this stylization suppression condition must be sufficient to withstand the number of stylizations required to program the page, ie, once per plane. Therefore, for a cube containing 8 memory cells, the stylized suppression condition of the unselected memory cell must be sufficient to withstand 8 stylized cycles.

It must be noted that the diode in this bit line string needs to slightly increase the bias voltage on the bit line by about 0.7V to compensate for the typical voltage drop of the diode.

Figure 24 shows a schematic diagram of the bias conditions for a cube erase operation. According to the bias condition shown in Fig. 24, the word line is coupled to a negative voltage of, for example, -5V, the common source line CSL and the bit line are coupled to a positive voltage of, for example, +8V, and the ground selection line. The GSL is coupled to a suitable high turn-on voltage such as +8V. This can suppress the breakdown scale of the source line bias. The ground selection line GSL and the serial selection line SSL of other blocks are turned off. The high voltage required for the bit line can be satisfied by the bit line driver design. Alternatively, the word line and the string select line may be grounded and the common source line CSL and the ground select line GSL are coupled to a high voltage such as +13V.

Figure 25 shows an alternative embodiment in which the diode 1492 application is formed by polysilicon plugs 1550, 1551 formed using in-situ p+ doping when forming a plug. In this case, the diodes are automatically aligned and the process steps can be reduced. The other structure is the same as that shown in Fig. 20. A twisted contact structure layout (as in Figure 27) can be used at less than 40 nm.

At self-voltage rise, the PN diode must withstand a boost channel potential of about 8V in tens of milliseconds. The estimated leakage current at 8V reverse bias should be less than 100pA to withstand this boost potential. Of course, the breakdown potential should be much higher than 8V. A lower turn-on voltage (approximately less than 0.7V) helps prevent sensing difficulties.

Figure 26 shows an alternative embodiment in which the diodes are placed at the common source line CSL end of the memory cell string. Therefore, in the region 1515, the source lines in each of the planes are coupled together by p+ lines or doping, forming a PN between the common source line decoder and the ground selection line GSL of each of the string lines. Diode. The other structure is the same as that shown in Fig. 20.

Different embodiments of the structure in Figure 26 use source extreme (source line) back sensing. In various embodiments, the diode suppresses the lost current path during read and program inhibit operations.

Figure 27 shows a schematic diagram of a cube in which two planes of the memory cell are shown, corresponding to the common source line CSL0 and the common source line CSL1, two rows of memory cells, corresponding bit lines BL0 and bit lines. BL1, the four columns of memory cells, respectively correspond to the word lines in the schema. The serial select line SSL in the cube is coupled to the serial select gate, and the ground select line GSL is coupled to the ground select gate. Similar to the self-pressurization stylization operation described previously for stylization, the application of a two-stage programmed voltage to the selected word line is described in more detail below. The diode is coupled between the corresponding memory cell string and the common source line CSL0 or the common source line CSL1.

In the following discussion, the region bit line is another noun in a string. In this configuration, all common source lines CSL can apply a high voltage to suppress stylization. When the selected common source line CSL becomes a low level, the high voltage of the area bit line does not become a low level. The page buffer can determine which memory cell should be programmed. When the bit line voltage is VDD, no stylization occurs. Stylization occurs when the bit line voltage is grounded.

For a reverse flash memory cell, the selected memory cell can be programmed using Fuller-Nordheim electron tunneling. In order to suppress the stylization of non-selected memory cells, a high voltage should be applied to the bit line or channel of the memory cell. To achieve stylized suppression, a stylized sequence as shown in Figures 28 and 29 can be applied.

This stylization operation involves applying a high voltage to the unselected common source line and applying VCC (about 3.3V) to the unselected bit line. When the word line changes to VCC or a high voltage turn-on voltage, the area bit line of the unselected bit line is boosted to a high voltage. The bit line of the bit line selected by the bit line is forced to a high voltage by the common source line or forced to be pulled down to the common source line by the bit line. When the word line of the selected memory cell changes to a stylized potential, all of the area bit lines are floated. The electrical energy applied during the stylization operation must be sufficient to cause any current (from VCC/high voltage to ground) caused by the voltage class on the bit line of an unselected bit line to not affect stylization or Causes stylized interference to occur.

Figure 28 shows a five-stage stylized sequence. In step 1, the ground select line turns on the ground select gate, and the tandem select line turns off the tandem select gate. The high voltage of the common source line is not selected to charge the area bit line in the unselected plane in the cube to a high voltage. The word line voltage of all word lines is raised to a first word line voltage. In step 2, the region bit line in the unselected row applies a supply potential to the unselected bit line and grounds the selected bit line by turning the string select gate on and the ground select gate off. In step 3, the word line is biased to the next turn-on voltage while the series select gate remains on and the ground select gate remains off. This causes the area bit line in the unselected area bit line to be coupled to the high voltage. In step 4, the shared bit line and a region bit line that does not select the common source line are charged to a high voltage. At this stage, the serial select line is turned off and the ground select line is turned on. In step 5, the word line voltage is biased to the programmed voltage while the serial select line and the ground select line remain off.

Figure 29 shows an alternative five-stage stylized sequence. In step 1, all of the region bit lines are charged to a high voltage via a common source line to a high voltage in the biased cube, turning on the ground select gate in the cube, and turning off the series select gate. After that, the ground selection gate in the cube is turned off, and the serial selection gate is turned on, which drives the area bit line in the bit line of the selected area to the ground voltage.

In step 3, the word line is biased to a turn-on voltage while the serial select gate remains on and the ground select gate remains off. This causes the area bit line in the selected area bit line to remain grounded and the area bit line in the unselected area bit line to float and be boosted by the word line. In step 4, by turning on the ground selection gate in the cube, and turning off the series selection gate pair, the common source line bias is not selected, and the bit line and the area bit of the common source line are not selected. The line is charged to a high voltage. In step 5, the word line is selected to receive the stylized voltage and the serial select gate and the ground select gate remain off. The algorithm in Fig. 29 can have better boost rejection characteristics and consume more power than Fig. 28. The self-raising region bit line LBL3 can improve the suppression result from the high voltage, and the bit line voltage in the region is higher and the suppression is improved. The result of changing from a common source line to a high voltage and discharging to ground increases power consumption.

Therefore, in this technique, the high voltage applied from the source line can suppress stylization. The stylized bit line is floating when the programmed voltage is applied to the selected bit line and the unselected source line is pulled down to ground. In addition, the bias voltage sequence is applied in a manner that suppresses stylization by maintaining correct boosting. When stylized, the current path of the diode is used to prevent current from returning to the common source.

Since the common source line is monolithic, the common source line can decode the entire array once. In contrast, decoding a string select line requires an additional string select line driver and contact area.

In various embodiments, the diode-decoded memory array reduces the number of serial select line gates to only one serial select line structure per block, or only one series per reverse gate train. Select the line gate. Such a structure greatly reduces the difficulty of the process, and has a high degree of symmetry and miniaturization. This architecture does not require a large number of serial selection lines when increasing the number of memory cell layers in a three-dimensional memory array. Similarly, only one ground selection line is required in a block.

Preferably, the three-dimensional vertical gate device uses a thin film transistor energy gap engineering polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS) device. Alternatively, similar devices using antifuse or other memory technologies can be developed (e.g., using other charge trapping devices having a high dielectric constant dielectric layer).

Figure 30 shows a timing diagram of another example stylized operation similar to the array in Figure 21.

At the T1 phase, the source line is self-boosted by the ground select line GSL and the Vcc on the unselected source line.

At the T2 phase, the unselected bit line is boosted to the high voltage HV by the string select line SSL and the high voltage HV on the unselected bit line. The channel voltage Vch of the memory cell B is also boosted. The channel voltage Vch whose memory cell C is boosted does not leak due to the diode on this bit line BL.

At the T3 phase, the memory cell A is programmed. Its inversion channel is already formed at the T1 phase.

Figure 31 shows a schematic diagram similar to the three-dimensional inverse gate flash memory structure of Figure 27, in which it is shown that the series includes a diode formed between the source line structure and the memory string. The location of these diodes can be used to support stylized suppression.

The target memory cell is the memory cell A in the figure, and the following interference conditions of the memory cell are considered: the memory cell B represents the same plane/source line and the same column/word line as the target memory cell A, but different rows/bits The memory cell of the meta-line, the memory cell C represents the same row/bit line and the same column/character line as the target memory cell A, but the memory cells of different plane/source lines, the memory cell D represents the target memory cell A In the same column/word line, but different row/bit lines and different plane/source lines, the memory cell E represents the same plane/source line and the same row/bit line as the target memory cell A, But the memory cells of different column/character lines. Memory cell E is disturbed by the turn-on voltage Vpass and can be ignored in many embodiments.

Figure 32 shows a timing diagram similar to one of the example stylized operations of the array in Figure 31.

At the T1 phase, the unselected bit lines (memory cells B and D) are self-boosted by the string select line SSL and the voltage Vcc on the unselected bit line.

In the T2 phase, the unselected source line is boosted to the high voltage HV by the ground select line GSL and the high voltage HV on the unselected source line. For example, the channel voltage Vch of the unselected source line of the memory cell C is also directly boosted. When the voltage of the source line SL is 0 V and the ground selection line GSL is turned on, for example, the channel voltage Vch of the memory cell B that has been boosted is not because of the small leakage of the reverse biased diode on the source line SL. Will leak.

At the T3 phase, although the serial selection line SSL is turned off, the memory cell A is still stylized. Its inversion channel is already formed at the T1 phase.

Figures 33A and 33B are photographs of a tunneling electron microscope of a portion of a three-dimensional inverse gate flash memory array.

Shown in the figure is a tunneling electron micrograph of a virtual grounding device with a 75 nm half-pitch (4F ² ). The channel width and length are 30 and 40 nm, respectively, and the channel height is 30 nm. Each device is a dual gate (vertical gate) vertical channel device in which the channel (buried channel device) is a lightly doped n-type to increase the read current. The outline of this bit line BL is a shape suitable for using a planar ONO. This process is suitably adapted to obtain smaller sidewall depressions. A very flat ONO is formed on the sidewall of the bit line BL.

Figure 33A is a cross-sectional view of the array in the X-axis direction. The figure shows two charge trapping energy gap polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS) devices formed on the sidewalls of each channel. Each device is a dual gate device. The channel current flows horizontally and the gates are vertically arranged. Has the smallest ONO sidewall recess.

Figure 33B is a cross-sectional view of the array in the Y-axis direction. Due to the tighter pitch and smaller bit line width, the tunneling electron micrograph of the focused ion beam shows a dual image of the polysilicon gate on the bit line (horizontal semiconductor strip) and the pitch. The device in the illustration has a channel length of approximately 40 nm.

Figure 34 is a graph showing the current-voltage (IV) characteristics of the experimentally measured polycrystalline germanium diode.

The forward and reverse current-voltage (IV) characteristics of the polysilicon PN diode are measured directly from the virtual ground and the vertical gate of the gate and the PN diode of the gate array. The height/width dimension of this polysilicon is 30/30 nm. The leakage current at -8 is well below 10pA, which is already in line with self-boosting and helps eliminate stylized interference. A source bias voltage Vs is applied, and a turn-on voltage Vpass of 7V is applied to all word lines. This P+-N diode (30 nm width and 30 nm height) shows a successful on/off ratio of more than 6 quantities and above. This forward current is clamped by the series resistors of the anti-gate series.

Figure 35 is a graph showing the read current characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory.

The three-dimensional inverse gate memory has 32 word lines. The voltage of both Vpass and Vread of the word line is 7V. The source line voltage Vsl varies among the following values: 2.5V, 2.0V, 1.0V, 0.5V, and 0.1V. In this illustration, the source line voltage Vsl exceeds 1.0 V resulting in a suitable sense current. The read voltage applied to the source terminal (source extreme sensing technique), in this case a positive voltage. The required bias voltage is boosted by the PN diode, which requires a sufficient turn-on voltage so that a source bias of more than 1.5V can generate sufficient read current.

Figure 36 is a diagram showing the stylized suppression characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory.

The figure shows typical stylized suppression characteristics of memory cells A, B, C, and D. In this case, Vcc = 3.3V, HV = 8V, and Vpass = 9V. An incremental step pulse ISSP method is applied to the memory cell A system. This pattern shows an interference-free interval of more than 5V. This is caused by the isolation characteristics of the diode.

Figure 37 shows the effect of the source bias effect of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory on the stylized interference.

The source line rejection bias (HV) has an effect on the stylized interference interval. The interference of memory cell C can be minimized by HV > 7V.

Figure 38 shows the effect of the turn-on gate voltage effect of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory on the stylized interference.

The turn-on gate voltage has an effect on stylized interference. Memory cell C interference can be reduced by Vpass > 6V.

Figure 39 is a schematic diagram of the block erase conversion current of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory.

Different bias voltages on the source line SL change the block erase conversion characteristics. Wiping is achieved by applying a positive source line bias and grounding all of the word lines WL. This means that the body of the three-dimensional anti-gate array is floated. The source select line SSL/ground select line GSL applies a suitable positive voltage to avoid interference. This erase transition is also shown in Figure 10. In some embodiments, this array does not use the electric field enhancement effect (because of the flat ONO), so that this erase is mainly performed by the energy gap polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS). Hole tunneling support.

Figure 40 is a schematic diagram showing the stylized and erased state current-voltage characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. The memory has a different number of stylized/erase cycles.

This current-voltage curve shows less degradation in less than 10,000 erase operations, especially at 1000 and once. The deterioration of endurance is usually caused by the interface state (Dit), which causes the subcritical slope to deteriorate, and the memory interval does not change. By adjusting the energy gap engineering polycrystalline germanium-yttria-yttria-yttria-yttria-yttria (BE-SONOS) stack, this device showed a reasonably small degradation compared to the giant device after 10,000 erase operations.

Figure 41 is a schematic diagram showing the critical voltage distribution of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. The memory has a stylized/erased memory cell with a checklist distribution.

A checklist of a single class of memory cells is used here in connection with a PN polycrystalline germanium diode connected to a three-dimensional inverse gate memory. The closest memory cell (in this three-dimensional sensing) is programmed to the opposite state to represent the worst interference situation. Traditional page stylization and stylization suppression methods are used in each layer, and then other unselected source lines (memory cells C and D) are suppressed. Program the page in other layers in turn. Memory cells that are not selected in a three-dimensional array are subject to many column and line stresses.

In many different embodiments, the diode of an alternate embodiment is connected to the 汲 terminal (bit line) or source (source line) and has a source select line SSL/ground select line GSL with a bit The roles of the meta/source lines are interchanged. These alternative operations are verified in the device class. However, in circuit design, the source line has a small capacitive load, so that it can perform better in speed and power consumption when a high voltage HV is applied to the source line.

The preferred embodiments and examples of the present invention are disclosed in detail above, but it should be understood that the above examples are merely exemplary and are not intended to limit the scope of the patent. For those skilled in the art, the related art can be modified and combined easily according to the scope of the following patent application.

10, 110. . . Insulation

11~14, 111~114. . . Long strip of semiconductor material

15, 115. . . Memory material

16, 17, 116, 117. . . wire

18, 19, 118, 119. . . Metal telluride

20, 120. . . ditch

21~24, 121~124. . . Insulation Materials

25, 26, 125, 126. . . Active area

30~35, 40~45, 70~78, 80, 82, 84. . . Memory cell

51~56. . . Long strip of semiconductor material stack

60 (60-1, 60-2, 60-3), 61, 160~162. . . Word line

86, 87. . . Source line

90~95. . . Block selection transistor

97, 397. . . Tunneling dielectric layer

98, 398. . . Charge storage layer

99, 399. . . Blocking dielectric layer

83. . . Serial selection line

85, 88, 89. . . Tandem selection transistor

106, 107, 108. . . Bit line

128, 129, 130. . . Source/bungee area

210, 212, 214. . . Insulation

211, 213. . . semiconductor

215. . . Memory material layer

250. . . Ridge stack

315. . . Charge trapping layer

225. . . wire

226, 1426. . . Metal telluride

875, 975. . . Integrated circuit

860. . . Three-dimensional programmable resistance read-only memory array with diodes in memory string

960. . . Three-dimensional anti-gate flash memory array with diodes in memory string

858, 958. . . Planar decoder

859, 959. . . Serial selection line

861, 961. . . Column decoder

862, 962. . . Word line

863, 963. . . Row decoder

864, 964. . . Bit line

865, 965, 867, 967. . . Busbar

866, 966. . . Sense amplifier / data input structure

874, 974. . . Other circuit

869, 969. . . State agency

868, 968. . . Bias adjustment supply voltage

871, 971. . . Data input line

872, 972. . . Data output line

410, 1410. . . Substrate

1412~1414. . . Long strip of semiconductor material

1415, 1515. . . region

1425-1 to 1425-n. . . wire

1427. . . Serial selection line SSL

1428. . . Overall source line GSL

1449. . . P+ planting area

1450, 1451, 1550, 1551. . . embolism

1491. . . Conductive material

1492, 1592. . . Dipole

1106. . . Serial selection line

1110~1113. . . Dipole

1160~1162. . . wire

1170~1175, 1180, 1182. . . Memory cell

1190, 1191. . . Ground selection transistor

1196, 1197. . . Tandem selection transistor

Figure 1 shows a schematic diagram of a three-dimensional memory structure as described herein, comprising a plurality of strips of semiconductor material plane parallel to the Y-axis and arranged in a plurality of ridge-like stacks, a memory layer on the side of the elongated semiconductor material, and a plurality The strip has a wire with a plurality of ridge-like stacked bottom surfaces below it.

Fig. 2 is a cross-sectional view showing the memory cell structure of Fig. 1 along the Z-X plane.

Fig. 3 is a cross-sectional view showing the memory cell structure of Fig. 1 along the Y-X plane.

Fig. 4 is a view showing the structure of the antifuse having the structure of Fig. 1 as a basic memory.

Figure 5 shows a schematic diagram of a three-dimensional inverse gate flash memory structure as described herein, comprising a plurality of strips of semiconductor material plane parallel to the Y-axis and arranged in a plurality of ridge-like stacks, a charge trapping memory layer in the strip The sides of the semiconductor material, and the plurality of wires having a plurality of ridge-like stacked bottom surfaces below it.

Fig. 6 is a cross-sectional view showing the memory cell structure of Fig. 5 along the Z-X plane.

Fig. 7 is a cross-sectional view showing the memory cell structure of Fig. 5 along the Y-X plane.

Fig. 8 is a view showing the reverse gate flash memory having the structures of Figs. 5 and 23.

Figure 9 shows a schematic diagram of an alternative embodiment of a three-dimensional inverse gate flash memory structure similar to that of Figure 5, in which the layer of memory material is removed from between the wires.

Fig. 10 is a cross-sectional view showing the memory cell structure of Fig. 9 along the Z-X plane.

Fig. 11 is a cross-sectional view showing the memory cell structure of Fig. 9 along the Y-X plane.

Fig. 12 is a schematic cross-sectional view showing the first stage of the process for fabricating the memory device of Figs. 1, 5, and 9.

Figure 13 shows a schematic cross-sectional view showing the second stage of the process for fabricating the memory device of Figures 1, 5, and 9.

Fig. 14A shows a schematic cross-sectional view showing the third stage of the process of manufacturing the memory device as shown in Fig. 1.

Fig. 14B shows a schematic cross-sectional view showing the third stage of the process of manufacturing the memory device as shown in Fig. 5.

Fig. 15 is a cross-sectional view showing the third stage of the process of manufacturing the memory device as shown in Figs. 1, 5, and 9.

Fig. 16 is a schematic cross-sectional view showing the fourth stage of the process of manufacturing the memory device as shown in Figs. 1, 5, and 9.

Figure 17 is a simplified schematic diagram of an integrated circuit in accordance with an embodiment of the present invention, wherein the integrated circuit includes a three-dimensional programmable resistive read-only memory array having row, column and planar decoding circuits.

Figure 18 is a simplified schematic diagram showing an integrated circuit in accordance with another embodiment of the present invention, wherein the integrated circuit includes a three-dimensional inverted gate flash memory array having row, column and plane decoding circuits.

Figure 19 is a tunneling electron micrograph of a portion of a three-dimensional inverse gate flash memory array.

Figure 20 is a cross-sectional view showing a bit line structure having a diode in the series and a memory string in a three-dimensional inverse gate flash memory structure.

Figure 21 is a schematic diagram showing the relationship between a bit line structure having a diode in the series and a memory string in a three-dimensional inverse gate flash memory structure, showing two memory cell planes, each having six planes The charge trapping memory cells are arranged to reverse the gate configuration.

Figure 22 shows a timing diagram similar to the stylized operation of the array in Figure 20.

Figure 23 is a cross-sectional view showing a three-dimensional inverse gate flash memory structure in which a bit line structure having a diode in the series and a memory string are read.

Figure 24 is a cross-sectional view showing a three-dimensional anti-gate flash memory structure in which a bit line structure having a diode is arranged in the series and a memory string in a stylized operation.

Figure 25 is a schematic diagram showing the structure of a bit line having a diode in this series and a memory string in a three-dimensional inverse gate flash memory structure, which uses a polysilicon plug as a diode.

Figure 26 is a cross-sectional view showing a source line structure having a diode in the series and a memory string in a three-dimensional inverse gate flash memory structure.

Figure 27 shows a schematic diagram of a source line structure having a diode in this series and a memory string in a three-dimensional inverse gate flash memory structure, showing two memory cell planes.

Figure 28 is a timing diagram showing a first example of the stylized operation of the array in Figure 21.

Figure 29 is a timing diagram showing a second example of the stylized operation of the array in Figure 21.

Figure 30 is a timing diagram showing another example of the stylized operation of the array in Figure 21.

Figure 31 shows a schematic diagram similar to the three-dimensional inverse gate flash memory structure of Figure 27, in which it is shown that the series includes a diode formed between the source line structure and the memory string.

Figure 32 is a timing diagram showing an example of the stylized operation of the array in Figure 31.

Figures 33A and 33B are photographs of a tunneling electron microscope of a portion of a three-dimensional inverse gate flash memory array.

Figure 34 is a graph showing the current-voltage (IV) characteristics of the experimentally measured polycrystalline germanium diode.

Figure 35 is a graph showing the read current characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory.

Figure 36 is a diagram showing the stylized suppression characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory.

Figure 37 shows the effect of the source bias effect of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory on the stylized interference.

Figure 38 shows the effect of the turn-on gate voltage effect of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory on the stylized interference.

Figure 39 is a schematic diagram of the block erase conversion current of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory.

Figure 40 is a schematic diagram showing the stylized and erased state current-voltage characteristics of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. The memory has a different number of stylized/erase cycles.

Figure 41 is a schematic diagram showing the critical voltage distribution of the polycrystalline germanium diode connected to the three-dimensional inverse gate memory. The memory has a stylized/erased memory cell with a checklist distribution.

10. . . Insulation

11~14. . . Long strip of semiconductor material

15. . . Memory material

16, 17. . . wire

18, 19. . . Metal telluride

20. . . ditch

21~24. . . Insulation Materials

Claims (24)

A memory device comprising: an integrated circuit substrate; a plurality of elongated semiconductor material stacks extending out of the integrated circuit substrate, the plurality of stacked layers having a ridge shape and comprising at least two elongated semiconductor materials separated by an insulating layer to form a plurality Different planar positions in the planar positions; the plurality of word lines are arranged orthogonal to the plurality of stacks and have a surface that is parallel to the plurality of stacks, such that the plurality of stacks and the plurality of characters An intersection of the line surfaces establishes a three-dimensional array of intersection regions; the memory component is in the intersection region, and the memory cells of the three-dimensional array are accessible via the plurality of strips of semiconductor material and the plurality of word lines, the memory The component is arranged in a string between the bit line structure and the source line, wherein the string is opposite to the gate string; and the diode is coupled to the string, and is connected to the memory string and the bit Between the line structure and the source line. The memory device of claim 1, wherein a specific bit line in the bit line structure, a specific source line in the source line, and a specific word line in the plurality of word lines The combination of the selection can identify a particular memory cell in the memory cell of the three-dimensional array. The memory device of claim 1, wherein the diode is coupled to the string between the memory cell string and the bit line structure. The memory device of claim 1, wherein the diode is coupled to the string between the memory cell string and the source line. The memory device of claim 1, further comprising: a series of selection lines arranged orthogonal to the plurality of stacks, and having a surface conforming to the plurality of stacks, such that the plurality of stacked and Aligning the intersection of the surface of the selection line to establish a tandem selection device; and a ground selection line arranged orthogonal to the plurality of stacks and having a surface conforming to the plurality of stacks, such that the plurality of stacks A ground selection device is established with the intersection of the surface of the ground selection line. The memory device of claim 5, wherein the diode is coupled between the string selection device and the bit line structure. The memory device of claim 5, wherein the diode is coupled between the ground selection device and the source line. The memory device of claim 1, wherein the memory device comprises a tunneling layer, a charge trapping layer and a barrier layer, respectively. The memory device of claim 1, wherein the elongated semiconductor material comprises an n-type germanium and the diode comprises a p-type region in the elongated semiconductor material. The memory device of claim 1, wherein the elongated semiconductor material comprises an n-type germanium and the diode comprises a p-type plug in contact with the elongated semiconductor material. The memory device of claim 1 further includes logic to apply a reverse bias to the diode in the unselected string of the memory cell when the memory cell is programmed body. A memory device comprising: an integrated circuit substrate; a three-dimensional array of memory cells in the integrated circuit substrate, the three-dimensional array comprising: a stack of inverted gate memory cells; and a diode coupled to the series Connected between the memory cell string and one of the bit line structure and the source line; and the plurality of word lines include at least one first word line to access the opposite gate on the different layers of the stack Serial. The memory device of claim 12, wherein a specific bit line in the bit line structure, a specific source line in the source line, and a specific word line in the plurality of word lines The combination of the selection can identify a particular memory cell in the memory cell of the three-dimensional array. The memory device of claim 12, wherein the diode is coupled to the string between the memory cell string and the bit line structure. The memory device of claim 12, wherein the diode is coupled to the series between the memory cell string and the source line. The memory device of claim 12, further comprising: a serial selection device between the bit line structure and the memory cell string; and a ground selection device interposed between the source line and the memory cell Between the series. The memory device of claim 16, wherein the diode is coupled between the string selection device and the bit line structure. The memory device of claim 16, wherein the diode is coupled between the ground selection device and the source line. The memory device of claim 12, wherein the memory device comprises a tunneling layer, a charge trapping layer and a barrier layer, respectively. A method for operating a three-dimensional anti-gate flash memory, comprising: applying a stylized adjustment bias sequence to the three-dimensional anti-gate flash memory, the three-dimensional anti-gate flash memory comprising a reverse gate memory Stacking the cells, and coupling the diodes to the series such that the two-pole system is between the memory cell string and one of the bit line structure and the source line structure; the three-dimensional inverse gate flash memory The body further includes at least one first word line for accessing the memory cell series in different layers of the three-dimensional anti-gate flash memory. The method of claim 20, wherein applying the stylized adjustment bias sequence comprises: one or more of the source line structures passing one or more of the diodes to the unselected series One or more charging, wherein the unselected string does not include a memory cell to be programmed by the stylized adjustment bias; the bit line structure and the source line structure are from the unselected string and include Deselecting a selected string of one or more of the memory cells programmed by the stylized adjustment bias; applying one or more word lines of the memory cell to be programmed by the stylized adjustment bias A stylized voltage is applied to the unselected string and the selected string. The method of claim 20, wherein applying the stylized adjustment bias sequence comprises: not passing one or more of the diodes and one or more of the source line structures to the unselected string One or more of the columns are charged, wherein the unselected string does not include a memory cell to be programmed by the stylized adjustment bias; the bit line structure and the source line structure are from the unselected series and Deselecting a selected series comprising one or more of the memory cells to be stylized by the stylized adjustment bias; and one or more words of the memory cell to be programmed by the stylized adjustment bias The line applies a stylized voltage to the unselected string and the selected string. The method of claim 20, wherein applying the stylized adjustment bias sequence comprises: one or more of the self-bit line structures passing through one or more of the diodes to the unselected series One or more of the charging, wherein the unselected string does not include a memory cell to be programmed by the stylized adjustment bias; the bit line structure and the source line structure are from the unselected series and included Decoupling a selected string of one or more of the memory cells to be stylized by the stylized adjustment bias; and one or more characters of the memory cell to be programmed by the stylized adjustment bias The line applies a stylized voltage to the unselected string and the selected string. The method of claim 20, wherein applying the stylized adjustment bias sequence comprises: one or more of the self-bit line structures not passing through one or more of the diodes One or more of the columns are charged, wherein the unselected string does not include a memory cell to be programmed by the stylized adjustment bias; the bit line structure and the source line structure are from the unselected series and Including Decoupling a selected string of one or more of the memory cells programmed by the stylized adjustment bias; and one or more characters of the memory cell to be programmed by the stylized adjustment bias The line applies a stylized voltage to the unselected string and the selected string.